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-rw-r--r--test_rrobin_problem/readme.txt26
-rw-r--r--test_rrobin_problem/rtl/box.vhd229
-rw-r--r--test_rrobin_problem/rtl/led_control_ahb.vhd137
-rw-r--r--test_rrobin_problem/rtl/top.vhd535
-rw-r--r--test_rrobin_problem/rtl_tb/top_tb.vhd465
-rw-r--r--test_rrobin_problem/simulation/Makefile55
-rw-r--r--test_rrobin_problem/simulation/run.do71
-rw-r--r--test_rrobin_problem/simulation/vhdl_files.txt22
-rw-r--r--test_rrobin_problem/simulation/wave.do27
-rw-r--r--test_rrobin_problem/synthesis/Makefile205
-rw-r--r--test_rrobin_problem/synthesis/program_fpga.cmd8
-rw-r--r--test_rrobin_problem/synthesis/program_spi.cmd9
-rw-r--r--test_rrobin_problem/synthesis/sp601.ucf372
-rw-r--r--test_rrobin_problem/synthesis/top.ut30
-rw-r--r--test_rrobin_problem/synthesis/top.xst53
15 files changed, 0 insertions, 2244 deletions
diff --git a/test_rrobin_problem/readme.txt b/test_rrobin_problem/readme.txt
deleted file mode 100644
index d4de6d8..0000000
--- a/test_rrobin_problem/readme.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-auf der Suche nach der Ursache warum am AHB mit mehreren Mastern
-und rrobin = 0 nix mehr geht
-
-offenbar baut XST Mist
-
-Testszenario:
-
-* zwei Master, die eine GPIO-LED umschalten
-* Hardware: Board SP601
-
-Problem: im Testszenario funktioniert alles erwartungsgemäß :-(
-
-
-Versuch auf neuer (alter) Hardware: Digilent S3E-Starterkit
-
--use_new_parser No
-mit rrobin = 1 --> work testflow ca. 180 sek
-mit rrobin = 0 --> fail testflow ca. 180 sek
-
--use_new_parser Yes
-mit rrobin = 1 --> work testflow ca. 85 sek
-mit rrobin = 0 --> work testflow ca. 65 sek
-
-
-Ergo: Problem tritt nur auf Spartan3E-Board mit "rrobin = 0" auf.
-evtl. testen Funktion auf Spartan 3
diff --git a/test_rrobin_problem/rtl/box.vhd b/test_rrobin_problem/rtl/box.vhd
deleted file mode 100644
index c651746..0000000
--- a/test_rrobin_problem/rtl/box.vhd
+++ /dev/null
@@ -1,229 +0,0 @@
---------------------------------------------------------------------------------
--- $Date$
--- $Author$
--- $Revision$
---------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library gaisler;
-use gaisler.misc.all; -- types
-use gaisler.uart.all; -- types
-use gaisler.net.all; -- types
-use gaisler.uart.apbuart;
-use gaisler.misc.grgpio;
-
-library grlib;
-use grlib.amba.all;
-
-library techmap;
-use techmap.gencomp.all; -- constants
-
-
-entity box is
- generic (
- time_factor : positive := 2500
- );
- port (
- clk : in std_ulogic;
- reset_n : in std_ulogic;
- --
- uarti : in uart_in_type;
- uarto : out uart_out_type;
- --
- gpioi : in gpio_in_type;
- gpioo : out gpio_out_type
- );
-end entity box;
-
-
-architecture rtl of box is
-
- signal ahbctrl_i0_msti : ahb_mst_in_type;
- signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
- signal ahbctrl_i0_slvi : ahb_slv_in_type;
- signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
- signal apbctrl_i0_apbi : apb_slv_in_type;
- signal apbo : apb_slv_out_vector := (others => apb_none);
- --
- signal grgpio_i0_gpioo : gpio_out_type;
-
-
-begin
-
-
- ---------------------------------------------------------------------
- --
- led_control_ahb_i0: entity work.led_control_ahb
- generic map (
- hindex => 0, -- : integer := 0;
- count => 20 * time_factor, -- : natural := 0;
- gpio_data => x"00000000" -- : std_logic_vector(31 downto 0)
- )
- port map (
- -- system
- clk => clk, -- : in std_ulogic;
- -- ahb
- ahbi => ahbctrl_i0_msti, -- : in ahb_mst_in_type;
- ahbo => ahbmo(0) -- : out ahb_mst_out_type
- );
- ---------------------------------------------------------------------
-
-
- ---------------------------------------------------------------------
- --
- led_control_ahb_i1: entity work.led_control_ahb
- generic map (
- hindex => 1, -- : integer := 0;
- count => 20 * time_factor + 3, -- : natural := 0;
- gpio_data => x"0000000f" -- : std_logic_vector(31 downto 0)
- )
- port map (
- -- system
- clk => clk, -- : in std_ulogic;
- -- ahb
- ahbi => ahbctrl_i0_msti, -- : in ahb_mst_in_type;
- ahbo => ahbmo(1) -- : out ahb_mst_out_type
- );
- ---------------------------------------------------------------------
-
-
- ---------------------------------------------------------------------
- -- AHB CONTROLLER
-
- --ahbmo(0) <= (ahbm_none);
- --ahbmo(1) <= (ahbm_none);
- ahbmo(2) <= (ahbm_none);
- ahbmo(3) <= (ahbm_none);
- --
- --ahbso(0) <= (ahbs_none); -- apbctrl_i0
- ahbso(1) <= (ahbs_none);
- ahbso(2) <= (ahbs_none);
- ahbso(3) <= (ahbs_none);
- ahbso(4) <= (ahbs_none); -- spimctrl
- ahbso(5) <= (ahbs_none); -- mctrl
- ahbso(6) <= (ahbs_none);
- ahbso(7) <= (ahbs_none);
-
- ahbctrl_i0 : ahbctrl -- AHB arbiter/multiplexer
- generic map (
- defmast => 0, -- default master
- --
- --
- rrobin => 0, -- round robin arbitration
- --
- --
- timeout => 11,
- disirq => 0, -- enable interrupt routing
- enbusmon => 0, -- enable bus monitor
- assertwarn => 1, -- enable assertions for warnings
- asserterr => 1 -- enable assertions for errors
- )
- port map (
- rst => reset_n, -- : in std_ulogic;
- clk => clk, -- : in std_ulogic;
- msti => ahbctrl_i0_msti, -- : out ahb_mst_in_type;
- msto => ahbmo, -- : in ahb_mst_out_vector;
- slvi => ahbctrl_i0_slvi, -- : out ahb_slv_in_type;
- slvo => ahbso, -- : in ahb_slv_out_vector;
- testen => '0',
- testrst => '1',
- scanen => '0',
- testoen => '1'
- );
- ----------------------------------------------------------------------
-
-
-
-
- ---------------------------------------------------------------------
- -- AHB/APB bridge
-
- apbo( 0) <= (apb_none);
- --apbo( 1) <= (apb_none); -- apbuart_i0
- apbo( 2) <= (apb_none); -- no gptimer_i0
- apbo( 3) <= (apb_none);
- --apbo( 4) <= (apb_none); -- grgpio_i0
- apbo( 5) <= (apb_none);
- apbo( 6) <= (apb_none); -- no apbvga_i0
- apbo( 7) <= (apb_none); -- no i2cmst_i0
- apbo( 8) <= (apb_none);
- apbo( 9) <= (apb_none);
- apbo(10) <= (apb_none); -- no i2cmst_i1
- apbo(11) <= (apb_none);
- apbo(12) <= (apb_none);
- apbo(13) <= (apb_none);
- apbo(14) <= (apb_none);
- apbo(15) <= (apb_none); -- no mctrl_i0
-
- apbctrl_i0: apbctrl
- generic map (
- hindex => 0, -- : integer := 0;
- haddr => 16#800#, -- : integer := 0;
- nslaves => 16, -- : integer range 1 to NAPBSLV := NAPBSLV;
- asserterr => 1,
- assertwarn => 1
- )
- port map (
- rst => reset_n, -- : in std_ulogic;
- clk => clk, -- : in std_ulogic;
- ahbi => ahbctrl_i0_slvi, -- : in ahb_slv_in_type;
- ahbo => ahbso(0), -- : out ahb_slv_out_type;
- apbi => apbctrl_i0_apbi, -- : out apb_slv_in_type;
- apbo => apbo -- : in apb_slv_out_vector
- );
- ----------------------------------------------------------------------
-
-
- ---------------------------------------------------------------------
- -- uart
- apbuart_i0: apbuart
- generic map (
- pindex => 1,
- paddr => 1,
- console => 1, -- fast simulation output
- parity => 0, -- no parity
- flow => 1, -- hardware handshake
- fifosize => 16
- )
- port map (
- rst => reset_n, -- : in std_ulogic;
- clk => clk, -- : in std_ulogic;
- apbi => apbctrl_i0_apbi, -- : in apb_slv_in_type;
- apbo => apbo(1), -- : out apb_slv_out_type;
- uarti => uarti, -- : in uart_in_type;
- uarto => uarto -- : out uart_out_type);
- );
- ---------------------------------------------------------------------
-
-
- ---------------------------------------------------------------------
- -- GPIO
- grgpio_i0: grgpio
- generic map (
- pindex => 4,
- paddr => 4,
- syncrst => 1, -- only synchronous reset
- nbits => 32 -- number of port bits
- )
- port map (
- rst => reset_n,
- clk => clk,
- apbi => apbctrl_i0_apbi,
- apbo => apbo(4),
- gpioi => gpioi,
- gpioo => grgpio_i0_gpioo
- );
- gpioo <= grgpio_i0_gpioo;
- -- gpio.dout gpio.din
- ---------------------------------------------------------------------
- -- 3 - 0 LED gpio_switch
- -- 7 - 4 unused gpio_button
- -- 15 - 8 header gpio_header_ls
- -- 30 - 16 unused
- -- 31 unused simulation_active
- ---------------------------------------------------------------------
-
-end architecture rtl;
diff --git a/test_rrobin_problem/rtl/led_control_ahb.vhd b/test_rrobin_problem/rtl/led_control_ahb.vhd
deleted file mode 100644
index b1105a1..0000000
--- a/test_rrobin_problem/rtl/led_control_ahb.vhd
+++ /dev/null
@@ -1,137 +0,0 @@
---------------------------------------------------------------------------------
--- $Date$
--- $Author$
--- $Revision$
---------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-
-library hzdr;
-use hzdr.devices_hzdr.all;
-
-
-entity led_control_ahb is
- generic(
- hindex : integer := 0;
- count : natural := 0;
- gpio_data : std_logic_vector(31 downto 0)
- );
- port (
- -- system
- clk : in std_ulogic;
- -- ahb
- ahbi : in ahb_mst_in_type;
- ahbo : out ahb_mst_out_type
- );
-end entity led_control_ahb;
-
-
-architecture rtl of led_control_ahb is
-
- constant revision_c : integer := 0;
- constant hconfig_c : ahb_config_type := (
- 0 => ahb_device_reg ( VENDOR_HZDR, 255, 0, revision_c, 0),
- others => (others => '0')
- );
-
- constant gpio_addr_c : std_ulogic_vector(31 downto 0) := x"80000404";
-
- constant default_ahb_mst_out_c : ahb_mst_out_type := (
- hbusreq => '0',
- hlock => '0',
- htrans => HTRANS_IDLE,
- haddr => (others => '0'),
- hwrite => '0',
- hsize => HSIZE_WORD,
- hburst => HBURST_SINGLE,
- hprot => "0001",
- hwdata => (others => '0'),
- hirq => (others => '0'),
- hconfig => hconfig_c,
- hindex => hindex
- );
-
- type state_t is (IDLE, ADDR_PHASE, DATA_PHASE);
-
- type reg_t is record
- state : state_t;
- counter : natural;
- ahbo : ahb_mst_out_type;
- end record;
- constant default_reg_c : reg_t := (
- state => IDLE,
- counter => 0,
- ahbo => default_ahb_mst_out_c
- );
-
- signal r : reg_t := default_reg_c;
- signal r_in : reg_t;
-
-begin
-
- comb: process(r, ahbi)
- variable v : reg_t;
- begin
- ahbo <= r.ahbo;
- v := r;
-
- case v.state is
- when IDLE =>
- -- have reach right time?
- if v.counter < count then
- v.counter := v.counter + 1;
- else
- -- bus write request
- v.ahbo.hbusreq := '1';
- v.ahbo.htrans := HTRANS_NONSEQ;
- v.ahbo.haddr := std_logic_vector( gpio_addr_c);
- v.ahbo.hwrite := '1';
- -- have grant?
- if ahbi.hgrant( hindex) = '1' then
- v.state := ADDR_PHASE;
- end if;
- end if;
-
- when ADDR_PHASE =>
- v.ahbo.hbusreq := '0';
- v.ahbo.htrans := HTRANS_IDLE;
- v.ahbo.haddr := (others => '0');
- v.ahbo.hwrite := '0';
- v.ahbo.hwdata := gpio_data;
- v.state := DATA_PHASE;
-
-
- when DATA_PHASE =>
- v.ahbo.hwdata := (others => '0');
- v.counter := 0;
- v.state := IDLE;
-
- end case;
-
- r_in <= v;
- end process comb;
-
-
- seq: process
- begin
- wait until rising_edge( clk);
- r <= r_in;
- end process seq;
-
-
- -- pragma translate_off
- bootmsg : report_version
- generic map (
- "led_control_ahb" & tost( hindex) & ": rev " & tost( revision_c) & ", gpio_data: " & tost( gpio_data)
- );
- -- pragma translate_on
-
-
-end architecture rtl;
-
diff --git a/test_rrobin_problem/rtl/top.vhd b/test_rrobin_problem/rtl/top.vhd
deleted file mode 100644
index 16a6fa8..0000000
--- a/test_rrobin_problem/rtl/top.vhd
+++ /dev/null
@@ -1,535 +0,0 @@
--- top level des beam position monitor
--- fr SP601
---
--- enthlt alle buffer/treiber fr die FPGA-Pins
---
---
-
---------------------------------------------------------------------------------
--- $Date$
--- $Author$
--- $Revision$
---------------------------------------------------------------------------------
-
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-library unisim;
-use unisim.vcomponents.bufg;
-use unisim.vcomponents.iddr2;
-use unisim.vcomponents.ibufgds_diff_out;
-use unisim.vcomponents.ibufgds;
-use unisim.vcomponents.ibufds;
-use unisim.vcomponents.dcm_sp;
-use unisim.vcomponents.bufgmux;
-
-
-entity top is
- generic (
- time_factor : positive := 2500
- );
- port (
- cpu_reset : in std_logic; -- SW9 pushbutton (active-high)
- --
- -- DDR2 memory 128 MB
- ddr2_a : out std_logic_vector(12 downto 0);
- ddr2_ba : out std_logic_vector(2 downto 0);
- ddr2_cas_b : out std_logic;
- ddr2_ras_b : out std_logic;
- ddr2_we_b : out std_logic;
- ddr2_cke : out std_logic;
- ddr2_clk_n : out std_logic;
- ddr2_clk_p : out std_logic;
- ddr2_dq : inout std_logic_vector(15 downto 0);
- ddr2_ldm : out std_logic;
- ddr2_udm : out std_logic;
- ddr2_ldqs_n : inout std_logic;
- ddr2_ldqs_p : inout std_logic;
- ddr2_udqs_n : inout std_logic;
- ddr2_udqs_p : inout std_logic;
- ddr2_odt : out std_logic;
- --
- -- flash memory
- flash_a : out std_logic_vector(24 downto 0);
- flash_d : inout std_logic_vector(7 downto 3);
- --
- fpga_d0_din_miso_miso1 : inout std_logic; -- dual use
- fpga_d1_miso2 : inout std_logic; -- dual use
- fpga_d2_miso3 : inout std_logic; -- dual use
- flash_we_b : out std_logic;
- flash_oe_b : out std_logic;
- flash_ce_b : out std_logic;
- --
- -- FCM connector
- -- M2C Mezzanine to Carrier
- -- C2M Carrier to Mezzanine
- fmc_clk0_m2c_n : in std_logic;
- fmc_clk0_m2c_p : in std_logic;
- fmc_clk1_m2c_n : in std_logic;
- fmc_clk1_m2c_p : in std_logic;
- -- IIC addresses:
- -- M24C08: 1010100..1010111
- -- 2kb EEPROM on FMC card: 1010010
- iic_scl_main : inout std_logic;
- iic_sda_main : inout std_logic;
- fmc_la00_cc_n : inout std_logic;
- fmc_la00_cc_p : inout std_logic;
- fmc_la01_cc_n : inout std_logic;
- fmc_la01_cc_p : inout std_logic;
- fmc_la02_n : inout std_logic;
- fmc_la02_p : inout std_logic;
- fmc_la03_n : inout std_logic;
- fmc_la03_p : inout std_logic;
- fmc_la04_n : inout std_logic;
- fmc_la04_p : inout std_logic;
- fmc_la05_n : inout std_logic;
- fmc_la05_p : inout std_logic;
- fmc_la06_n : inout std_logic;
- fmc_la06_p : inout std_logic;
- fmc_la07_n : inout std_logic;
- fmc_la07_p : inout std_logic;
- fmc_la08_n : inout std_logic;
- fmc_la08_p : inout std_logic;
- fmc_la09_n : inout std_logic;
- fmc_la09_p : inout std_logic;
- fmc_la10_n : inout std_logic;
- fmc_la10_p : inout std_logic;
- fmc_la11_n : inout std_logic;
- fmc_la11_p : inout std_logic;
- fmc_la12_n : inout std_logic;
- fmc_la12_p : inout std_logic;
- fmc_la13_n : inout std_logic;
- fmc_la13_p : inout std_logic;
- fmc_la14_n : inout std_logic;
- fmc_la14_p : inout std_logic;
- fmc_la15_n : inout std_logic;
- fmc_la15_p : inout std_logic;
- fmc_la16_n : inout std_logic;
- fmc_la16_p : inout std_logic;
- fmc_la17_cc_n : inout std_logic;
- fmc_la17_cc_p : inout std_logic;
- fmc_la18_cc_n : inout std_logic;
- fmc_la18_cc_p : inout std_logic;
- fmc_la19_n : inout std_logic;
- fmc_la19_p : inout std_logic;
- fmc_la20_n : inout std_logic;
- fmc_la20_p : inout std_logic;
- fmc_la21_n : inout std_logic;
- fmc_la21_p : inout std_logic;
- fmc_la22_n : inout std_logic;
- fmc_la22_p : inout std_logic;
- fmc_la23_n : inout std_logic;
- fmc_la23_p : inout std_logic;
- fmc_la24_n : inout std_logic;
- fmc_la24_p : inout std_logic;
- fmc_la25_n : inout std_logic;
- fmc_la25_p : inout std_logic;
- fmc_la26_n : inout std_logic;
- fmc_la26_p : inout std_logic;
- fmc_la27_n : inout std_logic;
- fmc_la27_p : inout std_logic;
- fmc_la28_n : inout std_logic;
- fmc_la28_p : inout std_logic;
- fmc_la29_n : inout std_logic;
- fmc_la29_p : inout std_logic;
- fmc_la30_n : inout std_logic;
- fmc_la30_p : inout std_logic;
- fmc_la31_n : inout std_logic;
- fmc_la31_p : inout std_logic;
- fmc_la32_n : inout std_logic;
- fmc_la32_p : inout std_logic;
- fmc_la33_n : inout std_logic;
- fmc_la33_p : inout std_logic;
- fmc_prsnt_m2c_l : in std_logic;
- fmc_pwr_good_flash_rst_b : out std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
- --
- -- ???
- fpga_awake : out std_logic;
- fpga_cclk : out std_logic;
- fpga_cmp_clk : in std_logic;
- fpga_cmp_cs_b : in std_logic;
- fpga_cmp_mosi : in std_logic;
- --
- fpga_hswapen : in std_logic;
- fpga_init_b : out std_logic; -- low active
- fpga_m0_cmp_miso : in std_logic; -- mode DIP switch SW1 active high
- fpga_m1 : in std_logic; -- mode DIP switch SW1 active high
- fpga_mosi_csi_b_miso0 : inout std_logic;
- fpga_onchip_term1 : inout std_logic;
- fpga_onchip_term2 : inout std_logic;
- --fpga_suspend : in std_logic;
- fpga_vtemp : in std_logic;
- --
- -- GPIOs
- gpio_button : in std_logic_vector(3 downto 0); -- active high
- gpio_header_ls : inout std_logic_vector(7 downto 0); --
- gpio_led : out std_logic_vector(3 downto 0);
- gpio_switch : in std_logic_vector(3 downto 0); -- active high
- --
- -- Ethernet Gigabit PHY,
- -- default settings:
- -- phy address = 0b00111
- -- ANEG[3..0] = "1111"
- -- ENA_XC = 1
- -- DIS_125 = 1
- -- HWCFG_MD[3..0] = "1111"
- -- DIS_FC = 1
- -- DIS_SLEEP = 1
- -- SEL_BDT = 0
- -- INT_POL = 1
- -- 75/50Ohm = 0
- phy_col : in std_logic;
- phy_crs : in std_logic;
- phy_int : out std_logic;
- phy_mdc : out std_logic;
- phy_mdio : inout std_logic;
- phy_reset : out std_logic;
- phy_rxclk : in std_logic;
- phy_rxctl_rxdv : in std_logic;
- phy_rxd : in std_logic_vector(7 downto 0);
- phy_rxer : in std_logic;
- phy_txclk : in std_logic;
- phy_txctl_txen : out std_logic;
- phy_txc_gtxclk : out std_logic;
- phy_txd : out std_logic_vector(7 downto 0);
- phy_txer : out std_logic;
- --
- --
- spi_cs_b : out std_logic;
- --
- -- 200 MHz oscillator, jitter 50 ppm
- sysclk_n : in std_logic;
- sysclk_p : in std_logic;
- --
- -- RS232 via USB
- usb_1_cts : out std_logic; -- function: RTS output
- usb_1_rts : in std_logic; -- function: CTS input
- usb_1_rx : out std_logic; -- function: TX data out
- usb_1_tx : in std_logic; -- function: RX data in
- --
- -- 27 MHz, oscillator socket
- user_clock : in std_logic;
- --
- -- user clock provided per SMA
- user_sma_clock_p : inout std_logic;
- user_sma_clock_n : inout std_logic
- );
-end entity top;
-
-
-
-
-library gaisler;
-use gaisler.misc.all; -- types
-use gaisler.uart.all; -- types
-
-
-architecture rtl of top is
-
- constant system_frequency_c : natural := 200_000_000;
-
- function simulation_active return std_ulogic is
- variable result : std_ulogic;
- begin
- result := '0';
- -- pragma translate_off
- result := '1';
- -- pragma translate_on
- return result;
- end function simulation_active;
-
- --
- -- signal definitions to resolve inout signals
- --
- signal sys_clk : std_ulogic;
- signal clk_box : std_ulogic;
- --
- signal reset_shreg : std_ulogic_vector(3 downto 0) := (others => '1');
- signal reset : std_ulogic := '1';
- signal reset_n : std_ulogic := '0';
- --
- signal uarti : uart_in_type;
- signal gpioi : gpio_in_type;
- --
- signal box_i0_uarto : uart_out_type;
- signal box_i0_gpioo : gpio_out_type;
-
-
-begin
-
-
- ------------------------------------------------------------
- -- clock stuff
- --
- clk_driver_b : block
- signal clk_fb0 : std_ulogic;
- signal dcm_sp_i0_clk0 : std_ulogic;
- signal dcm_sp_i0_clkfx : std_ulogic;
- signal dcm_sp_i0_clkdv : std_ulogic;
- signal dcm_sp_i0_clkdv_n : std_ulogic;
- signal clk_fb1 : std_ulogic;
- signal dcm_sp_i1_clk0 : std_ulogic;
- signal dcm_sp_i1_clk180 : std_ulogic;
- signal dcm_sp_i1_locked : std_ulogic;
- signal dcm_sp_i1_status : std_logic_vector(7 downto 0);
- begin
-
- -- global differential input buffer
- ibufgds_i0 : ibufgds
- generic map (
- diff_term => true
- )
- port map (
- i => sysclk_p,
- ib => sysclk_n,
- o => sys_clk
- );
-
- -- DCM
- dcm_sp_i0: dcm_sp
- generic map (
- clkin_divide_by_2 => false,
- clkdv_divide => 4.0,
- clkfx_multiply => 13,
- clkfx_divide => 25,
- clk_feedback => "1x"
- )
- port map (
- clkin => sys_clk,
- clk0 => dcm_sp_i0_clk0,
- clkdv => dcm_sp_i0_clkdv,
- clkfx => dcm_sp_i0_clkfx,
- clkfb => clk_fb0
- );
-
- clk_fb0 <= dcm_sp_i0_clk0;
- --clk_box <= dcm_sp_i0_clkfx; -- 52 MHz
- clk_box <= dcm_sp_i0_clk0; -- 200 MHz
-
- end block;
-
-
- ------------------------------------------------------------
- -- reset generation
- reset_generator_p: process
- begin
- wait until rising_edge( clk_box);
- reset_shreg <= reset_shreg(reset_shreg'left-1 downto 0) & '0';
- reset <= reset_shreg(reset_shreg'left);
- if cpu_reset = '1' then
- reset_shreg <= (others => '1');
- end if;
- end process;
- reset_n <= not reset;
-
-
-
-
--- chipscope_i0 : chipscope
--- port map (
--- clk => adc_clk_buf, --: in std_ulogic;
--- data => adc_data_16bit, --: in std_ulogic_vector(15 downto 0);
--- trig => '1' --: in std_ulogic
--- );
-
-
- -- default output drivers
- --
- fmc_la00_cc_n <= 'Z';
- fmc_la00_cc_p <= 'Z';
- fmc_la01_cc_n <= 'Z';
- fmc_la01_cc_p <= 'Z';
- fmc_la02_n <= 'Z';
- fmc_la02_p <= 'Z';
- fmc_la03_n <= 'Z';
- fmc_la03_p <= 'Z';
- fmc_la04_n <= 'Z';
- fmc_la04_p <= 'Z';
- fmc_la05_n <= 'Z';
- fmc_la05_p <= 'Z';
- fmc_la06_n <= 'Z';
- fmc_la06_p <= 'Z';
- fmc_la07_n <= 'Z';
- fmc_la07_p <= 'Z';
- fmc_la08_n <= 'Z';
- fmc_la08_p <= 'Z';
- fmc_la09_n <= 'Z';
- fmc_la09_p <= 'Z';
- fmc_la10_n <= 'Z';
- fmc_la10_p <= 'Z';
- fmc_la11_n <= 'Z';
- fmc_la11_p <= 'Z';
- fmc_la12_n <= 'Z';
- fmc_la12_p <= 'Z';
- fmc_la13_n <= 'Z';
- fmc_la13_p <= 'Z';
- fmc_la14_n <= 'Z';
- fmc_la14_p <= 'Z';
- fmc_la15_n <= 'Z';
- fmc_la15_p <= 'Z';
- fmc_la16_n <= 'Z';
- fmc_la16_p <= 'Z';
- fmc_la17_cc_n <= 'Z';
- fmc_la17_cc_p <= 'Z';
- fmc_la18_cc_n <= 'Z';
- fmc_la18_cc_p <= 'Z';
- fmc_la19_n <= 'Z';
- fmc_la19_p <= 'Z';
- fmc_la20_n <= 'Z';
- fmc_la20_p <= 'Z';
- fmc_la21_n <= 'Z';
- fmc_la21_p <= 'Z';
- fmc_la22_n <= 'Z';
- fmc_la22_p <= 'Z';
- fmc_la23_n <= 'Z';
- fmc_la23_p <= 'Z';
- fmc_la24_n <= 'Z';
- fmc_la24_p <= 'Z';
- fmc_la25_n <= 'Z';
- fmc_la25_p <= 'Z';
- fmc_la26_n <= 'Z';
- fmc_la26_p <= 'Z';
- fmc_la27_n <= 'Z';
- fmc_la27_p <= 'Z';
- fmc_la28_n <= 'Z';
- fmc_la28_p <= 'Z';
- fmc_la29_n <= 'Z';
- fmc_la29_p <= 'Z';
- fmc_la30_n <= 'Z';
- fmc_la30_p <= 'Z';
- fmc_la31_n <= 'Z';
- fmc_la31_p <= 'Z';
- fmc_la32_n <= 'Z';
- fmc_la32_p <= 'Z';
- fmc_la33_n <= 'Z';
- fmc_la33_p <= 'Z';
- fpga_awake <= 'Z';
- fpga_init_b <= '1';
- fpga_onchip_term1 <= 'Z';
- fpga_onchip_term2 <= 'Z';
- --
- ddr2_a <= (others => '1');
- ddr2_ba <= (others => '1');
- ddr2_cas_b <= '1';
- ddr2_ras_b <= '1';
- ddr2_we_b <= '1';
- ddr2_cke <= '0';
- ddr2_clk_n <= '0';
- ddr2_clk_p <= '1';
- ddr2_dq <= (others => 'Z');
- ddr2_ldm <= '0';
- ddr2_udm <= '0';
- ddr2_ldqs_n <= 'Z';
- ddr2_ldqs_p <= 'Z';
- ddr2_udqs_n <= 'Z';
- ddr2_udqs_p <= 'Z';
- ddr2_odt <= '1';
- --
- phy_int <= 'Z';
- phy_mdc <= '0';
- phy_mdio <= 'Z';
- phy_reset <= '0';
- phy_txc_gtxclk <= '0';
- phy_txctl_txen <= '0';
- phy_txd <= (others => '1');
- phy_txer <= '0';
- --
- user_sma_clock_p <= 'Z';
- user_sma_clock_n <= 'Z';
-
-
-
-
- ------------------------------------------------------------
- -- SPI memory pads
- -- SPI X4 (Winbond W25Q64VSFIG) 64-Mbit flash memory
- fpga_d2_miso3 <= 'Z'; -- /hold
- fpga_d1_miso2 <= 'Z'; -- /write_protect
- fpga_cclk <= '0';
- fpga_mosi_csi_b_miso0 <= 'Z';
- spi_cs_b <= 'Z';
-
-
- ------------------------------------------------------------
- -- BPI parallel flash
-
- -- inout
- fpga_d0_din_miso_miso1 <= 'Z';
- fpga_d1_miso2 <= 'Z';
- fpga_d2_miso3 <= 'Z';
- flash_d(7 downto 3) <= "ZZZZZ";
- -- out
- fmc_pwr_good_flash_rst_b <= reset_n;
- flash_ce_b <= '1';
- flash_oe_b <= '1';
- flash_we_b <= '1';
-
- flash_a <= (others => 'Z');
-
-
-
- ------------------------------------------------------------
- -- gpio input pads
- gpioi.sig_in <= (others => '0');
- gpioi.sig_en <= (others => '0');
- gpioi.din( 3 downto 0) <= std_logic_vector( gpio_switch);
- gpioi.din( 7 downto 4) <= gpio_button;
- gpioi.din(15 downto 8) <= gpio_header_ls;
- gpioi.din(30 downto 16) <= (others => '0');
- gpioi.din(31) <= simulation_active;
-
-
- ------------------------------------------------------------
- -- uart input
- uarti.rxd <= usb_1_tx; -- function: RX data in
- uarti.ctsn <= usb_1_rts; -- not( usb_1_rts); function: CTS input
- uarti.extclk <= '0';
-
- ------------------------------------------------------------
- -- box system
- box_i0: entity work.box
- generic map (
- time_factor => time_factor --: positive
- )
- port map (
- clk => clk_box, --: in std_ulogic;
- reset_n => reset_n, --: in std_ulogic;
- --
- uarti => uarti, --: in uart_in_type;
- uarto => box_i0_uarto, --: out uart_out_type;
- --
- gpioi => gpioi, --: in gpio_in_type;
- gpioo => box_i0_gpioo --: out gpio_out_type;
- );
-
- ------------------------------------------------------------
- -- gpio output pads
- -- placement on board: LED0, LED1, LED2, LED3
- gpio_led <= box_i0_gpioo.dout( 3 downto 0);
- --gpio_header_ls <= box_i0_gpioo.dout(15 downto 8);
- gpio_header_ls(0) <= box_i0_gpioo.dout( 8) when box_i0_gpioo.oen( 8) = '0' else 'Z';
- gpio_header_ls(1) <= box_i0_gpioo.dout( 9) when box_i0_gpioo.oen( 9) = '0' else 'Z';
- gpio_header_ls(2) <= box_i0_gpioo.dout(10) when box_i0_gpioo.oen(10) = '0' else 'Z';
- gpio_header_ls(3) <= box_i0_gpioo.dout(11) when box_i0_gpioo.oen(11) = '0' else 'Z';
- gpio_header_ls(4) <= box_i0_gpioo.dout(12) when box_i0_gpioo.oen(12) = '0' else 'Z';
- gpio_header_ls(5) <= box_i0_gpioo.dout(13) when box_i0_gpioo.oen(13) = '0' else 'Z';
- gpio_header_ls(6) <= box_i0_gpioo.dout(14) when box_i0_gpioo.oen(14) = '0' else 'Z';
- gpio_header_ls(7) <= box_i0_gpioo.dout(15) when box_i0_gpioo.oen(15) = '0' else 'Z';
- fpga_awake <= not box_i0_gpioo.dout( 0);
-
-
- ------------------------------------------------------------
- -- uart output
- usb_1_rx <= box_i0_uarto.txd; -- function: TX data out
- usb_1_cts <= box_i0_uarto.rtsn; -- function: RTS
-
-
- ------------------------------------------------------------
- -- fmc/main i2c io pads
- iic_scl_main <= 'Z';
-
- iic_sda_main <= 'Z';
-
-end architecture rtl;
diff --git a/test_rrobin_problem/rtl_tb/top_tb.vhd b/test_rrobin_problem/rtl_tb/top_tb.vhd
deleted file mode 100644
index b4b9e16..0000000
--- a/test_rrobin_problem/rtl_tb/top_tb.vhd
+++ /dev/null
@@ -1,465 +0,0 @@
--- top testbench
---
--- contains:
---
--- +--------------+
--- | board_sp601 |
--- | |XFMCX
--- | |XLPCX
--- | FPGA |
--- +--------------+
---
--- +-------------------------------------------------------------------------+
--- | top_tb (= eval board sp605) |
--- | |
--- | +----------------+ |
--- | | top (= FPGA) | |
--- | | | |
--- | | | |
--- | +----------------+ |
--- | *FMC LPC* |
--- | |
--- +-------------------------------------------------------------------------+
-
---------------------------------------------------------------------------------
--- $Date$
--- $Author$
--- $Revision$
---------------------------------------------------------------------------------
-
-entity top_tb is
-end entity top_tb;
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library std;
-use std.textio.all;
-
-
-
-architecture testbench of top_tb is
-
-
- constant me_c : string := testbench'path_name;
-
- constant gnd : std_logic := '0';
-
- signal simulation_run : boolean := true;
- signal tb_simulation_break : std_logic;
-
-
- signal tb_cpu_reset : std_logic; -- SW6 pushbutton (active-high)
- --
- -- DDR2 memory
- signal tb_ddr2_a : std_logic_vector(12 downto 0);
- signal tb_ddr2_ba : std_logic_vector(2 downto 0);
- signal tb_ddr2_cas_b : std_logic;
- signal tb_ddr2_ras_b : std_logic;
- signal tb_ddr2_we_b : std_logic;
- signal tb_ddr2_cke : std_logic;
- signal tb_ddr2_clk_n : std_logic;
- signal tb_ddr2_clk_p : std_logic;
- signal tb_ddr2_dq : std_logic_vector(15 downto 0);
- signal tb_ddr2_ldm : std_logic;
- signal tb_ddr2_udm : std_logic;
- signal tb_ddr2_ldqs_n : std_logic;
- signal tb_ddr2_ldqs_p : std_logic;
- signal tb_ddr2_udqs_n : std_logic;
- signal tb_ddr2_udqs_p : std_logic;
- signal tb_ddr2_odt : std_logic;
- --
- -- flash memory
- signal tb_flash_a : std_logic_vector(24 downto 0);
- signal tb_flash_d : std_logic_vector( 7 downto 0);
- --
- signal tb_fpga_d0_din_miso_miso1 : std_logic; -- dual use
- signal tb_fpga_d1_miso2 : std_logic; -- dual use
- signal tb_fpga_d2_miso3 : std_logic; -- dual use
- signal tb_flash_we_b : std_logic;
- signal tb_flash_oe_b : std_logic;
- signal tb_flash_ce_b : std_logic;
- --
- -- FCM connector
- -- M2C Mezzanine to Carrier
- -- C2M Carrier to Mezzanine
- signal tb_iic_scl_main : std_logic;
- signal tb_iic_sda_main : std_logic;
- signal tb_fmc_prsnt_m2c_l : std_logic;
- signal tb_FMC_PWR_GOOD_FLASH_RST_B : std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
- --
- -- ???
- signal tb_FPGA_AWAKE : std_logic;
- signal tb_FPGA_CCLK : std_logic;
- signal tb_FPGA_CMP_CLK : std_logic;
- signal tb_FPGA_CMP_CS_B : std_logic;
- signal tb_FPGA_CMP_MOSI : std_logic;
- --
- signal tb_FPGA_HSWAPEN : std_logic;
- signal tb_FPGA_INIT_B : std_logic;
- signal tb_FPGA_M0_CMP_MISO : std_logic;
- signal tb_FPGA_M1 : std_logic;
- signal tb_FPGA_MOSI_CSI_B_MISO0 : std_logic;
- signal tb_FPGA_ONCHIP_TERM1 : std_logic;
- signal tb_FPGA_ONCHIP_TERM2 : std_logic;
- signal tb_FPGA_VTEMP : std_logic;
- --
- -- GPIOs
- signal tb_gpio_button : std_logic_vector(3 downto 0); -- active high
- signal tb_gpio_header_ls : std_logic_vector(7 downto 0);
- signal tb_gpio_led : std_logic_vector(3 downto 0);
- signal tb_gpio_switch : std_logic_vector(3 downto 0); -- active high
- --
- -- Ethernet Gigabit PHY
- signal tb_PHY_COL : std_logic;
- signal tb_PHY_CRS : std_logic;
- signal tb_PHY_INT : std_logic;
- signal tb_PHY_MDC : std_logic;
- signal tb_PHY_MDIO : std_logic;
- signal tb_PHY_RESET : std_logic;
- signal tb_PHY_RXCLK : std_logic;
- signal tb_PHY_RXCTL_RXDV : std_logic;
- signal tb_PHY_RXD : std_logic_vector(7 downto 0);
- signal tb_PHY_RXER : std_logic;
- signal tb_PHY_TXCLK : std_logic;
- signal tb_PHY_TXCTL_TXEN : std_logic;
- signal tb_PHY_TXC_GTXCLK : std_logic;
- signal tb_PHY_TXD : std_logic_vector(7 downto 0);
- signal tb_PHY_TXER : std_logic;
- --
- --
- signal tb_SPI_CS_B : std_logic;
- --
- -- 200 MHz oscillator
- constant tb_sysclk_period : time := (1 sec / 200_000_000);
- signal tb_sysclk_n : std_logic := '0';
- signal tb_sysclk_p : std_logic := '1';
- --
- -- RS232 via USB
- signal tb_usb_1_cts : std_logic;
- signal tb_usb_1_rts : std_logic;
- signal tb_usb_1_rx : std_logic;
- signal tb_usb_1_tx : std_logic;
- --
- -- 27 MHz, oscillator socket
- constant tb_user_clock_period : time := (1 sec / 27_000_000);
- signal tb_user_clock : std_logic := '0';
- signal tb_user_sma_clock_p : std_logic;
- signal tb_user_sma_clock_n : std_logic;
- --
- --
- --
- signal tb_fmc_lpc_row_c : std_logic_vector(40 downto 1);
- signal tb_fmc_lpc_row_d : std_logic_vector(40 downto 1);
- signal tb_fmc_lpc_row_g : std_logic_vector(40 downto 1);
- signal tb_fmc_lpc_row_h : std_logic_vector(40 downto 1);
-
-
-begin
-
- -- clock generators
- tb_user_clock <= not tb_user_clock after tb_user_clock_period / 2 when simulation_run;
- tb_sysclk_n <= not tb_sysclk_n after tb_sysclk_period / 2 when simulation_run;
- tb_sysclk_p <= not tb_sysclk_p after tb_sysclk_period / 2 when simulation_run;
-
-
- -- stimuli for buttons and switches
- tb_gpio_button <= "0000", "0001" after 500 us, "0000" after 700 us;
- tb_gpio_switch <= "0000", "1111" after 600 us;
-
-
- top_i0: entity work.top
- generic map (
- time_factor => 1 --: positive
- )
- port map (
- cpu_reset => tb_cpu_reset, --: in std_logic; -- SW6 pushbutton (active-high)
- --
- -- DDR2 memory
- ddr2_a => tb_ddr2_a, --: out std_logic_vector(12 downto 0);
- ddr2_ba => tb_ddr2_ba, --: out std_logic_vector(2 downto 0);
- ddr2_cas_b => tb_ddr2_cas_b, --: out std_logic;
- ddr2_ras_b => tb_ddr2_ras_b, --: out std_logic;
- ddr2_we_b => tb_ddr2_we_b, --: out std_logic;
- ddr2_cke => tb_ddr2_cke, --: out std_logic;
- ddr2_clk_n => tb_ddr2_clk_n, --: out std_logic;
- ddr2_clk_p => tb_ddr2_clk_p, --: out std_logic;
- ddr2_dq => tb_ddr2_dq, --: inout std_logic_vector(15 downto 0);
- ddr2_ldm => tb_ddr2_ldm, --: out std_logic;
- ddr2_udm => tb_ddr2_udm, --: out std_logic;
- ddr2_ldqs_n => tb_ddr2_ldqs_n, --: inout std_logic;
- ddr2_ldqs_p => tb_ddr2_ldqs_p, --: inout std_logic;
- ddr2_udqs_n => tb_ddr2_udqs_n, --: inout std_logic;
- ddr2_udqs_p => tb_ddr2_udqs_p, --: inout std_logic;
- ddr2_odt => tb_ddr2_odt, --: out std_logic;
- --
- -- flash memory
- flash_a => tb_flash_a, --: out std_logic_vector(24 downto 0);
- flash_d => tb_flash_d(7 downto 3), --: inout std_logic_vector( 7 downto 3);
- --
- fpga_d0_din_miso_miso1 => tb_fpga_d0_din_miso_miso1, --: inout std_logic; -- dual use
- fpga_d1_miso2 => tb_fpga_d1_miso2, --: inout std_logic; -- dual use
- fpga_d2_miso3 => tb_fpga_d2_miso3, --: inout std_logic; -- dual use
- flash_we_b => tb_flash_we_b, --: out std_logic;
- flash_oe_b => tb_flash_oe_b, --: out std_logic;
- flash_ce_b => tb_flash_ce_b, --: out std_logic;
- --
- -- FCM connector
- -- M2C Mezzanine to Carrier
- -- C2M Carrier to Mezzanine
- fmc_clk0_m2c_n => tb_fmc_lpc_row_h(5), --: std_logic;
- fmc_clk0_m2c_p => tb_fmc_lpc_row_h(4), --: std_logic;
- fmc_clk1_m2c_n => tb_fmc_lpc_row_g(3), --: std_logic;
- fmc_clk1_m2c_p => tb_fmc_lpc_row_g(2), --: std_logic;
- iic_scl_main => tb_fmc_lpc_row_c(30), --: inout std_logic;
- iic_sda_main => tb_fmc_lpc_row_c(31), --: inout std_logic;
- fmc_la00_cc_n => tb_fmc_lpc_row_g(7), --: std_logic;
- fmc_la00_cc_p => tb_fmc_lpc_row_g(6), --: std_logic;
- fmc_la01_cc_n => tb_fmc_lpc_row_d(9), --: std_logic := 'Z';
- fmc_la01_cc_p => tb_fmc_lpc_row_d(8), --: std_logic := 'Z';
- fmc_la02_n => tb_fmc_lpc_row_h(8), --: std_logic;
- fmc_la02_p => tb_fmc_lpc_row_h(7), --: std_logic;
- fmc_la03_n => tb_fmc_lpc_row_g(10), --: std_logic;
- fmc_la03_p => tb_fmc_lpc_row_g(9), --: std_logic;
- fmc_la04_n => tb_fmc_lpc_row_h(11), --: std_logic;
- fmc_la04_p => tb_fmc_lpc_row_h(10), --: std_logic;
- fmc_la05_n => tb_fmc_lpc_row_d(12), --: std_logic := 'Z';
- fmc_la05_p => tb_fmc_lpc_row_d(11), --: std_logic := 'Z';
- fmc_la06_n => tb_fmc_lpc_row_c(11), --: std_logic := 'Z';
- fmc_la06_p => tb_fmc_lpc_row_c(10), --: std_logic := 'Z';
- fmc_la07_n => tb_fmc_lpc_row_h(14), --: std_logic;
- fmc_la07_p => tb_fmc_lpc_row_h(13), --: std_logic;
- fmc_la08_n => tb_fmc_lpc_row_g(13), --: std_logic;
- fmc_la08_p => tb_fmc_lpc_row_g(12), --: std_logic;
- fmc_la09_n => tb_fmc_lpc_row_d(15), --: std_logic := 'Z';
- fmc_la09_p => tb_fmc_lpc_row_d(14), --: std_logic := 'Z';
- fmc_la10_n => tb_fmc_lpc_row_c(15), --: std_logic := 'Z';
- fmc_la10_p => tb_fmc_lpc_row_c(14), --: std_logic := 'Z';
- fmc_la11_n => tb_fmc_lpc_row_h(17), --: std_logic;
- fmc_la11_p => tb_fmc_lpc_row_h(16), --: std_logic;
- fmc_la12_n => tb_fmc_lpc_row_g(16), --: std_logic := 'Z';
- fmc_la12_p => tb_fmc_lpc_row_g(15), --: std_logic;
- fmc_la13_n => tb_fmc_lpc_row_d(18), --: std_logic := 'Z';
- fmc_la13_p => tb_fmc_lpc_row_d(17), --: std_logic := 'Z';
- fmc_la14_n => tb_fmc_lpc_row_c(19), --: std_logic := 'Z';
- fmc_la14_p => tb_fmc_lpc_row_c(18), --: std_logic := 'Z';
- fmc_la15_n => tb_fmc_lpc_row_h(20), --: std_logic;
- fmc_la15_p => tb_fmc_lpc_row_h(19), --: std_logic;
- fmc_la16_n => tb_fmc_lpc_row_g(19), --: std_logic := 'Z';
- fmc_la16_p => tb_fmc_lpc_row_g(18), --: std_logic := 'Z';
- fmc_la17_cc_n => tb_fmc_lpc_row_d(21), --: std_logic := 'Z';
- fmc_la17_cc_p => tb_fmc_lpc_row_d(20), --: std_logic := 'Z';
- fmc_la18_cc_n => tb_fmc_lpc_row_c(23), --: std_logic := 'Z';
- fmc_la18_cc_p => tb_fmc_lpc_row_c(22), --: std_logic := 'Z';
- fmc_la19_n => tb_fmc_lpc_row_h(23), --: std_logic;
- fmc_la19_p => tb_fmc_lpc_row_h(22), --: std_logic;
- fmc_la20_n => tb_fmc_lpc_row_g(22), --: std_logic := 'Z';
- fmc_la20_p => tb_fmc_lpc_row_g(21), --: std_logic := 'Z';
- fmc_la21_n => tb_fmc_lpc_row_h(26), --: std_logic;
- fmc_la21_p => tb_fmc_lpc_row_h(25), --: std_logic;
- fmc_la22_n => tb_fmc_lpc_row_g(25), --: std_logic := 'Z';
- fmc_la22_p => tb_fmc_lpc_row_g(24), --: std_logic := 'Z';
- fmc_la23_n => tb_fmc_lpc_row_d(24), --: std_logic := 'Z';
- fmc_la23_p => tb_fmc_lpc_row_d(23), --: std_logic := 'Z';
- fmc_la24_n => tb_fmc_lpc_row_h(29), --: std_logic;
- fmc_la24_p => tb_fmc_lpc_row_h(28), --: std_logic;
- fmc_la25_n => tb_fmc_lpc_row_g(28), --: std_logic := 'Z';
- fmc_la25_p => tb_fmc_lpc_row_g(27), --: std_logic := 'Z';
- fmc_la26_n => tb_fmc_lpc_row_d(27), --: std_logic := 'Z';
- fmc_la26_p => tb_fmc_lpc_row_d(26), --: std_logic := 'Z';
- fmc_la27_n => tb_fmc_lpc_row_c(27), --: std_logic := 'Z';
- fmc_la27_p => tb_fmc_lpc_row_c(26), --: std_logic := 'Z';
- fmc_la28_n => tb_fmc_lpc_row_h(32), --: std_logic;
- fmc_la28_p => tb_fmc_lpc_row_h(31), --: std_logic;
- fmc_la29_n => tb_fmc_lpc_row_g(31), --: std_logic := 'Z';
- fmc_la29_p => tb_fmc_lpc_row_g(30), --: std_logic := 'Z';
- fmc_la30_n => tb_fmc_lpc_row_h(35), --: std_logic;
- fmc_la30_p => tb_fmc_lpc_row_h(34), --: std_logic := 'Z';
- fmc_la31_n => tb_fmc_lpc_row_g(34), --: std_logic := 'Z';
- fmc_la31_p => tb_fmc_lpc_row_g(33), --: std_logic := 'Z';
- fmc_la32_n => tb_fmc_lpc_row_h(38), --: std_logic;
- fmc_la32_p => tb_fmc_lpc_row_h(37), --: std_logic;
- fmc_la33_n => tb_fmc_lpc_row_g(37), --: std_logic := 'Z';
- fmc_la33_p => tb_fmc_lpc_row_g(36), --: std_logic := 'Z';
- fmc_prsnt_m2c_l => tb_fmc_prsnt_m2c_l, --: std_logic;
- FMC_PWR_GOOD_FLASH_RST_B => tb_FMC_PWR_GOOD_FLASH_RST_B, --: out std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
- --
- -- ???
- FPGA_AWAKE => tb_FPGA_AWAKE, --: out std_logic;
- FPGA_CCLK => tb_FPGA_CCLK, --: in std_logic;
- FPGA_CMP_CLK => tb_FPGA_CMP_CLK, --: in std_logic;
- FPGA_CMP_CS_B => tb_FPGA_CMP_CS_B, --: in std_logic;
- FPGA_CMP_MOSI => tb_FPGA_CMP_MOSI, --: in std_logic;
- --
- FPGA_HSWAPEN => tb_FPGA_HSWAPEN, --: in std_logic;
- FPGA_INIT_B => tb_FPGA_INIT_B, --: out std_logic;
- FPGA_M0_CMP_MISO => tb_FPGA_M0_CMP_MISO, --: in std_logic;
- FPGA_M1 => tb_FPGA_M1, --: in std_logic;
- FPGA_MOSI_CSI_B_MISO0 => tb_FPGA_MOSI_CSI_B_MISO0, --: in std_logic;
- FPGA_ONCHIP_TERM1 => tb_FPGA_ONCHIP_TERM1, --: inout std_logic;
- FPGA_ONCHIP_TERM2 => tb_FPGA_ONCHIP_TERM2, --: inout std_logic;
- FPGA_VTEMP => tb_FPGA_VTEMP, --: in std_logic;
- --
- -- GPIOs
- gpio_button => tb_gpio_button, --: in std_logic_vector(3 downto 0); -- active high
- gpio_header_ls => tb_gpio_header_ls, --: inout std_logic_vector(7 downto 0);
- gpio_led => tb_gpio_led, --: out std_logic_vector(3 downto 0);
- gpio_switch => tb_gpio_switch, --: in std_logic_vector(3 downto 0); -- active high
- --
- -- Ethernet Gigabit PHY
- PHY_COL => tb_PHY_COL, --: in std_logic;
- PHY_CRS => tb_PHY_CRS, --: in std_logic;
- PHY_INT => tb_PHY_INT, --: out std_logic;
- PHY_MDC => tb_PHY_MDC, --: out std_logic;
- PHY_MDIO => tb_PHY_MDIO, --: inout std_logic;
- PHY_RESET => tb_PHY_RESET, --: out std_logic;
- PHY_RXCLK => tb_PHY_RXCLK, --: in std_logic;
- PHY_RXCTL_RXDV => tb_PHY_RXCTL_RXDV, --: in std_logic;
- PHY_RXD => tb_PHY_RXD, --: in std_logic_vector(7 downto 0);
- PHY_RXER => tb_PHY_RXER, --: in std_logic;
- PHY_TXCLK => tb_PHY_TXCLK, --: in std_logic;
- PHY_TXCTL_TXEN => tb_PHY_TXCTL_TXEN, --: out std_logic;
- PHY_TXC_GTXCLK => tb_PHY_TXC_GTXCLK, --: out std_logic;
- PHY_TXD => tb_PHY_TXD, --: out std_logic_vector(7 downto 0);
- PHY_TXER => tb_PHY_TXER, --: out std_logic;
- --
- --
- SPI_CS_B => tb_SPI_CS_B, --: in std_logic;
- --
- -- 200 MHz oscillator
- SYSCLK_N => tb_sysclk_n, --: in std_logic;
- SYSCLK_P => tb_sysclk_p, --: in std_logic;
- --
- -- RS232 via USB
- usb_1_cts => tb_usb_1_cts, --: out std_logic;
- usb_1_rts => tb_usb_1_rts, --: in std_logic;
- usb_1_rx => tb_usb_1_rx, --: out std_logic;
- usb_1_tx => tb_usb_1_tx, --: in std_logic;
- --
- -- 27 MHz, oscillator socket
- user_clock => tb_user_clock, --: in std_logic;
- user_sma_clock_p => tb_user_sma_clock_p, --: inout std_logic;
- user_sma_clock_n => tb_user_sma_clock_n --: inout std_logic;
- );
-
-
-
- -- ethernet phy signals
- tb_phy_mdio <= 'H'; -- pullup
- tb_phy_txclk <= 'H'; -- : out std_logic;
- tb_phy_rxclk <= 'H'; -- : out std_logic;
- tb_phy_rxd <= (others => 'H'); -- : out std_logic_vector(7 downto 0);
- tb_phy_rxctl_rxdv <= 'H'; -- : out std_logic;
- tb_phy_rxer <= 'H'; -- : out std_logic;
- tb_phy_col <= 'H'; -- : out std_logic;
- tb_phy_crs <= 'H'; -- : out std_logic;
-
-
- -- predefined connections on fmc connector
- -- X - power, 0 - gnd, U - unknown signal
- -- row c
- tb_fmc_lpc_row_c(1) <= gnd;
- tb_fmc_lpc_row_c(2) <= 'U';
- tb_fmc_lpc_row_c(3) <= 'U';
- tb_fmc_lpc_row_c(4) <= gnd;
- tb_fmc_lpc_row_c(5) <= gnd;
- tb_fmc_lpc_row_c(6) <= 'U';
- tb_fmc_lpc_row_c(7) <= 'U';
- tb_fmc_lpc_row_c(8) <= gnd;
- tb_fmc_lpc_row_c(9) <= gnd;
- tb_fmc_lpc_row_c(12) <= gnd;
- tb_fmc_lpc_row_c(13) <= gnd;
- tb_fmc_lpc_row_c(16) <= gnd;
- tb_fmc_lpc_row_c(17) <= gnd;
- tb_fmc_lpc_row_c(20) <= gnd;
- tb_fmc_lpc_row_c(21) <= gnd;
- tb_fmc_lpc_row_c(24) <= gnd;
- tb_fmc_lpc_row_c(25) <= gnd;
- tb_fmc_lpc_row_c(28) <= gnd;
- tb_fmc_lpc_row_c(29) <= gnd;
- tb_fmc_lpc_row_c(30) <= tb_iic_scl_main;
- tb_fmc_lpc_row_c(31) <= tb_iic_sda_main;
- tb_fmc_lpc_row_c(32) <= gnd;
- tb_fmc_lpc_row_c(33) <= gnd;
- tb_fmc_lpc_row_c(34) <= 'U';
- tb_fmc_lpc_row_c(35) <= 'X';
- tb_fmc_lpc_row_c(36) <= gnd;
- tb_fmc_lpc_row_c(37) <= 'X';
- tb_fmc_lpc_row_c(38) <= gnd;
- tb_fmc_lpc_row_c(39) <= 'X';
- tb_fmc_lpc_row_c(40) <= gnd;
- -- row d
- tb_fmc_lpc_row_d(2) <= gnd;
- tb_fmc_lpc_row_d(3) <= gnd;
- tb_fmc_lpc_row_d(4) <= 'U';
- tb_fmc_lpc_row_d(5) <= 'U';
- tb_fmc_lpc_row_d(6) <= gnd;
- tb_fmc_lpc_row_d(7) <= gnd;
- tb_fmc_lpc_row_d(10) <= gnd;
- tb_fmc_lpc_row_d(13) <= gnd;
- tb_fmc_lpc_row_d(16) <= gnd;
- tb_fmc_lpc_row_d(19) <= gnd;
- tb_fmc_lpc_row_d(22) <= gnd;
- tb_fmc_lpc_row_d(25) <= gnd;
- tb_fmc_lpc_row_d(28) <= gnd;
- tb_fmc_lpc_row_d(29) <= 'U';
- tb_fmc_lpc_row_d(30) <= 'U';
- tb_fmc_lpc_row_d(31) <= 'U';
- tb_fmc_lpc_row_d(32) <= 'X';
- tb_fmc_lpc_row_d(33) <= 'U';
- tb_fmc_lpc_row_d(34) <= 'U';
- tb_fmc_lpc_row_d(35) <= 'U';
- tb_fmc_lpc_row_d(36) <= 'X';
- tb_fmc_lpc_row_d(37) <= gnd;
- tb_fmc_lpc_row_d(38) <= 'X';
- tb_fmc_lpc_row_d(39) <= gnd;
- tb_fmc_lpc_row_d(40) <= 'X';
- -- row g
- tb_fmc_lpc_row_g(1) <= gnd;
- tb_fmc_lpc_row_g(4) <= gnd;
- tb_fmc_lpc_row_g(5) <= gnd;
- tb_fmc_lpc_row_g(8) <= gnd;
- tb_fmc_lpc_row_g(11) <= gnd;
- tb_fmc_lpc_row_g(14) <= gnd;
- tb_fmc_lpc_row_g(17) <= gnd;
- tb_fmc_lpc_row_g(20) <= gnd;
- tb_fmc_lpc_row_g(23) <= gnd;
- tb_fmc_lpc_row_g(26) <= gnd;
- tb_fmc_lpc_row_g(29) <= gnd;
- tb_fmc_lpc_row_g(32) <= gnd;
- tb_fmc_lpc_row_g(35) <= gnd;
- tb_fmc_lpc_row_g(38) <= gnd;
- tb_fmc_lpc_row_g(39) <= 'X';
- tb_fmc_lpc_row_g(40) <= gnd;
- -- row h
- tb_fmc_lpc_row_h(1) <= 'X';
- tb_fmc_lpc_row_h(3) <= gnd;
- tb_fmc_lpc_row_h(6) <= gnd;
- tb_fmc_lpc_row_h(9) <= gnd;
- tb_fmc_lpc_row_h(12) <= gnd;
- tb_fmc_lpc_row_h(15) <= gnd;
- tb_fmc_lpc_row_h(18) <= gnd;
- tb_fmc_lpc_row_h(21) <= gnd;
- tb_fmc_lpc_row_h(24) <= gnd;
- tb_fmc_lpc_row_h(27) <= gnd;
- tb_fmc_lpc_row_h(30) <= gnd;
- tb_fmc_lpc_row_h(33) <= gnd;
- tb_fmc_lpc_row_h(36) <= gnd;
- tb_fmc_lpc_row_h(39) <= gnd;
- tb_fmc_lpc_row_h(40) <= 'X';
-
-
- main: process
- begin
-
- wait for 2 ms;
- simulation_run <= false;
- report "Simlation ended." severity note;
- wait;
-
- end process;
-
-
-end architecture testbench;
diff --git a/test_rrobin_problem/simulation/Makefile b/test_rrobin_problem/simulation/Makefile
deleted file mode 100644
index 9ed290d..0000000
--- a/test_rrobin_problem/simulation/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/hardware/board_sp605/simulation/Makefile $
-# $Date$
-# $Author$
-# $Revision$
-#
-
-library = test_rrobin
-top = top_tb
-
-software_dir = ../software
-
-
-# http://sourceforge.net/projects/vmk/
-VMK = vmk
-
-# generate list of used libs
-library_list = $(shell cut --field 1 --delimiter=" " --only-delimited vhdl_files.txt | grep --invert "\#" | sort --unique)
-
-
-all: compile simulate
-
-
-software:
- test ! -d $(software_dir) || make --directory $(software_dir) | ccze -A
-
-compile: Makefile.msim
- export ANAFLAGS="-quiet -2008"; \
- make -f Makefile.msim | ccze -A
-
-
-simulate:
- export top=$(top); \
- vsim -quiet -gui $(library).$(top) -do run.do -l transcript.log
-
-
-clean:
- @# modelsim stuff
- rm -f transcript.log
- rm -f *.wlf
- rm -f wlf*
- @# vmk stuff
- -make -f Makefile.msim clean
- rm -f Makefile.msim
- rm -rf $(library_list)
-
-
-# generate Makefile.msim with vmk
-Makefile.msim: software vhdl_files.txt $(library_list)
- $(VMK) -t modelsim -O -w $(library) -F vhdl_files.txt
-
-$(library_list):
- vlib $@
-
-
diff --git a/test_rrobin_problem/simulation/run.do b/test_rrobin_problem/simulation/run.do
deleted file mode 100644
index 36d1969..0000000
--- a/test_rrobin_problem/simulation/run.do
+++ /dev/null
@@ -1,71 +0,0 @@
-
-#
-# helper functions
-#
-
-
-# neues Spiel, neues Glueck
-proc nsng {} {
-
- restart -f
- global StdArithNoWarnings
- global NumericStdNoWarnings
- set StdArithNoWarnings 1
- set NumericStdNoWarnings 1
-
- when -label enable_Warn {reset == '0'} {echo "Enable Warnings" ; set StdArithNoWarnings 0 ; set NumericStdNoWarnings 0 ;}
-
- run -all
-}
-
-
-proc r {} {
- restart -f
- run -all
-}
-
-
-# restart with clear
-proc rc {} {
- .main clear
- r
-}
-
-
-
-proc my_debug {} {
- global env
- foreach key [array names env] {
- puts "$key=$env($key)"
- }
-}
-
-
-proc e {} {
- exit -force
-}
-
-proc x {} {
- exit -force
-}
-
-
-
-
-# get env variables
-global env
-quietly set top $env(top)
-
-
-if {[file exists wave_$top.do]} {
- do wave_$top.do
-} else {
- if {[file exists wave.do]} {
- do wave.do
- } else {
- puts "INFO: no wave file found."
- }
-}
-
-
-run -all
diff --git a/test_rrobin_problem/simulation/vhdl_files.txt b/test_rrobin_problem/simulation/vhdl_files.txt
deleted file mode 100644
index d2f9c6f..0000000
--- a/test_rrobin_problem/simulation/vhdl_files.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-test_rrobin ../rtl/led_control_ahb.vhd
-test_rrobin ../rtl/box.vhd
-test_rrobin ../rtl/top.vhd
-test_rrobin ../rtl_tb/top_tb.vhd
-hzdr ../../hzdr/rtl/devices_hzdr.vhd
-grlib ../../grlib/rtl/ahbctrl.vhd
-grlib ../../grlib/rtl/amba.vhd
-grlib ../../grlib/rtl/apbctrl.vhd
-grlib ../../grlib/rtl/devices.vhd
-grlib ../../grlib/rtl/config.vhd
-grlib ../../grlib/rtl/util.vhd
-grlib ../../grlib/rtl/testlib.vhd
-grlib ../../grlib/rtl/stdlib.vhd
-grlib ../../grlib/rtl/version.vhd
-grlib ../../grlib/rtl_tb/stdio.vhd
-techmap ../../techmap/rtl/gencomp.vhd
-gaisler ../../gaisler/rtl/apbuart.vhd
-gaisler ../../gaisler/rtl/grgpio.vhd
-gaisler ../../gaisler/rtl/grgpreg.vhd
-gaisler ../../gaisler/rtl/misc.vhd
-gaisler ../../gaisler/rtl/net.vhd
-gaisler ../../gaisler/rtl/uart.vhd
diff --git a/test_rrobin_problem/simulation/wave.do b/test_rrobin_problem/simulation/wave.do
deleted file mode 100644
index 7ba2647..0000000
--- a/test_rrobin_problem/simulation/wave.do
+++ /dev/null
@@ -1,27 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /top_tb/top_i0/box_i0/clk
-add wave -noupdate /top_tb/top_i0/box_i0/ahbctrl_i0/msto(0).hbusreq
-add wave -noupdate /top_tb/top_i0/box_i0/ahbctrl_i0/msto(1).hbusreq
-add wave -noupdate -divider ahbctrl
-add wave -noupdate -expand /top_tb/top_i0/box_i0/ahbctrl_i0/msti.hgrant
-add wave -noupdate /top_tb/top_i0/box_i0/ahbctrl_i0/msti.hready
-add wave -noupdate -divider gpio
-add wave -noupdate -expand /top_tb/top_i0/gpio_led
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {64180831 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {1840927 ps}
diff --git a/test_rrobin_problem/synthesis/Makefile b/test_rrobin_problem/synthesis/Makefile
deleted file mode 100644
index 9aa0be7..0000000
--- a/test_rrobin_problem/synthesis/Makefile
+++ /dev/null
@@ -1,205 +0,0 @@
-#
-# $Date$
-# $Author$
-# $Revision$
-#
-
-MODULE = top
-SPEEDGRADE = 2
-DEVICE = xc6slx16-csg324-$(SPEEDGRADE)
-UCF_FILE = sp601.ucf
-CORES = ../cores/
-SOFTWARE = ../software
-BMM_FILE = zpu_i0_memory_64k.bmm
-
-BUILDDIR = isebuild
-DATE = $(shell date +"%Y-%m-%d__%H_%M")
-LOGFILE = synthesis_log_$(DATE).txt
-export XST_LOGFILE := $(LOGFILE)
-
-
-all:
- @echo "check - look for timing and other synthesis issues"
- @echo "xst - generate ngc file (netlist, replaces edif and netlist constrains)"
- @echo "translate - generate ngd file (native generic database [reduced to primitives])"
- @echo "map - generate ncd file (native ciruit description)"
- @echo "par - place&route ncd file (design implementation)"
- @echo "trace - generate timing report"
- @echo "bitgen - generate bit file (ncd -> bit)"
- @echo "update - update bitstream with elf file"
- @echo "program - program fpga with bit file"
- @echo "genmcs - genrate mcs file"
- @echo "progspi - program spi flash with mcs file"
- @echo "clean"
- @echo "..."
- @echo "testflow - update bitgen update program check"
- @echo "finalflow - update bitgen update progspi check"
-
-testflow:
- time $(MAKE) software bitgen update program check 2>&1 | tee $(XST_LOGFILE)
-
-finalflow:
- time $(MAKE) software bitgen update progspi check 2>&1 | tee $(XST_LOGFILE)
-
-
-check:
- @echo -e "Timing score: "
- @grep --with-filename "Timing Score" $(BUILDDIR)/*.par
- @echo -e "\nUnwanted Latches (737): "
- @grep --with-filename "WARNING:Xst:737" $(BUILDDIR)/*.syr || echo -n
- @echo -e "\nUnassigned signals (653): "
- @grep --with-filename "WARNING:Xst:653" $(BUILDDIR)/*.syr || echo -n
- @echo -e "\nInternal tristates (2042): "
- @grep --with-filename "WARNING:Xst:2042" $(BUILDDIR)/*.syr || echo -n
- @echo -e "\nCombinatoric loops (2170): "
- @grep --with-filename "WARNING:Xst:2170" $(BUILDDIR)/*.syr || echo -n
- @echo -e "\nGated clocks (372): "
- @grep --with-filename "WARNING:PhysDesignRules:372" $(BUILDDIR)/*.bgn || echo -n
-
-
-software:
- ###
- #############################################################################
- ### (re)compile software
- ###
- test ! -d $(SOFTWARE) || make all --directory $(SOFTWARE)
-
-
-update: $(BUILDDIR)/$(MODULE).bit
- ###
- #############################################################################
- ### update the bitfile
- ###
- test ! -d $(SOFTWARE) || data2mem -bm $(BMM_FILE) -bd $(SOFTWARE)/*.elf -bt $(BUILDDIR)/$(MODULE).bit -o b $(MODULE)_update.bit
- test -d $(SOFTWARE) || cp $(BUILDDIR)/$(MODULE).bit $(MODULE)_update.bit
-
-
-program:
- ###
- #############################################################################
- ### configure FPGA
- ###
- impact -batch program_fpga.cmd
-
-
-genmcs: $(MODULE)_update.mcs
-
-$(MODULE)_update.mcs: $(MODULE)_update.bit
- ###
- #############################################################################
- ### generate flash file
- ###
- promgen -spi -p mcs -w -o $(MODULE)_update.mcs -s 8192 -u 0 $(MODULE)_update.bit
-
-
-progspi: genmcs
- ###
- #############################################################################
- ### program flash
- ###
- impact -batch program_spi.cmd
-
-
-clean:
- rm -f $(MODULE).prj
- rm -f *.log
- rm -f _impact.cmd
- rm -f *.cfi
- rm -f *.prm
- rm -rf $(BUILDDIR)
-
-
-dir: $(MODULE).prj
- ###
- #############################################################################
- ### generate build directory
- ###
- mkdir -p $(BUILDDIR)
- mkdir -p $(BUILDDIR)/projnav.tmp
-
-
-
-$(MODULE).prj: ../simulation/vhdl_files.txt
- ###
- #############################################################################
- ### generate project file
- ###
- grep --invert rtl_tb ../simulation/vhdl_files.txt | grep --invert "\#" | grep --invert "^$$" | awk '{printf "vhdl %s %s\n",$$1,$$2}' > $(MODULE).prj
-
-
-xst: $(MODULE).ngc
-translate: $(MODULE).ngd
-map: $(MODULE)_map.ncd
-par: $(MODULE).ncd
-
-
-hw_timestamp:
- ###
- #############################################################################
- #### update hw timestamp
- ###
- test ! -f ../rtl/Makefile || make --directory ../rtl
-
-$(MODULE).ngc: dir hw_timestamp
- ###
- #############################################################################
- ### synthesis
- ###
- cd $(BUILDDIR) ; xst -ifn ../$(MODULE).xst -ofn $(MODULE).syr
-
-
-$(MODULE).ngd: $(MODULE).ngc $(UCF_FILE)
- ###
- #############################################################################
- ### translate
- ###
- cd $(BUILDDIR) ; ngdbuild -dd _ngo -nt timestamp -uc ../$(UCF_FILE) -p $(DEVICE) -sd ../$(CORES) $(MODULE).ngc $(MODULE).ngd
-
-$(MODULE)_map.ncd: $(MODULE).ngd
- ###
- #############################################################################
- ### map
- ###
- @# explanation of map parameters:
- @# -p part number
- @# -mt multi-threading
- @# -w overwrite existing files
- @# -logic_opt logic optimization
- @# -ol overall effor level (std|high)
- @# -t placer cost table
- @# -xt extra placer cost table
- @# -register_duplication duplicate registers
- @# -global_opt Global Optimization (off|speed|area|power)
- @# -ir ignore RLOCs
- @# -pr pack registers in IO (off|i|o|b)
- @# -lc lut combining (auto|area|off)
- @# -power Virtex 6 Power Optimization (on|off|high|xe)
- @# -detail Generate Detailed MAP Report
- @# -o Output File Name
- @# -bp enables block RAM mapping
- cd $(BUILDDIR) ; export XIL_PAR_DESIGN_CHECK_VERBOSE=1; map -p $(DEVICE) -mt 2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -ir off -pr off -lc off -power off -detail -o $(MODULE)_map.ncd $(MODULE).ngd $(MODULE).pcf
-
-
-$(MODULE).ncd: $(MODULE)_map.ncd
- ###
- #############################################################################
- ### place & route
- ###
- cd $(BUILDDIR) ; par -w -mt 4 -ol high $(MODULE)_map.ncd $(MODULE).ncd $(MODULE).pcf
-
-
-trace:
- cd $(BUILDDIR) ; trce -e -a -u 100 -s $(SPEEDGRADE) -xml $(MODULE).twx $(MODULE).ncd -o $(MODULE).twr $(MODULE).pcf
-
-tracefast:
- cd $(BUILDDIR) ; trce -v 12 -u 100 -s $(SPEEDGRADE) -fastpaths -xml $(MODULE).twx -o $(MODULE).twr $(MODULE).ncd $(MODULE).pcf
-
-
-bitgen: $(MODULE).ncd
- ###
- #############################################################################
- ### generate bitfile
- ###
- cd $(BUILDDIR) ; bitgen -f ../$(MODULE).ut $(MODULE).ncd
-
-
diff --git a/test_rrobin_problem/synthesis/program_fpga.cmd b/test_rrobin_problem/synthesis/program_fpga.cmd
deleted file mode 100644
index e025d0a..0000000
--- a/test_rrobin_problem/synthesis/program_fpga.cmd
+++ /dev/null
@@ -1,8 +0,0 @@
-setMode -bscan
-#setCable -port auto
-setCable -port usb21
-Identify
-assignFile -p 1 -file "top_update.bit"
-Program -p 1
-closeCable
-quit
diff --git a/test_rrobin_problem/synthesis/program_spi.cmd b/test_rrobin_problem/synthesis/program_spi.cmd
deleted file mode 100644
index c6fcbc0..0000000
--- a/test_rrobin_problem/synthesis/program_spi.cmd
+++ /dev/null
@@ -1,9 +0,0 @@
-setMode -bs
-setCable -port auto
-Identify -inferir
-identifyMPM
-attachflash -position 1 -spi "W25Q64BV"
-assignfiletoattachedflash -position 1 -file "top_update.mcs"
-Program -p 1 -dataWidth 4 -spionly -e -v -loadfpga
-closeCable
-quit
diff --git a/test_rrobin_problem/synthesis/sp601.ucf b/test_rrobin_problem/synthesis/sp601.ucf
deleted file mode 100644
index 90a9d07..0000000
--- a/test_rrobin_problem/synthesis/sp601.ucf
+++ /dev/null
@@ -1,372 +0,0 @@
-
-############################################################
-# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/hardware/board_sp601/rtl/teilerregister.vhd $
-# $Date$
-# $Author$
-# $Revision$
-
-
-############################################################
-# SPARTAN-6 SP601 BOARD CONSTRAINTS FILE
-#
-# Bank Voltage
-# Bank 0: 2.5 V
-# Bank 1: 2.5 V
-# Bank 2: 2.5 V
-# Bank 3: 1.8 V
-# VCCAUX: 2.5 V
-
-# following pins are connected to VCC1V8/2:
-# N3, M5, C1
-
-
-############################################################
-## clock specialities
-############################################################
-#
-# separete VGA clock from system clock
-# no VGA -> no VGA clk
-#NET "clk_driver_b.dcm_sp_i0_clkfx" TNM_NET = "clkfx";
-#NET "clk_driver_b.dcm_sp_i0_clkdv" TNM_NET = "clkdv";
-#TIMESPEC "TS_clkfx_clkdv" = FROM "clkfx" to "clkdv" TIG;
-
-
-
-
-############################################################
-## placement constraints
-############################################################
-
-### internal memory for zpu 8x4 bit = 32 bit width
-### zpu_core_small
-#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram1" AREA_GROUP = "ZPU_MEM1" ;
-#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram2" AREA_GROUP = "ZPU_MEM2" ;
-#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram3" AREA_GROUP = "ZPU_MEM3" ;
-#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram4" AREA_GROUP = "ZPU_MEM4" ;
-#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram5" AREA_GROUP = "ZPU_MEM5" ;
-#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram6" AREA_GROUP = "ZPU_MEM6" ;
-#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram7" AREA_GROUP = "ZPU_MEM7" ;
-#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram8" AREA_GROUP = "ZPU_MEM8" ;
-
-### zpu_core_medium
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram1" AREA_GROUP = "ZPU_MEM1" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram2" AREA_GROUP = "ZPU_MEM2" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram3" AREA_GROUP = "ZPU_MEM3" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram4" AREA_GROUP = "ZPU_MEM4" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram5" AREA_GROUP = "ZPU_MEM5" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram6" AREA_GROUP = "ZPU_MEM6" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram7" AREA_GROUP = "ZPU_MEM7" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram8" AREA_GROUP = "ZPU_MEM8" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram9" AREA_GROUP = "ZPU_MEM9" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram10" AREA_GROUP = "ZPU_MEM10" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram11" AREA_GROUP = "ZPU_MEM11" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram12" AREA_GROUP = "ZPU_MEM12" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram13" AREA_GROUP = "ZPU_MEM13" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram14" AREA_GROUP = "ZPU_MEM14" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram15" AREA_GROUP = "ZPU_MEM15" ;
-#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram16" AREA_GROUP = "ZPU_MEM16" ;
-
-### planahead has problems with "" around range
-AREA_GROUP "ZPU_MEM1" RANGE = RAMB16_X0Y14:RAMB16_X0Y14 ;
-AREA_GROUP "ZPU_MEM2" RANGE = RAMB16_X0Y12:RAMB16_X0Y12 ;
-AREA_GROUP "ZPU_MEM3" RANGE = RAMB16_X0Y10:RAMB16_X0Y10 ;
-AREA_GROUP "ZPU_MEM4" RANGE = RAMB16_X0Y8:RAMB16_X0Y8 ;
-AREA_GROUP "ZPU_MEM5" RANGE = RAMB16_X0Y6:RAMB16_X0Y6 ;
-AREA_GROUP "ZPU_MEM6" RANGE = RAMB16_X0Y4:RAMB16_X0Y4 ;
-AREA_GROUP "ZPU_MEM7" RANGE = RAMB16_X0Y2:RAMB16_X0Y2 ;
-AREA_GROUP "ZPU_MEM8" RANGE = RAMB16_X0Y0:RAMB16_X0Y0 ;
-AREA_GROUP "ZPU_MEM9" RANGE = RAMB16_X1Y14:RAMB16_X1Y14 ;
-AREA_GROUP "ZPU_MEM10" RANGE = RAMB16_X1Y12:RAMB16_X1Y12 ;
-AREA_GROUP "ZPU_MEM11" RANGE = RAMB16_X1Y10:RAMB16_X1Y10 ;
-AREA_GROUP "ZPU_MEM12" RANGE = RAMB16_X1Y8:RAMB16_X1Y8 ;
-AREA_GROUP "ZPU_MEM13" RANGE = RAMB16_X1Y6:RAMB16_X1Y6 ;
-AREA_GROUP "ZPU_MEM14" RANGE = RAMB16_X1Y4:RAMB16_X1Y4 ;
-AREA_GROUP "ZPU_MEM15" RANGE = RAMB16_X1Y2:RAMB16_X1Y2 ;
-AREA_GROUP "ZPU_MEM16" RANGE = RAMB16_X1Y0:RAMB16_X1Y0 ;
-
-
-
-############################################################
-## pin constraints
-############################################################
-
-
-NET "CPU_RESET" LOC = "N4";
-##
-## 128 MB DDR2 Component Memory
-NET "DDR2_A<12>" LOC ="G6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<11>" LOC ="D3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<10>" LOC ="F4"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<9>" LOC ="D1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<8>" LOC ="D2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<7>" LOC ="H6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<6>" LOC ="H3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<5>" LOC ="H4"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<4>" LOC ="F3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<3>" LOC ="L7"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<2>" LOC ="H5"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<1>" LOC ="J6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<0>" LOC ="J7"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<15>" LOC ="U1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<14>" LOC ="U2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<13>" LOC ="T1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<12>" LOC ="T2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<11>" LOC ="N1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<10>" LOC ="N2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<9>" LOC ="M1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<8>" LOC ="M3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<7>" LOC ="J1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<6>" LOC ="J3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<5>" LOC ="H1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<4>" LOC ="H2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<3>" LOC ="K1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<2>" LOC ="K2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<1>" LOC ="L1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<0>" LOC ="L2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_WE_B" LOC ="E3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_UDQS_P" LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_UDQS_N" LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_UDM" LOC ="K4"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_RAS_B" LOC ="L5"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_ODT" LOC ="K6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_LDQS_P" LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_LDQS_N" LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_LDM" LOC ="K3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_CLK_P" LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_CLK_N" LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_CKE" LOC ="H7"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_CAS_B" LOC ="K5"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_BA<2>" LOC ="E1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_BA<1>" LOC ="F1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_BA<0>" LOC ="F2"; # | IOSTANDARD = SSTL18_II ;
-##
-##
-NET "FLASH_A<0>" LOC = "K18";
-NET "FLASH_A<1>" LOC = "K17";
-NET "FLASH_A<2>" LOC = "J18";
-NET "FLASH_A<3>" LOC = "J16";
-NET "FLASH_A<4>" LOC = "G18";
-NET "FLASH_A<5>" LOC = "G16";
-NET "FLASH_A<6>" LOC = "H16";
-NET "FLASH_A<7>" LOC = "H15";
-NET "FLASH_A<8>" LOC = "H14";
-NET "FLASH_A<9>" LOC = "H13";
-NET "FLASH_A<10>" LOC = "F18";
-NET "FLASH_A<11>" LOC = "F17";
-NET "FLASH_A<12>" LOC = "K13";
-NET "FLASH_A<13>" LOC = "K12";
-NET "FLASH_A<14>" LOC = "E18";
-NET "FLASH_A<15>" LOC = "E16";
-NET "FLASH_A<16>" LOC = "G13";
-NET "FLASH_A<17>" LOC = "H12";
-NET "FLASH_A<18>" LOC = "D18";
-NET "FLASH_A<19>" LOC = "D17";
-NET "FLASH_A<20>" LOC = "G14";
-NET "FLASH_A<21>" LOC = "F14";
-NET "FLASH_A<22>" LOC = "C18";
-NET "FLASH_A<23>" LOC = "C17";
-NET "FLASH_A<24>" LOC = "F16";
-NET "FLASH_CE_B" LOC = "L17";
-#NET "FLASH_D<0>" LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;
-#NET "FLASH_D<1>" LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;
-#NET "FLASH_D<2>" LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<3>" LOC = "U5" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<4>" LOC = "V5" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<5>" LOC = "R3" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<6>" LOC = "T3" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<7>" LOC = "R5" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_OE_B" LOC = "L18";
-NET "FLASH_WE_B" LOC = "M16";
-
-# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)
-NET "FMC_CLK0_M2C_N" LOC = "A10";
-NET "FMC_CLK0_M2C_P" LOC = "C10";
-NET "FMC_CLK1_M2C_N" LOC = "V9" ;
-NET "FMC_CLK1_M2C_P" LOC = "T9" ;
-NET "FMC_LA00_CC_N" LOC = "C9" ;
-NET "FMC_LA00_CC_P" LOC = "D9" ;
-NET "FMC_LA01_CC_N" LOC = "C11" | TNM_NET = "ADC_CLK";
-NET "FMC_LA01_CC_P" LOC = "D11" | TNM_NET = "ADC_CLK";
-TIMESPEC "TS_ADC_CLK" = PERIOD "ADC_CLK" 52 MHz HIGH 50 %;
-NET "FMC_LA02_N" LOC = "A15";
-NET "FMC_LA02_P" LOC = "C15";
-NET "FMC_LA03_N" LOC = "A13";
-NET "FMC_LA03_P" LOC = "C13";
-NET "FMC_LA04_N" LOC = "A16";
-NET "FMC_LA04_P" LOC = "B16";
-NET "FMC_LA05_N" LOC = "A14";
-NET "FMC_LA05_P" LOC = "B14";
-NET "FMC_LA06_N" LOC = "C12";
-NET "FMC_LA06_P" LOC = "D12";
-NET "FMC_LA07_N" LOC = "E8" ;
-NET "FMC_LA07_P" LOC = "E7" ;
-NET "FMC_LA08_N" LOC = "E11";
-NET "FMC_LA08_P" LOC = "F11";
-NET "FMC_LA09_N" LOC = "F10";
-NET "FMC_LA09_P" LOC = "G11";
-NET "FMC_LA10_N" LOC = "C8" ;
-NET "FMC_LA10_P" LOC = "D8" ;
-NET "FMC_LA11_N" LOC = "A12";
-NET "FMC_LA11_P" LOC = "B12";
-NET "FMC_LA12_N" LOC = "C6" ;
-NET "FMC_LA12_P" LOC = "D6" ;
-NET "FMC_LA13_N" LOC = "A11";
-NET "FMC_LA13_P" LOC = "B11";
-NET "FMC_LA14_N" LOC = "A2" ;
-NET "FMC_LA14_P" LOC = "B2" ;
-NET "FMC_LA15_N" LOC = "F9" ;
-NET "FMC_LA15_P" LOC = "G9" ;
-NET "FMC_LA16_N" LOC = "A7" ;
-NET "FMC_LA16_P" LOC = "C7" ;
-NET "FMC_LA17_CC_N" LOC = "T8" ;
-NET "FMC_LA17_CC_P" LOC = "R8" ;
-NET "FMC_LA18_CC_N" LOC = "T10";
-NET "FMC_LA18_CC_P" LOC = "R10";
-NET "FMC_LA19_N" LOC = "P7" ;
-NET "FMC_LA19_P" LOC = "N6" ;
-NET "FMC_LA20_N" LOC = "P8" ;
-NET "FMC_LA20_P" LOC = "N7" ;
-NET "FMC_LA21_N" LOC = "V4" ;
-NET "FMC_LA21_P" LOC = "T4" ;
-NET "FMC_LA22_N" LOC = "T7" ;
-NET "FMC_LA22_P" LOC = "R7" ;
-NET "FMC_LA23_N" LOC = "P6" ;
-NET "FMC_LA23_P" LOC = "N5" ;
-NET "FMC_LA24_N" LOC = "V8" ;
-NET "FMC_LA24_P" LOC = "U8" ;
-NET "FMC_LA25_N" LOC = "N11";
-NET "FMC_LA25_P" LOC = "M11";
-NET "FMC_LA26_N" LOC = "V7" ;
-NET "FMC_LA26_P" LOC = "U7" ;
-NET "FMC_LA27_N" LOC = "T11";
-NET "FMC_LA27_P" LOC = "R11";
-NET "FMC_LA28_N" LOC = "V11";
-NET "FMC_LA28_P" LOC = "U11";
-NET "FMC_LA29_N" LOC = "N8" ;
-NET "FMC_LA29_P" LOC = "M8" ;
-NET "FMC_LA30_N" LOC = "V12";
-NET "FMC_LA30_P" LOC = "T12";
-NET "FMC_LA31_N" LOC = "V6" ;
-NET "FMC_LA31_P" LOC = "T6" ;
-NET "FMC_LA32_N" LOC = "V15";
-NET "FMC_LA32_P" LOC = "U15";
-NET "FMC_LA33_N" LOC = "N9" ;
-NET "FMC_LA33_P" LOC = "M10";
-NET "FMC_PRSNT_M2C_L" LOC = "U13";
-NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
-
-
-NET "FPGA_AWAKE" LOC = "P15"| SLEW = SLOW | DRIVE = 2;
-NET "FPGA_CCLK" LOC = "R15";
-NET "FPGA_CMP_CLK" LOC = "U16";
-#NET "FPGA_CMP_CS_B" LOC = "P13";
-NET "FPGA_CMP_MOSI" LOC = "V16";
-NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
-NET "FPGA_D1_MISO2" LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
-NET "FPGA_D2_MISO3" LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12
-#NET "FPGA_DONE" LOC = "V17"| SLEW = SLOW | DRIVE = 8; # findet MAP nicht, kein IOB
-NET "FPGA_HSWAPEN" LOC = "D4";
-NET "FPGA_INIT_B" LOC = "U3" | SLEW = SLOW | DRIVE = 4;
-NET "FPGA_M0_CMP_MISO" LOC = "T15";
-NET "FPGA_M1" LOC = "N12";
-NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13" | DRIVE = 4;
-NET "FPGA_ONCHIP_TERM1" LOC = "L6";
-NET "FPGA_ONCHIP_TERM2" LOC = "C2";
-#NET "FPGA_PROG_B" LOC = "V2" | IOSTANDARD = LVTTL | PULLDOWN; # kein IOB
-#NET "FPGA_SUSPEND" LOC = "R16"; # ERROR:MapLib:30
-#NET "FPGA_TCK" LOC = "A17"; # kein IOB
-#NET "FPGA_TDI" LOC = "D15"; # kein IOB
-#NET "FPGA_TDO" LOC = "D16"; # kein IOB
-#NET "FPGA_TMS" LOC = "B18";
-NET "FPGA_VTEMP" LOC = "P3";
-##
-## Pushbuttons, Bank 3, external Pulldown
-NET "GPIO_BUTTON<0>" LOC = "P4" ;
-NET "GPIO_BUTTON<1>" LOC = "F6" ;
-NET "GPIO_BUTTON<2>" LOC = "E4" ;
-NET "GPIO_BUTTON<3>" LOC = "F5" ;
-NET "GPIO_BUTTON*" TIG;
-##
-## 8 Pin IO Header J13, Bank 0,1,2
-NET "GPIO_HEADER_LS<0>" LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<1>" LOC = "M18"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<2>" LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<3>" LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<4>" LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<5>" LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<6>" LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<7>" LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;
-##
-## 4 GP LEDs, Bank 0
-NET "GPIO_LED<0>" LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED<1>" LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED<2>" LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED<3>" LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED*" TIG;
-##
-## GP IO Dip Switches, Bank 0,2, external Pulldown
-NET "GPIO_SWITCH<0>" LOC = "D14";
-NET "GPIO_SWITCH<1>" LOC = "E12";
-NET "GPIO_SWITCH<2>" LOC = "F12";
-NET "GPIO_SWITCH<3>" LOC = "V13";
-NET "GPIO_SWITCH*" TIG;
-##
-## IIC Bus
-NET "IIC_SCL_MAIN" LOC = "P11";
-NET "IIC_SDA_MAIN" LOC = "N10";
-##
-## 10/100/1000 Tri-Speed Ethernet PHY
-NET "PHY_COL" LOC = "L14";
-NET "PHY_CRS" LOC = "M13";
-NET "PHY_INT" LOC = "J13";
-NET "PHY_MDC" LOC = "N14" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_MDIO" LOC = "P16" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_RESET" LOC = "L13";
-NET "PHY_RXCLK" LOC = "L16";
-NET "PHY_RXCTL_RXDV" LOC = "N18";
-NET "PHY_RXD<0>" LOC = "M14";
-NET "PHY_RXD<1>" LOC = "U18";
-NET "PHY_RXD<2>" LOC = "U17";
-NET "PHY_RXD<3>" LOC = "T18";
-NET "PHY_RXD<4>" LOC = "T17";
-NET "PHY_RXD<5>" LOC = "N16";
-NET "PHY_RXD<6>" LOC = "N15";
-NET "PHY_RXD<7>" LOC = "P18";
-NET "PHY_RXER" LOC = "P17";
-NET "PHY_TXCLK" LOC = "B9" ;
-NET "PHY_TXCTL_TXEN" LOC = "B8" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXC_GTXCLK" LOC = "A9" ;
-NET "PHY_TXD<0>" LOC = "F8" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<1>" LOC = "G8" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<2>" LOC = "A6" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<3>" LOC = "B6" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<4>" LOC = "E6" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<5>" LOC = "F7" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<6>" LOC = "A5" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<7>" LOC = "C5" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXER" LOC = "A8" | SLEW = SLOW | DRIVE = 4;
-##
-## SPI x4 Flash
-NET "SPI_CS_B" LOC = "V3";
-##
-## 200 MHz oscillator (differential)
-NET "SYSCLK_N" LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
-NET "SYSCLK_P" LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
-TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 200 MHz HIGH 50 %;
-##
-## USB-UART
-## this names are real net names
-NET "USB_1_CTS" LOC = "U10"| DRIVE = 4 | SLEW = SLOW; # RTS output
-NET "USB_1_RTS" LOC = "T5" ; # CTS input
-NET "USB_1_RX" LOC = "L12"| DRIVE = 4 | SLEW = SLOW; # TX data out
-NET "USB_1_TX" LOC = "K14"; # RX data in
-##
-## 27 MHz
-NET "USER_CLOCK" LOC = "V10"| IOSTANDARD = LVCMOS33 ;
-NET "USER_CLOCK" PERIOD = 27 MHz HIGH 40%;
-##
-NET "USER_SMA_CLOCK_N" LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";
-NET "USER_SMA_CLOCK_P" LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";
-#TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 52 MHz HIGH 50 %;
-
-
diff --git a/test_rrobin_problem/synthesis/top.ut b/test_rrobin_problem/synthesis/top.ut
deleted file mode 100644
index ea9319f..0000000
--- a/test_rrobin_problem/synthesis/top.ut
+++ /dev/null
@@ -1,30 +0,0 @@
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g Reset_on_err:No
--g ConfigRate:2
--g ProgPin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g ExtMasterCclk_en:No
--g SPI_buswidth:1
--g TIMER_CFG:0xFFFF
--g multipin_wakeup:No
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
--g en_sw_gsr:No
--g drive_awake:No
--g sw_clk:Startupclk
--g sw_gwe_cycle:5
--g sw_gts_cycle:4
diff --git a/test_rrobin_problem/synthesis/top.xst b/test_rrobin_problem/synthesis/top.xst
deleted file mode 100644
index ae0c0c7..0000000
--- a/test_rrobin_problem/synthesis/top.xst
+++ /dev/null
@@ -1,53 +0,0 @@
-set -tmpdir "projnav.tmp"
-set -xsthdpdir "xst"
-run
--ifn ../top.prj
--ifmt mixed
--ofn top
--ofmt NGC
--p xc6slx16-2-csg324
--top top
--opt_mode Speed
--opt_level 1
--power NO
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--dsp_utilization_ratio 100
--lc Auto
--reduce_control_sets Auto
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--shreg_extract YES
--rom_style Auto
--auto_bram_packing NO
--resource_sharing YES
--async_to_sync NO
--shreg_min_size 2
--use_dsp48 Auto
--iobuf YES
--max_fanout 100000
--bufg 16
--register_duplication YES
--register_balancing No
--optimize_primitives NO
--use_clock_enable Auto
--use_sync_set Auto
--use_sync_reset Auto
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
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