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|
############################################################
# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/hardware/board_sp601/rtl/teilerregister.vhd $
# $Date$
# $Author$
# $Revision$
############################################################
# SPARTAN-6 SP601 BOARD CONSTRAINTS FILE
#
# Bank Voltage
# Bank 0: 2.5 V
# Bank 1: 2.5 V
# Bank 2: 2.5 V
# Bank 3: 1.8 V
# VCCAUX: 2.5 V
# following pins are connected to VCC1V8/2:
# N3, M5, C1
############################################################
## clock specialities
############################################################
#
# separete VGA clock from system clock
# no VGA -> no VGA clk
#NET "clk_driver_b.dcm_sp_i0_clkfx" TNM_NET = "clkfx";
#NET "clk_driver_b.dcm_sp_i0_clkdv" TNM_NET = "clkdv";
#TIMESPEC "TS_clkfx_clkdv" = FROM "clkfx" to "clkdv" TIG;
############################################################
## placement constraints
############################################################
### internal memory for zpu 8x4 bit = 32 bit width
### zpu_core_small
#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram1" AREA_GROUP = "ZPU_MEM1" ;
#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram2" AREA_GROUP = "ZPU_MEM2" ;
#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram3" AREA_GROUP = "ZPU_MEM3" ;
#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram4" AREA_GROUP = "ZPU_MEM4" ;
#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram5" AREA_GROUP = "ZPU_MEM5" ;
#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram6" AREA_GROUP = "ZPU_MEM6" ;
#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram7" AREA_GROUP = "ZPU_MEM7" ;
#INST "box_i0/zpu_ahb_i0/zpu_i0/memory/Mram_ram8" AREA_GROUP = "ZPU_MEM8" ;
### zpu_core_medium
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram1" AREA_GROUP = "ZPU_MEM1" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram2" AREA_GROUP = "ZPU_MEM2" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram3" AREA_GROUP = "ZPU_MEM3" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram4" AREA_GROUP = "ZPU_MEM4" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram5" AREA_GROUP = "ZPU_MEM5" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram6" AREA_GROUP = "ZPU_MEM6" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram7" AREA_GROUP = "ZPU_MEM7" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram8" AREA_GROUP = "ZPU_MEM8" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram9" AREA_GROUP = "ZPU_MEM9" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram10" AREA_GROUP = "ZPU_MEM10" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram11" AREA_GROUP = "ZPU_MEM11" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram12" AREA_GROUP = "ZPU_MEM12" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram13" AREA_GROUP = "ZPU_MEM13" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram14" AREA_GROUP = "ZPU_MEM14" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram15" AREA_GROUP = "ZPU_MEM15" ;
#INST "box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram16" AREA_GROUP = "ZPU_MEM16" ;
### planahead has problems with "" around range
AREA_GROUP "ZPU_MEM1" RANGE = RAMB16_X0Y14:RAMB16_X0Y14 ;
AREA_GROUP "ZPU_MEM2" RANGE = RAMB16_X0Y12:RAMB16_X0Y12 ;
AREA_GROUP "ZPU_MEM3" RANGE = RAMB16_X0Y10:RAMB16_X0Y10 ;
AREA_GROUP "ZPU_MEM4" RANGE = RAMB16_X0Y8:RAMB16_X0Y8 ;
AREA_GROUP "ZPU_MEM5" RANGE = RAMB16_X0Y6:RAMB16_X0Y6 ;
AREA_GROUP "ZPU_MEM6" RANGE = RAMB16_X0Y4:RAMB16_X0Y4 ;
AREA_GROUP "ZPU_MEM7" RANGE = RAMB16_X0Y2:RAMB16_X0Y2 ;
AREA_GROUP "ZPU_MEM8" RANGE = RAMB16_X0Y0:RAMB16_X0Y0 ;
AREA_GROUP "ZPU_MEM9" RANGE = RAMB16_X1Y14:RAMB16_X1Y14 ;
AREA_GROUP "ZPU_MEM10" RANGE = RAMB16_X1Y12:RAMB16_X1Y12 ;
AREA_GROUP "ZPU_MEM11" RANGE = RAMB16_X1Y10:RAMB16_X1Y10 ;
AREA_GROUP "ZPU_MEM12" RANGE = RAMB16_X1Y8:RAMB16_X1Y8 ;
AREA_GROUP "ZPU_MEM13" RANGE = RAMB16_X1Y6:RAMB16_X1Y6 ;
AREA_GROUP "ZPU_MEM14" RANGE = RAMB16_X1Y4:RAMB16_X1Y4 ;
AREA_GROUP "ZPU_MEM15" RANGE = RAMB16_X1Y2:RAMB16_X1Y2 ;
AREA_GROUP "ZPU_MEM16" RANGE = RAMB16_X1Y0:RAMB16_X1Y0 ;
############################################################
## pin constraints
############################################################
NET "CPU_RESET" LOC = "N4";
##
## 128 MB DDR2 Component Memory
NET "DDR2_A<12>" LOC ="G6"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<11>" LOC ="D3"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<10>" LOC ="F4"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<9>" LOC ="D1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<8>" LOC ="D2"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<7>" LOC ="H6"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<6>" LOC ="H3"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<5>" LOC ="H4"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<4>" LOC ="F3"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<3>" LOC ="L7"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<2>" LOC ="H5"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<1>" LOC ="J6"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_A<0>" LOC ="J7"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<15>" LOC ="U1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<14>" LOC ="U2"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<13>" LOC ="T1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<12>" LOC ="T2"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<11>" LOC ="N1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<10>" LOC ="N2"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<9>" LOC ="M1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<8>" LOC ="M3"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<7>" LOC ="J1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<6>" LOC ="J3"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<5>" LOC ="H1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<4>" LOC ="H2"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<3>" LOC ="K1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<2>" LOC ="K2"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<1>" LOC ="L1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ<0>" LOC ="L2"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_WE_B" LOC ="E3"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_UDQS_P" LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;
NET "DDR2_UDQS_N" LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;
NET "DDR2_UDM" LOC ="K4"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_RAS_B" LOC ="L5"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_ODT" LOC ="K6"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_LDQS_P" LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;
NET "DDR2_LDQS_N" LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;
NET "DDR2_LDM" LOC ="K3"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_CLK_P" LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;
NET "DDR2_CLK_N" LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;
NET "DDR2_CKE" LOC ="H7"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_CAS_B" LOC ="K5"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA<2>" LOC ="E1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA<1>" LOC ="F1"; # | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA<0>" LOC ="F2"; # | IOSTANDARD = SSTL18_II ;
##
##
NET "FLASH_A<0>" LOC = "K18";
NET "FLASH_A<1>" LOC = "K17";
NET "FLASH_A<2>" LOC = "J18";
NET "FLASH_A<3>" LOC = "J16";
NET "FLASH_A<4>" LOC = "G18";
NET "FLASH_A<5>" LOC = "G16";
NET "FLASH_A<6>" LOC = "H16";
NET "FLASH_A<7>" LOC = "H15";
NET "FLASH_A<8>" LOC = "H14";
NET "FLASH_A<9>" LOC = "H13";
NET "FLASH_A<10>" LOC = "F18";
NET "FLASH_A<11>" LOC = "F17";
NET "FLASH_A<12>" LOC = "K13";
NET "FLASH_A<13>" LOC = "K12";
NET "FLASH_A<14>" LOC = "E18";
NET "FLASH_A<15>" LOC = "E16";
NET "FLASH_A<16>" LOC = "G13";
NET "FLASH_A<17>" LOC = "H12";
NET "FLASH_A<18>" LOC = "D18";
NET "FLASH_A<19>" LOC = "D17";
NET "FLASH_A<20>" LOC = "G14";
NET "FLASH_A<21>" LOC = "F14";
NET "FLASH_A<22>" LOC = "C18";
NET "FLASH_A<23>" LOC = "C17";
NET "FLASH_A<24>" LOC = "F16";
NET "FLASH_CE_B" LOC = "L17";
#NET "FLASH_D<0>" LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;
#NET "FLASH_D<1>" LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;
#NET "FLASH_D<2>" LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;
NET "FLASH_D<3>" LOC = "U5" | SLEW = "SLOW" | DRIVE = 2;
NET "FLASH_D<4>" LOC = "V5" | SLEW = "SLOW" | DRIVE = 2;
NET "FLASH_D<5>" LOC = "R3" | SLEW = "SLOW" | DRIVE = 2;
NET "FLASH_D<6>" LOC = "T3" | SLEW = "SLOW" | DRIVE = 2;
NET "FLASH_D<7>" LOC = "R5" | SLEW = "SLOW" | DRIVE = 2;
NET "FLASH_OE_B" LOC = "L18";
NET "FLASH_WE_B" LOC = "M16";
# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)
NET "FMC_CLK0_M2C_N" LOC = "A10";
NET "FMC_CLK0_M2C_P" LOC = "C10";
NET "FMC_CLK1_M2C_N" LOC = "V9" ;
NET "FMC_CLK1_M2C_P" LOC = "T9" ;
NET "FMC_LA00_CC_N" LOC = "C9" ;
NET "FMC_LA00_CC_P" LOC = "D9" ;
NET "FMC_LA01_CC_N" LOC = "C11" | TNM_NET = "ADC_CLK";
NET "FMC_LA01_CC_P" LOC = "D11" | TNM_NET = "ADC_CLK";
TIMESPEC "TS_ADC_CLK" = PERIOD "ADC_CLK" 52 MHz HIGH 50 %;
NET "FMC_LA02_N" LOC = "A15";
NET "FMC_LA02_P" LOC = "C15";
NET "FMC_LA03_N" LOC = "A13";
NET "FMC_LA03_P" LOC = "C13";
NET "FMC_LA04_N" LOC = "A16";
NET "FMC_LA04_P" LOC = "B16";
NET "FMC_LA05_N" LOC = "A14";
NET "FMC_LA05_P" LOC = "B14";
NET "FMC_LA06_N" LOC = "C12";
NET "FMC_LA06_P" LOC = "D12";
NET "FMC_LA07_N" LOC = "E8" ;
NET "FMC_LA07_P" LOC = "E7" ;
NET "FMC_LA08_N" LOC = "E11";
NET "FMC_LA08_P" LOC = "F11";
NET "FMC_LA09_N" LOC = "F10";
NET "FMC_LA09_P" LOC = "G11";
NET "FMC_LA10_N" LOC = "C8" ;
NET "FMC_LA10_P" LOC = "D8" ;
NET "FMC_LA11_N" LOC = "A12";
NET "FMC_LA11_P" LOC = "B12";
NET "FMC_LA12_N" LOC = "C6" ;
NET "FMC_LA12_P" LOC = "D6" ;
NET "FMC_LA13_N" LOC = "A11";
NET "FMC_LA13_P" LOC = "B11";
NET "FMC_LA14_N" LOC = "A2" ;
NET "FMC_LA14_P" LOC = "B2" ;
NET "FMC_LA15_N" LOC = "F9" ;
NET "FMC_LA15_P" LOC = "G9" ;
NET "FMC_LA16_N" LOC = "A7" ;
NET "FMC_LA16_P" LOC = "C7" ;
NET "FMC_LA17_CC_N" LOC = "T8" ;
NET "FMC_LA17_CC_P" LOC = "R8" ;
NET "FMC_LA18_CC_N" LOC = "T10";
NET "FMC_LA18_CC_P" LOC = "R10";
NET "FMC_LA19_N" LOC = "P7" ;
NET "FMC_LA19_P" LOC = "N6" ;
NET "FMC_LA20_N" LOC = "P8" ;
NET "FMC_LA20_P" LOC = "N7" ;
NET "FMC_LA21_N" LOC = "V4" ;
NET "FMC_LA21_P" LOC = "T4" ;
NET "FMC_LA22_N" LOC = "T7" ;
NET "FMC_LA22_P" LOC = "R7" ;
NET "FMC_LA23_N" LOC = "P6" ;
NET "FMC_LA23_P" LOC = "N5" ;
NET "FMC_LA24_N" LOC = "V8" ;
NET "FMC_LA24_P" LOC = "U8" ;
NET "FMC_LA25_N" LOC = "N11";
NET "FMC_LA25_P" LOC = "M11";
NET "FMC_LA26_N" LOC = "V7" ;
NET "FMC_LA26_P" LOC = "U7" ;
NET "FMC_LA27_N" LOC = "T11";
NET "FMC_LA27_P" LOC = "R11";
NET "FMC_LA28_N" LOC = "V11";
NET "FMC_LA28_P" LOC = "U11";
NET "FMC_LA29_N" LOC = "N8" ;
NET "FMC_LA29_P" LOC = "M8" ;
NET "FMC_LA30_N" LOC = "V12";
NET "FMC_LA30_P" LOC = "T12";
NET "FMC_LA31_N" LOC = "V6" ;
NET "FMC_LA31_P" LOC = "T6" ;
NET "FMC_LA32_N" LOC = "V15";
NET "FMC_LA32_P" LOC = "U15";
NET "FMC_LA33_N" LOC = "N9" ;
NET "FMC_LA33_P" LOC = "M10";
NET "FMC_PRSNT_M2C_L" LOC = "U13";
NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
NET "FPGA_AWAKE" LOC = "P15"| SLEW = SLOW | DRIVE = 2;
NET "FPGA_CCLK" LOC = "R15";
NET "FPGA_CMP_CLK" LOC = "U16";
#NET "FPGA_CMP_CS_B" LOC = "P13";
NET "FPGA_CMP_MOSI" LOC = "V16";
NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
NET "FPGA_D1_MISO2" LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
NET "FPGA_D2_MISO3" LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12
#NET "FPGA_DONE" LOC = "V17"| SLEW = SLOW | DRIVE = 8; # findet MAP nicht, kein IOB
NET "FPGA_HSWAPEN" LOC = "D4";
NET "FPGA_INIT_B" LOC = "U3" | SLEW = SLOW | DRIVE = 4;
NET "FPGA_M0_CMP_MISO" LOC = "T15";
NET "FPGA_M1" LOC = "N12";
NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13" | DRIVE = 4;
NET "FPGA_ONCHIP_TERM1" LOC = "L6";
NET "FPGA_ONCHIP_TERM2" LOC = "C2";
#NET "FPGA_PROG_B" LOC = "V2" | IOSTANDARD = LVTTL | PULLDOWN; # kein IOB
#NET "FPGA_SUSPEND" LOC = "R16"; # ERROR:MapLib:30
#NET "FPGA_TCK" LOC = "A17"; # kein IOB
#NET "FPGA_TDI" LOC = "D15"; # kein IOB
#NET "FPGA_TDO" LOC = "D16"; # kein IOB
#NET "FPGA_TMS" LOC = "B18";
NET "FPGA_VTEMP" LOC = "P3";
##
## Pushbuttons, Bank 3, external Pulldown
NET "GPIO_BUTTON<0>" LOC = "P4" ;
NET "GPIO_BUTTON<1>" LOC = "F6" ;
NET "GPIO_BUTTON<2>" LOC = "E4" ;
NET "GPIO_BUTTON<3>" LOC = "F5" ;
NET "GPIO_BUTTON*" TIG;
##
## 8 Pin IO Header J13, Bank 0,1,2
NET "GPIO_HEADER_LS<0>" LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_HEADER_LS<1>" LOC = "M18"| SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_HEADER_LS<2>" LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_HEADER_LS<3>" LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_HEADER_LS<4>" LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_HEADER_LS<5>" LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_HEADER_LS<6>" LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_HEADER_LS<7>" LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;
##
## 4 GP LEDs, Bank 0
NET "GPIO_LED<0>" LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_LED<1>" LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_LED<2>" LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_LED<3>" LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;
NET "GPIO_LED*" TIG;
##
## GP IO Dip Switches, Bank 0,2, external Pulldown
NET "GPIO_SWITCH<0>" LOC = "D14";
NET "GPIO_SWITCH<1>" LOC = "E12";
NET "GPIO_SWITCH<2>" LOC = "F12";
NET "GPIO_SWITCH<3>" LOC = "V13";
NET "GPIO_SWITCH*" TIG;
##
## IIC Bus
NET "IIC_SCL_MAIN" LOC = "P11";
NET "IIC_SDA_MAIN" LOC = "N10";
##
## 10/100/1000 Tri-Speed Ethernet PHY
NET "PHY_COL" LOC = "L14";
NET "PHY_CRS" LOC = "M13";
NET "PHY_INT" LOC = "J13";
NET "PHY_MDC" LOC = "N14" | SLEW = SLOW | DRIVE = 4;
NET "PHY_MDIO" LOC = "P16" | SLEW = SLOW | DRIVE = 4;
NET "PHY_RESET" LOC = "L13";
NET "PHY_RXCLK" LOC = "L16";
NET "PHY_RXCTL_RXDV" LOC = "N18";
NET "PHY_RXD<0>" LOC = "M14";
NET "PHY_RXD<1>" LOC = "U18";
NET "PHY_RXD<2>" LOC = "U17";
NET "PHY_RXD<3>" LOC = "T18";
NET "PHY_RXD<4>" LOC = "T17";
NET "PHY_RXD<5>" LOC = "N16";
NET "PHY_RXD<6>" LOC = "N15";
NET "PHY_RXD<7>" LOC = "P18";
NET "PHY_RXER" LOC = "P17";
NET "PHY_TXCLK" LOC = "B9" ;
NET "PHY_TXCTL_TXEN" LOC = "B8" | SLEW = SLOW | DRIVE = 4;
NET "PHY_TXC_GTXCLK" LOC = "A9" ;
NET "PHY_TXD<0>" LOC = "F8" | SLEW = SLOW | DRIVE = 4;
NET "PHY_TXD<1>" LOC = "G8" | SLEW = SLOW | DRIVE = 4;
NET "PHY_TXD<2>" LOC = "A6" | SLEW = SLOW | DRIVE = 4;
NET "PHY_TXD<3>" LOC = "B6" | SLEW = SLOW | DRIVE = 4;
NET "PHY_TXD<4>" LOC = "E6" | SLEW = SLOW | DRIVE = 4;
NET "PHY_TXD<5>" LOC = "F7" | SLEW = SLOW | DRIVE = 4;
NET "PHY_TXD<6>" LOC = "A5" | SLEW = SLOW | DRIVE = 4;
NET "PHY_TXD<7>" LOC = "C5" | SLEW = SLOW | DRIVE = 4;
NET "PHY_TXER" LOC = "A8" | SLEW = SLOW | DRIVE = 4;
##
## SPI x4 Flash
NET "SPI_CS_B" LOC = "V3";
##
## 200 MHz oscillator (differential)
NET "SYSCLK_N" LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
NET "SYSCLK_P" LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 200 MHz HIGH 50 %;
##
## USB-UART
## this names are real net names
NET "USB_1_CTS" LOC = "U10"| DRIVE = 4 | SLEW = SLOW; # RTS output
NET "USB_1_RTS" LOC = "T5" ; # CTS input
NET "USB_1_RX" LOC = "L12"| DRIVE = 4 | SLEW = SLOW; # TX data out
NET "USB_1_TX" LOC = "K14"; # RX data in
##
## 27 MHz
NET "USER_CLOCK" LOC = "V10"| IOSTANDARD = LVCMOS33 ;
NET "USER_CLOCK" PERIOD = 27 MHz HIGH 40%;
##
NET "USER_SMA_CLOCK_N" LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";
NET "USER_SMA_CLOCK_P" LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";
#TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 52 MHz HIGH 50 %;
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