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* Move Intel SPI initialisation to ichspi.cMichael Karcher2010-07-221-200/+18
| | | | | | | | | | | Smarter version could decide whether SPI is vital or not depending on straps. Straps are currently implemented for ICH7. EP80579 is in the comment, PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI". Corresponding to flashrom svn r1098. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Fix out-of-bounds ICH FREG permission printingCarl-Daniel Hailfinger2010-07-131-3/+4
| | | | | | | | | | | | | | A bit was masked, but not shifted, and that led to worst-case accesses of index 24 in an array with 4 members. I've improved readability in the variable declaration block as well. Thanks to Stephen Kou for reporting the bug. Corresponding to flashrom svn r1076. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stephen Kou <stephen@hyarros.com>
* Unify programmer parameter extractionCarl-Daniel Hailfinger2010-07-081-1/+1
| | | | | | | | | | | Make programmer_param static by converting all users to extract_programmer_param. Programmer parameters can no longer be separated with a colon, they have to be separated with a comma. Corresponding to flashrom svn r1072. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Various places in the flashrom source feature custom parameter extraction ↵Carl-Daniel Hailfinger2010-07-061-5/+10
| | | | | | | | | | | | | | | | | | | | from programmer_param This led to wildly differing syntax for programmer parameters, and it also voids pretty much every assumption you could make about programmer_param. The latter is a problem for libflashrom. Use extract_param everywhere, clean up related code and make it more foolproof. Add two instances of exit(1) where we have no option to return an error. Remove six instances of exit(1) where returning an error was possible. WARNING: This changes programmer parameter syntax for a few programmers! Corresponding to flashrom svn r1070. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Kill global variables, constants and functions if local scope sufficesCarl-Daniel Hailfinger2010-07-031-30/+30
| | | | | | | | | | | | | | | | | | | | | | | Constify variables where possible. Initialize programmer-related variables explicitly in programmer_init to allow running programmer_init from a clean state after programmer_shutdown. Prohibit registering programmer shutdown functions before init or after shutdown. Kill some dead code. Rename global variables with namespace-polluting names. Use a previously unused locking helper function in sst49lfxxxc.c. This is needed for libflashrom. Effects on the binary size of flashrom are minimal (300 bytes shrinkage), but the data section shrinks by 4384 bytes, and that's a good thing if flashrom is operating in constrained envionments. Corresponding to flashrom svn r1068. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* ICH9/10: display FRAP/FREGx access controlsJoshua Roys2010-07-011-15/+47
| | | | | | | Corresponding to flashrom svn r1066. Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Kill unneeded #include wherever possibleCarl-Daniel Hailfinger2010-06-211-3/+1
| | | | | | | | | | Tested on Linux, FreeBSD, NetBSD, OpenBSD, DOS. Thanks to Jonathan A. Kollasch and Idwer Vollering for testing. Corresponding to flashrom svn r1057. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer+lists.flashrom@gmail.com>
* Fill in buses_supported for remaining Intel chipsets (ICH0-ICH5, Poulsbo)Carl-Daniel Hailfinger2010-06-201-0/+2
| | | | | | | Corresponding to flashrom svn r1055. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com>
* VIA: disable byte mergingMichael Karcher2010-06-131-7/+52
| | | | | | | | | | | | | | | | All mentioned north bridges have been checked against data sheet. That's all north bridges google found a datasheet for with "byte merge" included. Runs multiple chipset enables if the first one requests further enables to be run. VIA byte-merging logic tested: works. multiple chipset logic: completely untested Corresponding to flashrom svn r1043. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Board-enable for MS-7025 (K8N Neo2 Platinum)Michael Karcher2010-06-121-0/+1
| | | | | | | | | | | Test report is http://www.coreboot.org/pipermail/flashrom/2010-April/002967.html Corresponding to flashrom svn r1041. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Tested-by: Valentine "Pegasus rider" Yatsenko <mr.qweo@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Remove unneeded #include statements completelyCarl-Daniel Hailfinger2010-05-301-0/+1
| | | | | | | | | | | | | | | Unistd.h was only used to get a definition of NULL in all files. Add our own NULL #define and remove unistd.h from flash.h stdio.h has no place in flash.h, it should be included only in files which really need it. Add #include statements in individual .c files where needed. Replace a few printf with msg_* to eliminate the need for stdio.h. Corresponding to flashrom svn r1021. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* ichspi: try harder to conform to address restrictionsCarl-Daniel Hailfinger2010-05-281-4/+4
| | | | | | | | | | | | | | ICH SPI can enforce address restrictions for all accesses which take an address (well, it could if the chipset implementation was not broken). Since exploiting the broken implementation is harder than conforming to the address restrictions wherever possible, conform to the address restrictions instead. This patch eliminates a lot of transaction errors people were seeing on chip probe. Corresponding to flashrom svn r1016. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Handle the following architectures in generic flashrom codeCarl-Daniel Hailfinger2010-05-261-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Misha Manulis for testing early versions of this patch on PowerPC (big endian) with the satasii programmer. Thanks to Segher Boessenkool for design review and for helping out with compiler tricks and pointing out that we need eieio on PowerPC. Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). Thanks to Uwe Hermann for compile and runtime testing on x86_64. DO NOT RUN flashrom ON NON-X86 AFTER APPLYING THIS PATCH! This patch only provides the infrastructure, but does not convert any drivers, so flashrom will compile, but it won't do the right thing on non-x86 platforms. Corresponding to flashrom svn r1013. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
* Print found PCI IDs during chipset detectionCarl-Daniel Hailfinger2010-05-221-0/+3
| | | | | | | | | | | | Add debug output of the exact matched chipset PCI ID to keep track of tested PCI IDs for chipsets with one name and multiple IDs. This will help avoid problems similar to the Tyan S2915 OEM undetected flash in the future. Corresponding to flashrom svn r1008. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Disable probing for one variant of MCP55 to enable Tyan S2915Carl-Daniel Hailfinger2010-05-221-1/+9
| | | | | | | | | | | | | | | | | | Fix Tyan S2915 OEM board by commenting out MCP55 LPC bridge PCI ID 10de:0361 which is the secondary LPC bridge. The same effect could be achieved by refusing to run enable_flash_mcp55 if the device class is not ISA bridge [0601]. Thanks to Alessandro Polverini, Joel Robertson, Nicolas Aveline, Phil LoCascio and Nils-Helge Garli Hegvik for testing flashrom on hardware and Michael Karcher for analyzing the factory BIOS for clues. In the end, no board enable was needed and it was a pure chipset issue. Corresponding to flashrom svn r1007. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Convert various prints to use msg_p* and msg_g* respectivelySean Nelson2010-05-071-108/+108
| | | | | | | | | Convert programmer print messages to msg_p* convert general print messages to msg_g* a few fixes as suggested by Carl-Daniel. Corresponding to flashrom svn r997. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Rename identifiers called 'byte'Michael Karcher2010-02-251-14/+14
| | | | | | | | | | | | Still fallout of adding "-Wshadow". Missed the ht1000 one (chipset_enable is not compied on Windows where we had the collision with "byte" last time) and the other occurrence is newly introduced. Old libpci defines a global symbol called "byte" too. Corresponding to flashrom svn r913. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Refactor MCP SPI detectionCarl-Daniel Hailfinger2010-02-181-54/+101
| | | | | | | | | | | | - Set supported buses based on ISA bridge reg 0x8a - Use MCP55 chipset enable only if LPC is detected - Allow LPC on MCP61 - Eliminate duplicated code where possible Corresponding to flashrom svn r906. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Add SPI mode diagnostics for all post-MCP55 (nForce 5) chipsets from NvidiaCarl-Daniel Hailfinger2010-02-131-1/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Huge thanks to Michael Karcher for reverse engineering the MCP67 chipset and writing a spec. Due to this, we were able to use the chinese wall technique for 100% clean room reverse engineering. This patch doesn't touch any of the new registers, it only reads them. Assuming that read has no side effects, this patch is a no-op and safe. We need "flashrom -V" output from all post-MCP55 (nForce 5) chipset boards. Please indicate if your board uses SPI flash or LPC flash (if you know it). Note: That output is only helpful if it is created with patched flashrom and if is from the first run of flashrom after a cold boot (reset or Ctrl-Alt-Del is not sufficient). There is a pattern based on which we can probably detect which flash type is present on the board. Thanks to Alessandro Polverini for testing earlier iterations of this patch. Note: The MCP67 should work. I guessed that the other recent Nvidia chipsets would work in a similar way, and created a simplified do-nothing catchall chipset enable function which dumps some info and instructs the user to send more info. Corresponding to flashrom svn r902. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Add Intel NM10 chipset enableDavid Hendricks2010-01-191-0/+1
| | | | | | | | | | | | | Public chipset documentation available at http://www.intel.com/Assets/PDF/datasheet/322896.pdf Tested on NM10-based customer reference board from Intel. Corresponding to flashrom svn r866. Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Don't use "byte" as identifierMichael Karcher2010-01-121-11/+11
| | | | | | | | | | Some mingw declares a global identifier "byte", causing -Werror -Wshadow to break compilation. This patch renames all identifiers called "byte". Corresponding to flashrom svn r861. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Chipset: Fix sis5x0 register write verificationLuc Verhaegen2010-01-101-13/+3
| | | | | | | | | | | Also remove separate sis 5596 routine: superio code will be handled separately, which then turns this routine into the sis 5511 chipset enable. Corresponding to flashrom svn r859. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Fix Intel FWH decode sizeMichael Karcher2010-01-031-2/+2
| | | | | | | | | Fixes wrong detection of area decoded to the FWH interfaces. Corresponding to flashrom svn r826. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add VIA VT8233A identification, mark as testedRaúl Soriano2009-12-231-0/+1
| | | | | | | Corresponding to flashrom svn r820. Signed-off-by: Raúl Soriano <GatoLoko@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enableLuc Verhaegen2009-12-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | Only done for VT8237R (possibly needed for VT8237 too), VT8235 does not need this (even if the original bios does so: Asus A7V8X-MX SE, MSI KT4V were verified). This then opens a floodgate of cleanups in the board enables. * EPIA SP board enable vanishes, taking EPIA CN match with it. * Asus A7V8X-MX/Tyan S2498 board enable then equals w836xx_memw_enable_2e * AOpen vKM400Am-S board enable then equals it8705_rom_write_enable * Epia M board enable becomes via_vt823x_gpio15_raise * Epia N board enable becomes via_vt823x_gpio9_raise * Asus M2V-MX board enable becomes via_vt823x_gpio5_raise * vt823x_gpio_set becomes via_vt823x_gpio_set, and now detects ISA bridge itself, in concordance with intel ich and nvidia mcp gpio. Corresponding to flashrom svn r815. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Chipset: Add support for Intel Poulsbo chipsetAdam Jurkowski2009-12-211-0/+22
| | | | | | | Corresponding to flashrom svn r809. Signed-off-by: Adam Jurkowski <adam.jurkowski@kontron.pl> Acked-by: Luc Verhaegen <libv@skynet.be>
* Use the maximum decode size infrastructureCarl-Daniel Hailfinger2009-12-171-27/+96
| | | | | | | | | | | | | | | | | | - Detect max FWH size for Intel 631xESB/632xESB/3100/ICH6/ICH7/ICH8/ICH9/ICH10. - Move IDSEL override before decode size checking for the chipsets listed above or flashrom will complain based on old values. - Adjust supported flash buses for the chipsets listed above (none of them supports LPC or Parallel). - Detect max parallel size for AMD/National Semiconductor CS5530. - Adjust supported flash buses for CS5530/CS5530A. - Set board-specific max decode size for Elitegroup K7VTA3. - Set board-specific max decode size for Shuttle AK38N. Corresponding to flashrom svn r806. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Internal (onboard) programming was the only feature which could not be disabledCarl-Daniel Hailfinger2009-12-131-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make various pieces of code conditional on support for internal programming. Code shared between PCI device programmers and onboard programming is now conditional as well. It is now possible to build only with dummy support: make CONFIG_INTERNAL=no CONFIG_NIC3COM=no CONFIG_SATASII=no CONFIG_DRKAISER=no CONFIG_SERPROG=no CONFIG_FT2232SPI=no This allows building for a specific use case only, and it also facilitates porting to a new architecture because it is possible to focus on highlevel code only. Note: Either internal or dummy programmer needs to be compiled in due to the current behaviour of always picking a default programmer if -p is not specified. Picking an arbitrary external programmer as default wouldn't make sense. Build and runtime tested in all 1024 possible build combinations. The only failures are by design as mentioned above. Corresponding to flashrom svn r797. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Chipset: remove sis630 chipset enable for sis540Luc Verhaegen2009-12-091-51/+17
| | | | | | | | | | | | | SiS630 chipset enable is equal to sis540 plus superio "poking". Superio poking equals IT8705F flash write enable, which is currently dealt with on a board by board basis in board_enable.c. Not all 630 and newer based boards come with it8705/sis950 superios. Corresponding to flashrom svn r794. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Intel PIIX* chipsets only support parallel flash (no LPC/FWH/SPI)Maciej Pijanka2009-12-081-0/+2
| | | | | | | Corresponding to flashrom svn r793. Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for Intel 3400 series / 5 series chipsetCarl-Daniel Hailfinger2009-11-261-0/+3
| | | | | | | | | | | | | | | Found in Intel document 322170 (Intel 5 Series Chipset and Intel 3400 Series Chipset Specification Update). According to http://pciids.sourceforge.net/ we probably should match all IDs from 0x3b00-0x3b1f, but so far I didn't find an Intel doc saying the same. If anybody has contacts at Intel and can check, I'd be happy to add the rest of the IDs. Corresponding to flashrom svn r784. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Mark Elitegroup K7S5A as supportedCarl-Daniel Hailfinger2009-11-151-28/+28
| | | | | | | | | | | | | Mark SiS 735 as supported. Remove "SiS" from the model number to avoid printing it twice. Reported by Adrian Glaubitz. Corresponding to flashrom svn r760. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for every single SiS chipset out thereCarl-Daniel Hailfinger2009-11-151-67/+200
| | | | | | | | | | | | | | | | | | | | | The two existing SiS chipset enables (compared to the 28 in this patch) were refactored, and one of them was fixed. A function to match PCI vendor/class combinations was added to generic code. Tested on the "Elitegroup K7S5A". Results are somewhat unexpected (some PCI settings seem to be inaccessible, but it still works). This is not based on any docs, but rather on detailed analysis of existing opensource code for some of the chipsets. Thanks to for Adrian Glaubitz testing. Corresponding to flashrom svn r759. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
* Add infrastructure to check the maximum supported flash size of chipsets and ↵Carl-Daniel Hailfinger2009-10-311-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mainboards The rationale is to warn users when they, for example, try to flash a 512KB parallel flash chip but their chipset only supports 256KB, or they try to flash 512KB and the chipset _does_ theoretically support 512KB but their special board doesn't wire all address lines and thus supports only 256 KB ROM chips at maximum. This has cost Uwe hours of debugging on some board already, until he figured out what was going on. We should try warn our users where possible about this. The chipset and the chip may have more than one bus in common (e.g. SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there are different limits for LPC and FWH. The only way to tell the user about the exact circumstances is to spew error messages per bus. The code will issue a warning during probe (which does fail for some chips if the size is too big) and abort before the first real read/write/erase action. If no action is specified, the warning is printed anyway. That way, a user can find out why probe might not have worked, and will be stopped before he/she gets incorrect results. Add a bitcount function to the infrastructure. Corresponding to flashrom svn r755. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Mark NVIDIA Nforce4/MCP04 as testedLuc Verhaegen2009-10-061-1/+1
| | | | | | | | | Oops. Corresponding to flashrom svn r747. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Luc Verhaegen <libv@skynet.be>
* Chipset support for the nVidia nForce 4Luc Verhaegen2009-10-051-0/+1
| | | | | | | | | | Add pciids for the new isa bridge, and hook it to the nforce2 chipset enable. Corresponding to flashrom svn r744. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Martin Szulecki <opensuse@sukimashita.com>
* Add chipset support for VIA VT82C596 by adding a PCI IDUwe Hermann2009-09-251-0/+1
| | | | | | | | | This is successfully tested by me on the Elitegroup P6VAP-A+ board. Corresponding to flashrom svn r732. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Enable flashrom on Wyse Winterm S50Nils Jacobs2009-09-231-0/+1
| | | | | | | | | | | | On the Wyse Winterm S50 lspci doesn`t show the cs5536 hostbridge and so flashrom doesn`t detect the cs5536. This patch is adding the cs5536 isa id [1022:2090] for chip detect. Corresponding to flashrom svn r729. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Use correct name for SB700/SB710/SB750 instead of calling them SB700Carl-Daniel Hailfinger2009-09-011-1/+1
| | | | | | | Corresponding to flashrom svn r706. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be>
* Add support for ICH9 engineering sampleCarl-Daniel Hailfinger2009-08-211-0/+1
| | | | | | | | | | | | | Anne Le Coq <annyvonne.le_coq@alcatel-lucent.fr> reported that flashrom didn't recognize her ICH9 LPC controller on the Green City Intel Customer Reference Board with ICH9 + Tylersburg Chipset. According to http://pci-ids.ucw.cz/read/PC/8086/2910 the ID 0x8086/0x2910 was used for engineering samples. No intel doc mentions this ID at all. Corresponding to flashrom svn r696. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Anne Le Coq <annyvonne.le_coq@alcatel-lucent.fr>
* Allow the user to override FWH IDSEL on ICH6 and laterCarl-Daniel Hailfinger2009-08-131-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Usage: flashrom -p internal=fwh_idsel=0 Corresponding to flashrom svn r685. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Log: flashrom v0.9.0-r670 coreboot table found at 0xcf7f3c00. Vendor ID: KONTRON, part ID: 986LCD-M Found chipset "Intel ICH7/ICH7R", enabling flash write... Setting IDSEL=0 for top 8 MBOK. This chipset supports the following protocols: LPC,FWH. Disabling flash write protection for board "Kontron 986LCD-M"... OK. Calibrating delay loop... OK. Found chip "SST SST49LF016C" (2048 KB, FWH) at physical address 0xffe00000. No operations were specified. Acked-by: Chris Kinney <cmkinne@sandia.gov>
* Fix up MSR handling to support more OSes than Linux. Stefan Reinauer2009-08-121-69/+13
| | | | | | | Corresponding to flashrom svn r677. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Make debug messages printf_debug(). Stefan Reinauer2009-08-111-15/+15
| | | | | | | Corresponding to flashrom svn r676. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add ICH6,ICH7,ICH8,ICH9,ICH10 FWH IDSEL settings and flash decode settings ↵Carl-Daniel Hailfinger2009-08-101-0/+36
| | | | | | | | | | | | | to the debug output This can help debug cases where the BIOS does not set up a correct flash decode for the given flash size. The Intel docs state that the decode applies to FWH and SPI flash. Corresponding to flashrom svn r675. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Chris Kinney <cmkinne@sandia.gov>
* Remove unnecessary #include filesCarl-Daniel Hailfinger2009-08-091-2/+1
| | | | | | | | | | Serprog compilation is now controlled by a Makefile variable. Replace munmap with physunmap where appropriate. Corresponding to flashrom svn r671. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* This is a workaround for a bug in SB600 and SB700Carl-Daniel Hailfinger2009-07-231-7/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we only send an opcode and no additional data/address, the SPI controller will read one byte too few from the chip. Basically, the last byte of the chip response is discarded and will not end up in the FIFO. It is unclear if the CS# line is set high too early as well. That hardware bug is undocumented as of now, but I'm working with AMD to add a detailed description of it to the errata. Add loads of additional debugging to SB600/SB700 init. Add explanatory comments for unintuitive code flow. Thanks go to Uwe for testing quite a few iterations of the patch. Kill the SB600 flash chip status register special case, which was a somewhat misguided workaround for that hardware erratum. Note for future added features in the SB600 SPI driver: It may be possible to read up to 15 bytes of command response with overlapping reads due to the ring buffer design of the FIFO if the command can be repeated without ill effects. Same for skipping up to 7 bytes between command and response. Corresponding to flashrom svn r661. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Random minor flashrom fixesUwe Hermann2009-06-281-1/+1
| | | | | | | | | | | | | | | - Properly escape '-' chars in manpage. - Fix typo in chipset_enable.c. - Drop useless 'return' in chip_readn(). - Random other whitespace or cosmetic fixes. Corresponding to flashrom svn r636. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Print the bus type(s) of both chipset and chip in the flashrom outputUwe Hermann2009-06-281-0/+2
| | | | | | | Corresponding to flashrom svn r635. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Chipset enable for VIA VT8233Mateusz Murawski2009-06-181-0/+1
| | | | | | | Corresponding to flashrom svn r603. Signed-off-by: Mateusz Murawski <matowy@tlen.pl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Move all printing code to print.cUwe Hermann2009-06-171-26/+0
| | | | | | | | | Drop no longer needed MAX macro, we have a max() function. Corresponding to flashrom svn r601. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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