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* - There's no need to overwrite the default device method with the defaultmarius2011-11-222-4/+2
| | | | | | | | | | one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID.
* Fix r222813: we need to include sys/cpuset.h. because the PIC interfacemarcel2011-07-311-2/+2
| | | | | | | uses cpuset_t. While here, fix the redundant inclusion of sys/bus.h and order the includes. Approved by: re (blanket)
* MFCattilio2011-05-292-12/+14
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| * o Determine the number of LAWs in a way the is future proof. Only themarcel2011-05-281-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | MPC8555(E) has 8 LAWs, so don't make that the default case. Current processors have 12 LAWs so use that as the default instead. o Determine the target ID of the PCI/PCI-X and PCI-E controllers in a way that's more future proof. There's almost a perfect mapping from HC register offset to target ID, so use that as the default. Handle the MPC8548(E) specially, since it has a non-standard target ID for the PCI-E controller. Don't worry about whether the processor implements the target ID here, because we should not get called for PCI/PCI-X or PCI-E host controllers that don't exist.
| * Remove unused defines. They're distracting...marcel2011-05-281-5/+0
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| * Retire isa_setup_intr() and isa_teardown_intr() and use the generic busjhb2011-05-061-17/+0
| | | | | | | | | | | | versions instead. They were never needed as bus_generic_intr() and bus_teardown_intr() had been changed to pass the original child device up in 42734, but the ISA bus was not converted to new-bus until 45720.
* | Fix compilation.attilio2011-05-181-1/+2
| | | | | | | | Submitted by: andreast
* | MFCattilio2011-05-061-17/+0
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* Rename INTR_VEC to MAP_IRQ. From the OFW or FDT we obtain amarcel2011-02-021-3/+3
| | | | | PIC handle with interrupt pin. This we map to the resource called SYS_RES_IRQ.
* Fix the interrupt code, broken 7 months ago. The interrupt frameworkmarcel2011-01-294-103/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | already supported nested PICs, but was limited to having a nested AT-PIC only. With G5 support the need for nested OpenPIC controllers needed to be added. This was done the wrong way and broke the MPC8555 eval system in the process. OFW, as well as FDT, describe the interrupt routing in terms of a controller and an interrupt pin on it. This needs to be mapped to a flat and global resource: the IRQ. The IRQ is the same as the PCI intline and as such needs to be representable in 8 bits. Secondly, ISA support pretty much dictates that IRQ 0-15 should be reserved for ISA interrupts, because of the internal workins of south bridges. Both were broken. This change reverts revision 209298 for a big part and re-implements it simpler. In particular: o The id() method of the PIC I/F is removed again. It's not needed. o The openpic_attach() function has been changed to take the OFW or FDT phandle of the controller as a second argument. All bus attachments that previously used openpic_attach() as the attach method of the device I/F now implement as bus-specific method and pass the phandle_t to the renamed openpic_attach(). o Change powerpc_register_pic() to take a few more arguments. In particular: - Pass the number of IPIs specificly. The number of IRQs carved out for a PIC is the sum of the number of int. pins and IPIs. - Pass a flag indicating whether the PIC is an AT-PIC or not. This tells the interrupt framework whether to assign IRQ 0-15 or some other range. o Until we implement proper multi-pass bus enumeration, we have to handle the case where we need to map from PIC+pin to IRQ *before* the PIC gets registered. This is done in a similar way as before, but rather than carving out 256 IRQs per PIC, we carve out 128 IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case, but should really be fixed properly using multiple passes. o Have the interrupt framework set root_pic in most cases and not put that burden in PIC drivers (for the most part). o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq(). Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN. Related to the above, fix the Freescale PCI controller driver, broken by the FDT code. Besides not attaching properly, bus numbers were assigned improperly and enumeration was broken in general. This prevented the AT PIC from being discovered and interrupt routing to work properly. Consequently, the ata(4) controller stopped functioning. Fix the driver, and FDT PCI support, enough to get the MPC8555CDS going again. The FDT PCI code needs a whole lot more work. No breakages are expected, but lackiong G5 hardware, it's possible that there are unpleasant side-effects. At least MPC85xx support is back to where it was 7 months ago -- it's amazing how badly support can be broken in just 7 months... Sponsored by: Juniper Networks
* Have nexus behave the same as the one on ARM (marvell SoCs), so as tomarcel2011-01-291-8/+17
| | | | prevent warnings during boot WRT to the fdtbus attachment.
* Restructure how reset and poweroff are handled on PowerPC systems, sincenwhitehorn2010-08-311-25/+0
| | | | | | | | | | | | | | | | | the existing code was very platform specific, and broken for SMP systems trying to reboot from KDB. - Add a new PLATFORM_RESET() method to the platform KOBJ interface, and migrate existing reset functions into platform modules. - Modify the OF_reboot() routine to submit the request by hand to avoid the IPIs involved in the regular openfirmware() routine. This fixes reboot from KDB on SMP machines. - Move non-KDB reset and poweroff functions on the Powermac platform into the relevant power control drivers (cuda, pmu, smu), instead of using them through the Open Firmware backdoor. - Rename platform_chrp to platform_powermac since it has become increasingly Powermac specific. When we gain support for IBM systems, we will grow a new platform_chrp.
* Convert Freescale PowerPC platforms to FDT convention.raj2010-07-1114-1990/+1694
| | | | | | | | | | | | | | | | | | | | | | | | | The following systems are affected: - MPC8555CDS - MPC8572DS This overhaul covers the following major changes: - All integrated peripherals drivers for Freescale MPC85XX SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values). - This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC, QUICC, UART, CFI. - Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire ocpbus(4) driver, which was based on hard-coded config data. Note that world for these platforms has to be built WITH_FDT. Reviewed by: imp Sponsored by: The FreeBSD Foundation
* Move the EOI logic when starting ithreads into intr_machdep instead ofnwhitehorn2010-07-061-2/+0
| | | | | relying on it as a side effect of PIC_MASK() in the PIC drivers, and add an inmplementation of assign_cpu() for the kernel interrupt layer.
* Remove the unneeded header <machine/intr.h>.marcel2010-07-022-2/+0
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* Assign PCI intline values for ISA interrupts using the new INTR_VEC()marcel2010-06-241-3/+3
| | | | macro.
* Pass the device_t of the AT PIC driver to atpic_intr() so thatmarcel2010-06-241-5/+2
| | | | | we don't have to use a global variable. Pass a NULL frame pointer to the dispatch function just like openpic(4).
* With openpic(4) using active-low as the default polarity, reconfiguremarcel2010-06-231-2/+9
| | | | | | | | | | the internal interrupt sources as active-high. The internal interrupt sources are disabled when programmed as active-low. Note that the internal interrupts have no sense bit like the external interrupts. We program them as edge-triggered to make sure we write a 0 value to a reserved register. It does not in any way say anything about the sense of internal interrupt.
* Configure interrupts on SMP systems to be distributed among all onlinenwhitehorn2010-06-231-0/+1
| | | | | | CPUs by default, and provide a functional version of BUS_BIND_INTR(). While here, fix some potential concurrency problems in the interrupt handling code.
* Provide for multiple, cascaded PICs on PowerPC systems, and extend thenwhitehorn2010-06-186-29/+58
| | | | | | OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
* Fix an off-by-one bug for the number of slots on a PCI/PCI-X bus.marcel2010-03-231-7/+8
| | | | | We failed to setup PCI devices on slot 31 and that's where the SATA controller is for the P2020 eval board.
* Add definitions for a 4th PCI host controller. No Freescale processormarcel2010-03-232-1/+16
| | | | | | has all 4 implemented, but across the processors we now support all the combinations. For example, the MPC8533 doesn't have a PCI controller at 0xA0000, but does at 0xB0000.
* Make PCI Express host controllers functional, by:marcel2010-02-011-0/+26
| | | | | | | | 1. checking whether there's a link before initializing devices on the bus. When there's no link any access onto the bus will wedge the CPU. 2. synthesizing the class & subclass so that the host controller appears as a standard PCI bridge, rather than a PowerPC CPU.
* Use the capability pointer to indicate whether the host controller ismarcel2010-02-011-12/+13
| | | | | | PCI Express, rather than a bit-field (boolean). Saving the capability pointer this way makes access to capability-specific configuration registers easy and efficient.
* Don't check the device ID. Instead, check the class, subclass andmarcel2010-01-291-28/+13
| | | | | | | | | | | | | programming I/F. New SoC designs have different device IDs, but don't need special treatment. Consequently, we fail to probe and attach for no other reason than not having added the device ID to the code. Bank on Freescale's sense of backward compatibility and assume that if we find a host controller, we know how work with it. This fixes detection of the PCI Express host controllers on Freescale's QorIQ family of processors (P1, P2 and P4).
* Always allocate PCI/ISA interrupts as shareable so that sharedmarcel2009-11-201-0/+1
| | | | interrupts don't cause driver attach failures.
* Do not use OCP85XX_LBC_OFF twice when accessing LBC registers on MPC85XX.raj2009-07-211-4/+4
| | | | | | | | | | | | | | It turns LBC control registers were not programmed correctly on MPC85XX. We were accessing bogus addresses as the base offset (OCP85XX_LBC_OFF) was erroneously added during offset calculations. Effectively the state of LBC control registers was not altered by the kernel initialization code, but everything worked as long as we coincided to use the same settings (LBC decode windows) as firmware has initialized. Submitted by: Lukasz Wojcik Reviewed by: marcel Approved by: re (kensmith) Obtained from: Semihalf
* More precise description of the DS1553 driver.raj2009-06-241-1/+1
| | | | Pointed out by: stas
* DS1553 RTC module driver. On the MPC8555CDS system it hangs off of the LBC bus.raj2009-06-223-0/+435
| | | | Obtained from: Semihalf
* Integrated I2C controller driver (found in MPC85xx and other SOC parts).raj2009-06-221-0/+440
| | | | Obtained from: Freescale, Semihalf
* Initial version of the sec(4) driver for the integrated security engine foundraj2009-06-062-0/+8
| | | | | | | | | | | in Freescale system-on-chip devices. The following algorithms and schemes are currently supported: - 3DES, AES, DES - MD5, SHA1, SHA256, SHA384, SHA512 Reviewed by: philip Obtained from: Freescale, Semihalf
* Mark the cascaded AT interrupt handler as MP safe to avoid havingmarcel2009-05-311-1/+1
| | | | it grab Giant. The next step would be to make it a filter.
* Initial support for SMP on PowerPC MPC85xx.raj2009-05-211-3/+19
| | | | | | Tested with Freescale dual-core MPC8572DS development system. Obtained from: Freescale, Semihalf
* Skip interleaved RAM target on MPC85xx during renitialization of the localraj2009-05-211-1/+2
| | | | | | | | access windows. This eliminates hangs on systems which are configured to use interleaved mode: prior to this fix we were simply cutting ourselves from access to the main memory in this case. Obtained from: Freescale, Semihalf
* Add suppport for ISA and ISA interrupts to make the ATAmarcel2009-04-244-66/+514
| | | | | | | controller in the VIA southbridge functional in the CDS (Configurable Development System) for MPC85XX. The embedded USB controllers look operational but the interrupt steering is still wrong.
* Make MPC85xx LAW handling and reset routines aware of the MPC8548 variant.raj2009-03-133-15/+8
| | | | Inspired by discussion with Alexey V Fedorov on freebsd-powerpc@.
* Extend and improve MPC85XX Local Bus management.raj2008-12-185-69/+346
| | | | | | | | | | | | | | | | | - Make LBC resources management self-contained: introduce explicit LBC resources definition (much like the OCP), provide dedicated rman for LB mem space. - Full configuration of an LB chip select device: program LAW and BR/OR, map into KVA, handle all LB attributes (bus width, machine select, ecc, write protect etc). - Factor out LAW manipulation routines into shared code, adjust OCP area accordingly. - Other LBC fixes and clean-ups. Obtained from: Semihalf
* Minor clean up of BookE/MPC85XX: iprove naming and style(9).raj2008-12-171-6/+2
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* Improve MPC85XX helper routines.raj2008-12-173-28/+65
| | | | | | - Move CCSR accessors to the shared MPC85XX area - Simplify SVR version subfield handling - Adjust OCP
* Add a driver for the Local Bus Controller.marcel2008-10-252-0/+368
| | | | Obtained from: Juniper Networks, Inc.
* Assign 0xff800000-0xffffffff to the LBC controller. That's wheremarcel2008-10-251-0/+4
| | | | the NOR flash lives by default.
* Remove mfsvr():marcel2008-04-272-2/+2
| | | | | | o The function is defined unconditionally but depends on SPR_SVR, which is defined conditionally. o spr.h defines mfspr() and mtspr(), which is no worse to use.
* Use RSTCR for resetting the MPC8572 (the old way does not apply).raj2008-04-262-7/+25
| | | | Obtained from: Freescale, Semihalf
* Introduce a dedicated file for MPC85xx-specific routines. Move cpu_reset()raj2008-04-261-0/+59
| | | | | there, as it's not relevant to Book-E specification, but is an implementation detail, directly dependent on the given SoC version.
* Improve handling of Local Access Windows on MPC85xx systems:raj2008-04-263-19/+39
| | | | | | | | - detect number of LAWs in run time and initalize accordingly - introduce decode windows target IDs used in MPC8572 - other minor updates Obtained from: Freescale, Semihalf
* Obtain TSEC h/w address from the parent bus (OCP) and not rely blindly on whatraj2008-03-121-0/+9
| | | | | | | | | | | | might be currently programmed into the registers. Underlying firmware (U-Boot) would typically program MAC address into the first unit only, and others are left uninitialized. It is now possible to retrieve and program MAC address for all units properly, provided they were passed on in the bootinfo metadata. Reviewed by: imp, marcel Approved by: cognet (mentor)
* Don't use in32() and out32() when writing to the CCSRBAR. Themarcel2008-03-091-9/+26
| | | | | | in*() and out*() primitives should not be used, other than by ISA drivers. In this case they were used for memory-mapped I/O and were not even used in the spirit of the primitives.
* Add support for the BUS_CONFIG_INTR() method to the platform and tomarcel2008-03-072-0/+17
| | | | | openpic(4). Make use of it in ocpbus(4). On the MPC85xxCDS, IRQ0:4 are active-low.
* o We don't have to keep track of the PIC, nor do we have to make suremarcel2008-03-051-28/+39
| | | | | | | it's probed first. The PowerPC platform code deals with everything. As such, probe devices in order of their location in the memory map. o Refactor the ocpbus_alloc_resource for readability and make sure we set the RID in the resource as per the new convention.
* o Various fixes related to PCI Express:marcel2008-03-051-37/+65
| | | | | | | | | | | | | | | | | | | | | | | | | - Even for the PCI Express host controller we need to use bus 0 for configuration space accesses to devices directly on the host controller's bus. - Pass the maximum number of slots to pci_ocp_init() because the caller knows how many slots the bus has. Previously a PCI or PCI-X bus underneath a PCI Express host controller would not be enumerated properly. o Pull the interrupt routing logic out of pci_ocp_init() and into its own function. The logic is not quite right and is expected to be a bit more complex. o Fix/add support for PCI domains. The PCI domain is the unit number as per other PCI host controller drivers. As such, we can use logical bus numbers again and don't have to guarantee globally unique bus numbers. Remove pci_ocp_busnr. Return the highest bus number ito the caller of pci_ocp_init() now that we don't have a global variable anymore. o BAR programming fixes: - Non-type0 headers have at most 1 BAR, not 0. - First write ~0 to the BAR in question and then read back its size. Obtained from: Juniper Networks (mostly)
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