diff options
| author | raj <raj@FreeBSD.org> | 2009-05-21 11:43:37 +0000 |
|---|---|---|
| committer | raj <raj@FreeBSD.org> | 2009-05-21 11:43:37 +0000 |
| commit | 84c7ebbafb3a322fc56b7ab3250657ab53cdd04b (patch) | |
| tree | ebbbb7780339b9700c01fbc128912a6b8e5e5257 /sys/powerpc/mpc85xx | |
| parent | e0229d3977fbe246e110f6fb915f0719e6f7356a (diff) | |
| download | FreeBSD-src-84c7ebbafb3a322fc56b7ab3250657ab53cdd04b.zip FreeBSD-src-84c7ebbafb3a322fc56b7ab3250657ab53cdd04b.tar.gz | |
Initial support for SMP on PowerPC MPC85xx.
Tested with Freescale dual-core MPC8572DS development system.
Obtained from: Freescale, Semihalf
Diffstat (limited to 'sys/powerpc/mpc85xx')
| -rw-r--r-- | sys/powerpc/mpc85xx/ocpbus.h | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/sys/powerpc/mpc85xx/ocpbus.h b/sys/powerpc/mpc85xx/ocpbus.h index 2c63804..f33f547 100644 --- a/sys/powerpc/mpc85xx/ocpbus.h +++ b/sys/powerpc/mpc85xx/ocpbus.h @@ -31,7 +31,18 @@ #define _MACHINE_OCP85XX_H_ /* - * Local access registers. + * Configuration control and status registers + */ +#define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0) +#define OCP85XX_BPTR (CCSRBAR_VA + 0x20) + +/* + * E500 Coherency Module registers + */ +#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010) + +/* + * Local access registers */ #define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n)) #define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n)) @@ -46,7 +57,12 @@ #define OCP85XX_TGTIF_RAM2 22 /* - * Power-On Reset configuration. + * L2 cache registers + */ +#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000) + +/* + * Power-On Reset configuration */ #define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c) #define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014) @@ -61,7 +77,7 @@ */ #define OCP85XX_I2C0_OFF 0x03000 #define OCP85XX_I2C1_OFF 0x03100 -#define OCP85XX_I2C_SIZE 0x15 +#define OCP85XX_I2C_SIZE 0x16 #define OCP85XX_UART0_OFF 0x04500 #define OCP85XX_UART1_OFF 0x04600 #define OCP85XX_UART_SIZE 0x10 |
