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* Print machine check address for Book-E.jhibbits2015-11-301-0/+2
| | | | | | | Bits in mcsr indicate if the address is valid, and whether it's a physical address or effective address. Sponsored by: Alex Perez/Inertial Computing
* Add PVR identifier for E6500, from the reference.jhibbits2015-09-091-0/+1
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* Add machine check register printingjhibbits2015-07-041-0/+8
| | | | | | | This will print out the Memory Subsystem Status Register on MPC745x (G4+ class), and the Machine Check Status Register on Book-E class CPUs, to aid in debugging machine checks. Other relevant registers, for other CPUs, can be added in the future.
* Add a new CPU id for a POWER8 variant.nwhitehorn2014-07-061-1/+2
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* Add hwpmc(4) support for the PowerPC 970 class processors, direct events.jhibbits2014-02-011-15/+21
| | | | | | | | | | | This also fixes asserts on removal of the module for the mpc74xx. The PowerPC 970 processors have two different types of events: direct events and indirect events. Thus far only direct events are supported. I included some documentation in the driver on how indirect events work, but support is for the future. MFC after: 1 month
* Add PMU-based CPU frequency scaling. This method is used on most Titaniumjhibbits2013-12-131-0/+4
| | | | | | PowerBooks. MFC after: 1 month
* Add POWER7+ and POWER8 to the CPU ID table.nwhitehorn2013-09-171-0/+2
| | | | Approved by: re (kib)
* Remove duplicate definition of SPR MMCR0.jhibbits2013-08-031-1/+0
| | | | MFC after: 3 days
* On Nintendo Wii CPUs, the mdp value will be garbage. Set it to NULLadrian2012-08-211-0/+1
| | | | | | so as to not confuse things. Submitted by: Margarida Gouveia
* Let us manage differences of Book-E PowerPC variations i.e. vendor /raj2012-05-271-5/+12
| | | | | | | | | | | | implementation specific vs. the common architecture definition. Bring PPC4XX defines (PSL, SPR, TLB). Note the new definitions under BOOKE_PPC4XX are not used in the code yet. This change set is not supposed to affect existing E500 support, it's just another reorg step before bringing support for E500mc, E5500 and PPC465. Obtained from: AppliedMicro, Freescale, Semihalf
* Provide SPR definitions for newer Book-E (E500mc, E5500, PPC465).raj2012-05-261-0/+36
| | | | Obtained from: Freescale, Semihalf.
* Unify SPR defines formatting, no funtional changes.raj2012-05-261-88/+87
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* Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x).jhibbits2011-12-241-6/+6
| | | | | | | Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
* o Add system versions for the P4040(E) and P4080(E).marcel2011-05-291-0/+4
| | | | | | | | | o In bare_probe(), change the logic that determines the maximum number of processors/cores into a switch statement and take advantage of the fact that bit 3 of the SVR value indicates whether we're running on a security enabled version. Since we don't care about that here, mask the bit. All -E versions are taken care of automatically.
* o Swap the SVR numbers for MPC8533 & MPC8533Emarcel2011-05-271-2/+10
| | | | o Add SVR defines for P1011(E), P1020(E), P2010(E) & P2020(E)
* Fix handling of NX pages on capable CPUs. Thanks to kib for prodding menwhitehorn2011-01-131-0/+3
| | | | in the right direction.
* Add CPU support code for the IBM Cell Broadband Engine.nwhitehorn2010-11-121-0/+4
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* MFppc64:nwhitehorn2010-07-131-1/+19
| | | | | | | Kernel sources for 64-bit PowerPC, along with build-system changes to keep 32-bit kernels compiling (build system changes for 64-bit kernels are coming later). Existing 32-bit PowerPC kernel configurations must be updated after this change to specify their architecture.
* The NetBSD Foundation has granted permission to remove clause 3 and 4 fromjoel2010-03-031-7/+0
| | | | | | their software. Obtained from: NetBSD
* Add SMP support on U3-based G5 systems. This does not yet work perfectly:nwhitehorn2009-10-231-4/+4
| | | | | | | | | | at least on my Xserve, getting the decrementer and timebase on APs to tick requires setting up a clock chip over I2C, which is not yet done. While here, correct the 64-bit tlbie function to set the CPU to 64-bit mode correctly. Hardware donated by: grehan
* Fix copy/paste typo in last revision. PMC0 control should be shifted 8nwhitehorn2009-06-231-1/+1
| | | | bits, not 6, on the PPC 970.
* Teach cpu_est_clockrate() about the G5's slightly different PMC. Thisnwhitehorn2009-06-171-1/+24
| | | | | allows the boot messages to include the CPU speed and makes possible the forthcoming cpufreq support for the PPC 970.
* Initial support for SMP on PowerPC MPC85xx.raj2009-05-211-0/+3
| | | | | | Tested with Freescale dual-core MPC8572DS development system. Obtained from: Freescale, Semihalf
* PowerPC common SMP startup and time base rework.raj2009-05-141-2/+0
| | | | | | | | | | - make mftb() shared, rewrite in C, provide complementary mttb() - adjust SMP startup per the above, additional comments, minor naming changes - eliminate redundant TB defines, other minor cosmetics Reviewed by: marcel, nwhitehorn Obtained from: Freescale, Semihalf
* Factor out platform dependent things unrelated to device drivers into anwhitehorn2009-05-141-0/+1
| | | | | | | | | | new platform module. These are probed in early boot, and have the responsibility of determining the layout of physical memory, determining the CPU timebase frequency, and handling the zoo of SMP mechanisms found on PowerPC. Reviewed by: marcel, raj Book-E parts by: raj
* Rework the way we get the cacheline size. Instead of having a table ofnwhitehorn2009-04-121-0/+2
| | | | | | CPUs known to use 128 byte cache lines and defaulting to 32, use the dcbz instruction to measure it. Also make dcbz behave the way you would expect on PPC 970.
* Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge modenwhitehorn2009-04-041-0/+42
| | | | | | | | | | provided, for example, on the PowerPC 970 (G5), as well as on related CPUs like the POWER3 and POWER4. This also adds support for various built-in hardware found on Apple G5 hardware (e.g. the IBM CPC925 northbridge). Reviewed by: grehan
* Make MPC85xx LAW handling and reset routines aware of the MPC8548 variant.raj2009-03-131-0/+2
| | | | Inspired by discussion with Alexey V Fedorov on freebsd-powerpc@.
* Improve MPC85XX helper routines.raj2008-12-171-9/+9
| | | | | | - Move CCSR accessors to the shared MPC85XX area - Simplify SVR version subfield handling - Adjust OCP
* o Remove SPR_TSR & SPR_TCR for AIM.marcel2008-09-151-8/+23
| | | | | o Remove SPR_HID2. o Add more SPR_L3CR bit definitions.
* Move System Revision defines to a bit better place, add MPC8572 systems IDs.raj2008-04-261-9/+9
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* Rework and extend PowerPC headers definitons towards Book-E/e500 CPUs support.raj2008-03-031-19/+148
| | | | | | Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
* Teach PowerPC CPU identification routines to recognize e500 cores. Fix styleraj2008-02-251-0/+2
| | | | | | | issues in this area. Approved by: cognet (mentor) MFp4: e500
* - add definitions for MPC7447A/7448 (i.e. miniMac)grehan2005-02-041-1/+3
| | | | | | - expand MPC745X_P macro to include these Obtained from: NetBSD
* /* -> /*- for license, minor formatting changesimp2005-01-071-1/+1
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* Definitions for MPC7457 CPU type and HID0 bitsgrehan2004-02-091-0/+2
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* - Update spr.hbenno2003-02-051-79/+196
| | | | | | | | | | - Add hid.h Obtained from: NetBSD NOTE: This undoes some changes I'd made to prefix the processor name defines with PVR_. This was due to my original decision to use MPC750 as a cpu name. With this changed, the PVR_ change is no longer required.
* Rename the constants for the contents of the PVR register so as not tobenno2002-05-091-17/+17
| | | | conflict with cpu names used in config files..
* Commit of stuff that's been sitting in my tree for a while.benno2002-04-291-0/+360
Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
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