| Commit message (Collapse) | Author | Age | Files | Lines |
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Bits in mcsr indicate if the address is valid, and whether it's a physical
address or effective address.
Sponsored by: Alex Perez/Inertial Computing
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This will print out the Memory Subsystem Status Register on MPC745x (G4+ class),
and the Machine Check Status Register on Book-E class CPUs, to aid in debugging
machine checks. Other relevant registers, for other CPUs, can be added in the
future.
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This also fixes asserts on removal of the module for the mpc74xx.
The PowerPC 970 processors have two different types of events: direct events
and indirect events. Thus far only direct events are supported. I included
some documentation in the driver on how indirect events work, but support is
for the future.
MFC after: 1 month
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PowerBooks.
MFC after: 1 month
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Approved by: re (kib)
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MFC after: 3 days
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so as to not confuse things.
Submitted by: Margarida Gouveia
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implementation specific vs. the common architecture definition.
Bring PPC4XX defines (PSL, SPR, TLB). Note the new definitions under
BOOKE_PPC4XX are not used in the code yet.
This change set is not supposed to affect existing E500 support, it's just
another reorg step before bringing support for E500mc, E5500 and PPC465.
Obtained from: AppliedMicro, Freescale, Semihalf
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Obtained from: Freescale, Semihalf.
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Sampling is in progress.
Approved by: nwhitehorn (mentor)
MFC after: 9.0-RELEASE
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o In bare_probe(), change the logic that determines the maximum
number of processors/cores into a switch statement and take
advantage of the fact that bit 3 of the SVR value indicates
whether we're running on a security enabled version. Since we
don't care about that here, mask the bit. All -E versions
are taken care of automatically.
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o Add SVR defines for P1011(E), P1020(E), P2010(E) & P2020(E)
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in the right direction.
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Kernel sources for 64-bit PowerPC, along with build-system changes to keep
32-bit kernels compiling (build system changes for 64-bit kernels are
coming later). Existing 32-bit PowerPC kernel configurations must be
updated after this change to specify their architecture.
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their software.
Obtained from: NetBSD
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at least on my Xserve, getting the decrementer and timebase on APs to tick
requires setting up a clock chip over I2C, which is not yet done.
While here, correct the 64-bit tlbie function to set the CPU to 64-bit
mode correctly.
Hardware donated by: grehan
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bits, not 6, on the PPC 970.
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allows the boot messages to include the CPU speed and makes possible
the forthcoming cpufreq support for the PPC 970.
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Tested with Freescale dual-core MPC8572DS development system.
Obtained from: Freescale, Semihalf
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- make mftb() shared, rewrite in C, provide complementary mttb()
- adjust SMP startup per the above, additional comments, minor naming
changes
- eliminate redundant TB defines, other minor cosmetics
Reviewed by: marcel, nwhitehorn
Obtained from: Freescale, Semihalf
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new platform module. These are probed in early boot, and have the
responsibility of determining the layout of physical memory, determining
the CPU timebase frequency, and handling the zoo of SMP mechanisms
found on PowerPC.
Reviewed by: marcel, raj
Book-E parts by: raj
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CPUs known to use 128 byte cache lines and defaulting to 32, use the dcbz
instruction to measure it. Also make dcbz behave the way you would
expect on PPC 970.
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provided, for example, on the PowerPC 970 (G5), as well as on related CPUs
like the POWER3 and POWER4.
This also adds support for various built-in hardware found on Apple G5
hardware (e.g. the IBM CPC925 northbridge).
Reviewed by: grehan
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Inspired by discussion with Alexey V Fedorov on freebsd-powerpc@.
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- Move CCSR accessors to the shared MPC85XX area
- Simplify SVR version subfield handling
- Adjust OCP
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o Remove SPR_HID2.
o Add more SPR_L3CR bit definitions.
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Approved by: cognet (mentor)
Obtained from: Juniper, Semihalf
MFp4: e500
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issues in this area.
Approved by: cognet (mentor)
MFp4: e500
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- expand MPC745X_P macro to include these
Obtained from: NetBSD
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- Add hid.h
Obtained from: NetBSD
NOTE: This undoes some changes I'd made to prefix the processor name defines
with PVR_. This was due to my original decision to use MPC750 as a cpu name.
With this changed, the PVR_ change is no longer required.
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conflict with cpu names used in config files..
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Highlights include:
- New low-level trap code from NetBSD. The high level code still needs a lot
of work.
- Fixes for some pmap handling in thread switching.
- The kernel will now get to attempting to jump into init in user mode. There
are some pmap/trap issues which prevent it from actually getting there though.
Obtained from: NetBSD (parts)
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