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| author | jhibbits <jhibbits@FreeBSD.org> | 2011-12-24 19:34:52 +0000 |
|---|---|---|
| committer | jhibbits <jhibbits@FreeBSD.org> | 2011-12-24 19:34:52 +0000 |
| commit | 8eb9e6b5487506b4d0f3e50d440fac3e93baf702 (patch) | |
| tree | cfe656c61e3dc2689d74c276ee2249f54a375705 /sys/powerpc/include/spr.h | |
| parent | 710f17be3ba715e7a297bf62e3944f4b95dd9fef (diff) | |
| download | FreeBSD-src-8eb9e6b5487506b4d0f3e50d440fac3e93baf702.zip FreeBSD-src-8eb9e6b5487506b4d0f3e50d440fac3e93baf702.tar.gz | |
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x).
Sampling is in progress.
Approved by: nwhitehorn (mentor)
MFC after: 9.0-RELEASE
Diffstat (limited to 'sys/powerpc/include/spr.h')
| -rw-r--r-- | sys/powerpc/include/spr.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h index 4f675c3..e356987 100644 --- a/sys/powerpc/include/spr.h +++ b/sys/powerpc/include/spr.h @@ -348,8 +348,8 @@ #define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ #define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ #define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ -#define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */ -#define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */ +#define SPR_MMCR0_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */ +#define SPR_MMCR0_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */ #define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ #define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ #define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ @@ -359,10 +359,10 @@ #define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ #define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ #define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ -#define SPR_MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */ -#define SPR_MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */ -#define SPR_MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */ -#define SPR_MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */ +#define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ +#define SPR_MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ +#define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ +#define SPR_MMCR1_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */ #define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */ #define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ |
