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| author | nwhitehorn <nwhitehorn@FreeBSD.org> | 2009-04-12 03:03:55 +0000 |
|---|---|---|
| committer | nwhitehorn <nwhitehorn@FreeBSD.org> | 2009-04-12 03:03:55 +0000 |
| commit | 32d233ecc5d49b564b71d9c7c48f3ad1980ab59f (patch) | |
| tree | 79c849a2370af4a5db95ef5e30a993a3e85dcdd5 /sys/powerpc/include/spr.h | |
| parent | 692f8aa2fac966ef1adc29843ad741d355db1ecd (diff) | |
| download | FreeBSD-src-32d233ecc5d49b564b71d9c7c48f3ad1980ab59f.zip FreeBSD-src-32d233ecc5d49b564b71d9c7c48f3ad1980ab59f.tar.gz | |
Rework the way we get the cacheline size. Instead of having a table of
CPUs known to use 128 byte cache lines and defaulting to 32, use the dcbz
instruction to measure it. Also make dcbz behave the way you would
expect on PPC 970.
Diffstat (limited to 'sys/powerpc/include/spr.h')
| -rw-r--r-- | sys/powerpc/include/spr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h index eb07208..84fab0d 100644 --- a/sys/powerpc/include/spr.h +++ b/sys/powerpc/include/spr.h @@ -391,6 +391,8 @@ #define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ #define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ +#define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ +#define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ #if defined(AIM) #define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ |
