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-rw-r--r--zpu/hdl/avalanche/core/zpu_core.v749
-rw-r--r--zpu/hdl/avalanche/core/zpu_core_defines.v322
-rw-r--r--zpu/hdl/avalanche/core/zpu_core_rom.v1017
-rw-r--r--zpu/hdl/avalanche/readme.txt91
-rw-r--r--zpu/hdl/example/.cvsignore3
-rw-r--r--zpu/hdl/example/bram_dmips.vhd3356
-rw-r--r--zpu/hdl/example/helloworld.vhd3154
-rw-r--r--zpu/hdl/example/interrupt.vhd3156
-rw-r--r--zpu/hdl/example/log.txt20
-rw-r--r--zpu/hdl/example/sim_small_fpga_top.vhd197
-rw-r--r--zpu/hdl/example/sim_small_fpga_top_noint.vhd184
-rw-r--r--zpu/hdl/example/simzpu_dmips.do29
-rw-r--r--zpu/hdl/example/simzpu_interrupt.do29
-rw-r--r--zpu/hdl/example/simzpu_small.do29
-rw-r--r--zpu/hdl/example/zpu_config.vhd55
-rw-r--r--zpu/hdl/example/zpuromgen.c59
-rw-r--r--zpu/hdl/example/zpuromgen.exebin0 -> 10274 bytes
-rw-r--r--zpu/hdl/example_ghdl/README44
-rw-r--r--zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh24
-rw-r--r--zpu/hdl/example_ghdl/dmipstrace_ghdl.sh24
-rw-r--r--zpu/hdl/example_ghdl/ghdl_import.sh16
-rw-r--r--zpu/hdl/example_ghdl/ghdl_make.sh4
-rw-r--r--zpu/hdl/example_ghdl/ghdl_options.sh2
-rw-r--r--zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh24
-rw-r--r--zpu/hdl/example_medium/.cvsignore4
-rw-r--r--zpu/hdl/example_medium/dram_dmips.vhd3308
-rw-r--r--zpu/hdl/example_medium/dram_hello.vhd3107
-rw-r--r--zpu/hdl/example_medium/sim_fpga_top.vhd194
-rw-r--r--zpu/hdl/example_medium/simzpu_medium.do28
-rw-r--r--zpu/hdl/example_medium/zpu_config_trace.vhd17
-rw-r--r--zpu/hdl/sim/dmipssmalltrace.do26
-rw-r--r--zpu/hdl/sim/dmipstrace.do30
-rw-r--r--zpu/hdl/spi/spi_controller.v235
-rw-r--r--zpu/hdl/wishbone/wishbone_pkg.vhd86
-rw-r--r--zpu/hdl/wishbone/zpu_system.vhd104
-rw-r--r--zpu/hdl/wishbone/zpu_wb_bridge.vhd83
-rw-r--r--zpu/hdl/zealot/0README.txt195
-rw-r--r--zpu/hdl/zealot/BSD20
-rw-r--r--zpu/hdl/zealot/GPL_V2341
-rw-r--r--zpu/hdl/zealot/devices/br_gen.vhdl91
-rw-r--r--zpu/hdl/zealot/devices/gpio.vhdl107
-rw-r--r--zpu/hdl/zealot/devices/phi_io.vhdl257
-rw-r--r--zpu/hdl/zealot/devices/rx_unit.vhdl108
-rw-r--r--zpu/hdl/zealot/devices/timer.vhdl91
-rw-r--r--zpu/hdl/zealot/devices/trace.vhdl258
-rw-r--r--zpu/hdl/zealot/devices/tx_unit.vhdl109
-rw-r--r--zpu/hdl/zealot/devices/txt_util.vhdl541
-rwxr-xr-xzpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh16
-rwxr-xr-xzpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh49
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do2
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do30
-rwxr-xr-xzpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh36
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf397
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj19
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut29
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst56
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd372
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd194
-rwxr-xr-xzpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh16
-rwxr-xr-xzpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh49
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do2
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do30
-rwxr-xr-xzpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh36
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf482
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj19
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut39
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst60
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd444
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd271
-rwxr-xr-xzpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh16
-rwxr-xr-xzpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh49
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do2
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do30
-rwxr-xr-xzpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh36
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf356
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj19
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut22
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst56
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd464
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd281
-rw-r--r--zpu/hdl/zealot/fpga/dmips_med1.vhdl119
-rw-r--r--zpu/hdl/zealot/fpga/dmips_small1.vhdl120
-rw-r--r--zpu/hdl/zealot/fpga/hello_med1.vhdl119
-rw-r--r--zpu/hdl/zealot/fpga/hello_small1.vhdl120
-rwxr-xr-xzpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh16
-rwxr-xr-xzpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh49
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do2
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do163
-rwxr-xr-xzpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh36
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj19
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut30
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst53
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf303
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd574
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd402
-rw-r--r--zpu/hdl/zealot/helpers/zpu_med1.vhdl187
-rw-r--r--zpu/hdl/zealot/helpers/zpu_small1.vhdl153
-rw-r--r--zpu/hdl/zealot/roms/dmips_bram.vhdl4462
-rw-r--r--zpu/hdl/zealot/roms/dmips_dbram.vhdl4485
-rw-r--r--zpu/hdl/zealot/roms/hello_bram.vhdl3056
-rw-r--r--zpu/hdl/zealot/roms/hello_dbram.vhdl3035
-rw-r--r--zpu/hdl/zealot/roms/rom_pkg.vhdl80
-rw-r--r--zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl134
-rw-r--r--zpu/hdl/zealot/testbenches/small1_tb.vhdl134
-rw-r--r--zpu/hdl/zealot/zpu_medium.vhdl948
-rw-r--r--zpu/hdl/zealot/zpu_pkg.vhdl292
-rw-r--r--zpu/hdl/zealot/zpu_small.vhdl472
-rw-r--r--zpu/hdl/zpu4/core/histogram.perl218
-rw-r--r--zpu/hdl/zpu4/core/zpu_config.vhd58
-rw-r--r--zpu/hdl/zpu4/core/zpu_core.vhd1014
-rw-r--r--zpu/hdl/zpu4/core/zpu_core_small.vhd602
-rw-r--r--zpu/hdl/zpu4/core/zpupkg.vhd218
-rw-r--r--zpu/hdl/zpu4/src/.cvsignore5
-rw-r--r--zpu/hdl/zpu4/src/clocks.vhd198
-rw-r--r--zpu/hdl/zpu4/src/io.vhd119
-rw-r--r--zpu/hdl/zpu4/src/timer.vhd61
-rw-r--r--zpu/hdl/zpu4/src/trace.vhd107
-rw-r--r--zpu/hdl/zpu4/src/txt_util.vhd539
-rw-r--r--zpu/hdl/zpu4/src/zpuio.vhd218
-rwxr-xr-xzpu/hdl/zpu4/test/dmips/build.sh4
-rw-r--r--zpu/hdl/zpu4/test/dmips/dmips.binbin0 -> 13028 bytes
-rw-r--r--zpu/hdl/zpu4/test/dmips/dmips.elfbin0 -> 82460 bytes
-rw-r--r--zpu/hdl/zpu4/test/dmips/dmips.ram3256
-rwxr-xr-xzpu/hdl/zpu4/test/gpiotest/build.sh4
-rw-r--r--zpu/hdl/zpu4/test/gpiotest/gpiotest.c72
-rwxr-xr-xzpu/hdl/zpu4/test/hello/build.sh4
-rw-r--r--zpu/hdl/zpu4/test/hello/hello.binbin0 -> 12224 bytes
-rw-r--r--zpu/hdl/zpu4/test/hello/hello.c47
-rw-r--r--zpu/hdl/zpu4/test/hello/hello.elfbin0 -> 150384 bytes
-rw-r--r--zpu/hdl/zpu4/test/hello/hello.ram3055
-rwxr-xr-xzpu/hdl/zpu4/test/interrupt/build.sh4
-rw-r--r--zpu/hdl/zpu4/test/interrupt/int.binbin0 -> 12232 bytes
-rw-r--r--zpu/hdl/zpu4/test/interrupt/int.c40
-rw-r--r--zpu/hdl/zpu4/test/interrupt/int.elfbin0 -> 150458 bytes
-rw-r--r--zpu/hdl/zpu4/test/interrupt/int.ram3057
-rw-r--r--zpu/hdl/zy2000/timer.vhd137
-rw-r--r--zpu/hdl/zy2000/trace.vhd84
-rw-r--r--zpu/hdl/zy2000/txt_util.vhd587
-rw-r--r--zpu/hdl/zy2000/zpu_config.vhd20
-rw-r--r--zpu/hdl/zy2000/zpu_config_fast.vhd20
-rw-r--r--zpu/hdl/zy2000/zpu_core.vhd948
-rw-r--r--zpu/hdl/zy2000/zpupkg.vhd168
142 files changed, 60334 insertions, 0 deletions
diff --git a/zpu/hdl/avalanche/core/zpu_core.v b/zpu/hdl/avalanche/core/zpu_core.v
new file mode 100644
index 0000000..e704fbc
--- /dev/null
+++ b/zpu/hdl/avalanche/core/zpu_core.v
@@ -0,0 +1,749 @@
+`timescale 1ns / 1ps
+`include "zpu_core_defines.v"
+
+/* MODULE: zpu_core
+ DESCRIPTION: Contains ZPU cpu
+ AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com)
+
+REVISION HISTORY:
+Revision 1.0, 14/09/2009
+Initial public release
+
+COPYRIGHT:
+Copyright (c) 2009 Antonio J. Anton
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.*/
+
+// --------- MICROPROGRAMMED ZPU CORE ---------------
+// all signals are polled on clk rising edge
+// all signals positive
+
+module zpu_core (
+`ifdef ENABLE_CPU_INTERRUPTS
+ interrupt, // interrupt request
+`endif
+ clk, // clock on rising edge
+ reset, // reset on rising edge
+ mem_read, // request memory read
+ mem_write, // request memory write
+ mem_done, // memory operation completed
+ mem_addr, // memory address
+ mem_data_read, // data readed
+ mem_data_write, // data written
+ byte_select // byte select on memory operation
+);
+
+input clk;
+input reset;
+output mem_read;
+output mem_write;
+input mem_done;
+input [31:0] mem_data_read;
+output [31:0] mem_data_write;
+output [31:0] mem_addr;
+output [3:0] byte_select;
+`ifdef ENABLE_CPU_INTERRUPTS
+input interrupt;
+`endif
+
+wire clk;
+wire reset;
+wire mem_read;
+wire mem_write;
+wire mem_done;
+wire [31:0] mem_data_read;
+wire [31:0] mem_data_write;
+wire [31:0] mem_addr;
+`ifdef ENABLE_CPU_INTERRUPTS
+wire interrupt;
+`endif
+
+`ifdef ENABLE_BYTE_SELECT
+// ------ unaligned byte/halfword memory operations -----
+/// TODO: think rewriting into microcode or in a less resource wasting way
+
+reg [3:0] byte_select;
+wire byte_op;
+wire halfw_op;
+
+reg [31:0] mem_data_read_int; // aligned data from memory
+reg [31:0] mem_data_write_out; // write data already aligned
+wire [31:0] mem_data_write_int; // write data from cpu to be aligned
+
+// --- byte select logic ---
+always @(mem_addr[1:0] or byte_op or halfw_op)
+begin
+ casez( { mem_addr[1:0], byte_op, halfw_op } )
+ 4'b00_1_? : byte_select <= 4'b0001; // byte select
+ 4'b01_1_? : byte_select <= 4'b0010;
+ 4'b10_1_? : byte_select <= 4'b0100;
+ 4'b11_1_? : byte_select <= 4'b1000;
+ 4'b0?_0_1 : byte_select <= 4'b0011; // half word select
+ 4'b1?_0_1 : byte_select <= 4'b1100;
+ default : byte_select <= 4'b1111; // word select
+ endcase
+end
+
+// --- input data to cpu ---
+always @(mem_data_read or mem_addr[1:0] or byte_op or halfw_op)
+begin
+ casez( { mem_addr[1:0], byte_op, halfw_op } )
+ 4'b00_1_? : mem_data_read_int <= { 24'b0, mem_data_read[7:0] }; // 8 bit read
+ 4'b01_1_? : mem_data_read_int <= { 24'b0, mem_data_read[15:8] };
+ 4'b10_1_? : mem_data_read_int <= { 24'b0, mem_data_read[23:16] };
+ 4'b11_1_? : mem_data_read_int <= { 24'b0, mem_data_read[31:24] };
+ 4'b0?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[7:0], mem_data_read[15:8] }; // 16 bit read
+ 4'b1?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[23:16], mem_data_read[31:24] };
+ default : mem_data_read_int <= { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] }; // 32 bit access (default)
+ endcase
+end
+
+// --- output data from cpu ---
+assign mem_data_write = mem_data_write_out;
+
+always @(mem_data_write_int or mem_addr[1:0] or byte_op or halfw_op)
+begin
+ casez( {mem_addr[1:0], byte_op, halfw_op } )
+ 4'b00_1_? : mem_data_write_out <= { 24'bX, mem_data_write_int[7:0] }; // 8 bit write
+ 4'b01_1_? : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], 8'bX };
+ 4'b10_1_? : mem_data_write_out <= { 8'bX, mem_data_write_int[7:0], 16'bX };
+ 4'b11_1_? : mem_data_write_out <= { mem_data_write_int[7:0], 24'bX };
+ 4'b0?_0_1 : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], mem_data_write_int[15:8] }; // 16 bit write
+ 4'b1?_0_1 : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], 16'bX };
+ default : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
+ endcase
+end
+`else
+// -------- only 32 bit memory access --------
+wire [3:0] byte_select = 4'b1111; // all memory operations are 32 bit wide
+wire [31:0] mem_data_read_int; // no byte/halfword memory access by HW
+wire [31:0] mem_data_write_int; // byte and halfword memory access must be emulated
+
+// ----- reorder bytes due to MSB-LSB configuration -----
+assign mem_data_read_int = { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] };
+assign mem_data_write = { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
+`endif
+
+// ------ datapath registers and connections -----------
+reg [31:0] pc; // program counter (byte align)
+reg [31:0] sp; // stack counter (word align)
+reg [31:0] a; // operand (address_out, data_out, alu_in)
+reg [31:0] b; // operand (address_out)
+reg idim; // im opcode being processed
+reg [7:0] opcode; // opcode being processed
+reg [31:2] pc_cached; // cached PC
+reg [31:0] opcode_cache; // cached opcodes (current word)
+`ifdef ENABLE_CPU_INTERRUPTS
+ reg int_requested; // interrupt has been requested
+ reg on_interrupt; // serving interrupt
+ wire exit_interrupt; // microcode says this is poppc_interrupt
+ wire enter_interrupt; // microcode says we are entering interrupt
+`endif
+wire [1:0] sel_opcode = pc[1:0]; // which opcode is selected
+wire sel_read; // mux for data-in
+wire [1:0] sel_alu; // mux for alu
+wire [1:0] sel_addr; // mux for addr
+wire w_pc; // write PC
+`ifdef ENABLE_PC_INCREMENT
+ wire w_pc_increment; // write PC+1
+`endif
+wire w_sp; // write SP
+wire w_a; // write A (from ALU result)
+wire w_a_mem; // write A (from MEM read)
+wire w_b; // write B
+wire w_op; // write OPCODE (opcode cache)
+wire set_idim; // set IDIM
+wire clear_idim; // clear IDIM
+wire is_op_cached = (pc[31:2] == pc_cached) ? 1'b1 : 1'b0; // is opcode available?
+wire a_is_zero; // A == 0
+wire a_is_neg; // A[31] == 1
+wire busy; // busy signal to microcode sequencer (stalls cpu)
+
+reg [`MC_MEM_BITS-1:0] mc_pc; // microcode PC
+initial mc_pc <= `MC_ADDR_RESET-1;
+wire [`MC_BITS-1:0] mc_op; // current microcode operation
+
+// memory addr / write ports
+assign mem_addr = (sel_addr == `SEL_ADDR_SP) ? sp :
+ (sel_addr == `SEL_ADDR_A) ? a :
+ (sel_addr == `SEL_ADDR_B) ? b : pc;
+assign mem_data_write_int = a; // only A can be written to memory
+
+// ------- alu instantiation -------
+wire [31:0] alu_a;
+wire [31:0] alu_b;
+wire [31:0] alu_r;
+wire [`ALU_OP_WIDTH-1:0] alu_op;
+wire alu_done;
+
+// alu inputs multiplexors
+// constant in microcode is sign extended (in order to implement substractions like adds)
+assign alu_a = (sel_read == `SEL_READ_DATA) ? mem_data_read_int : mem_addr;
+assign alu_b = (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } : // most priority
+ (sel_alu == `SEL_ALU_A) ? a :
+ (sel_alu == `SEL_ALU_B) ? b : { {24{1'b0}} , opcode }; // `SEL_ALU_OPCODE is less priority
+
+zpu_core_alu alu(
+ .alu_a(alu_a),
+ .alu_b(alu_b),
+ .alu_r(alu_r),
+ .alu_op(alu_op),
+ .flag_idim(idim),
+ .clk(clk),
+ .done(alu_done)
+);
+
+// -------- pc : program counter --------
+always @(posedge clk)
+begin
+ if(w_pc) pc <= alu_r;
+`ifdef ENABLE_PC_INCREMENT // microcode optimization
+ else if(w_pc_increment) pc <= pc + 1; // usually pc=pc+1
+`endif
+end
+
+// -------- sp : stack pointer --------
+always @(posedge clk)
+begin
+ if(w_sp) sp <= alu_r;
+end
+
+// -------- a : acumulator register ---------
+always @(posedge clk)
+begin
+ if(w_a) a <= alu_r;
+ else if(w_a_mem) a <= mem_data_read_int;
+end
+
+// alu results over a register instead of alu result
+// in order to improve speed
+assign a_is_zero = (a == 0);
+assign a_is_neg = a[31];
+
+// -------- b : auxiliary register ---------
+always @(posedge clk)
+begin
+ if(w_b) b <= alu_r;
+end
+
+// -------- opcode and opcode_cache --------
+always @(posedge clk)
+begin
+ if(w_op)
+ begin
+ opcode_cache <= alu_r; // store all opcodes in the word
+ pc_cached <= pc[31:2]; // store PC address of cached opcodes
+ end
+end
+
+// -------- opcode : based on pc[1:0] ---------
+always @(sel_opcode or opcode_cache) // select current opcode from
+begin // the cached opcode word
+ case(sel_opcode)
+ 0 : opcode <= opcode_cache[31:24];
+ 1 : opcode <= opcode_cache[23:16];
+ 2 : opcode <= opcode_cache[15:8];
+ 3 : opcode <= opcode_cache[7:0];
+ endcase
+end
+
+// ------- idim : immediate opcode handling ----------
+always @(posedge clk)
+begin
+ if(set_idim) idim <= 1'b1;
+ else if(clear_idim) idim <= 1'b0;
+end
+
+`ifdef ENABLE_CPU_INTERRUPTS
+// ------ on interrupt status bit -----
+always @(posedge clk)
+begin
+ if(reset | exit_interrupt) on_interrupt <= 1'b0;
+ else if(enter_interrupt) on_interrupt <= 1'b1;
+end
+`endif
+
+// ------ microcode execution unit --------
+assign sel_read = mc_op[`P_SEL_READ]; // map datapath signals with microcode program bits
+assign sel_alu = mc_op[`P_SEL_ALU+1:`P_SEL_ALU];
+assign sel_addr = mc_op[`P_SEL_ADDR+1:`P_SEL_ADDR];
+assign alu_op = mc_op[`P_ALU+3:`P_ALU];
+assign w_sp = mc_op[`P_W_SP] & ~busy;
+assign w_pc = mc_op[`P_W_PC] & ~busy;
+assign w_a = mc_op[`P_W_A] & ~busy;
+assign w_a_mem = mc_op[`P_W_A_MEM] & ~busy;
+assign w_b = mc_op[`P_W_B] & ~busy;
+assign w_op = mc_op[`P_W_OPCODE] & ~busy;
+assign mem_read = mc_op[`P_MEM_R];
+assign mem_write = mc_op[`P_MEM_W];
+assign set_idim = mc_op[`P_SET_IDIM] & ~busy;
+assign clear_idim= mc_op[`P_CLEAR_IDIM] & ~busy;
+`ifdef ENABLE_BYTE_SELECT
+assign byte_op = mc_op[`P_BYTE];
+assign halfw_op = mc_op[`P_HALFWORD];
+`endif
+`ifdef ENABLE_PC_INCREMENT
+ assign w_pc_increment = mc_op[`P_PC_INCREMENT] & ~busy;
+`endif
+`ifdef ENABLE_CPU_INTERRUPTS
+ assign exit_interrupt = mc_op[`P_EXIT_INT] & ~busy;
+ assign enter_interrupt = mc_op[`P_ENTER_INT] & ~busy;
+`endif
+
+wire cond_op_not_cached = mc_op[`P_OP_NOT_CACHED]; // conditional: true if opcode not cached
+wire cond_a_zero = mc_op[`P_A_ZERO]; // conditional: true if A is zero
+wire cond_a_neg = mc_op[`P_A_NEG]; // conditional: true if A is negative
+wire decode = mc_op[`P_DECODE]; // decode means jumps to apropiate microcode based on zpu opcode
+wire branch = mc_op[`P_BRANCH]; // unconditional jump inside microcode
+
+wire [`MC_MEM_BITS-1:0] mc_goto = { mc_op[`P_ADDR+6:`P_ADDR], 2'b00 }; // microcode goto (goto = high 7 bits)
+wire [`MC_MEM_BITS-1:0] mc_entry = { opcode[6:0], 2'b00 }; // microcode entry point for opcode
+reg [`MC_MEM_BITS-1:0] next_mc_pc; // next microcode operation to be executed
+initial next_mc_pc <= `MC_ADDR_RESET-1;
+
+wire cond_branch = (cond_op_not_cached & ~is_op_cached) | // sum of all conditionals
+ (cond_a_zero & a_is_zero) |
+ (cond_a_neg & a_is_neg);
+
+assign busy = ((mem_read | mem_write) & ~mem_done) | ~alu_done; // busy signal for microcode sequencer
+
+// ------- handle interrupts ---------
+`ifdef ENABLE_CPU_INTERRUPTS
+always @(posedge clk)
+begin
+ if(reset | on_interrupt) int_requested <= 0;
+ else if(interrupt & ~on_interrupt & ~int_requested) int_requested <= 1; // interrupt requested
+end
+`endif
+
+// ----- calculate next microcode address (next, decode, branch, specific opcode, etc.) -----
+always @(reset or mc_pc or mc_goto or opcode[7:4] or idim or
+ decode or branch or cond_branch or mc_entry or busy
+`ifdef ENABLE_CPU_INTERRUPTS
+ or int_requested
+`endif
+)
+begin
+ // default, next microcode instruction
+ next_mc_pc <= mc_pc + 1;
+ if(reset) next_mc_pc <= `MC_ADDR_RESET;
+ else if(~busy)
+ begin
+ // get next microcode instruction
+ if(branch | cond_branch) next_mc_pc <= mc_goto;
+ else if(decode) // decode: entry point of a new zpu opcode
+ begin
+`ifdef ENABLE_CPU_INTERRUPTS
+ if(int_requested & ~idim) next_mc_pc <= `MC_ADDR_INTERRUPT; // microde to enter interrupt mode
+ else
+`endif
+ if(opcode[7] == `OP_IM) next_mc_pc <= (idim ? `MC_ADDR_IM_IDIM : `MC_ADDR_IM_NOIDIM);
+ else if(opcode[7:5] == `OP_STORESP) next_mc_pc <= `MC_ADDR_STORESP;
+ else if(opcode[7:5] == `OP_LOADSP) next_mc_pc <= `MC_ADDR_LOADSP;
+ else if(opcode[7:4] == `OP_ADDSP) next_mc_pc <= `MC_ADDR_ADDSP;
+ else next_mc_pc <= mc_entry; // includes EMULATE opcodes
+ end
+ end
+ else next_mc_pc <= mc_pc; // in case of cpu stalled (busy=1)
+end
+
+// set microcode program counter
+always @(posedge clk) mc_pc <= next_mc_pc;
+
+// ----- microcode program ------
+zpu_core_rom microcode (
+ .addr(next_mc_pc),
+ .data(mc_op),
+ .clk(clk)
+);
+
+// -------------- ZPU debugger --------------------
+`ifdef ZPU_CORE_DEBUG
+//synthesis translate_off
+// ---- register operation dump ----
+always @(posedge clk)
+begin
+ if(~reset)
+ begin
+ if(w_pc) $display("zpu_core: set PC=0x%h", alu.alu_r);
+`ifdef ENABLE_PC_INCREMENT
+ if(w_pc_increment) $display("zpu_core: set PC=0x%h (PC+1)", pc);
+`endif
+ if(w_sp) $display("zpu_core: set SP=0x%h", alu.alu_r);
+ if(w_a) $display("zpu_core: set A=0x%h", alu.alu_r);
+ if(w_a_mem) $display("zpu_core: set A=0x%h (from MEM)", mem_data_read_int);
+ if(w_b) $display("zpu_core: set B=0x%h", alu.alu_r);
+ if(w_op & ~is_op_cached) $display("zpu_core: set opcode_cache=0x%h, pc_cached=0x%h", alu.alu_r, {pc[31:2], 2'b0});
+`ifdef ENABLE_CPU_INTERRUPTS
+ if(~busy & mc_pc == `MC_ADDR_INTERRUPT) $display("zpu_core: ***** ENTERING INTERRUPT MICROCODE ******");
+ if(~busy & exit_interrupt) $display("zpu_core: ***** INTERRUPT FLAG CLEARED *****");
+ if(~busy & enter_interrupt) $display("zpu_core: ***** INTERRUPT FLAG SET *****");
+`endif
+ if(set_idim & ~idim) $display("zpu_core: IDIM=1");
+ if(clear_idim & idim) $display("zpu_core: IDIM=0");
+
+// ---- microcode debug ----
+`ifdef ZPU_CORE_DEBUG_MICROCODE
+ if(~busy)
+ begin
+ $display("zpu_core: mc_op[%d]=0b%b", mc_pc, mc_op);
+ if(branch) $display("zpu_core: microcode: branch=%d", mc_goto);
+ if(cond_branch) $display("zpu_core: microcode: CONDITION branch=%d", mc_goto);
+ if(decode) $display("zpu_core: decoding opcode=0x%h (0b%b) : branch to=%d ", opcode, opcode, mc_entry);
+ end
+ else $display("zpu_core: busy");
+`endif
+
+// ---- cpu abort in case of unaligned memory access ---
+`ifdef ASSERT_NON_ALIGNMENT
+ /* unaligned word access (except PC) */
+ if(sel_addr != `SEL_ADDR_PC & mem_addr[1:0] != 2'b00 & (mem_read | mem_write) & !byte_op & !halfw_op)
+ begin
+ $display("zpu_core: unaligned word operation at addr=0x%x", mem_addr);
+ $finish;
+ end
+
+ /* unaligned halfword access */
+ if(mem_addr[0] & (mem_read | mem_write) & !byte_op & halfw_op)
+ begin
+ $display("zpu_core: unaligned halfword operation at addr=0x%x", mem_addr);
+ $finish;
+ end
+`endif
+
+ end
+end
+
+// ----- opcode dissasembler ------
+always @(posedge clk)
+begin
+if(~busy)
+case(mc_pc)
+0 : begin
+ $display("zpu_core: ------ breakpoint ------");
+ $finish;
+ end
+4 : $display("zpu_core: ------ shiftleft ------");
+8 : $display("zpu_core: ------ pushsp ------");
+12 : $display("zpu_core: ------ popint ------");
+16 : $display("zpu_core: ------ poppc ------");
+20 : $display("zpu_core: ------ add ------");
+24 : $display("zpu_core: ------ and ------");
+28 : $display("zpu_core: ------ or ------");
+32 : $display("zpu_core: ------ load ------");
+36 : $display("zpu_core: ------ not ------");
+40 : $display("zpu_core: ------ flip ------");
+44 : $display("zpu_core: ------ nop ------");
+48 : $display("zpu_core: ------ store ------");
+52 : $display("zpu_core: ------ popsp ------");
+56 : $display("zpu_core: ------ ipsum ------");
+60 : $display("zpu_core: ------ sncpy ------");
+
+`MC_ADDR_IM_NOIDIM : $display("zpu_core: ------ im 0x%h (1st) ------", opcode[6:0] );
+`MC_ADDR_IM_IDIM : $display("zpu_core: ------ im 0x%h (cont) ------", opcode[6:0] );
+`MC_ADDR_STORESP : $display("zpu_core: ------ storesp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
+`MC_ADDR_LOADSP : $display("zpu_core: ------ loadsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
+`MC_ADDR_ADDSP : $display("zpu_core: ------ addsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
+`MC_ADDR_EMULATE : $display("zpu_core: ------ emulate 0x%h ------", b[2:0]); // opcode[5:0] );
+
+128 : $display("zpu_core: ------ mcpy ------");
+132 : $display("zpu_core: ------ mset ------");
+136 : $display("zpu_core: ------ loadh ------");
+140 : $display("zpu_core: ------ storeh ------");
+144 : $display("zpu_core: ------ lessthan ------");
+148 : $display("zpu_core: ------ lessthanorequal ------");
+152 : $display("zpu_core: ------ ulessthan ------");
+156 : $display("zpu_core: ------ ulessthanorequal ------");
+160 : $display("zpu_core: ------ swap ------");
+164 : $display("zpu_core: ------ mult ------");
+168 : $display("zpu_core: ------ lshiftright ------");
+172 : $display("zpu_core: ------ ashiftleft ------");
+176 : $display("zpu_core: ------ ashiftright ------");
+180 : $display("zpu_core: ------ call ------");
+184 : $display("zpu_core: ------ eq ------");
+188 : $display("zpu_core: ------ neq ------");
+192 : $display("zpu_core: ------ neg ------");
+196 : $display("zpu_core: ------ sub ------");
+200 : $display("zpu_core: ------ xor ------");
+204 : $display("zpu_core: ------ loadb ------");
+208 : $display("zpu_core: ------ storeb ------");
+212 : $display("zpu_core: ------ div ------");
+216 : $display("zpu_core: ------ mod ------");
+220 : $display("zpu_core: ------ eqbranch ------");
+224 : $display("zpu_core: ------ neqbranch ------");
+228 : $display("zpu_core: ------ poppcrel ------");
+232 : $display("zpu_core: ------ config ------");
+236 : $display("zpu_core: ------ pushpc ------");
+240 : $display("zpu_core: ------ syscall_emulate ------");
+244 : $display("zpu_core: ------ pushspadd ------");
+248 : $display("zpu_core: ------ halfmult ------");
+252 : $display("zpu_core: ------ callpcrel ------");
+//default : $display("zpu_core: mc_pc=0x%h", decode_mcpc);
+endcase
+end
+//synthesis translate_on
+`endif
+endmodule
+
+// --------- ZPU CORE ALU UNIT ---------------
+module zpu_core_alu(
+ alu_a, // parameter A
+ alu_b, // parameter B
+ alu_r, // computed result
+ flag_idim, // for IMM alu op
+ alu_op, // ALU operation
+ clk, // clock for syncronous multicycle operations
+ done // done signal for alu operation
+);
+
+input [31:0] alu_a;
+input [31:0] alu_b;
+input [`ALU_OP_WIDTH-1:0] alu_op;
+input flag_idim;
+output [31:0] alu_r;
+input clk;
+output done;
+
+wire [31:0] alu_a;
+wire [31:0] alu_b;
+wire [`ALU_OP_WIDTH-1:0] alu_op;
+wire flag_idim;
+reg [31:0] alu_r;
+wire clk;
+reg done;
+
+`ifdef ENABLE_MULT
+// implement 32 bit pipeline multiplier
+reg mul_running;
+reg [2:0] mul_counter;
+wire mul_done = (mul_counter == 3);
+reg [31:0] mul_result, mul_tmp1;
+reg [31:0] a_in, b_in;
+
+always@(posedge clk)
+begin
+ a_in <= 0;
+ b_in <= 0;
+ mul_tmp1 <= 0;
+ mul_result <= 0;
+ mul_counter <= 0;
+ if(mul_running)
+ begin // infer pipeline multiplier
+ a_in <= alu_a;
+ b_in <= alu_b;
+ mul_tmp1 <= a_in * b_in;
+ mul_result <= mul_tmp1;
+ mul_counter <= mul_counter + 1;
+ end
+end
+`endif
+
+`ifdef ENABLE_DIV
+// implement 32 bit divider
+// Unsigned/Signed division based on Patterson and Hennessy's algorithm.
+// Description: Calculates quotient. The "sign" input determines whether
+// signs (two's complement) should be taken into consideration.
+// references: http://www.ece.lsu.edu/ee3755/2002/l07.html
+reg [63:0] qr;
+wire [33:0] diff;
+wire [31:0] quotient;
+wire [31:0] dividend;
+wire [31:0] divider;
+reg [6:0] bit;
+wire div_done;
+reg div_running;
+reg divide_sign;
+reg negative_output;
+
+assign div_done = !bit;
+assign diff = qr[63:31] - {1'b0, divider};
+assign quotient = (!negative_output) ? qr[31:0] : ~qr[31:0] + 1'b1;
+assign dividend = (!divide_sign || !alu_a[31]) ? alu_a : ~alu_a + 1'b1;
+assign divider = (!divide_sign || !alu_b[31]) ? alu_b : ~alu_b + 1'b1;
+
+always@(posedge clk)
+begin
+ bit <= 7'b1_000000; // divider stopped
+ if(div_running)
+ begin
+ if(bit[6]) // divider started: initialize registers
+ begin
+ bit <= 7'd32;
+ qr <= { 32'd0, dividend };
+ negative_output <= divide_sign && ((alu_b[31] && !alu_a[31]) || (!alu_b[31] && alu_a[31]));
+ end
+ else // step by step divide
+ begin
+ if( diff[32] ) qr <= { qr[62:0], 1'd0 };
+ else qr <= { diff[31:0], qr[30:0], 1'd1 };
+ bit <= bit - 1;
+ end
+ end
+end
+`endif
+
+`ifdef ENABLE_BARREL
+// implement 32 bit barrel shift
+// alu_b[6] == 1 ? left(only arithmetic) : right
+// alu_b[5] == 1 ? logical : arithmetic
+reg bs_running;
+reg [31:0] bs_result;
+reg [4:0] bs_counter; // 5 bits
+wire bs_left = alu_b[6];
+wire bs_logical = alu_b[5];
+wire [4:0] bs_moves = alu_b[4:0];
+wire bs_done = (bs_counter == bs_moves);
+
+always @(posedge clk)
+begin
+ bs_counter <= 0;
+ bs_result <= alu_a;
+ if(bs_running)
+ begin
+ if(bs_left) bs_result <= { bs_result[30:0], 1'b0 }; // shift left
+ else
+ begin
+ if(bs_logical) bs_result <= { 1'b0, bs_result[31:1] }; // shift logical right
+ else bs_result <= { bs_result[31], bs_result[31], bs_result[30:1] };// shift arithmetic right
+ end
+ bs_counter <= bs_counter + 1;
+ end
+end
+`endif
+
+// ----- alu add/sub -----
+reg [31:0] alu_b_tmp;
+always @(alu_b or alu_op)
+begin
+ alu_b_tmp <= alu_b; // by default, ALU_B as is
+ if(alu_op == `ALU_PLUS_OFFSET) alu_b_tmp <= { {25{1'b0}}, ~alu_b[4], alu_b[3:0], 2'b0 }; // ALU_B is an offset if ALU_PLUS_OFFSET operation
+end
+
+reg [31:0] alu_r_addsub; // compute R=A+B or A-B based on opcode (ALU_PLUSxx / ALU_SUB-CMP)
+always @(alu_a or alu_b_tmp or alu_op)
+begin
+`ifdef ENABLE_CMP
+ if(alu_op == `ALU_CMP_SIGNED || alu_op == `ALU_CMP_UNSIGNED) // in case of sub or cmp --> operation is '-'
+ begin
+ alu_r_addsub <= alu_a - alu_b_tmp;
+ end
+ else
+`endif
+ begin
+ alu_r_addsub <= alu_a + alu_b_tmp; // by default '+' operation
+ end
+end
+
+`ifdef ENABLE_CMP
+// handle overflow/underflow exceptions in ALU_CMP_SIGNED
+reg cmp_exception;
+always @(alu_a[31] or alu_b[31] or alu_r_addsub[31])
+begin
+ cmp_exception <= 0;
+ if( (alu_a[31] == 0 && alu_b[31] == 1 && alu_r_addsub[31] == 1) ||
+ (alu_a[31] == 1 && alu_b[31] == 0 && alu_r_addsub[31] == 0) ) cmp_exception <= 1;
+end
+`endif
+
+// ----- alu operation selection -----
+always @(alu_a or alu_b or alu_op or flag_idim or alu_r_addsub
+`ifdef ENABLE_CMP
+ or cmp_exception
+`endif
+`ifdef ENABLE_MULT
+ or mul_done or mul_result
+`endif
+`ifdef ENABLE_BARREL
+ or bs_done or bs_result
+`endif
+`ifdef ENABLE_DIV
+ or div_done or div_result
+`endif
+)
+begin
+ done <= 1; // default alu operations are 1 cycle
+`ifdef ENABLE_MULT
+ mul_running <= 0;
+`endif
+`ifdef ENABLE_BARREL
+ bs_running <= 0;
+`endif
+`ifdef ENABLE_DIV
+ div_running <= 0;
+`endif
+ alu_r <= alu_r_addsub; // ALU_PLUS, ALU_PLUS_OFFSET, ALU_SUB and part of ALU_CMP
+ case(alu_op)
+ `ALU_NOP : alu_r <= alu_a;
+ `ALU_NOP_B : alu_r <= alu_b;
+ `ALU_AND : alu_r <= alu_a & alu_b;
+ `ALU_OR : alu_r <= alu_a | alu_b;
+ `ALU_NOT : alu_r <= ~alu_a;
+ `ALU_FLIP : alu_r <= { alu_a[0], alu_a[1], alu_a[2], alu_a[3], alu_a[4], alu_a[5], alu_a[6], alu_a[7],
+ alu_a[8],alu_a[9],alu_a[10],alu_a[11],alu_a[12],alu_a[13],alu_a[14],alu_a[15],
+ alu_a[16],alu_a[17],alu_a[18],alu_a[19],alu_a[20],alu_a[21],alu_a[22],alu_a[23],
+ alu_a[24],alu_a[25],alu_a[26],alu_a[27],alu_a[28],alu_a[29],alu_a[30],alu_a[31] };
+ `ALU_IM : if(flag_idim) alu_r <= { alu_a[24:0], alu_b[6:0] };
+ else alu_r <= { {25{alu_b[6]}}, alu_b[6:0] };
+`ifdef ENABLE_CMP
+ `ALU_CMP_UNSIGNED:if( (alu_a[31] == alu_b[31] && cmp_exception) ||
+ (alu_a[31] != alu_b[31] && ~cmp_exception) )
+ begin
+ alu_r[31] <= ~alu_r_addsub[31];
+ end
+ `ALU_CMP_SIGNED : if(cmp_exception)
+ begin
+ alu_r[31] <= ~alu_r_addsub[31];
+ end
+`endif
+`ifdef ENABLE_XOR
+ `ALU_XOR : alu_r <= alu_a ^ alu_b;
+`endif
+`ifdef ENABLE_A_SHIFT
+ `ALU_A_SHIFT_RIGHT: alu_r <= { alu_a[31], alu_a[31], alu_a[30:1] }; // arithmetic shift left
+`endif
+`ifdef ENABLE_MULT
+ `ALU_MULT : begin
+ mul_running <= ~mul_done;
+ done <= mul_done;
+ alu_r <= mul_result;
+ end
+`endif
+`ifdef ENABLE_BARREL
+ `ALU_BARREL : begin
+ bs_running <= ~bs_done;
+ done <= bs_done;
+ alu_r <= bs_result;
+ end
+`endif
+`ifdef ENABLE_DIV
+ `ALU_DIV : begin
+ div_running<= ~div_done;
+ done <= div_done;
+ alu_r <= quotient;
+ end
+ `ALU_MOD : begin
+ div_running<= ~div_done;
+ done <= div_done;
+ alu_r <= qr[31:0];
+ end
+`endif
+ endcase
+end
+
+endmodule
diff --git a/zpu/hdl/avalanche/core/zpu_core_defines.v b/zpu/hdl/avalanche/core/zpu_core_defines.v
new file mode 100644
index 0000000..228f46b
--- /dev/null
+++ b/zpu/hdl/avalanche/core/zpu_core_defines.v
@@ -0,0 +1,322 @@
+/* MODULE: zpu_core_defines
+ DESCRIPTION: Contains ZPU parameters and other cpu related definitions
+ AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com)
+
+REVISION HISTORY:
+Revision 1.0, 14/09/2009
+Initial public release
+
+COPYRIGHT:
+Copyright (c) 2009 Antonio J. Anton
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.*/
+
+/* --------------- ISA DOCUMENTATION ------------------
+ stack: top of stack = sp, mem[sp]=valid data
+ push: sp=sp-1, then mem[sp]=data
+ pop: data=mem[sp], then sp=sp+1
+
+ immediates: any opcode instead of im sets idim=0
+
+ MNEMONIC OPCODE HEX OPERATION
+- im x 1_xxxxxxx if(~idim) { idim=1; sp=sp-1; mem[sp]={{25{b[6]}},b[6:0]} }
+ else { idim=1; mem[sp]={mem[sp][24:0], b[6:0]} }
+- emulate x 001_xxxxx sp=sp-1; mem[sp]=pc+1; pc=mem[@VECTOR_EMULATE + <b>]; fetch (used only by microcode)
+- storesp x 010_xxxxx mem[sp+x<<2] = mem[sp]; sp=sp+1
+- loadsp x 011_xxxxx mem[sp-1] = mem [sp+x<<2]; sp=sp-1
+- addsp x 0001_xxxx (1x) mem[sp] = mem[sp]+mem[sp+x<<2]
+
+- breakpoint 0000_0000 (00) call exception vector
+ shiftleft 0000_0001 (01)
+- pushsp 0000_0010 (02) mem[sp-1] = sp; sp = sp - 1
+- popint 0000_0011 (03) pc=mem[sp]; sp = sp + 1 ; fetch ; decode ; clear_interrupt_flag
+- poppc 0000_0100 (04) pc=mem[sp]; sp = sp + 1
+- add 0000_0101 (05) mem[sp+1] = mem[sp+1] + mem[sp]; sp = sp + 1
+- and 0000_0110 (06) mem[sp+1] = mem[sp+1] & mem[sp]; sp = sp + 1
+- or 0000_0111 (07) mem[sp+1] = mem[sp+1] | mem[sp]; sp = sp + 1
+- load 0000_1000 (08) mem[sp] = mem[ mem[sp] ]
+- not 0000_1001 (09) mem[sp] = ~mem[sp]
+- flip 0000_1010 (0a) mem[sp] = flip(mem[sp])
+- nop 0000_1011 (0b) -
+- store 0000_1100 (0c) mem[mem[sp]] = mem[sp+1]; sp = sp + 2
+- popsp 0000_1101 (0d) sp = mem[sp]
+ compare 0000_1110 (0e) ???? --> opcode recycled (see below)
+ popint 0000_1111 (0f) duplicated of 0x03 ????? --> opcode recycled (see below)
+
+- ipsum 0000_1110 (0e) c=mem[sp],s=mem[sp+1]; sum=0; while(c-->0) {sum+=halfword(mem[s],s);s+=2}; sp=sp+1; mem[sp]=sum (overwrites mem[0] & mem[4] words)
+- sncpy 0000_1111 (0f) c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while( *(char*)s != 0 && c>0 ) {*((char*)d++)=*((char*)s++));c--}; sp=sp+3 (overwrites mem[0] & mem[4] words)
+- wcpy 001_00000 (20) c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while(c-->0) mem[d++]=mem[s++]; sp=sp+3 (overwrites mem[0] & mem[4] words)
+- wset 001_00001 (21) v=mem[sp],c=mem[sp+1],d=mem[sp+2]; while(c-->0) mem[d++]=v; sp=sp+3 (overwrites mem[0] & mem[4] words)
+
+- loadh 001_00010 (22) mem[sp] = halfword[ mem[sp] ]
+- storeh 001_00011 (23) halfword[mem[sp]] = (mem[sp+1] & 0xFFFF); sp = sp + 2
+- lessthan 001_00100 (24) (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+- lessthanorequal 001_00101 (25) (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+- ulessthan 001_00110 (26) (unsigned(mem[sp])-unsigned(mem[sp+1])) < 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+- ulessthanorequal 001_00111 (27) (unsigned(mem[sp])-unsigned(mem[sp+1])) <= 0 || == 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+ swap 001_01000 (28)
+- mult 001_01001 (29) mem[sp+1] = mem[sp+1] * mem[sp]; sp = sp + 1
+- lshiftright 001_01010 (2a) mem[sp+1] = mem[sp+1] >> (mem[sp] & 0x1f); sp = sp + 1
+- ashiftleft 001_01011 (2b) mem[sp+1] = mem[sp+1] << (mem[sp] & 0x1f); sp = sp + 1
+- ashiftright 001_01100 (2c) mem[sp+1] = mem[sp+1] signed>> (mem[sp] & 0x1f); sp = sp + 1
+- call 001_01101 (2d) a = mem[sp]; mem[sp]=pc + 1; pc = a
+- eq 001_01110 (2e) mem[sp+1] = (mem[sp] == mem[sp+1]) ? 1 : 0; sp = sp + 1
+- neq 001_01111 (2f) mem[sp+1] = (mem[sp] != mem[sp+1]) ? 1 : 0; sp = sp + 1
+- neg 001_10000 (30) mem[sp] = NOT(mem[sp])+1
+- sub 001_10001 (31) mem[sp+1]=mem[sp+1]-mem[sp]; sp=sp+1
+- xor 001_10010 (32) mem[sp+1]=mem[sp] ^ mem[sp+1]; sp=sp+1
+- loadb 001_10011 (33) mem[sp] = byte[ mem[sp] ]
+- storeb 001_10100 (34) byte[mem[sp]] = (mem[sp+1] & 0xFF); sp = sp + 2
+ div 001_10101 (35)
+ mod 001_10110 (36)
+- eqbranch 001_10111 (37) mem[sp+1] == 0 ? pc = pc + mem[sp]; sp = sp + 2
+- neqbranch 001_11000 (38) mem[sp+1] != 0 ? pc = pc + mem[sp]; sp = sp + 2
+- poppcrel 001_11001 (39) pc = pc + mem[sp]; sp = sp + 1
+ config 001_11010 (3a)
+- pushpc 001_11011 (3b) sp=sp-1; mem[sp]=pc
+ syscall 001_11100 (3c)
+- pushspadd 001_11101 (3d) mem[sp] = sp + (mem[sp] << 2)
+- halfmult 001_11110 (3e) mem[sp+1] = 16bits(mem[sp]) * 16bits(mem[sp+1]); sp = sp + 1
+- callpcrel 001_11111 (3f) a = mem[sp]; mem[sp]=pc+1; pc = pc + a;
+
+ gcc seems to be using only:
+
+ add, addsp, and, ashiftleft, ashiftright, call, callpcrel, div, eq, flip, im, lessthan,
+ lessthanorequal, loadb, loadh, load, loadsp, lshiftright, mod, mult, neg, neqbranch,
+ not, or, poppc, poppcrel, popsp, pushpc, pushspadd, pushsp, storeb, storeh, store, storesp,
+ sub, ulessthan, ulessthanorequal, xor
+
+ --------- memory access ----------------------------
+
+ data is stored in big-endian format into memory:
+ 00 MSB .. .. LSB
+ 05 .. .. .. ..
+
+ ---------------------------------------------------- */
+`define SP_START 32'h10 // after reset change in startup code
+`define EMULATION_VECTOR 32'h10 // table of emulated opcodes (interrupt & exception vectors plus up to 5 emulated opcodes)
+`define RESET_VECTOR 32'h20 // reset entry point (can be moved up to 0x3c as per emulation table needs)
+
+// ---- zpu core optimizations/features ----
+`define ZPU_CORE_DEBUG
+//`define ZPU_CORE_DEBUG_MICROCODE
+`define ASSERT_NON_ALIGNMENT /* abort cpu in case of non-aligned memory access (only simulation) */
+
+`define ENABLE_BYTE_SELECT /* allow byte / halfword memory accesses */
+`define ENABLE_CPU_INTERRUPTS /* enable interrupts to cpu */
+//`define ENABLE_PC_INCREMENT /* gain 1 clk per opcode but requires microcode changes ** not done at the moment ** */
+//`define ENABLE_A_SHIFT /* 1 bit arithmetic shift (right) mutual exclusive with barrel shift */
+//`define ENABLE_XOR /* 1 cycle x-or */
+//`define ENABLE_MULT /* 32 bit pipelined (3 stages) multiplier */
+//`define ENABLE_DIV /* 32 bit, up to 32 cycles serial divider */
+`define ENABLE_BARREL /* n bit logical & arithmetic shift mutual exclusive with 1 bit shift */
+`define ENABLE_CMP /* enable ALU_CMP_SIGNED and ALU_CMP_UNSIGNED */
+
+// ------- microcode zpu core datapath selectors --------
+`define SEL_READ_DATA 0
+`define SEL_READ_ADDR 1
+
+`define SEL_ALU_A 0
+`define SEL_ALU_OPCODE 1
+`define SEL_ALU_MC_CONST 2
+`define SEL_ALU_B 3
+
+`define SEL_ADDR_PC 0
+`define SEL_ADDR_SP 1
+`define SEL_ADDR_A 2
+`define SEL_ADDR_B 3
+
+`define ALU_OP_WIDTH 4 // alu operation is 4 bits
+
+`define ALU_NOP 0 // r = a
+`define ALU_NOP_B 1 // r = b
+`define ALU_PLUS 2 // r = a + b
+`define ALU_PLUS_OFFSET 3 // r = a + { 27'b0, ~b[4], b[3:0] }
+`define ALU_AND 4 // r = a AND b
+`define ALU_OR 5 // r = a OR b
+`define ALU_NOT 6 // r = NOT a
+`define ALU_FLIP 7 // r = FLIP a
+`define ALU_IM 8 // r = IDIM ? { a[24:0], b[6:0] } : { 25{b[6]}, b[6:0] }
+`ifdef ENABLE_CMP
+ `define ALU_CMP_UNSIGNED 9 // r = (unsigned)a - (unsigned)b (r[31] is overflow/underflow adjusted)
+ `define ALU_CMP_SIGNED 10 // r = (signed)a - (signed)b (r[31] is overflow/underflow adjusted)
+`endif
+`ifdef ENABLE_BARREL
+ `define ALU_BARREL 11 // r = a <<|>> b (logical, arithmetical)
+`endif
+`ifdef ENABLE_A_SHIFT
+ `define ALU_A_SHIFT_RIGHT 11 // r = { a[31], a[31], a[30:29] } = (signed)a >> 1
+`endif
+`ifdef ENABLE_XOR
+ `define ALU_XOR 12 // r = a XOR b
+`endif
+`ifdef ENABLE_MULT
+ `define ALU_MULT 13 // r = a * b
+`endif
+`ifdef ENABLE_DIV
+ `define ALU_DIV 14 // r = a / b
+ `define ALU_MOD 15 // r = a mod b
+`endif
+
+// ------- special zpu opcodes ------
+`define OP_NOP 8'b0000_1011 // default value for opcode cache on reset
+`define OP_IM 1'b1
+`define OP_EMULATE 3'b001
+`define OP_STORESP 3'b010
+`define OP_LOADSP 3'b011
+`define OP_ADDSP 4'b0001
+
+// ------- microcode memory settings ------
+`define MC_MEM_BITS 9 // 512 microcode operations
+`define MC_BITS 36 // microcode opcode width
+
+// ------- microcode labels for opcode execution -------
+// based on microcode program
+`define MC_ADDR_IM_NOIDIM 488
+`define MC_ADDR_IM_IDIM 491
+`define MC_ADDR_STORESP 493
+`define MC_ADDR_LOADSP 496
+`define MC_ADDR_ADDSP 500
+`define MC_ADDR_EMULATE 504
+`define MC_ADDR_INTERRUPT 484
+`define MC_ADDR_FETCH_NEXT 480
+`define MC_ADDR_FETCH 476
+`define MC_ADDR_RESET 474
+
+// ---------- microcode settings --------------------
+`define P_SEL_READ 0 // alu-A multiplexor between data-in and addr-out (1 bit)
+`define P_SEL_ALU 1 // alu-B multiplexor between a, b, mc_const or opcode (2 bits)
+`define P_SEL_ADDR 3 // addr-out multiplexor between sp, pc, a, b (2 bits)
+`define P_ALU 5 // alu operation (4 bits)
+`define P_W_SP 9 // write sp (from alu-out)
+`define P_W_PC 10 // write pc (from alu-out)
+`define P_W_A 11 // write a (from alu-out)
+`define P_W_B 12 // write b (from alu-out)
+`define P_SET_IDIM 13 // set idim flag
+`define P_CLEAR_IDIM 14 // clear idim flag
+`define P_W_OPCODE 15 // write opcode (from alu-out) : check if can be written directly from data-in
+`define P_DECODE 16 // jump to microcode entry point based on current opcode
+`define P_MEM_R 17 // request memory read
+`define P_MEM_W 18 // request memory write
+`define P_ADDR 19 // microcode address (7 bits (granularity is 4 words)) or constant to be used at microcode level
+`define P_BRANCH 26 // microcode inconditional branch to address
+`define P_OP_NOT_CACHED 27 // microcode branch if byte[pc] is not cached at opcode
+`define P_A_ZERO 28 // microcode branch if a is zero
+`define P_A_NEG 29 // microcode branch if a is negative a[31]=1
+`define P_W_A_MEM 30 // write a directly from data-in (alu datapath is free to perform any other operation in parallel)
+`ifdef ENABLE_BYTE_SELECT
+ `define P_BYTE 31 // byte memory operation
+ `define P_HALFWORD 32 // half word memory operation
+`endif
+`ifdef ENABLE_PC_INCREMENT
+ `define P_PC_INCREMENT 33 // autoincrement PC bypassing ALU (1 clock gain per opcode) : not implemented at microcode level
+`endif
+`ifdef ENABLE_CPU_INTERRUPTS
+ `define P_EXIT_INT 34 // clear interrupt flag (exit from interrupt)
+ `define P_ENTER_INT 35 // set interrupt flag (enter interrupt)
+`endif
+
+`define MC_SEL_READ_DATA (`SEL_READ_DATA << `P_SEL_READ) // 1 bit
+`define MC_SEL_READ_ADDR (`SEL_READ_ADDR << `P_SEL_READ)
+
+`define MC_SEL_ALU_A (`SEL_ALU_A << `P_SEL_ALU) // 2 bit
+`define MC_SEL_ALU_OPCODE (`SEL_ALU_OPCODE << `P_SEL_ALU)
+`define MC_SEL_ALU_MC_CONST (`SEL_ALU_MC_CONST << `P_SEL_ALU)
+`define MC_SEL_ALU_B (`SEL_ALU_B << `P_SEL_ALU)
+
+`define MC_SEL_ADDR_PC (`SEL_ADDR_PC << `P_SEL_ADDR) // 2 bits
+`define MC_SEL_ADDR_SP (`SEL_ADDR_SP << `P_SEL_ADDR)
+`define MC_SEL_ADDR_A (`SEL_ADDR_A << `P_SEL_ADDR)
+`define MC_SEL_ADDR_B (`SEL_ADDR_B << `P_SEL_ADDR)
+
+`define MC_ALU_NOP (`ALU_NOP << `P_ALU) // 4 bits
+`define MC_ALU_NOP_B (`ALU_NOP_B << `P_ALU)
+`define MC_ALU_PLUS (`ALU_PLUS << `P_ALU)
+`define MC_ALU_AND (`ALU_AND << `P_ALU)
+`define MC_ALU_OR (`ALU_OR << `P_ALU)
+`define MC_ALU_NOT (`ALU_NOT << `P_ALU)
+`define MC_ALU_FLIP (`ALU_FLIP << `P_ALU)
+`define MC_ALU_IM (`ALU_IM << `P_ALU)
+`define MC_ALU_PLUS_OFFSET (`ALU_PLUS_OFFSET << `P_ALU)
+`ifdef ENABLE_CMP
+ `define MC_ALU_CMP_SIGNED (`ALU_CMP_SIGNED << `P_ALU)
+ `define MC_ALU_CMP_UNSIGNED (`ALU_CMP_UNSIGNED << `P_ALU)
+`endif
+`ifdef ENABLE_XOR
+ `define MC_ALU_XOR (`ALU_XOR << `P_ALU)
+`endif
+`ifdef ENABLE_A_SHIFT
+ `define MC_ALU_A_SHIFT_RIGHT (`ALU_A_SHIFT_RIGHT << `P_ALU)
+`endif
+`ifdef ENABLE_MULT
+ `define MC_ALU_MULT (`ALU_MULT << `P_ALU)
+`endif
+`ifdef ENABLE_DIV
+ `define MC_ALU_DIV (`ALU_DIV << `P_ALU)
+ `define MC_ALU_MOD (`ALU_MOD << `P_ALU)
+`endif
+`ifdef ENABLE_BARREL
+ `define MC_ALU_BARREL (`ALU_BARREL << `P_ALU)
+`endif
+
+`define MC_W_SP (1 << `P_W_SP)
+`define MC_W_PC (1 << `P_W_PC)
+`define MC_W_A (1 << `P_W_A)
+`define MC_W_A_MEM (1 << `P_W_A_MEM)
+`define MC_W_B (1 << `P_W_B)
+`define MC_W_OPCODE (1 << `P_W_OPCODE)
+`define MC_SET_IDIM (1 << `P_SET_IDIM)
+`define MC_CLEAR_IDIM (1 << `P_CLEAR_IDIM)
+`ifdef ENABLE_BYTE_SELECT
+ `define MC_BYTE (1 << `P_BYTE)
+ `define MC_HALFWORD (1 << `P_HALFWORD)
+`endif
+`ifdef ENABLE_PC_INCREMENT
+ `define MC_PC_INCREMENT (1 << `P_PC_INCREMENT)
+`endif
+`ifdef ENABLE_CPU_INTERRUPTS
+ `define MC_EXIT_INTERRUPT (1 << `P_EXIT_INT)
+ `define MC_ENTER_INTERRUPT (1 << `P_ENTER_INT)
+`endif
+
+`define MC_MEM_R (1 << `P_MEM_R)
+`define MC_MEM_W (1 << `P_MEM_W)
+
+`define MC_DECODE (1 << `P_DECODE)
+`define MC_BRANCH (1 << `P_BRANCH)
+`define MC_BRANCHIF_OP_NOT_CACHED (1 << `P_OP_NOT_CACHED)
+`define MC_BRANCHIF_A_ZERO (1 << `P_A_ZERO)
+`define MC_BRANCHIF_A_NEG (1 << `P_A_NEG)
+
+// microcode common operations
+
+`define MC_ADDR_FETCH_OP ( (`MC_ADDR_FETCH >> 2) << `P_ADDR) // fetch opcode from memory then decode
+`define MC_ADDR_NEXT_OP ( (`MC_ADDR_FETCH_NEXT >> 2) << `P_ADDR) // go to next opcode
+`define MC_ADDR_EMULATE_OP ( (`MC_ADDR_EMULATE >> 2) << `P_ADDR) // EMULATE opcode
+
+`define MC_PC_PLUS_1 (`MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS | (1 << `P_ADDR) | `MC_W_PC)
+`define MC_SP_MINUS_4 (`MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS | ((-4 & 127) << `P_ADDR) | `MC_W_SP)
+`define MC_SP_PLUS_4 (`MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS | (4 << `P_ADDR) | `MC_W_SP)
+`define MC_EMULATE (`MC_BRANCH | `MC_ADDR_EMULATE_OP)
+
+`define MC_FETCH (`MC_BRANCHIF_OP_NOT_CACHED | `MC_ADDR_FETCH_OP | `MC_DECODE) // fetch and decode current PC opcode
+`define MC_GO_NEXT (`MC_BRANCH | `MC_ADDR_NEXT_OP) // go to next opcode (PC=PC+1, fetch, decode)
+`define MC_GO_FETCH (`MC_BRANCH | `MC_ADDR_FETCH_OP) // go to fetch opcode at PC, then decode
+`define MC_GO_BREAKPOINT (`MC_BRANCH | ((0 >> 2) << `P_ADDR)) // go to breakpoint opcode
+
diff --git a/zpu/hdl/avalanche/core/zpu_core_rom.v b/zpu/hdl/avalanche/core/zpu_core_rom.v
new file mode 100644
index 0000000..62b7229
--- /dev/null
+++ b/zpu/hdl/avalanche/core/zpu_core_rom.v
@@ -0,0 +1,1017 @@
+`timescale 1ns / 1ps
+`include "zpu_core_defines.v"
+
+/* MODULE: zpu_core_rom
+ DESCRIPTION: Contains microcode program
+ AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com)
+
+REVISION HISTORY:
+Revision 1.0, 14/09/2009
+Initial public release
+
+COPYRIGHT:
+Copyright (c) 2009 Antonio J. Anton
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.*/
+
+module zpu_core_rom (
+ clk,
+ addr,
+ data
+);
+
+input [`MC_MEM_BITS-1:0] addr;
+output [`MC_BITS-1:0] data;
+input clk;
+
+wire [`MC_MEM_BITS-1:0] addr;
+reg [`MC_BITS-1:0] data;
+reg [`MC_BITS-1:0] memory[(1<<`MC_MEM_BITS)-1:0];
+
+initial data <= 0;
+always @(posedge clk) data <= memory[addr];
+
+// --- clear all memory at startup; for any reason, xilinx xst
+// will not syntetize as block ram if not all memory is initialized ---
+integer n;
+initial begin
+// initialize all memory array
+for(n = 0; n < (1<<`MC_MEM_BITS); n = n + 1) memory[n] = 0;
+
+// ------------------------- MICROCODE MEMORY START -----------------------------------
+
+// As per zpu_core.v, each opcode is executed by microcode. Each opcode microcode entry point
+// is at <opcode> << 2 (example pushsp = 0x02 has microcode entry point of 0x08); this leaves
+// room of 4 microcode operations per opcode; if the opcode microcode needs more space,
+// it can jump & link to other microcode address (with the two lower bits at 0). The lower 256 addresses
+// of microcode memory are entry points and code for 0..127 opcodes; other specific opcodes like im, storesp, etc.
+// are directly hardwired to specific microcode addresses at the memory end. Upper 256 addresses are
+// used by microcode continuation (eg. opcodes which needs more microcode operations), entry points, initializations, etc.
+// the idea is to fit the microcode program in a xilinx blockram 512x36.
+
+// ----- OPCODES WITHOUT CONSTANT ------
+
+// 0000_0000 (00) breakpoint -------------------------------------
+memory[0] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | // b = 4 (#1 in emulate table)
+ `MC_W_B;
+memory[1] = `MC_EMULATE; // emulate #1 (exception)
+
+// 0000_0001 (01) shiftleft -------------------------------------
+memory[4] = `MC_GO_BREAKPOINT;
+
+// 0000_0010 (02) pushsp -------------------------------------
+// mem[sp-1] = sp
+// sp = sp - 1
+memory[8] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp
+ `MC_ALU_NOP | `MC_W_A;
+memory[9] = `MC_SP_MINUS_4; // sp = sp - 1
+memory[10] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp]=a
+
+// 0000_0011 (03) popint -------------------------------------
+`ifdef ENABLE_CPU_INTERRUPTS
+// pc=mem[sp]-1 (emulate stores pc+1 but we must return to
+// sp=sp+1 pc because interrupt takes precedence to decode)
+// fetch & decode, then clear_interrupt_flag
+// this guarantees that a continous interrupt allows to execute at least one
+// opcode of mainstream program before reentry to interrupt handler
+memory[12] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // pc = mem[sp]-1
+ `MC_MEM_R | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST |
+ ((-1 & 127) << `P_ADDR) | `MC_W_PC;
+memory[13] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R | // opcode_cache = mem[pc]
+ `MC_W_OPCODE;
+memory[14] = `MC_SP_PLUS_4 | `MC_DECODE | `MC_EXIT_INTERRUPT; // sp=sp+1, decode opcode, exit_interrupt
+`else
+memory[12] = `MC_GO_BREAKPOINT;
+`endif
+
+// 0000_0100 (04) poppc -------------------------------------
+// pc=mem[sp]
+// sp = sp + 1
+memory[16] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // pc = mem[sp]
+ `MC_MEM_R | `MC_W_PC;
+memory[17] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[18] = `MC_FETCH; // opcode cached ? decode : fetch,decode
+
+// 0000_0101 (05) add -------------------------------------
+// mem[sp+1] = mem[sp+1] + mem[sp]
+// sp = sp + 1
+memory[20] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[21] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a + mem[sp]
+ `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A;
+memory[22] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_0110 (06) and -------------------------------------
+// mem[sp+1] = mem[sp+1] & mem[sp]
+// sp = sp + 1
+memory[24] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[25] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a & mem[sp]
+ `MC_ALU_AND |`MC_SEL_ALU_A | `MC_W_A;
+memory[26] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_0111 (07) or -------------------------------------
+// mem[sp+1] = mem[sp+1] | mem[sp]
+// sp = sp + 1
+memory[28] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[29] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a | mem[sp]
+ `MC_ALU_OR | `MC_SEL_ALU_A | `MC_W_A;
+memory[30] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_1000 (08) load -------------------------------------
+// mem[sp] = mem[ mem[sp] ]
+memory[32] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp]
+ `MC_MEM_R | `MC_W_A;
+memory[33] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[34] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_1001 (09) not -------------------------------------
+// mem[sp] = ~mem[sp]
+memory[36] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = ~mem[sp]
+ `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[37] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_1010 (0a) flip -------------------------------------
+// mem[sp] = flip(mem[sp])
+memory[40] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = FLIP(mem[sp])
+ `MC_MEM_R | `MC_ALU_FLIP | `MC_W_A;
+memory[41] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_1011 (0b) nop -------------------------------------
+memory[44] = `MC_CLEAR_IDIM | `MC_PC_PLUS_1; // IDIM=0
+memory[45] = `MC_FETCH;
+
+// 0000_1100 (0c) store -------------------------------------
+// mem[mem[sp]] <= mem[sp+1]
+// sp = sp + 2
+memory[48] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[49] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[50] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | `MC_SP_PLUS_4; // a = mem[sp] || sp = sp + 1
+memory[51] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT; // mem[b] = a
+
+// 0000_1101 (0d) popsp -------------------------------------
+// sp = mem[sp]
+memory[52] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // sp = mem[sp]
+ `MC_W_SP | `MC_GO_NEXT;
+
+// 0000_1110 (0e) ipsum ------------------------------------
+// compare: opcode recycled --> ipsum
+// c=mem[sp];s=mem[sp+1]; sum=0;
+// while(c-->0) {sum+=halfword(mem[s],s);s++};
+// sp=sp+1; mem[sp]=sum (overwrites mem[0] & mem[4] words)
+// requires HALFWORD memory access
+`ifdef ENABLE_BYTE_SELECT
+memory[56] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0
+ (0 << `P_ADDR) | `MC_W_B;
+memory[57] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1 save next pc on mem[0]
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[58] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[59] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @ipsum_continue1
+ `MC_BRANCH | ((116 >> 2) << `P_ADDR);
+`else
+memory[56] = `MC_GO_BREAKPOINT;
+`endif
+
+// 0000_1111 (0f) sncpy ---------------------------------------
+// c=mem[sp],d=mem[sp+1],s=mem[sp+2];
+// while( *(char*)s != 0 && c>0 ) { *((char*)d++)=*((char*)s++)); c-- };
+// sp=sp+1; mem[sp+1]=d; mem[sp]=c
+// (overwrites mem[0] & mem[4] words)
+// requires BYTE memory access
+`ifdef ENABLE_BYTE_SELECT
+memory[60] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0
+ (0 << `P_ADDR) | `MC_W_B;
+memory[61] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1 save next pc on mem[0]
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[62] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[63] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @sncpy_continue1
+ `MC_BRANCH | ((100 >> 2) << `P_ADDR);
+`else
+memory[60] = `MC_GO_BREAKPOINT;
+`endif
+
+// ------------- microcode opcode continuations ---------------
+// wset_continue1: ------------------------
+memory[64] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+12 save clear stack on mem[4]
+ `MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
+memory[65] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a
+memory[66] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (data)
+memory[67] = `MC_SP_PLUS_4; // sp=sp+4
+memory[68] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B; // b=mem[sp] (count)
+memory[69] = `MC_SP_PLUS_4; // sp=sp+4
+memory[70] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (destination @)
+memory[71] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (count)
+// wset_loop:
+memory[72] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @wset_end
+memory[73] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b=b-1 (count)
+ `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
+memory[74] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_W_A; // a=pc (data)
+memory[75] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SP_PLUS_4; // mem[sp]=a || sp=sp+4 (sp=destination@)
+memory[76] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | // a=b (count) || goto @wset_loop
+ `MC_BRANCH | ((72 >> 2) << `P_ADDR);
+// wset_end: wcpy_end: sncpy_end:
+memory[80] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC; // pc=mem[a] (a is 0)
+memory[81] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | // b=4
+ `MC_W_B;
+memory[82] = `MC_SEL_ADDR_B | `MC_MEM_R | `MC_SEL_READ_DATA | // sp=mem[b] || goto @fetch
+ `MC_W_SP | `MC_FETCH;
+
+// wcpy_continue1: ------------------------
+memory[84] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+12 save clear stack on mem[4]
+ `MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
+memory[85] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a
+memory[86] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B; // b=mem[sp] (count)
+memory[87] = `MC_SP_PLUS_4; // sp=sp+4
+memory[88] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (destination @)
+memory[89] = `MC_SP_PLUS_4; // sp=sp+4
+memory[90] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (source @)
+memory[91] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (count)
+// wcpy_loop:
+memory[92] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @wcpy_end
+memory[93] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b=b-1 (count)
+ `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
+memory[94] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+4 (sp=source@)
+ `MC_SP_PLUS_4;
+memory[95] = `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR | // mem[pc]=a || pc=pc+4 (pc=destination@)
+ `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_PC;
+memory[96] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | // a=b (count) || goto @wcpy_loop
+ `MC_BRANCH | ((92 >> 2) << `P_ADDR);
+
+`ifdef ENABLE_BYTE_SELECT
+// sncpy_continue1: ---------------------
+memory[100] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+12
+ `MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
+memory[101] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a
+memory[102] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;// b=mem[sp] (count)
+memory[103] = `MC_SP_PLUS_4; // sp=sp+4
+memory[104] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (destination @)
+memory[105] = `MC_SP_PLUS_4; // sp=sp+4
+memory[106] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (source @)
+memory[107] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (count)
+// sncpy_loop:
+memory[108] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @sncpy_end (count==0?)
+memory[109] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_BYTE | `MC_W_A_MEM | // a=BYTE(mem[sp],sp) || sp=sp+1 (sp=source@)
+ `MC_SEL_READ_ADDR | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST |
+ (1 << `P_ADDR) | `MC_W_SP;
+memory[110] = `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR | // BYTE(mem[pc],pc)=a || pc=pc+1 (pc=destination@)
+ `MC_BYTE | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST |
+ (1 << `P_ADDR) | `MC_W_PC;
+memory[111] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @sncpy_end (mem[src]==0?)
+memory[112] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b=b-1 (count)
+ `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
+memory[113] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | // a=b (count) || goto @sncpy_loop
+ `MC_BRANCH | ((108 >> 2) << `P_ADDR);
+
+// ipsum_continue1: -------------------
+memory[116] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_A;
+memory[117] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a save return sp on mem[4]
+memory[118] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // pc=mem[sp] (count)
+ `MC_W_PC;
+memory[119] = `MC_SP_PLUS_4; // sp=sp+4
+memory[120] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // sp=mem[sp] (start @)
+ `MC_W_SP;
+memory[121] = `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | `MC_W_B | // b=0 (sum)
+ `MC_ALU_NOP_B;
+memory[122] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_W_A; // a=pc (count)
+// ipsum_loop:
+memory[124] = `MC_BRANCHIF_A_ZERO | ((392 >> 2) << `P_ADDR); // a == 0 ? goto @ipsum_end
+
+memory[125] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_HALFWORD | // b=mem[sp]+b
+ `MC_SEL_READ_DATA | `MC_ALU_PLUS | `MC_SEL_ALU_B | `MC_W_B;
+memory[126] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // sp=sp+2
+ `MC_SEL_ALU_MC_CONST | (2 << `P_ADDR) | `MC_W_SP;
+memory[127] = `MC_BRANCH | ((408 >> 2) << `P_ADDR); // goto @ipsum_continue2
+`endif
+
+// -------------------------------------------------------------
+
+// 001_00000 (20) wcpy -----------------------------------------
+// before using this opcode you must save mem[0] & mem[4] words, then wcpy, then restore mems
+// c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while(c-->0) mem[d++]=mem[s++]; sp=sp+3
+memory[128] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0
+ (0 << `P_ADDR) | `MC_W_B;
+memory[129] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[130] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[131] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @wcpy_continue1
+ `MC_BRANCH | ((84 >> 2) << `P_ADDR);
+
+// 001_00001 (21) wset ----------------------------------------
+// before using this opcode you must save mem[0] & mem[4] words, then wset, then restore mems
+// v=mem[sp],c=mem[sp+1],d=mem[sp+2]; while(c-->0) mem[d++]=v; sp=sp+3
+memory[132] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0
+ (0 << `P_ADDR) | `MC_W_B;
+memory[133] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[134] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[135] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @wset_continue1
+ `MC_BRANCH | ((64 >> 2) << `P_ADDR);
+
+// 001_00010 (22) loadh -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+// mem[sp] = HALFWORD(mem[sp], mem[mem[sp]])
+memory[136] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp]
+ `MC_MEM_R | `MC_W_A;
+memory[137] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | // a = halfword(a, mem[a])
+ `MC_W_A | `MC_HALFWORD;
+memory[138] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[136] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00011 (23) storeh -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+// HALFWORD( mem[mem[sp]] <= mem[sp+1] )
+// sp = sp + 2
+memory[140] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[141] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[142] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a = mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[143] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_HALFWORD | `MC_GO_NEXT; // HALFWORD(mem[b] = a)
+`else
+memory[140] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00100 (24) lessthan -------------------------------------
+// (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[144] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[145] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B; // b=mem[sp]
+memory[146] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthan_check
+ `MC_ALU_CMP_SIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[144] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00101 (25) lessthanorequal -------------------------------------
+// (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[148] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[149] = `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B; // b=mem[sp]
+memory[150] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthanorequal_check
+ `MC_ALU_CMP_SIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[148] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00110 (26) ulessthan -------------------------------------
+// signA!=signB -> (unsigA < unsigB) == ~(sigA < sigA)
+// signA==signB -> (unsigA < unsigB) == (sigA < sigB)
+// (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[152] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[153] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B; // b=mem[sp]
+memory[154] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthan_check
+ `MC_ALU_CMP_UNSIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[152] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00111 (27) ulessthanorequal -------------------------------------
+// (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[156] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[157] = `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B; // b=mem[sp]
+memory[158] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthanorequal_check
+ `MC_ALU_CMP_UNSIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[156] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_01000 (28) swap -------------------------------------
+memory[160] = `MC_GO_BREAKPOINT;
+
+// 001_01001 (29) mult -------------------------------------
+`ifdef ENABLE_MULT
+// mem[sp+1] = mem[sp+1] * mem[sp]
+// sp = sp + 1
+memory[164] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[165] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp]
+ `MC_W_B;
+memory[166] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = a * b DON'T COMBINE MULTICYCLE ALU
+ `MC_ALU_MULT | `MC_W_A; // OPERATIONS WITH MEMORY READ/WRITE
+memory[167] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[164] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | // b = 8 (#2 in emulate table)
+ `MC_W_B;
+memory[165] = `MC_EMULATE; // emulate #2 (mult opcode)
+`endif
+
+// 001_01010 (2a) lshiftright -------------------------------------
+`ifdef ENABLE_BARREL
+// b = mem[sp] & 5'b1111 : limit to 5 bits (max 31 shifts)
+// b = b | 7'b01_00000 : shift right, logical
+// sp=sp+1
+// a = mem[sp]
+// a = a >> b
+// mem[sp] = a
+memory[168] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B;
+memory[169] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR | // b = b | 7'b01_00000 (shift right, logical)
+ `MC_SEL_ALU_MC_CONST | (32 << `P_ADDR) | `MC_W_B;
+memory[170] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[171] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] | goto @shift_cont
+ `MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
+`else
+ `ifdef ENABLE_A_SHIFT
+// a = mem[sp] & 5'b11111
+// sp=sp+1
+// b = FLIP(mem[sp])
+// label: a <= 0 ? goto @fin
+// b = b << 1
+// a = a - 1 || goto @label
+// fin: a = FLIP(b)
+// mem[sp]=a
+memory[168] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |
+ (31 << `P_ADDR) | `MC_W_A;
+memory[169] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[170] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = FLIP(mem[sp])
+ `MC_ALU_FLIP | `MC_W_B;
+memory[171] = `MC_BRANCH | ((448 >> 2) << `P_ADDR); // goto @lshiftleft_loop
+ `else
+ memory[168] = `MC_GO_BREAKPOINT;
+ `endif
+`endif
+
+// 001_01011 (2b) ashiftleft -------------------------------------
+`ifdef ENABLE_BARREL
+// b = mem[sp] & 5'b11111 : 5 bit shift
+// b = b | 7'b10_00000 : shift left, arithmetic
+// sp=sp+1
+// a = mem[sp]
+// a = a <<signed b
+// mem[sp] = a
+memory[172] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B;
+memory[173] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR | // b = b | 7'b10_00000 (shift left, arithmetic)
+ `MC_SEL_ALU_MC_CONST | (64 << `P_ADDR) | `MC_W_B;
+memory[174] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[175] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] | goto @shift_cont
+ `MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
+`else
+// a = mem[sp] & 5'b11111
+// sp = sp + 1
+// b = mem[sp]
+// label: a <= 0 ? goto @fin
+// b = b << 1
+// a = a - 1 || goto @label
+// fin: a = b
+// mem[sp] = a
+memory[172] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |
+ (31 << `P_ADDR) | `MC_W_A;
+memory[173] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[174] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp]
+ `MC_W_B;
+memory[175] = `MC_BRANCH | ((440 >> 2) << `P_ADDR); // goto @ashiftleft_loop
+`endif
+
+// 001_01100 (2c) ashiftright -------------------------------------
+`ifdef ENABLE_BARREL
+// b = mem[sp] & 5'b11111 : 5 bit shift
+// b = b | 7'b00_00000 : shift right, arithmetic
+// sp=sp+1
+// a = mem[sp]
+// a = a >>signed b
+// mem[sp] = a
+memory[176] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B;
+memory[177] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[178] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] | goto @shift_cont
+ `MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
+`else
+ `ifdef ENABLE_A_SHIFT
+// a = mem[sp] & 5'b11111
+// sp = sp + 1
+// b = FLIP(mem[sp])
+// label: a <= 0 ? goto @fin
+// b = b signed_<< 1
+// a = a - 1 || goto @label
+// fin: a = FLIP(b)
+// mem[sp] = a
+memory[176] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |
+ (31 << `P_ADDR) | `MC_W_A;
+memory[177] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[178] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = FLIP(mem[sp])
+ `MC_ALU_FLIP | `MC_W_B;
+memory[179] = `MC_BRANCH | ((432 >> 2) << `P_ADDR); // goto @ashiftright_loop
+ `else
+memory[176] = `MC_GO_BREAKPOINT;
+ `endif
+`endif
+
+// 001_01101 (2d) call -------------------------------------
+// a = mem[sp]
+// mem[sp]=pc+1
+// pc = a
+memory[180] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[181] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; // a = pc + 1
+memory[182] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_ALU_NOP_B | // mem[sp] = a || pc = b
+ `MC_SEL_ALU_B | `MC_W_PC;
+memory[183] = `MC_FETCH; // op_cached? decode : goto next
+
+// 001_01110 (2e) eq -------------------------------------
+// a = mem[sp]
+// sp = sp + 1
+// (mem[sp] - a == 0) ? mem[sp] = 1 : mem[sp] = 0
+memory[184] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = NOT(mem[sp])
+ `MC_SEL_READ_DATA | `MC_ALU_NOT | `MC_W_A;
+memory[185] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS | // a = a + 1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[186] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[187] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] + a || goto @eq_check
+ `MC_ALU_PLUS |`MC_SEL_ALU_A | `MC_W_A |
+ ( (416 >> 2) << `P_ADDR) | `MC_BRANCH;
+
+// 001_01111 (2f) neq -------------------------------------
+// a = mem[sp]
+// sp = sp + 1
+// (mem[sp] - a != 0) ? mem[sp] = 1 : mem[sp] = 0
+memory[188] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = NOT(mem[sp])
+ `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[189] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS | // a = a + 1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[190] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[191] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] + a || goto @neq_check
+ `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A |
+ ( (412 >> 2) << `P_ADDR) | `MC_BRANCH;
+
+// 001_10000 (30) neg -------------------------------------
+// a = NOT(mem[sp])
+// a = a + 1
+// mem[sp] = a
+memory[192] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = NOT(mem[sp])
+ `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[193] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + 1
+ (1 << `P_ADDR) | `MC_SEL_ALU_MC_CONST | `MC_W_A;
+memory[194] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 001_10001 (31) sub -------------------------------------
+// mem[sp+1] = mem[sp+1] - mem[sp]
+// sp = sp + 1
+memory[196] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = NOT(mem[sp])
+ `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[197] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + 1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[198] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[199] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] + a || goto @sub_cont (set_mem[sp]=a)
+ `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | ((400>>2) << `P_ADDR) |
+ `MC_BRANCH;
+
+// 001_10010 (32) xor -------------------------------------
+`ifdef ENABLE_XOR
+// mem[sp+1] = mem[sp+1] ^ mem[sp]
+// sp = sp + 1
+memory[200] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[201] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a ^ mem[sp]
+ `MC_ALU_XOR |`MC_SEL_ALU_A | `MC_W_A;
+memory[202] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+// ALU doesn't perform XOR operation
+// mem[sp+1] = mem[sp] ^ mem[sp+1] -> A^B=(A&~B)|(~A&B)
+// a = ~mem[sp] --> a = ~A
+// sp = sp + 1
+// a = mem[sp] & a --> a = ~A&B
+// b = ~a --> b = A&~B
+// a = a | b --> a = ~A&B | A&~B
+// mem[sp] = a
+memory[200] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = ~mem[sp] --> a=~A
+ `MC_ALU_NOT | `MC_W_A;
+memory[201] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[202] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] & a --> a = ~A&B
+ `MC_ALU_AND | `MC_SEL_ALU_A | `MC_W_A;
+memory[203] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_NOT | // b = ~a || goto @xor_cont --> b = A&~B
+ `MC_W_B | `MC_BRANCH | ((428 >> 2) << `P_ADDR);
+`endif
+
+// 001_10011 (33) loadb -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+// mem[sp] = BYTE(mem[sp], mem[mem[sp]])
+memory[204] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp]
+ `MC_MEM_R | `MC_W_A;
+memory[205] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | // a = byte(a, mem[a])
+ `MC_W_A | `MC_BYTE;
+memory[206] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+// b=pc
+// pc = mem[sp]
+// opcode_cache=mem[pc]
+// a = opcode
+// mem[sp]=a
+// pc=b
+// fetch
+memory[204] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | // b = pc
+ `MC_W_B;
+memory[205] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // pc = mem[sp]
+ `MC_W_PC;
+memory[206] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R | // opcode_cache = mem[pc]
+ `MC_W_OPCODE;
+memory[207] = `MC_SEL_ALU_OPCODE | `MC_ALU_NOP_B | `MC_W_A | // a = opcode -> byte(pc, mem[pc]) || goto @loadb_continued
+ `MC_BRANCH | ( (396 >> 2) << `P_ADDR);
+`endif
+
+// 001_10100 (34) storeb -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+// BYTE( mem[mem[sp]] <= mem[sp+1] )
+// sp = sp + 2
+memory[208] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[209] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[210] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a = mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[211] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_BYTE | `MC_GO_NEXT; // BYTE(mem[b] = a)
+`else
+memory[208] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_10101 (35) div -------------------------------------
+`ifdef ENABLE_DIV
+// *** TODO: CHECK IF DIVIDE BY ZERO AND RAISE EXCEPTION ***
+// mem[sp+1] = mem[sp+1] / mem[sp]
+// sp = sp + 1
+memory[212] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[213] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp]
+ `MC_W_B;
+memory[214] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = a / b DON'T COMBINE MULTICYCLE ALU
+ `MC_ALU_DIV | `MC_W_A; // OPERATIONS WITH MEMORY READ/WRITE
+memory[215] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[212] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_10110 (36) mod -------------------------------------
+`ifdef ENABLE_DIV
+// mem[sp+1] = mem[sp+1] % mem[sp]
+// sp = sp + 1
+memory[216] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[217] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp]
+ `MC_W_B;
+memory[218] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = a % b DON'T COMBINE MULTICYCLE ALU
+ `MC_ALU_MOD | `MC_W_A; // OPERATIONS WITH MEMORY READ/WRITE
+memory[219] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[216] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_10111 (37) eqbranch -------------------------------------
+// a = sp + 1
+// a = mem[a]
+// a = mem[sp] || a == 0 ? { pc = pc + a; sp = sp + 2 }
+// else { sp = sp + 2, pc = pc + 1 }
+memory[220] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + 1
+ `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
+ `MC_W_A;
+memory[221] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[222] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A | // a = mem[sp] || a == 0 ? goto 456 (sp=sp+2, pc=pc+a)
+ `MC_BRANCHIF_A_ZERO | ((456>>2) << `P_ADDR);
+memory[223] = `MC_BRANCH | ((460>>2) << `P_ADDR); // else goto 460 (sp=sp+2, pc=pc+1)
+
+// 001_11000 (38) neqbranch -------------------------------------
+// a = sp + 1
+// a = mem[a]
+// a = mem[sp] || a == 0 ? { sp = sp + 2, pc = pc + 1 }
+// else { sp = sp + 2, pc = pc + a }
+memory[224] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + 1
+ `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
+ `MC_W_A;
+memory[225] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[226] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A | // a = mem[sp] || a == 0 ? goto 460 (sp=sp+2, pc=pc+1)
+ `MC_BRANCHIF_A_ZERO | ((460>>2) << `P_ADDR);
+memory[227] = `MC_BRANCH | ((456>>2) << `P_ADDR); // else goto 456 (sp=sp+2, pc=pc+a)
+
+// 001_11001 (39) poppcrel -------------------------------------
+// a = mem[sp]
+// sp = sp + 1
+// pc = pc + a
+memory[228] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a=mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[229] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // pc = pc + a
+ `MC_ALU_PLUS | `MC_W_PC;
+memory[230] = `MC_FETCH; // op_cached? decode : goto next
+
+// 001_11010 (3a) config -------------------------------------
+memory[232] = `MC_GO_BREAKPOINT;
+
+// 001_11011 (3b) pushpc -------------------------------------
+// sp = sp - 1
+// mem[sp] = pc
+memory[236] = `MC_CLEAR_IDIM | `MC_SP_MINUS_4 | `MC_W_A; // a = sp = sp - 1
+memory[237] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 001_11100 (3c) syscall_emulate ------------------------------
+memory[240] = `MC_GO_BREAKPOINT;
+
+// 001_11101 (3d) pushspadd -------------------------------------
+// a = mem[sp] << 2
+// mem[sp] = a + sp
+`ifdef ENABLE_BARREL
+memory[244] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp]
+ `MC_W_A_MEM;
+memory[245] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL | // a = a << 2 (left,arithmetic->10_00010)
+ `MC_SEL_ALU_MC_CONST | ( 66 << `P_ADDR) | `MC_W_A;
+memory[246] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + sp
+ `MC_ALU_PLUS | `MC_W_A;
+memory[247] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[244] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM; // a = mem[sp]
+memory[245] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + a
+ `MC_ALU_PLUS | `MC_W_A;
+memory[246] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + a
+ `MC_ALU_PLUS | `MC_W_A;
+memory[247] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + sp || goto @cont (->mem[sp] = a)
+ `MC_ALU_PLUS | `MC_W_A | ((400>>2) << `P_ADDR) | `MC_BRANCH;
+`endif
+
+// 001_11110 (3e) halfmult -------------------------------------
+memory[248] = `MC_GO_BREAKPOINT;
+
+// 001_11111 (3f) callpcrel -------------------------------------
+// a = mem[sp]
+// mem[sp]=pc+1
+// pc = pc + a
+memory[252] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[253] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = pc + 1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[254] = `MC_SEL_ADDR_SP | `MC_MEM_W; // mem[sp] = a;
+memory[255] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // pc = pc + b, goto @fetch
+ `MC_ALU_PLUS | `MC_W_PC | `MC_GO_FETCH;
+
+// --------------------- MICROCODE HOLE -----------------------------------
+
+
+
+
+// --------------------- CONTINUATION OF COMPLEX OPCODES ------------------
+
+`ifdef ENABLE_BYTE_SELECT
+// ipsum_end: ----------
+memory[392] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | // sp=0
+ `MC_W_SP;
+memory[393] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // pc=mem[sp] restore next pc
+ `MC_W_PC;
+memory[394] = `MC_SP_PLUS_4; // sp=sp+4
+memory[395] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // sp=mem[sp] restore sp
+ `MC_W_SP;
+memory[396] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (sum)
+memory[397] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_FETCH; // mem[sp]=a || fetch (return sum)
+`endif
+
+`ifndef ENABLE_BYTE_SELECT
+// loadb continued microcode -----
+// mem[sp]=a || pc=b
+// opcode_cache=mem[pc] || go next
+memory[396] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SEL_ALU_B | // mem[sp]=a || pc=b
+ `MC_ALU_NOP_B | `MC_W_PC;
+memory[397] = `MC_SEL_ADDR_PC | `MC_MEM_R | `MC_W_OPCODE | `MC_GO_NEXT; // opcode_cache=mem[pc] || go next
+`endif
+
+// sub/pushspadd continued microcode ----------------
+memory[400] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// ----- hole ------
+
+`ifdef ENABLE_BYTE_SELECT
+// ipsum_continue2: ------------
+memory[408] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // pc=pc-1; a=pc
+ `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_PC |
+ `MC_W_A;
+memory[409] = `MC_BRANCH | ((124 >> 2) << `P_ADDR); // goto @ipsum_loop
+`endif
+
+// neqcheck ----------
+memory[412] = `MC_BRANCHIF_A_ZERO | ((468 >> 2) << `P_ADDR); // a == 0 ? goto @set_mem[sp]=0
+memory[413] = `MC_BRANCH | ((464 >> 2) << `P_ADDR); // else goto @set_mem[sp]=1
+
+// eqcheck ----------
+memory[416] = `MC_BRANCHIF_A_ZERO | ((464 >> 2) << `P_ADDR); // a == 0 ? goto @set_mem[sp]=1
+memory[417] = `MC_BRANCH | ((468 >> 2) << `P_ADDR); // else goto @set_mem[sp]=0
+
+// lessthanorequal_check ----
+memory[420] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR); // a <= 0 ? goto @set_mem[sp]=1
+memory[421] = `MC_BRANCH | ((468 >> 2) << `P_ADDR); // else goto @set_mem[sp]=0
+
+// lessthan_check ----
+memory[424] = `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR); // a < 0 ? goto @set_mem[sp]=1
+memory[425] = `MC_BRANCH | ((468 >> 2) << `P_ADDR); // else goto @set_mem[sp]=0
+
+// xor_cont continued microcode -----------------------------------
+`ifndef ENABLE_XOR
+memory[428] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_OR | // a = a | b --> a = ~A&B | A&~B
+ `MC_SEL_ALU_B | `MC_W_A;
+memory[429] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`endif
+
+// ashiftright_loop continued microcode -----------------------------------
+`ifdef ENABLE_BARREL
+memory[432] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL | // a = a {<<|>>} b
+ `MC_SEL_ALU_B | `MC_W_A;
+memory[433] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+ `ifdef ENABLE_A_SHIFT
+memory[432] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((436 >> 2) << `P_ADDR); // (a <= 0) ? goto @ashiftright_exit
+memory[433] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + (-1)
+ `MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
+memory[434] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b = b signed_<< 1 || goto @ashiftright_loop
+ `MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((432 >>2) << `P_ADDR);
+// ashiftright_exit
+memory[436] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP | // a = FLIP(b)
+ `MC_W_A;
+memory[437] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+ `endif
+`endif
+
+// ashiftleft_loop continued microcode -----------------------------------
+`ifndef ENABLE_BARREL
+memory[440] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((444 >> 2) << `P_ADDR);// (a <= 0) ? goto @ashiftleft_exit
+memory[441] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + (-1)
+ `MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
+memory[442] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b = b << 1 || goto @ashiftleft_loop
+ `MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((440 >>2) << `P_ADDR);
+// ashiftleft_exit
+memory[444] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_NOP | // a = b
+ `MC_W_A;
+memory[445] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`endif
+
+// lshiftright_loop continued microcode -----------------------------------
+`ifdef ENABLE_A_SHIFT
+memory[448] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((452 >> 2) << `P_ADDR);// (a <= 0) ? goto @lshiftright_exit
+memory[449] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + (-1)
+ `MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
+memory[450] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b = b << 1 || goto @lshiftright_loop
+ `MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((448 >>2) << `P_ADDR);
+// lshiftright_exit
+memory[452] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP | // a = FLIP(b)
+ `MC_W_A;
+memory[453] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`endif
+
+// neqbranch / eqbranch --- continued microcode -------------------------------------
+// sp = sp + 2
+// pc = pc + a
+memory[456] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // sp = sp + 2
+ `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP;
+memory[457] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // pc = pc + a
+ `MC_ALU_PLUS | `MC_W_PC;
+memory[458] = `MC_FETCH; // op_cached? decode : goto fetch
+
+// neqbranch / eqbranch --- continued microcode -------------------------------------
+// sp = sp + 2
+// pc = pc + 1
+memory[460] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // sp = sp + 2
+ `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP;
+memory[461] = `MC_PC_PLUS_1; // pc = pc + 1
+memory[462] = `MC_FETCH; // op_cached? decode : goto fetch
+
+// neq / eq / lessthan_1 --- continued microcode --------------------
+// mem[sp] = 1
+memory[464] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (1 << `P_ADDR) | // a = 1
+ `MC_W_A;
+memory[465] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// neq / eq / lessthan_0 --- continued microcode --------------------
+// mem[sp] = 0
+memory[468] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (0 << `P_ADDR) | // a = 0
+ `MC_W_A;
+memory[469] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// MICROCODE ENTRY POINT AFTER RESET -------------------------------
+// initialize cpu registers
+// sp = @SP_START
+// pc = @RESET_VECTOR
+memory[473] = 0; // reserved and empty for correct cpu startup
+memory[474] = `MC_CLEAR_IDIM |`MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | // sp = @SP_START
+ (`SP_START << `P_ADDR) | `MC_W_SP;
+memory[475] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | `MC_W_PC | // pc = @RESET
+ (`RESET_VECTOR << `P_ADDR) | `MC_EXIT_INTERRUPT; // enable interrupts on reset
+// fall throught fetch/decode
+
+// FETCH / DECODE -------------------------------------
+// opcode=mem[pc]
+// decode (goto microcode entry point for opcode)
+memory[476] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R | // opcode_cache = mem[pc]
+ `MC_W_OPCODE;
+memory[477] = `MC_DECODE; // decode jump to microcode
+
+// NEXT OPCODE -------------------------------------
+// pc = pc + 1
+// opcode cached ? decode : goto fetch
+memory[480] = `MC_PC_PLUS_1; // pc = pc + 1
+memory[481] = `MC_FETCH; // pc_cached ? decode else fetch,decode
+
+// INTERRUPT REQUEST -------------------------------------
+// sp = sp - 1
+// mem[sp] = pc
+// pc = mem[EMULATED_VECTORS + 0]
+memory[484] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | // b = 0 (#0 in emulate table) || disable interrupts
+ `MC_W_B | `MC_ENTER_INTERRUPT;
+memory[485] = `MC_EMULATE; // emulate #0 (interrupt)
+
+// ---------------- OPCODES WITH PARAMETER IN OPCODE ----------------
+
+// im x (idim=0) 1_xxxxxxx -------------------------------------
+// sp = sp - 1
+// mem[sp] = IMM(IDIM, opcode)
+// idim = 1
+memory[488] = `MC_SP_MINUS_4; // sp = sp - 1
+memory[489] = `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A; // a = IMM(IDIM, opcode)
+memory[490] = `MC_SET_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_W | // MEM[sp] = a; IDIM=1
+ `MC_GO_NEXT;
+
+// 1_xxxxxxx im x (idim=1) -------------------------------------
+// mem[sp] = IMM(IDIM, mem[sp], opcode)
+memory[491] = `MC_SET_IDIM | `MC_SEL_READ_DATA | `MC_SEL_ADDR_SP | // a = IMM(IDIM, MEM[sp], opcode)
+ `MC_MEM_R | `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A;
+memory[492] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // MEM[sp] = a
+
+// 010_xxxxx storesp x
+// mem[sp + x<<2] = mem[sp]
+// sp = sp + 1
+memory[493] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // b = sp + offset
+ `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_B;
+memory[494] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[495] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT; // mem[b] = a
+
+// 011_xxxxx loadsp x -------------------------------------
+// mem[sp-1] = mem [sp + x<<2]
+// sp = sp - 1
+memory[496] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + offset
+ `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A;
+memory[497] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[498] = `MC_SP_MINUS_4; // sp = sp - 1
+memory[499] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0001_xxxx addsp x -------------------------------------
+// mem[sp] = mem[sp] + mem[sp + x<<2]
+memory[500] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + offset
+ `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A;
+memory[501] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[502] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
+ `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A; // a = a + mem[sp]
+memory[503] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 001_xxxxx emulate x -------------------------------------
+// <expects b = offset into table for emulated opcode>
+// sp = sp - 1
+// mem[sp] = pc + 1 emulated opcode microcode must set b to
+// a=@EMULATION_TABLE offset inside emulated_table prior to
+// pc = mem[a + b] calling the emulate microcode
+// fetch
+memory[504] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | // a = pc + 1
+ `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[505] = `MC_SP_MINUS_4; // sp = sp - 1
+memory[506] = `MC_SEL_ADDR_SP | `MC_MEM_W; // mem[sp] = a
+memory[507] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | `MC_W_A | // a = @vector_emulated
+ (`EMULATION_VECTOR << `P_ADDR);
+memory[508] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + b
+ `MC_SEL_ALU_B | `MC_W_A;
+memory[509] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | // pc = mem[a]
+ `MC_ALU_NOP | `MC_W_PC;
+memory[510] = `MC_FETCH;
+
+// --------------------- END OF MICROCODE PROGRAM --------------------------
+end
+
+endmodule
diff --git a/zpu/hdl/avalanche/readme.txt b/zpu/hdl/avalanche/readme.txt
new file mode 100644
index 0000000..3eb1baf
--- /dev/null
+++ b/zpu/hdl/avalanche/readme.txt
@@ -0,0 +1,91 @@
+This ZPU implementation, codenamed "avalanche" was
+contributed by Antonio Anton <antonio.anton@anro-ingenieros.com>.
+
+It's most interesting aspects are it's implementation using
+microcode, small size, reduced code size overhead and that
+it's implemented in Verilog.
+
+Please direct any questions to the zylin-zpu mailing list.
+
+The most urgently needed patches would be to provide working
+simulation examples and improved documentation.
+
+
+Øyvind Harboe
+
+
+Notes from Antonio:
+
+Hi,
+
+attached goes my zpu implementation in verilog in case anybody is
+interested in. Code is quite commented. Also microcode and opcodes are
+exhaustive commented (and more accurate that the HTML documentation in
+some cases :-) ).
+
+At the moment I have no time to send a working environment but I will
+get some time in next days and prepare a clean environment
+(software/hardware) and send to the list. The target HW is spartan3
+starter kit board (all peripherals working: vga, sram, uarts, etc.).
+
+Feel free to ask any question to the list I will do my best to answer
+quickly.
+
+Regards
+Antonio
+
+Hi,
+
+the zpu_core is complete and lot of bugs has been solved in the past but
+extensive testing and a complete test program has not been
+defined/executed; anyway I'm quite confident it works: this core
+executes eCos, FreeRTOS, Forth and other applications.
+
+Regarding FPGA resources for a "balanced" implementation (not the
+smallest, not the fastest):
+
+-cpu+alu+microcode rom: 671 LUT + 239 FF + 1 BRAM (50% of LUT is ALU)
+-complete soc (cpu, vga, uart, memory controller, interrupt controller,
+timers, gpio, spi, etc.): 1317 LUT + 716 FF + 1 BRAM
+
+Regarding "modelsim hello world"; I'm sorry but I don't modelsim;
+instead I use Icarus Verilog & gtkwave. The core has a "debug" facility
+which displays all opcode and registers (memory changes, sp, pc, etc..)
+during simulation execution.
+
+Regards
+Antonio
+
+
+> > Regarding FPGA resources for a "balanced" implementation (not the
+> > smallest, not the fastest):
+> >
+> > -cpu+alu+microcode rom: 671 LUT + 239 FF + 1 BRAM (50% of LUT is ALU)
+>
+> Are there any emulated instructions not implemented in
+> microcode?
+>
+
+*All* zpu opcodes are microcoded. For some opcodes (like *shift*),
+there are two versions; 32 bit barrel shift in HDL (up to 32 clocks) or
+1 bit shift in HDL microcode drived (up to ~130 clocks). They are
+selectable via `DEFINES in the zpu_core_defines.v
+
+Other opcodes like mult and div are 32 bit HDL only at the moment (there
+are enough room in microcode memory to implement as microcode) and
+software emulable as well.
+
+For the above figures (671 LUT + 239 FF): *shift* are 32 bit HDL and
+mult/div are software implemented.
+
+There are new opcodes (as per my needs) like memory bulk copy (sncpy,
+wcpy, wset) and ip checksum calculation (ipsum). There are room in
+microccode memory to define new opcodes using the holes in the ISA (for
+a complete list of opcodes and its function please see
+zpu_core_defines.v).
+
+Some future ideas (easy to implement in microcode)
+-on-chip debug
+-microcode update via software
+
+Regards
diff --git a/zpu/hdl/example/.cvsignore b/zpu/hdl/example/.cvsignore
new file mode 100644
index 0000000..8238018
--- /dev/null
+++ b/zpu/hdl/example/.cvsignore
@@ -0,0 +1,3 @@
+work
+vsim.wlf
+install
diff --git a/zpu/hdl/example/bram_dmips.vhd b/zpu/hdl/example/bram_dmips.vhd
new file mode 100644
index 0000000..07b19f4
--- /dev/null
+++ b/zpu/hdl/example/bram_dmips.vhd
@@ -0,0 +1,3356 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+ 0 => x"0b0b0b0b",
+ 1 => x"82700b0b",
+ 2 => x"80d5f40c",
+ 3 => x"3a0b0b80",
+ 4 => x"c4fb0400",
+ 5 => x"00000000",
+ 6 => x"00000000",
+ 7 => x"00000000",
+ 8 => x"80088408",
+ 9 => x"88080b0b",
+ 10 => x"80c5c22d",
+ 11 => x"880c840c",
+ 12 => x"800c0400",
+ 13 => x"00000000",
+ 14 => x"00000000",
+ 15 => x"00000000",
+ 16 => x"71fd0608",
+ 17 => x"72830609",
+ 18 => x"81058205",
+ 19 => x"832b2a83",
+ 20 => x"ffff0652",
+ 21 => x"04000000",
+ 22 => x"00000000",
+ 23 => x"00000000",
+ 24 => x"71fd0608",
+ 25 => x"83ffff73",
+ 26 => x"83060981",
+ 27 => x"05820583",
+ 28 => x"2b2b0906",
+ 29 => x"7383ffff",
+ 30 => x"0b0b0b0b",
+ 31 => x"83a70400",
+ 32 => x"72098105",
+ 33 => x"72057373",
+ 34 => x"09060906",
+ 35 => x"73097306",
+ 36 => x"070a8106",
+ 37 => x"53510400",
+ 38 => x"00000000",
+ 39 => x"00000000",
+ 40 => x"72722473",
+ 41 => x"732e0753",
+ 42 => x"51040000",
+ 43 => x"00000000",
+ 44 => x"00000000",
+ 45 => x"00000000",
+ 46 => x"00000000",
+ 47 => x"00000000",
+ 48 => x"71737109",
+ 49 => x"71068106",
+ 50 => x"30720a10",
+ 51 => x"0a720a10",
+ 52 => x"0a31050a",
+ 53 => x"81065151",
+ 54 => x"53510400",
+ 55 => x"00000000",
+ 56 => x"72722673",
+ 57 => x"732e0753",
+ 58 => x"51040000",
+ 59 => x"00000000",
+ 60 => x"00000000",
+ 61 => x"00000000",
+ 62 => x"00000000",
+ 63 => x"00000000",
+ 64 => x"00000000",
+ 65 => x"00000000",
+ 66 => x"00000000",
+ 67 => x"00000000",
+ 68 => x"00000000",
+ 69 => x"00000000",
+ 70 => x"00000000",
+ 71 => x"00000000",
+ 72 => x"0b0b0b88",
+ 73 => x"c3040000",
+ 74 => x"00000000",
+ 75 => x"00000000",
+ 76 => x"00000000",
+ 77 => x"00000000",
+ 78 => x"00000000",
+ 79 => x"00000000",
+ 80 => x"720a722b",
+ 81 => x"0a535104",
+ 82 => x"00000000",
+ 83 => x"00000000",
+ 84 => x"00000000",
+ 85 => x"00000000",
+ 86 => x"00000000",
+ 87 => x"00000000",
+ 88 => x"72729f06",
+ 89 => x"0981050b",
+ 90 => x"0b0b88a6",
+ 91 => x"05040000",
+ 92 => x"00000000",
+ 93 => x"00000000",
+ 94 => x"00000000",
+ 95 => x"00000000",
+ 96 => x"72722aff",
+ 97 => x"739f062a",
+ 98 => x"0974090a",
+ 99 => x"8106ff05",
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+ 2625 => x"00000000",
+ 2626 => x"56415820",
+ 2627 => x"4d495053",
+ 2628 => x"20726174",
+ 2629 => x"696e6720",
+ 2630 => x"2a203130",
+ 2631 => x"3030203d",
+ 2632 => x"20256420",
+ 2633 => x"0a000000",
+ 2634 => x"50726f67",
+ 2635 => x"72616d20",
+ 2636 => x"636f6d70",
+ 2637 => x"696c6564",
+ 2638 => x"20776974",
+ 2639 => x"686f7574",
+ 2640 => x"20277265",
+ 2641 => x"67697374",
+ 2642 => x"65722720",
+ 2643 => x"61747472",
+ 2644 => x"69627574",
+ 2645 => x"650a0000",
+ 2646 => x"4d656173",
+ 2647 => x"75726564",
+ 2648 => x"2074696d",
+ 2649 => x"6520746f",
+ 2650 => x"6f20736d",
+ 2651 => x"616c6c20",
+ 2652 => x"746f206f",
+ 2653 => x"62746169",
+ 2654 => x"6e206d65",
+ 2655 => x"616e696e",
+ 2656 => x"6766756c",
+ 2657 => x"20726573",
+ 2658 => x"756c7473",
+ 2659 => x"0a000000",
+ 2660 => x"506c6561",
+ 2661 => x"73652069",
+ 2662 => x"6e637265",
+ 2663 => x"61736520",
+ 2664 => x"6e756d62",
+ 2665 => x"6572206f",
+ 2666 => x"66207275",
+ 2667 => x"6e730a00",
+ 2668 => x"44485259",
+ 2669 => x"53544f4e",
+ 2670 => x"45205052",
+ 2671 => x"4f475241",
+ 2672 => x"4d2c2033",
+ 2673 => x"27524420",
+ 2674 => x"53545249",
+ 2675 => x"4e470000",
+ 2676 => x"00010202",
+ 2677 => x"03030303",
+ 2678 => x"04040404",
+ 2679 => x"04040404",
+ 2680 => x"05050505",
+ 2681 => x"05050505",
+ 2682 => x"05050505",
+ 2683 => x"05050505",
+ 2684 => x"06060606",
+ 2685 => x"06060606",
+ 2686 => x"06060606",
+ 2687 => x"06060606",
+ 2688 => x"06060606",
+ 2689 => x"06060606",
+ 2690 => x"06060606",
+ 2691 => x"06060606",
+ 2692 => x"07070707",
+ 2693 => x"07070707",
+ 2694 => x"07070707",
+ 2695 => x"07070707",
+ 2696 => x"07070707",
+ 2697 => x"07070707",
+ 2698 => x"07070707",
+ 2699 => x"07070707",
+ 2700 => x"07070707",
+ 2701 => x"07070707",
+ 2702 => x"07070707",
+ 2703 => x"07070707",
+ 2704 => x"07070707",
+ 2705 => x"07070707",
+ 2706 => x"07070707",
+ 2707 => x"07070707",
+ 2708 => x"08080808",
+ 2709 => x"08080808",
+ 2710 => x"08080808",
+ 2711 => x"08080808",
+ 2712 => x"08080808",
+ 2713 => x"08080808",
+ 2714 => x"08080808",
+ 2715 => x"08080808",
+ 2716 => x"08080808",
+ 2717 => x"08080808",
+ 2718 => x"08080808",
+ 2719 => x"08080808",
+ 2720 => x"08080808",
+ 2721 => x"08080808",
+ 2722 => x"08080808",
+ 2723 => x"08080808",
+ 2724 => x"08080808",
+ 2725 => x"08080808",
+ 2726 => x"08080808",
+ 2727 => x"08080808",
+ 2728 => x"08080808",
+ 2729 => x"08080808",
+ 2730 => x"08080808",
+ 2731 => x"08080808",
+ 2732 => x"08080808",
+ 2733 => x"08080808",
+ 2734 => x"08080808",
+ 2735 => x"08080808",
+ 2736 => x"08080808",
+ 2737 => x"08080808",
+ 2738 => x"08080808",
+ 2739 => x"08080808",
+ 2740 => x"43000000",
+ 2741 => x"64756d6d",
+ 2742 => x"792e6578",
+ 2743 => x"65000000",
+ 2744 => x"00ffffff",
+ 2745 => x"ff00ffff",
+ 2746 => x"ffff00ff",
+ 2747 => x"ffffff00",
+ 2748 => x"00000000",
+ 2749 => x"00000000",
+ 2750 => x"00000000",
+ 2751 => x"000032dc",
+ 2752 => x"0000c350",
+ 2753 => x"00000000",
+ 2754 => x"00000000",
+ 2755 => x"00000000",
+ 2756 => x"00000000",
+ 2757 => x"00000000",
+ 2758 => x"00000000",
+ 2759 => x"00000000",
+ 2760 => x"00000000",
+ 2761 => x"00000000",
+ 2762 => x"00000000",
+ 2763 => x"00000000",
+ 2764 => x"00000000",
+ 2765 => x"00000000",
+ 2766 => x"ffffffff",
+ 2767 => x"00000000",
+ 2768 => x"00020000",
+ 2769 => x"00000000",
+ 2770 => x"00000000",
+ 2771 => x"00002b44",
+ 2772 => x"00002b44",
+ 2773 => x"00002b4c",
+ 2774 => x"00002b4c",
+ 2775 => x"00002b54",
+ 2776 => x"00002b54",
+ 2777 => x"00002b5c",
+ 2778 => x"00002b5c",
+ 2779 => x"00002b64",
+ 2780 => x"00002b64",
+ 2781 => x"00002b6c",
+ 2782 => x"00002b6c",
+ 2783 => x"00002b74",
+ 2784 => x"00002b74",
+ 2785 => x"00002b7c",
+ 2786 => x"00002b7c",
+ 2787 => x"00002b84",
+ 2788 => x"00002b84",
+ 2789 => x"00002b8c",
+ 2790 => x"00002b8c",
+ 2791 => x"00002b94",
+ 2792 => x"00002b94",
+ 2793 => x"00002b9c",
+ 2794 => x"00002b9c",
+ 2795 => x"00002ba4",
+ 2796 => x"00002ba4",
+ 2797 => x"00002bac",
+ 2798 => x"00002bac",
+ 2799 => x"00002bb4",
+ 2800 => x"00002bb4",
+ 2801 => x"00002bbc",
+ 2802 => x"00002bbc",
+ 2803 => x"00002bc4",
+ 2804 => x"00002bc4",
+ 2805 => x"00002bcc",
+ 2806 => x"00002bcc",
+ 2807 => x"00002bd4",
+ 2808 => x"00002bd4",
+ 2809 => x"00002bdc",
+ 2810 => x"00002bdc",
+ 2811 => x"00002be4",
+ 2812 => x"00002be4",
+ 2813 => x"00002bec",
+ 2814 => x"00002bec",
+ 2815 => x"00002bf4",
+ 2816 => x"00002bf4",
+ 2817 => x"00002bfc",
+ 2818 => x"00002bfc",
+ 2819 => x"00002c04",
+ 2820 => x"00002c04",
+ 2821 => x"00002c0c",
+ 2822 => x"00002c0c",
+ 2823 => x"00002c14",
+ 2824 => x"00002c14",
+ 2825 => x"00002c1c",
+ 2826 => x"00002c1c",
+ 2827 => x"00002c24",
+ 2828 => x"00002c24",
+ 2829 => x"00002c2c",
+ 2830 => x"00002c2c",
+ 2831 => x"00002c34",
+ 2832 => x"00002c34",
+ 2833 => x"00002c3c",
+ 2834 => x"00002c3c",
+ 2835 => x"00002c44",
+ 2836 => x"00002c44",
+ 2837 => x"00002c4c",
+ 2838 => x"00002c4c",
+ 2839 => x"00002c54",
+ 2840 => x"00002c54",
+ 2841 => x"00002c5c",
+ 2842 => x"00002c5c",
+ 2843 => x"00002c64",
+ 2844 => x"00002c64",
+ 2845 => x"00002c6c",
+ 2846 => x"00002c6c",
+ 2847 => x"00002c74",
+ 2848 => x"00002c74",
+ 2849 => x"00002c7c",
+ 2850 => x"00002c7c",
+ 2851 => x"00002c84",
+ 2852 => x"00002c84",
+ 2853 => x"00002c8c",
+ 2854 => x"00002c8c",
+ 2855 => x"00002c94",
+ 2856 => x"00002c94",
+ 2857 => x"00002c9c",
+ 2858 => x"00002c9c",
+ 2859 => x"00002ca4",
+ 2860 => x"00002ca4",
+ 2861 => x"00002cac",
+ 2862 => x"00002cac",
+ 2863 => x"00002cb4",
+ 2864 => x"00002cb4",
+ 2865 => x"00002cbc",
+ 2866 => x"00002cbc",
+ 2867 => x"00002cc4",
+ 2868 => x"00002cc4",
+ 2869 => x"00002ccc",
+ 2870 => x"00002ccc",
+ 2871 => x"00002cd4",
+ 2872 => x"00002cd4",
+ 2873 => x"00002cdc",
+ 2874 => x"00002cdc",
+ 2875 => x"00002ce4",
+ 2876 => x"00002ce4",
+ 2877 => x"00002cec",
+ 2878 => x"00002cec",
+ 2879 => x"00002cf4",
+ 2880 => x"00002cf4",
+ 2881 => x"00002cfc",
+ 2882 => x"00002cfc",
+ 2883 => x"00002d04",
+ 2884 => x"00002d04",
+ 2885 => x"00002d0c",
+ 2886 => x"00002d0c",
+ 2887 => x"00002d14",
+ 2888 => x"00002d14",
+ 2889 => x"00002d1c",
+ 2890 => x"00002d1c",
+ 2891 => x"00002d24",
+ 2892 => x"00002d24",
+ 2893 => x"00002d2c",
+ 2894 => x"00002d2c",
+ 2895 => x"00002d34",
+ 2896 => x"00002d34",
+ 2897 => x"00002d3c",
+ 2898 => x"00002d3c",
+ 2899 => x"00002d44",
+ 2900 => x"00002d44",
+ 2901 => x"00002d4c",
+ 2902 => x"00002d4c",
+ 2903 => x"00002d54",
+ 2904 => x"00002d54",
+ 2905 => x"00002d5c",
+ 2906 => x"00002d5c",
+ 2907 => x"00002d64",
+ 2908 => x"00002d64",
+ 2909 => x"00002d6c",
+ 2910 => x"00002d6c",
+ 2911 => x"00002d74",
+ 2912 => x"00002d74",
+ 2913 => x"00002d7c",
+ 2914 => x"00002d7c",
+ 2915 => x"00002d84",
+ 2916 => x"00002d84",
+ 2917 => x"00002d8c",
+ 2918 => x"00002d8c",
+ 2919 => x"00002d94",
+ 2920 => x"00002d94",
+ 2921 => x"00002d9c",
+ 2922 => x"00002d9c",
+ 2923 => x"00002da4",
+ 2924 => x"00002da4",
+ 2925 => x"00002dac",
+ 2926 => x"00002dac",
+ 2927 => x"00002db4",
+ 2928 => x"00002db4",
+ 2929 => x"00002dbc",
+ 2930 => x"00002dbc",
+ 2931 => x"00002dc4",
+ 2932 => x"00002dc4",
+ 2933 => x"00002dcc",
+ 2934 => x"00002dcc",
+ 2935 => x"00002dd4",
+ 2936 => x"00002dd4",
+ 2937 => x"00002ddc",
+ 2938 => x"00002ddc",
+ 2939 => x"00002de4",
+ 2940 => x"00002de4",
+ 2941 => x"00002dec",
+ 2942 => x"00002dec",
+ 2943 => x"00002df4",
+ 2944 => x"00002df4",
+ 2945 => x"00002dfc",
+ 2946 => x"00002dfc",
+ 2947 => x"00002e04",
+ 2948 => x"00002e04",
+ 2949 => x"00002e0c",
+ 2950 => x"00002e0c",
+ 2951 => x"00002e14",
+ 2952 => x"00002e14",
+ 2953 => x"00002e1c",
+ 2954 => x"00002e1c",
+ 2955 => x"00002e24",
+ 2956 => x"00002e24",
+ 2957 => x"00002e2c",
+ 2958 => x"00002e2c",
+ 2959 => x"00002e34",
+ 2960 => x"00002e34",
+ 2961 => x"00002e3c",
+ 2962 => x"00002e3c",
+ 2963 => x"00002e44",
+ 2964 => x"00002e44",
+ 2965 => x"00002e4c",
+ 2966 => x"00002e4c",
+ 2967 => x"00002e54",
+ 2968 => x"00002e54",
+ 2969 => x"00002e5c",
+ 2970 => x"00002e5c",
+ 2971 => x"00002e64",
+ 2972 => x"00002e64",
+ 2973 => x"00002e6c",
+ 2974 => x"00002e6c",
+ 2975 => x"00002e74",
+ 2976 => x"00002e74",
+ 2977 => x"00002e7c",
+ 2978 => x"00002e7c",
+ 2979 => x"00002e84",
+ 2980 => x"00002e84",
+ 2981 => x"00002e8c",
+ 2982 => x"00002e8c",
+ 2983 => x"00002e94",
+ 2984 => x"00002e94",
+ 2985 => x"00002e9c",
+ 2986 => x"00002e9c",
+ 2987 => x"00002ea4",
+ 2988 => x"00002ea4",
+ 2989 => x"00002eac",
+ 2990 => x"00002eac",
+ 2991 => x"00002eb4",
+ 2992 => x"00002eb4",
+ 2993 => x"00002ebc",
+ 2994 => x"00002ebc",
+ 2995 => x"00002ec4",
+ 2996 => x"00002ec4",
+ 2997 => x"00002ecc",
+ 2998 => x"00002ecc",
+ 2999 => x"00002ed4",
+ 3000 => x"00002ed4",
+ 3001 => x"00002edc",
+ 3002 => x"00002edc",
+ 3003 => x"00002ee4",
+ 3004 => x"00002ee4",
+ 3005 => x"00002eec",
+ 3006 => x"00002eec",
+ 3007 => x"00002ef4",
+ 3008 => x"00002ef4",
+ 3009 => x"00002efc",
+ 3010 => x"00002efc",
+ 3011 => x"00002f04",
+ 3012 => x"00002f04",
+ 3013 => x"00002f0c",
+ 3014 => x"00002f0c",
+ 3015 => x"00002f14",
+ 3016 => x"00002f14",
+ 3017 => x"00002f1c",
+ 3018 => x"00002f1c",
+ 3019 => x"00002f24",
+ 3020 => x"00002f24",
+ 3021 => x"00002f2c",
+ 3022 => x"00002f2c",
+ 3023 => x"00002f34",
+ 3024 => x"00002f34",
+ 3025 => x"00002f3c",
+ 3026 => x"00002f3c",
+ 3027 => x"00002f50",
+ 3028 => x"00000000",
+ 3029 => x"000031b8",
+ 3030 => x"00003214",
+ 3031 => x"00003270",
+ 3032 => x"00000000",
+ 3033 => x"00000000",
+ 3034 => x"00000000",
+ 3035 => x"00000000",
+ 3036 => x"00000000",
+ 3037 => x"00000000",
+ 3038 => x"00000000",
+ 3039 => x"00000000",
+ 3040 => x"00000000",
+ 3041 => x"00002ad0",
+ 3042 => x"00000000",
+ 3043 => x"00000000",
+ 3044 => x"00000000",
+ 3045 => x"00000000",
+ 3046 => x"00000000",
+ 3047 => x"00000000",
+ 3048 => x"00000000",
+ 3049 => x"00000000",
+ 3050 => x"00000000",
+ 3051 => x"00000000",
+ 3052 => x"00000000",
+ 3053 => x"00000000",
+ 3054 => x"00000000",
+ 3055 => x"00000000",
+ 3056 => x"00000000",
+ 3057 => x"00000000",
+ 3058 => x"00000000",
+ 3059 => x"00000000",
+ 3060 => x"00000000",
+ 3061 => x"00000000",
+ 3062 => x"00000000",
+ 3063 => x"00000000",
+ 3064 => x"00000000",
+ 3065 => x"00000000",
+ 3066 => x"00000000",
+ 3067 => x"00000000",
+ 3068 => x"00000000",
+ 3069 => x"00000000",
+ 3070 => x"00000001",
+ 3071 => x"330eabcd",
+ 3072 => x"1234e66d",
+ 3073 => x"deec0005",
+ 3074 => x"000b0000",
+ 3075 => x"00000000",
+ 3076 => x"00000000",
+ 3077 => x"00000000",
+ 3078 => x"00000000",
+ 3079 => x"00000000",
+ 3080 => x"00000000",
+ 3081 => x"00000000",
+ 3082 => x"00000000",
+ 3083 => x"00000000",
+ 3084 => x"00000000",
+ 3085 => x"00000000",
+ 3086 => x"00000000",
+ 3087 => x"00000000",
+ 3088 => x"00000000",
+ 3089 => x"00000000",
+ 3090 => x"00000000",
+ 3091 => x"00000000",
+ 3092 => x"00000000",
+ 3093 => x"00000000",
+ 3094 => x"00000000",
+ 3095 => x"00000000",
+ 3096 => x"00000000",
+ 3097 => x"00000000",
+ 3098 => x"00000000",
+ 3099 => x"00000000",
+ 3100 => x"00000000",
+ 3101 => x"00000000",
+ 3102 => x"00000000",
+ 3103 => x"00000000",
+ 3104 => x"00000000",
+ 3105 => x"00000000",
+ 3106 => x"00000000",
+ 3107 => x"00000000",
+ 3108 => x"00000000",
+ 3109 => x"00000000",
+ 3110 => x"00000000",
+ 3111 => x"00000000",
+ 3112 => x"00000000",
+ 3113 => x"00000000",
+ 3114 => x"00000000",
+ 3115 => x"00000000",
+ 3116 => x"00000000",
+ 3117 => x"00000000",
+ 3118 => x"00000000",
+ 3119 => x"00000000",
+ 3120 => x"00000000",
+ 3121 => x"00000000",
+ 3122 => x"00000000",
+ 3123 => x"00000000",
+ 3124 => x"00000000",
+ 3125 => x"00000000",
+ 3126 => x"00000000",
+ 3127 => x"00000000",
+ 3128 => x"00000000",
+ 3129 => x"00000000",
+ 3130 => x"00000000",
+ 3131 => x"00000000",
+ 3132 => x"00000000",
+ 3133 => x"00000000",
+ 3134 => x"00000000",
+ 3135 => x"00000000",
+ 3136 => x"00000000",
+ 3137 => x"00000000",
+ 3138 => x"00000000",
+ 3139 => x"00000000",
+ 3140 => x"00000000",
+ 3141 => x"00000000",
+ 3142 => x"00000000",
+ 3143 => x"00000000",
+ 3144 => x"00000000",
+ 3145 => x"00000000",
+ 3146 => x"00000000",
+ 3147 => x"00000000",
+ 3148 => x"00000000",
+ 3149 => x"00000000",
+ 3150 => x"00000000",
+ 3151 => x"00000000",
+ 3152 => x"00000000",
+ 3153 => x"00000000",
+ 3154 => x"00000000",
+ 3155 => x"00000000",
+ 3156 => x"00000000",
+ 3157 => x"00000000",
+ 3158 => x"00000000",
+ 3159 => x"00000000",
+ 3160 => x"00000000",
+ 3161 => x"00000000",
+ 3162 => x"00000000",
+ 3163 => x"00000000",
+ 3164 => x"00000000",
+ 3165 => x"00000000",
+ 3166 => x"00000000",
+ 3167 => x"00000000",
+ 3168 => x"00000000",
+ 3169 => x"00000000",
+ 3170 => x"00000000",
+ 3171 => x"00000000",
+ 3172 => x"00000000",
+ 3173 => x"00000000",
+ 3174 => x"00000000",
+ 3175 => x"00000000",
+ 3176 => x"00000000",
+ 3177 => x"00000000",
+ 3178 => x"00000000",
+ 3179 => x"00000000",
+ 3180 => x"00000000",
+ 3181 => x"00000000",
+ 3182 => x"00000000",
+ 3183 => x"00000000",
+ 3184 => x"00000000",
+ 3185 => x"00000000",
+ 3186 => x"00000000",
+ 3187 => x"00000000",
+ 3188 => x"00000000",
+ 3189 => x"00000000",
+ 3190 => x"00000000",
+ 3191 => x"00000000",
+ 3192 => x"00000000",
+ 3193 => x"00000000",
+ 3194 => x"00000000",
+ 3195 => x"00000000",
+ 3196 => x"00000000",
+ 3197 => x"00000000",
+ 3198 => x"00000000",
+ 3199 => x"00000000",
+ 3200 => x"00000000",
+ 3201 => x"00000000",
+ 3202 => x"00000000",
+ 3203 => x"00000000",
+ 3204 => x"00000000",
+ 3205 => x"00000000",
+ 3206 => x"00000000",
+ 3207 => x"00000000",
+ 3208 => x"00000000",
+ 3209 => x"00000000",
+ 3210 => x"00000000",
+ 3211 => x"00000000",
+ 3212 => x"00000000",
+ 3213 => x"00000000",
+ 3214 => x"00000000",
+ 3215 => x"00000000",
+ 3216 => x"00000000",
+ 3217 => x"00000000",
+ 3218 => x"00000000",
+ 3219 => x"00000000",
+ 3220 => x"00000000",
+ 3221 => x"00000000",
+ 3222 => x"00000000",
+ 3223 => x"00000000",
+ 3224 => x"00000000",
+ 3225 => x"00000000",
+ 3226 => x"00000000",
+ 3227 => x"00000000",
+ 3228 => x"00000000",
+ 3229 => x"00000000",
+ 3230 => x"00000000",
+ 3231 => x"00000000",
+ 3232 => x"00000000",
+ 3233 => x"00000000",
+ 3234 => x"00000000",
+ 3235 => x"00000000",
+ 3236 => x"00000000",
+ 3237 => x"00000000",
+ 3238 => x"00000000",
+ 3239 => x"00000000",
+ 3240 => x"00000000",
+ 3241 => x"00000000",
+ 3242 => x"00000000",
+ 3243 => x"00000000",
+ 3244 => x"00000000",
+ 3245 => x"00000000",
+ 3246 => x"00000000",
+ 3247 => x"00000000",
+ 3248 => x"00000000",
+ 3249 => x"00000000",
+ 3250 => x"00000000",
+ 3251 => x"00002ad4",
+ 3252 => x"ffffffff",
+ 3253 => x"00000000",
+ 3254 => x"ffffffff",
+ 3255 => x"00000000",
+ 3256 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+ report "write collision" severity failure;
+ end if;
+
+ if (memAWriteEnable = '1') then
+ ram(to_integer(unsigned(memAAddr))) := memAWrite;
+ memARead <= memAWrite;
+ else
+ memARead <= ram(to_integer(unsigned(memAAddr)));
+ end if;
+ end if;
+end process;
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memBWriteEnable = '1') then
+ ram(to_integer(unsigned(memBAddr))) := memBWrite;
+ memBRead <= memBWrite;
+ else
+ memBRead <= ram(to_integer(unsigned(memBAddr)));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd
new file mode 100644
index 0000000..cc8d8c6
--- /dev/null
+++ b/zpu/hdl/example/helloworld.vhd
@@ -0,0 +1,3154 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"c4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"9f2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"e32d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfd40c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6d93f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc0",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c0085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"d408802e",
+299 => x"a43880cf",
+300 => x"d808822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc00c",
+304 => x"82a0800b",
+305 => x"80dfc40c",
+306 => x"8290800b",
+307 => x"80dfc80c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc0",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfc40cf8",
+314 => x"80808480",
+315 => x"0b80dfc8",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c00c80c0",
+320 => x"a880940b",
+321 => x"80dfc40c",
+322 => x"0b0b80cf",
+323 => x"8c0b80df",
+324 => x"c80c0470",
+325 => x"7080dfcc",
+326 => x"335170a7",
+327 => x"3880cfe0",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe00c",
+332 => x"702d80cf",
+333 => x"e0087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfcc3450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"bc08802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
+342 => x"802e0981",
+343 => x"06833850",
+344 => x"040b0b80",
+345 => x"dfbc510b",
+346 => x"0b0bf594",
+347 => x"3f500404",
+348 => x"fe3d0d89",
+349 => x"5380cf90",
+350 => x"5182c13f",
+351 => x"80cfa051",
+352 => x"82ba3f81",
+353 => x"0a0b80df",
+354 => x"d80cff0b",
+355 => x"80dfdc0c",
+356 => x"ff135372",
+357 => x"8025de38",
+358 => x"72800c84",
+359 => x"3d0d04fb",
+360 => x"3d0d7779",
+361 => x"55558056",
+362 => x"757524ab",
+363 => x"38807424",
+364 => x"9d388053",
+365 => x"73527451",
+366 => x"80e13f80",
+367 => x"08547580",
+368 => x"2e853880",
+369 => x"08305473",
+370 => x"800c873d",
+371 => x"0d047330",
+372 => x"76813257",
+373 => x"54dc3974",
+374 => x"30558156",
+375 => x"738025d2",
+376 => x"38ec39fa",
+377 => x"3d0d787a",
+378 => x"57558057",
+379 => x"767524a4",
+380 => x"38759f2c",
+381 => x"54815375",
+382 => x"74327431",
+383 => x"5274519b",
+384 => x"3f800854",
+385 => x"76802e85",
+386 => x"38800830",
+387 => x"5473800c",
+388 => x"883d0d04",
+389 => x"74305581",
+390 => x"57d739fc",
+391 => x"3d0d7678",
+392 => x"53548153",
+393 => x"80747326",
+394 => x"52557280",
+395 => x"2e983870",
+396 => x"802eab38",
+397 => x"807224a6",
+398 => x"38711073",
+399 => x"10757226",
+400 => x"53545272",
+401 => x"ea387351",
+402 => x"78833874",
+403 => x"5170800c",
+404 => x"863d0d04",
+405 => x"720a100a",
+406 => x"720a100a",
+407 => x"53537280",
+408 => x"2ee43871",
+409 => x"7426ed38",
+410 => x"73723175",
+411 => x"7407740a",
+412 => x"100a740a",
+413 => x"100a5555",
+414 => x"5654e339",
+415 => x"f73d0d7c",
+416 => x"70525380",
+417 => x"f93f7254",
+418 => x"80085580",
+419 => x"cfb05681",
+420 => x"57800881",
+421 => x"055a8b3d",
+422 => x"e4115953",
+423 => x"8259f413",
+424 => x"527b8811",
+425 => x"08525381",
+426 => x"b23f8008",
+427 => x"30708008",
+428 => x"079f2c8a",
+429 => x"07800c53",
+430 => x"8b3d0d04",
+431 => x"f63d0d7c",
+432 => x"80cfe408",
+433 => x"71535553",
+434 => x"b53f7255",
+435 => x"80085680",
+436 => x"cfb05781",
+437 => x"58800881",
+438 => x"055b8c3d",
+439 => x"e4115a53",
+440 => x"825af413",
+441 => x"52881408",
+442 => x"5180f03f",
+443 => x"80083070",
+444 => x"8008079f",
+445 => x"2c8a0780",
+446 => x"0c548c3d",
+447 => x"0d047070",
+448 => x"70707570",
+449 => x"71830653",
+450 => x"555270b4",
+451 => x"38717008",
+452 => x"7009f7fb",
+453 => x"fdff1206",
+454 => x"f8848281",
+455 => x"80065452",
+456 => x"53719b38",
+457 => x"84137008",
+458 => x"7009f7fb",
+459 => x"fdff1206",
+460 => x"f8848281",
+461 => x"80065452",
+462 => x"5371802e",
+463 => x"e7387252",
+464 => x"71335372",
+465 => x"802e8a38",
+466 => x"81127033",
+467 => x"545272f8",
+468 => x"38717431",
+469 => x"800c5050",
+470 => x"505004f2",
+471 => x"3d0d6062",
+472 => x"88110870",
+473 => x"58565f5a",
+474 => x"73802e81",
+475 => x"8c388c1a",
+476 => x"2270832a",
+477 => x"81328106",
+478 => x"56587486",
+479 => x"38901a08",
+480 => x"91387951",
+481 => x"90b73fff",
+482 => x"55800880",
+483 => x"ec388c1a",
+484 => x"22587d08",
+485 => x"55807883",
+486 => x"ffff0670",
+487 => x"0a100a81",
+488 => x"06415c57",
+489 => x"7e772e80",
+490 => x"d7387690",
+491 => x"38740884",
+492 => x"16088817",
+493 => x"57585676",
+494 => x"802ef238",
+495 => x"76548880",
+496 => x"77278438",
+497 => x"88805473",
+498 => x"5375529c",
+499 => x"1a0851a4",
+500 => x"1a085877",
+501 => x"2d800b80",
+502 => x"082582e0",
+503 => x"38800816",
+504 => x"77800831",
+505 => x"7f880508",
+506 => x"80083170",
+507 => x"6188050c",
+508 => x"5b585678",
+509 => x"ffb43880",
+510 => x"5574800c",
+511 => x"903d0d04",
+512 => x"7a813281",
+513 => x"06774056",
+514 => x"75802e81",
+515 => x"bd387690",
+516 => x"38740884",
+517 => x"16088817",
+518 => x"57585976",
+519 => x"802ef238",
+520 => x"881a0878",
+521 => x"83ffff06",
+522 => x"70892a81",
+523 => x"06565956",
+524 => x"73802e82",
+525 => x"f8387577",
+526 => x"278b3877",
+527 => x"872a8106",
+528 => x"5c7b82b5",
+529 => x"38767627",
+530 => x"83387656",
+531 => x"75537852",
+532 => x"79085185",
+533 => x"833f881a",
+534 => x"08763188",
+535 => x"1b0c7908",
+536 => x"167a0c76",
+537 => x"56751977",
+538 => x"77317f88",
+539 => x"05087831",
+540 => x"70618805",
+541 => x"0c415859",
+542 => x"7e802efe",
+543 => x"fa388c1a",
+544 => x"2258ff8a",
+545 => x"39787954",
+546 => x"7c537b52",
+547 => x"5684c93f",
+548 => x"881a0879",
+549 => x"31881b0c",
+550 => x"7908197a",
+551 => x"0c7c7631",
+552 => x"5d7c8e38",
+553 => x"79518ff2",
+554 => x"3f800881",
+555 => x"8f388008",
+556 => x"5f751c77",
+557 => x"77317f88",
+558 => x"05087831",
+559 => x"70618805",
+560 => x"0c5d585c",
+561 => x"7a802efe",
+562 => x"ae387681",
+563 => x"83387408",
+564 => x"84160888",
+565 => x"1757585c",
+566 => x"76802ef2",
+567 => x"3876538a",
+568 => x"527b5182",
+569 => x"d33f8008",
+570 => x"7c318105",
+571 => x"5d800884",
+572 => x"3881175d",
+573 => x"815f7c59",
+574 => x"767d2783",
+575 => x"38765994",
+576 => x"1a08881b",
+577 => x"08115758",
+578 => x"807a085c",
+579 => x"54901a08",
+580 => x"7b278338",
+581 => x"81547579",
+582 => x"25843873",
+583 => x"ba387779",
+584 => x"24fee238",
+585 => x"77537b52",
+586 => x"9c1a0851",
+587 => x"a41a0859",
+588 => x"782d8008",
+589 => x"56800880",
+590 => x"24fee238",
+591 => x"8c1a2280",
+592 => x"c0075e7d",
+593 => x"8c1b23ff",
+594 => x"5574800c",
+595 => x"903d0d04",
+596 => x"7effa338",
+597 => x"ff873975",
+598 => x"537b527a",
+599 => x"5182f93f",
+600 => x"7908167a",
+601 => x"0c79518e",
+602 => x"b13f8008",
+603 => x"cf387c76",
+604 => x"315d7cfe",
+605 => x"bc38feac",
+606 => x"39901a08",
+607 => x"7a087131",
+608 => x"78117056",
+609 => x"5a575280",
+610 => x"cfe40851",
+611 => x"84943f80",
+612 => x"08802eff",
+613 => x"a7388008",
+614 => x"901b0c80",
+615 => x"08167a0c",
+616 => x"77941b0c",
+617 => x"76881b0c",
+618 => x"7656fd99",
+619 => x"39790858",
+620 => x"901a0878",
+621 => x"27833881",
+622 => x"54757727",
+623 => x"843873b3",
+624 => x"38941a08",
+625 => x"54737726",
+626 => x"80d33873",
+627 => x"5378529c",
+628 => x"1a0851a4",
+629 => x"1a085877",
+630 => x"2d800856",
+631 => x"80088024",
+632 => x"fd83388c",
+633 => x"1a2280c0",
+634 => x"075e7d8c",
+635 => x"1b23ff55",
+636 => x"fed73975",
+637 => x"53785277",
+638 => x"5181dd3f",
+639 => x"7908167a",
+640 => x"0c79518d",
+641 => x"953f8008",
+642 => x"802efcd9",
+643 => x"388c1a22",
+644 => x"80c0075e",
+645 => x"7d8c1b23",
+646 => x"ff55fead",
+647 => x"39767754",
+648 => x"79537852",
+649 => x"5681b13f",
+650 => x"881a0877",
+651 => x"31881b0c",
+652 => x"7908177a",
+653 => x"0cfcae39",
+654 => x"fa3d0d7a",
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+2522 => x"08525270",
+2523 => x"ff2e9138",
+2524 => x"702dfc12",
+2525 => x"70085252",
+2526 => x"70ff2e09",
+2527 => x"8106f138",
+2528 => x"50500404",
+2529 => x"ffbb8c3f",
+2530 => x"04000000",
+2531 => x"00000040",
+2532 => x"48656c6c",
+2533 => x"6f20776f",
+2534 => x"726c6420",
+2535 => x"310a0000",
+2536 => x"48656c6c",
+2537 => x"6f20776f",
+2538 => x"726c6420",
+2539 => x"320a0000",
+2540 => x"0a000000",
+2541 => x"43000000",
+2542 => x"64756d6d",
+2543 => x"792e6578",
+2544 => x"65000000",
+2545 => x"00ffffff",
+2546 => x"ff00ffff",
+2547 => x"ffff00ff",
+2548 => x"ffffff00",
+2549 => x"00000000",
+2550 => x"00000000",
+2551 => x"00000000",
+2552 => x"00002fb8",
+2553 => x"000027e8",
+2554 => x"00000000",
+2555 => x"00002a50",
+2556 => x"00002aac",
+2557 => x"00002b08",
+2558 => x"00000000",
+2559 => x"00000000",
+2560 => x"00000000",
+2561 => x"00000000",
+2562 => x"00000000",
+2563 => x"00000000",
+2564 => x"00000000",
+2565 => x"00000000",
+2566 => x"00000000",
+2567 => x"000027b4",
+2568 => x"00000000",
+2569 => x"00000000",
+2570 => x"00000000",
+2571 => x"00000000",
+2572 => x"00000000",
+2573 => x"00000000",
+2574 => x"00000000",
+2575 => x"00000000",
+2576 => x"00000000",
+2577 => x"00000000",
+2578 => x"00000000",
+2579 => x"00000000",
+2580 => x"00000000",
+2581 => x"00000000",
+2582 => x"00000000",
+2583 => x"00000000",
+2584 => x"00000000",
+2585 => x"00000000",
+2586 => x"00000000",
+2587 => x"00000000",
+2588 => x"00000000",
+2589 => x"00000000",
+2590 => x"00000000",
+2591 => x"00000000",
+2592 => x"00000000",
+2593 => x"00000000",
+2594 => x"00000000",
+2595 => x"00000000",
+2596 => x"00000001",
+2597 => x"330eabcd",
+2598 => x"1234e66d",
+2599 => x"deec0005",
+2600 => x"000b0000",
+2601 => x"00000000",
+2602 => x"00000000",
+2603 => x"00000000",
+2604 => x"00000000",
+2605 => x"00000000",
+2606 => x"00000000",
+2607 => x"00000000",
+2608 => x"00000000",
+2609 => x"00000000",
+2610 => x"00000000",
+2611 => x"00000000",
+2612 => x"00000000",
+2613 => x"00000000",
+2614 => x"00000000",
+2615 => x"00000000",
+2616 => x"00000000",
+2617 => x"00000000",
+2618 => x"00000000",
+2619 => x"00000000",
+2620 => x"00000000",
+2621 => x"00000000",
+2622 => x"00000000",
+2623 => x"00000000",
+2624 => x"00000000",
+2625 => x"00000000",
+2626 => x"00000000",
+2627 => x"00000000",
+2628 => x"00000000",
+2629 => x"00000000",
+2630 => x"00000000",
+2631 => x"00000000",
+2632 => x"00000000",
+2633 => x"00000000",
+2634 => x"00000000",
+2635 => x"00000000",
+2636 => x"00000000",
+2637 => x"00000000",
+2638 => x"00000000",
+2639 => x"00000000",
+2640 => x"00000000",
+2641 => x"00000000",
+2642 => x"00000000",
+2643 => x"00000000",
+2644 => x"00000000",
+2645 => x"00000000",
+2646 => x"00000000",
+2647 => x"00000000",
+2648 => x"00000000",
+2649 => x"00000000",
+2650 => x"00000000",
+2651 => x"00000000",
+2652 => x"00000000",
+2653 => x"00000000",
+2654 => x"00000000",
+2655 => x"00000000",
+2656 => x"00000000",
+2657 => x"00000000",
+2658 => x"00000000",
+2659 => x"00000000",
+2660 => x"00000000",
+2661 => x"00000000",
+2662 => x"00000000",
+2663 => x"00000000",
+2664 => x"00000000",
+2665 => x"00000000",
+2666 => x"00000000",
+2667 => x"00000000",
+2668 => x"00000000",
+2669 => x"00000000",
+2670 => x"00000000",
+2671 => x"00000000",
+2672 => x"00000000",
+2673 => x"00000000",
+2674 => x"00000000",
+2675 => x"00000000",
+2676 => x"00000000",
+2677 => x"00000000",
+2678 => x"00000000",
+2679 => x"00000000",
+2680 => x"00000000",
+2681 => x"00000000",
+2682 => x"00000000",
+2683 => x"00000000",
+2684 => x"00000000",
+2685 => x"00000000",
+2686 => x"00000000",
+2687 => x"00000000",
+2688 => x"00000000",
+2689 => x"00000000",
+2690 => x"00000000",
+2691 => x"00000000",
+2692 => x"00000000",
+2693 => x"00000000",
+2694 => x"00000000",
+2695 => x"00000000",
+2696 => x"00000000",
+2697 => x"00000000",
+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000000",
+2707 => x"00000000",
+2708 => x"00000000",
+2709 => x"00000000",
+2710 => x"00000000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"ffffffff",
+2790 => x"00000000",
+2791 => x"00020000",
+2792 => x"00000000",
+2793 => x"00000000",
+2794 => x"00002ba0",
+2795 => x"00002ba0",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+ report "write collision" severity failure;
+ end if;
+
+ if (memAWriteEnable = '1') then
+ ram(to_integer(unsigned(memAAddr))) := memAWrite;
+ memARead <= memAWrite;
+ else
+ memARead <= ram(to_integer(unsigned(memAAddr)));
+ end if;
+ end if;
+end process;
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memBWriteEnable = '1') then
+ ram(to_integer(unsigned(memBAddr))) := memBWrite;
+ memBRead <= memBWrite;
+ else
+ memBRead <= ram(to_integer(unsigned(memBAddr)));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/interrupt.vhd b/zpu/hdl/example/interrupt.vhd
new file mode 100644
index 0000000..d2bc709
--- /dev/null
+++ b/zpu/hdl/example/interrupt.vhd
@@ -0,0 +1,3156 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfe00c",
+3 => x"3a0b0b80",
+4 => x"c6e00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0b8af02d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
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+2641 => x"00000000",
+2642 => x"00000000",
+2643 => x"00000000",
+2644 => x"00000000",
+2645 => x"00000000",
+2646 => x"00000000",
+2647 => x"00000000",
+2648 => x"00000000",
+2649 => x"00000000",
+2650 => x"00000000",
+2651 => x"00000000",
+2652 => x"00000000",
+2653 => x"00000000",
+2654 => x"00000000",
+2655 => x"00000000",
+2656 => x"00000000",
+2657 => x"00000000",
+2658 => x"00000000",
+2659 => x"00000000",
+2660 => x"00000000",
+2661 => x"00000000",
+2662 => x"00000000",
+2663 => x"00000000",
+2664 => x"00000000",
+2665 => x"00000000",
+2666 => x"00000000",
+2667 => x"00000000",
+2668 => x"00000000",
+2669 => x"00000000",
+2670 => x"00000000",
+2671 => x"00000000",
+2672 => x"00000000",
+2673 => x"00000000",
+2674 => x"00000000",
+2675 => x"00000000",
+2676 => x"00000000",
+2677 => x"00000000",
+2678 => x"00000000",
+2679 => x"00000000",
+2680 => x"00000000",
+2681 => x"00000000",
+2682 => x"00000000",
+2683 => x"00000000",
+2684 => x"00000000",
+2685 => x"00000000",
+2686 => x"00000000",
+2687 => x"00000000",
+2688 => x"00000000",
+2689 => x"00000000",
+2690 => x"00000000",
+2691 => x"00000000",
+2692 => x"00000000",
+2693 => x"00000000",
+2694 => x"00000000",
+2695 => x"00000000",
+2696 => x"00000000",
+2697 => x"00000000",
+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000000",
+2707 => x"00000000",
+2708 => x"00000000",
+2709 => x"00000000",
+2710 => x"00000000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"00000000",
+2790 => x"00000000",
+2791 => x"ffffffff",
+2792 => x"00000000",
+2793 => x"00020000",
+2794 => x"00000000",
+2795 => x"00000000",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"00002fa0",
+3051 => x"00002fa0",
+3052 => x"000027c0",
+3053 => x"ffffffff",
+3054 => x"00000000",
+3055 => x"ffffffff",
+3056 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+ report "write collision" severity failure;
+ end if;
+
+ if (memAWriteEnable = '1') then
+ ram(to_integer(unsigned(memAAddr))) := memAWrite;
+ memARead <= memAWrite;
+ else
+ memARead <= ram(to_integer(unsigned(memAAddr)));
+ end if;
+ end if;
+end process;
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memBWriteEnable = '1') then
+ ram(to_integer(unsigned(memBAddr))) := memBWrite;
+ memBRead <= memBWrite;
+ else
+ memBRead <= ram(to_integer(unsigned(memBAddr)));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/log.txt b/zpu/hdl/example/log.txt
new file mode 100644
index 0000000..6ee1d94
--- /dev/null
+++ b/zpu/hdl/example/log.txt
@@ -0,0 +1,20 @@
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd
new file mode 100644
index 0000000..909ea21
--- /dev/null
+++ b/zpu/hdl/example/sim_small_fpga_top.vhd
@@ -0,0 +1,197 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity fpga_top is
+end fpga_top;
+
+
+architecture behave of fpga_top is
+
+
+ signal clk : std_logic;
+
+ signal areset : std_logic := '1';
+
+
+ component zpu_io is
+ generic (
+ log_file: string := "log.txt"
+ );
+ port (
+ clk : in std_logic;
+ areset : in std_logic;
+ busy : out std_logic;
+ writeEnable : in std_logic;
+ readEnable : in std_logic;
+ write : in std_logic_vector(wordSize-1 downto 0);
+ read : out std_logic_vector(wordSize-1 downto 0);
+ addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+ );
+ end component;
+
+
+ signal mem_busy : std_logic;
+ signal mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+ signal mem_writeEnable : std_logic;
+ signal mem_readEnable : std_logic;
+ signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal enable : std_logic;
+
+ signal dram_mem_busy : std_logic;
+ signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_writeEnable : std_logic;
+ signal dram_mem_readEnable : std_logic;
+ signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal io_busy : std_logic;
+
+ signal io_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal io_mem_writeEnable : std_logic;
+ signal io_mem_readEnable : std_logic;
+
+ signal dram_ready : std_logic;
+ signal io_ready : std_logic;
+ signal io_reading : std_logic;
+ signal interruptcounter : unsigned(15 downto 0);
+ signal interrupt : std_logic;
+
+ signal break : std_logic;
+
+begin
+
+ zpu: zpu_core
+ port map (
+ clk => clk,
+ reset => areset,
+ enable => enable,
+ in_mem_busy => mem_busy,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => mem_addr,
+ out_mem_writeEnable => mem_writeEnable,
+ out_mem_readEnable => mem_readEnable,
+ mem_writeMask => mem_writeMask,
+ interrupt => interrupt,
+ break => break
+ );
+
+
+ ioMap: zpu_io
+ port map (
+ clk => clk,
+ areset => areset,
+ busy => io_busy,
+ writeEnable => io_mem_writeEnable,
+ readEnable => io_mem_readEnable,
+ write => mem_write,
+ read => io_mem_read,
+ addr => mem_addr(maxAddrBit downto minAddrBit)
+ );
+
+ dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+ dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+ io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+ io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+ mem_busy <= io_busy;
+
+
+ -- Memory reads either come from IO or DRAM. We need to pick the right one.
+ memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+ begin
+ mem_read <= (others => 'U');
+ if dram_ready='1' then
+ mem_read <= dram_mem_read;
+ end if;
+
+ if io_ready='1' then
+ mem_read <= (others => '0');
+ mem_read <= io_mem_read;
+ end if;
+ end process;
+
+
+ io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+ memoryControlSync: process(clk, areset)
+ begin
+ if areset = '1' then
+ enable <= '0';
+ io_reading <= '0';
+ dram_ready <= '0';
+
+ interruptcounter <= to_unsigned(0, 16);
+ interrupt <= '0';
+
+ elsif rising_edge(clk) then
+ enable <= '1';
+ io_reading <= io_busy or io_mem_readEnable;
+ dram_ready <= dram_mem_readEnable;
+
+ -- keep interrupt signal high for 16 cycles
+ interruptcounter <= interruptcounter + 1;
+ if (interruptcounter < 16) then
+ report "Interrupt asserted!" severity note;
+ interrupt <='1';
+ else
+ interrupt <='0';
+ end if;
+ end if;
+ end process;
+
+ -- wiggle the clock @ 100MHz
+ clock: process
+ begin
+ clk <= '0';
+ wait for 5 ns;
+ clk <= '1';
+ wait for 5 ns;
+ areset <= '0';
+ end process clock;
+
+
+end architecture behave;
diff --git a/zpu/hdl/example/sim_small_fpga_top_noint.vhd b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
new file mode 100644
index 0000000..23b92cc
--- /dev/null
+++ b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
@@ -0,0 +1,184 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity fpga_top is
+end fpga_top;
+
+
+architecture behave of fpga_top is
+
+
+ signal clk : std_logic;
+
+ signal areset : std_logic := '1';
+
+
+ component zpu_io is
+ generic (
+ log_file: string := "log.txt"
+ );
+ port (
+ clk : in std_logic;
+ areset : in std_logic;
+ busy : out std_logic;
+ writeEnable : in std_logic;
+ readEnable : in std_logic;
+ write : in std_logic_vector(wordSize-1 downto 0);
+ read : out std_logic_vector(wordSize-1 downto 0);
+ addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+ );
+ end component;
+
+
+ signal mem_busy : std_logic;
+ signal mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+ signal mem_writeEnable : std_logic;
+ signal mem_readEnable : std_logic;
+ signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal enable : std_logic;
+
+ signal dram_mem_busy : std_logic;
+ signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_writeEnable : std_logic;
+ signal dram_mem_readEnable : std_logic;
+ signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal io_busy : std_logic;
+
+ signal io_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal io_mem_writeEnable : std_logic;
+ signal io_mem_readEnable : std_logic;
+
+ signal dram_ready : std_logic;
+ signal io_ready : std_logic;
+ signal io_reading : std_logic;
+
+ signal break : std_logic;
+
+
+begin
+
+ zpu: zpu_core
+ port map (
+ clk => clk,
+ reset => areset,
+ enable => enable,
+ in_mem_busy => mem_busy,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => mem_addr,
+ out_mem_writeEnable => mem_writeEnable,
+ out_mem_readEnable => mem_readEnable,
+ mem_writeMask => mem_writeMask,
+ interrupt => '0',
+ break => break
+ );
+
+
+ ioMap: zpu_io
+ port map (
+ clk => clk,
+ areset => areset,
+ busy => io_busy,
+ writeEnable => io_mem_writeEnable,
+ readEnable => io_mem_readEnable,
+ write => mem_write,
+ read => io_mem_read,
+ addr => mem_addr(maxAddrBit downto minAddrBit)
+ );
+
+ dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+ dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+ io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+ io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+ mem_busy <= io_busy;
+
+
+ -- Memory reads either come from IO or DRAM. We need to pick the right one.
+ memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+ begin
+ mem_read <= (others => 'U');
+ if dram_ready='1' then
+ mem_read <= dram_mem_read;
+ end if;
+
+ if io_ready='1' then
+ mem_read <= (others => '0');
+ mem_read <= io_mem_read;
+ end if;
+ end process;
+
+
+
+ io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+ memoryControlSync: process(clk, areset)
+ begin
+ if areset = '1' then
+ enable <= '0';
+ io_reading <= '0';
+ dram_ready <= '0';
+
+ elsif rising_edge(clk) then
+ enable <= '1';
+ io_reading <= io_busy or io_mem_readEnable;
+ dram_ready <= dram_mem_readEnable;
+ end if;
+ end process;
+
+ -- wiggle the clock @ 100MHz
+ clock: process
+ begin
+ clk <= '0';
+ wait for 5 ns;
+ clk <= '1';
+ wait for 5 ns;
+ areset <= '0';
+ end process clock;
+
+
+end architecture behave;
diff --git a/zpu/hdl/example/simzpu_dmips.do b/zpu/hdl/example/simzpu_dmips.do
new file mode 100644
index 0000000..883259e
--- /dev/null
+++ b/zpu/hdl/example/simzpu_dmips.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+#
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_dmips.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_small_fpga_top_noint.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit bram_dmips.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/simzpu_interrupt.do b/zpu/hdl/example/simzpu_interrupt.do
new file mode 100644
index 0000000..864bf76
--- /dev/null
+++ b/zpu/hdl/example/simzpu_interrupt.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+#
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_interrupt.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_small_fpga_top.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit interrupt.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do
new file mode 100644
index 0000000..2b64926
--- /dev/null
+++ b/zpu/hdl/example/simzpu_small.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+#
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_small.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_small_fpga_top_noint.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit helloworld.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd
new file mode 100644
index 0000000..cd4163d
--- /dev/null
+++ b/zpu/hdl/example/zpu_config.vhd
@@ -0,0 +1,55 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package zpu_config is
+ -- generate trace output
+ constant Generate_Trace : boolean := true;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
+ -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+ constant maxAddrBitIncIO : integer := 27;
+ constant maxAddrBitBRAM : integer := 16;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
+ std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1));
+end zpu_config;
diff --git a/zpu/hdl/example/zpuromgen.c b/zpu/hdl/example/zpuromgen.c
new file mode 100644
index 0000000..fb8c4ba
--- /dev/null
+++ b/zpu/hdl/example/zpuromgen.c
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+// by Adam Pierce
+// 29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef uint8_t BYTE;
+
+main(int argc, char **argv)
+{
+ BYTE opcode[4];
+ int fd;
+ int addr = 0;
+ ssize_t s;
+
+// Check the user has given us an input file.
+ if(argc < 2)
+ {
+ printf("Usage: %s <binary_file>\n\n", argv[0]);
+ return 1;
+ }
+
+// Open the input file.
+ fd = open(argv[1], 0);
+ if(fd == -1)
+ {
+ perror("File Open");
+ return 2;
+ }
+
+ while(1)
+ {
+ // Read 32 bits.
+ s = read(fd, opcode, 4);
+ if(s == -1)
+ {
+ perror("File read");
+ return 3;
+ }
+
+ if(s == 0)
+ break; // End of file.
+
+ // Output to STDOUT.
+ printf("%6d => x\"%02x%02x%02x%02x\",\n",
+ addr++, opcode[0], opcode[1],
+ opcode[2], opcode[3]);
+ }
+
+ close(fd);
+ return 0;
+}
+
diff --git a/zpu/hdl/example/zpuromgen.exe b/zpu/hdl/example/zpuromgen.exe
new file mode 100644
index 0000000..6655412
--- /dev/null
+++ b/zpu/hdl/example/zpuromgen.exe
Binary files differ
diff --git a/zpu/hdl/example_ghdl/README b/zpu/hdl/example_ghdl/README
new file mode 100644
index 0000000..a098c0c
--- /dev/null
+++ b/zpu/hdl/example_ghdl/README
@@ -0,0 +1,44 @@
+This directory contains a quick setup of the helloworld example for
+the GHDL simulator.
+
+ http://ghdl.free.fr/
+
+Compiled by Arnim Laeuger, 17-Apr-2008.
+Removed ROC/unisim dependency 16-Jun-2008.
+
+Compiling the example
+---------------------
+
+Make all shell scripts executable:
+ $ chmod +x *.sh
+
+On Linux, convert files from DOS format:
+ $ dos2unix *.sh
+
+You need to import the project sources once by running
+ $ ./ghdl_import.sh
+
+Compilation (using GHDL's make feature) is invoked by
+ $ ./ghdl_make.sh
+
+Whenever the VHDL sources change, it's enough to execute ghdl_make.sh. GHDL
+will trace the dependencies and will rebuild only the modified sources.
+
+
+Simulation
+----------
+
+Simulation finally happens by running the fpga_top executable generated by the
+compilation step. Don't forget to set a stop time or the testbench might run
+forever:
+
+ $ ./fpga_top --stop-time=2100us
+
+The log.txt and trace.txt files are generated as simulation progresses. They
+should be compared to the files given in the example directory.
+
+Waveforms can be obtained by specifying the ghw file name:
+
+ $ ./fpga_top --stop-time=1ms --wave=zpu.ghw
+
+They can be inspected with gtkwave from http://home.nc.rr.com/gtkwave/.
diff --git a/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh
new file mode 100644
index 0000000..b3be1a6
--- /dev/null
+++ b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/bram_dmips.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=1ms"
+fi
diff --git a/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh
new file mode 100644
index 0000000..53474d4
--- /dev/null
+++ b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_dmips.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=2500us"
+fi
diff --git a/zpu/hdl/example_ghdl/ghdl_import.sh b/zpu/hdl/example_ghdl/ghdl_import.sh
new file mode 100644
index 0000000..b1c2713
--- /dev/null
+++ b/zpu/hdl/example_ghdl/ghdl_import.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+. ghdl_options.sh
+
+mkdir -p work
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/interrupt.vhd
+# to execute helloworld comment interrupt.vhd above
+# and edit sim_small_fpga_top.vhd to never assert interrupts
+#ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/helloworld.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd
diff --git a/zpu/hdl/example_ghdl/ghdl_make.sh b/zpu/hdl/example_ghdl/ghdl_make.sh
new file mode 100644
index 0000000..948b100
--- /dev/null
+++ b/zpu/hdl/example_ghdl/ghdl_make.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+. ghdl_options.sh
+
+ghdl -m ${MAKE_OPTIONS} fpga_top
diff --git a/zpu/hdl/example_ghdl/ghdl_options.sh b/zpu/hdl/example_ghdl/ghdl_options.sh
new file mode 100644
index 0000000..aba231c
--- /dev/null
+++ b/zpu/hdl/example_ghdl/ghdl_options.sh
@@ -0,0 +1,2 @@
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
diff --git a/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh
new file mode 100644
index 0000000..8ba5078
--- /dev/null
+++ b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_hello.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=1ms"
+fi
diff --git a/zpu/hdl/example_medium/.cvsignore b/zpu/hdl/example_medium/.cvsignore
new file mode 100644
index 0000000..3add443
--- /dev/null
+++ b/zpu/hdl/example_medium/.cvsignore
@@ -0,0 +1,4 @@
+vsim.wlf
+work
+log.txt
+trace.txt
diff --git a/zpu/hdl/example_medium/dram_dmips.vhd b/zpu/hdl/example_medium/dram_dmips.vhd
new file mode 100644
index 0000000..0437adc
--- /dev/null
+++ b/zpu/hdl/example_medium/dram_dmips.vhd
@@ -0,0 +1,3308 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+areset : std_logic;
+ mem_writeEnable : in std_logic;
+ mem_readEnable : in std_logic;
+ mem_addr : in std_logic_vector(maxAddrBit downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_busy : out std_logic;
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80d5f40c",
+3 => x"3a0b0b80",
+4 => x"c4fb0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c5c22d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
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+2586 => x"653a2020",
+2587 => x"20444852",
+2588 => x"5953544f",
+2589 => x"4e452050",
+2590 => x"524f4752",
+2591 => x"414d2c20",
+2592 => x"32274e44",
+2593 => x"20535452",
+2594 => x"494e470a",
+2595 => x"00000000",
+2596 => x"55736572",
+2597 => x"2074696d",
+2598 => x"653a2025",
+2599 => x"640a0000",
+2600 => x"4d696372",
+2601 => x"6f736563",
+2602 => x"6f6e6473",
+2603 => x"20666f72",
+2604 => x"206f6e65",
+2605 => x"2072756e",
+2606 => x"20746872",
+2607 => x"6f756768",
+2608 => x"20446872",
+2609 => x"7973746f",
+2610 => x"6e653a20",
+2611 => x"00000000",
+2612 => x"2564200a",
+2613 => x"00000000",
+2614 => x"44687279",
+2615 => x"73746f6e",
+2616 => x"65732070",
+2617 => x"65722053",
+2618 => x"65636f6e",
+2619 => x"643a2020",
+2620 => x"20202020",
+2621 => x"20202020",
+2622 => x"20202020",
+2623 => x"20202020",
+2624 => x"20202020",
+2625 => x"00000000",
+2626 => x"56415820",
+2627 => x"4d495053",
+2628 => x"20726174",
+2629 => x"696e6720",
+2630 => x"2a203130",
+2631 => x"3030203d",
+2632 => x"20256420",
+2633 => x"0a000000",
+2634 => x"50726f67",
+2635 => x"72616d20",
+2636 => x"636f6d70",
+2637 => x"696c6564",
+2638 => x"20776974",
+2639 => x"686f7574",
+2640 => x"20277265",
+2641 => x"67697374",
+2642 => x"65722720",
+2643 => x"61747472",
+2644 => x"69627574",
+2645 => x"650a0000",
+2646 => x"4d656173",
+2647 => x"75726564",
+2648 => x"2074696d",
+2649 => x"6520746f",
+2650 => x"6f20736d",
+2651 => x"616c6c20",
+2652 => x"746f206f",
+2653 => x"62746169",
+2654 => x"6e206d65",
+2655 => x"616e696e",
+2656 => x"6766756c",
+2657 => x"20726573",
+2658 => x"756c7473",
+2659 => x"0a000000",
+2660 => x"506c6561",
+2661 => x"73652069",
+2662 => x"6e637265",
+2663 => x"61736520",
+2664 => x"6e756d62",
+2665 => x"6572206f",
+2666 => x"66207275",
+2667 => x"6e730a00",
+2668 => x"44485259",
+2669 => x"53544f4e",
+2670 => x"45205052",
+2671 => x"4f475241",
+2672 => x"4d2c2033",
+2673 => x"27524420",
+2674 => x"53545249",
+2675 => x"4e470000",
+2676 => x"00010202",
+2677 => x"03030303",
+2678 => x"04040404",
+2679 => x"04040404",
+2680 => x"05050505",
+2681 => x"05050505",
+2682 => x"05050505",
+2683 => x"05050505",
+2684 => x"06060606",
+2685 => x"06060606",
+2686 => x"06060606",
+2687 => x"06060606",
+2688 => x"06060606",
+2689 => x"06060606",
+2690 => x"06060606",
+2691 => x"06060606",
+2692 => x"07070707",
+2693 => x"07070707",
+2694 => x"07070707",
+2695 => x"07070707",
+2696 => x"07070707",
+2697 => x"07070707",
+2698 => x"07070707",
+2699 => x"07070707",
+2700 => x"07070707",
+2701 => x"07070707",
+2702 => x"07070707",
+2703 => x"07070707",
+2704 => x"07070707",
+2705 => x"07070707",
+2706 => x"07070707",
+2707 => x"07070707",
+2708 => x"08080808",
+2709 => x"08080808",
+2710 => x"08080808",
+2711 => x"08080808",
+2712 => x"08080808",
+2713 => x"08080808",
+2714 => x"08080808",
+2715 => x"08080808",
+2716 => x"08080808",
+2717 => x"08080808",
+2718 => x"08080808",
+2719 => x"08080808",
+2720 => x"08080808",
+2721 => x"08080808",
+2722 => x"08080808",
+2723 => x"08080808",
+2724 => x"08080808",
+2725 => x"08080808",
+2726 => x"08080808",
+2727 => x"08080808",
+2728 => x"08080808",
+2729 => x"08080808",
+2730 => x"08080808",
+2731 => x"08080808",
+2732 => x"08080808",
+2733 => x"08080808",
+2734 => x"08080808",
+2735 => x"08080808",
+2736 => x"08080808",
+2737 => x"08080808",
+2738 => x"08080808",
+2739 => x"08080808",
+2740 => x"43000000",
+2741 => x"64756d6d",
+2742 => x"792e6578",
+2743 => x"65000000",
+2744 => x"00ffffff",
+2745 => x"ff00ffff",
+2746 => x"ffff00ff",
+2747 => x"ffffff00",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"000032dc",
+2752 => x"0000c350",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"ffffffff",
+2767 => x"00000000",
+2768 => x"00020000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00002b44",
+2772 => x"00002b44",
+2773 => x"00002b4c",
+2774 => x"00002b4c",
+2775 => x"00002b54",
+2776 => x"00002b54",
+2777 => x"00002b5c",
+2778 => x"00002b5c",
+2779 => x"00002b64",
+2780 => x"00002b64",
+2781 => x"00002b6c",
+2782 => x"00002b6c",
+2783 => x"00002b74",
+2784 => x"00002b74",
+2785 => x"00002b7c",
+2786 => x"00002b7c",
+2787 => x"00002b84",
+2788 => x"00002b84",
+2789 => x"00002b8c",
+2790 => x"00002b8c",
+2791 => x"00002b94",
+2792 => x"00002b94",
+2793 => x"00002b9c",
+2794 => x"00002b9c",
+2795 => x"00002ba4",
+2796 => x"00002ba4",
+2797 => x"00002bac",
+2798 => x"00002bac",
+2799 => x"00002bb4",
+2800 => x"00002bb4",
+2801 => x"00002bbc",
+2802 => x"00002bbc",
+2803 => x"00002bc4",
+2804 => x"00002bc4",
+2805 => x"00002bcc",
+2806 => x"00002bcc",
+2807 => x"00002bd4",
+2808 => x"00002bd4",
+2809 => x"00002bdc",
+2810 => x"00002bdc",
+2811 => x"00002be4",
+2812 => x"00002be4",
+2813 => x"00002bec",
+2814 => x"00002bec",
+2815 => x"00002bf4",
+2816 => x"00002bf4",
+2817 => x"00002bfc",
+2818 => x"00002bfc",
+2819 => x"00002c04",
+2820 => x"00002c04",
+2821 => x"00002c0c",
+2822 => x"00002c0c",
+2823 => x"00002c14",
+2824 => x"00002c14",
+2825 => x"00002c1c",
+2826 => x"00002c1c",
+2827 => x"00002c24",
+2828 => x"00002c24",
+2829 => x"00002c2c",
+2830 => x"00002c2c",
+2831 => x"00002c34",
+2832 => x"00002c34",
+2833 => x"00002c3c",
+2834 => x"00002c3c",
+2835 => x"00002c44",
+2836 => x"00002c44",
+2837 => x"00002c4c",
+2838 => x"00002c4c",
+2839 => x"00002c54",
+2840 => x"00002c54",
+2841 => x"00002c5c",
+2842 => x"00002c5c",
+2843 => x"00002c64",
+2844 => x"00002c64",
+2845 => x"00002c6c",
+2846 => x"00002c6c",
+2847 => x"00002c74",
+2848 => x"00002c74",
+2849 => x"00002c7c",
+2850 => x"00002c7c",
+2851 => x"00002c84",
+2852 => x"00002c84",
+2853 => x"00002c8c",
+2854 => x"00002c8c",
+2855 => x"00002c94",
+2856 => x"00002c94",
+2857 => x"00002c9c",
+2858 => x"00002c9c",
+2859 => x"00002ca4",
+2860 => x"00002ca4",
+2861 => x"00002cac",
+2862 => x"00002cac",
+2863 => x"00002cb4",
+2864 => x"00002cb4",
+2865 => x"00002cbc",
+2866 => x"00002cbc",
+2867 => x"00002cc4",
+2868 => x"00002cc4",
+2869 => x"00002ccc",
+2870 => x"00002ccc",
+2871 => x"00002cd4",
+2872 => x"00002cd4",
+2873 => x"00002cdc",
+2874 => x"00002cdc",
+2875 => x"00002ce4",
+2876 => x"00002ce4",
+2877 => x"00002cec",
+2878 => x"00002cec",
+2879 => x"00002cf4",
+2880 => x"00002cf4",
+2881 => x"00002cfc",
+2882 => x"00002cfc",
+2883 => x"00002d04",
+2884 => x"00002d04",
+2885 => x"00002d0c",
+2886 => x"00002d0c",
+2887 => x"00002d14",
+2888 => x"00002d14",
+2889 => x"00002d1c",
+2890 => x"00002d1c",
+2891 => x"00002d24",
+2892 => x"00002d24",
+2893 => x"00002d2c",
+2894 => x"00002d2c",
+2895 => x"00002d34",
+2896 => x"00002d34",
+2897 => x"00002d3c",
+2898 => x"00002d3c",
+2899 => x"00002d44",
+2900 => x"00002d44",
+2901 => x"00002d4c",
+2902 => x"00002d4c",
+2903 => x"00002d54",
+2904 => x"00002d54",
+2905 => x"00002d5c",
+2906 => x"00002d5c",
+2907 => x"00002d64",
+2908 => x"00002d64",
+2909 => x"00002d6c",
+2910 => x"00002d6c",
+2911 => x"00002d74",
+2912 => x"00002d74",
+2913 => x"00002d7c",
+2914 => x"00002d7c",
+2915 => x"00002d84",
+2916 => x"00002d84",
+2917 => x"00002d8c",
+2918 => x"00002d8c",
+2919 => x"00002d94",
+2920 => x"00002d94",
+2921 => x"00002d9c",
+2922 => x"00002d9c",
+2923 => x"00002da4",
+2924 => x"00002da4",
+2925 => x"00002dac",
+2926 => x"00002dac",
+2927 => x"00002db4",
+2928 => x"00002db4",
+2929 => x"00002dbc",
+2930 => x"00002dbc",
+2931 => x"00002dc4",
+2932 => x"00002dc4",
+2933 => x"00002dcc",
+2934 => x"00002dcc",
+2935 => x"00002dd4",
+2936 => x"00002dd4",
+2937 => x"00002ddc",
+2938 => x"00002ddc",
+2939 => x"00002de4",
+2940 => x"00002de4",
+2941 => x"00002dec",
+2942 => x"00002dec",
+2943 => x"00002df4",
+2944 => x"00002df4",
+2945 => x"00002dfc",
+2946 => x"00002dfc",
+2947 => x"00002e04",
+2948 => x"00002e04",
+2949 => x"00002e0c",
+2950 => x"00002e0c",
+2951 => x"00002e14",
+2952 => x"00002e14",
+2953 => x"00002e1c",
+2954 => x"00002e1c",
+2955 => x"00002e24",
+2956 => x"00002e24",
+2957 => x"00002e2c",
+2958 => x"00002e2c",
+2959 => x"00002e34",
+2960 => x"00002e34",
+2961 => x"00002e3c",
+2962 => x"00002e3c",
+2963 => x"00002e44",
+2964 => x"00002e44",
+2965 => x"00002e4c",
+2966 => x"00002e4c",
+2967 => x"00002e54",
+2968 => x"00002e54",
+2969 => x"00002e5c",
+2970 => x"00002e5c",
+2971 => x"00002e64",
+2972 => x"00002e64",
+2973 => x"00002e6c",
+2974 => x"00002e6c",
+2975 => x"00002e74",
+2976 => x"00002e74",
+2977 => x"00002e7c",
+2978 => x"00002e7c",
+2979 => x"00002e84",
+2980 => x"00002e84",
+2981 => x"00002e8c",
+2982 => x"00002e8c",
+2983 => x"00002e94",
+2984 => x"00002e94",
+2985 => x"00002e9c",
+2986 => x"00002e9c",
+2987 => x"00002ea4",
+2988 => x"00002ea4",
+2989 => x"00002eac",
+2990 => x"00002eac",
+2991 => x"00002eb4",
+2992 => x"00002eb4",
+2993 => x"00002ebc",
+2994 => x"00002ebc",
+2995 => x"00002ec4",
+2996 => x"00002ec4",
+2997 => x"00002ecc",
+2998 => x"00002ecc",
+2999 => x"00002ed4",
+3000 => x"00002ed4",
+3001 => x"00002edc",
+3002 => x"00002edc",
+3003 => x"00002ee4",
+3004 => x"00002ee4",
+3005 => x"00002eec",
+3006 => x"00002eec",
+3007 => x"00002ef4",
+3008 => x"00002ef4",
+3009 => x"00002efc",
+3010 => x"00002efc",
+3011 => x"00002f04",
+3012 => x"00002f04",
+3013 => x"00002f0c",
+3014 => x"00002f0c",
+3015 => x"00002f14",
+3016 => x"00002f14",
+3017 => x"00002f1c",
+3018 => x"00002f1c",
+3019 => x"00002f24",
+3020 => x"00002f24",
+3021 => x"00002f2c",
+3022 => x"00002f2c",
+3023 => x"00002f34",
+3024 => x"00002f34",
+3025 => x"00002f3c",
+3026 => x"00002f3c",
+3027 => x"00002f50",
+3028 => x"00000000",
+3029 => x"000031b8",
+3030 => x"00003214",
+3031 => x"00003270",
+3032 => x"00000000",
+3033 => x"00000000",
+3034 => x"00000000",
+3035 => x"00000000",
+3036 => x"00000000",
+3037 => x"00000000",
+3038 => x"00000000",
+3039 => x"00000000",
+3040 => x"00000000",
+3041 => x"00002ad0",
+3042 => x"00000000",
+3043 => x"00000000",
+3044 => x"00000000",
+3045 => x"00000000",
+3046 => x"00000000",
+3047 => x"00000000",
+3048 => x"00000000",
+3049 => x"00000000",
+3050 => x"00000000",
+3051 => x"00000000",
+3052 => x"00000000",
+3053 => x"00000000",
+3054 => x"00000000",
+3055 => x"00000000",
+3056 => x"00000000",
+3057 => x"00000000",
+3058 => x"00000000",
+3059 => x"00000000",
+3060 => x"00000000",
+3061 => x"00000000",
+3062 => x"00000000",
+3063 => x"00000000",
+3064 => x"00000000",
+3065 => x"00000000",
+3066 => x"00000000",
+3067 => x"00000000",
+3068 => x"00000000",
+3069 => x"00000000",
+3070 => x"00000001",
+3071 => x"330eabcd",
+3072 => x"1234e66d",
+3073 => x"deec0005",
+3074 => x"000b0000",
+3075 => x"00000000",
+3076 => x"00000000",
+3077 => x"00000000",
+3078 => x"00000000",
+3079 => x"00000000",
+3080 => x"00000000",
+3081 => x"00000000",
+3082 => x"00000000",
+3083 => x"00000000",
+3084 => x"00000000",
+3085 => x"00000000",
+3086 => x"00000000",
+3087 => x"00000000",
+3088 => x"00000000",
+3089 => x"00000000",
+3090 => x"00000000",
+3091 => x"00000000",
+3092 => x"00000000",
+3093 => x"00000000",
+3094 => x"00000000",
+3095 => x"00000000",
+3096 => x"00000000",
+3097 => x"00000000",
+3098 => x"00000000",
+3099 => x"00000000",
+3100 => x"00000000",
+3101 => x"00000000",
+3102 => x"00000000",
+3103 => x"00000000",
+3104 => x"00000000",
+3105 => x"00000000",
+3106 => x"00000000",
+3107 => x"00000000",
+3108 => x"00000000",
+3109 => x"00000000",
+3110 => x"00000000",
+3111 => x"00000000",
+3112 => x"00000000",
+3113 => x"00000000",
+3114 => x"00000000",
+3115 => x"00000000",
+3116 => x"00000000",
+3117 => x"00000000",
+3118 => x"00000000",
+3119 => x"00000000",
+3120 => x"00000000",
+3121 => x"00000000",
+3122 => x"00000000",
+3123 => x"00000000",
+3124 => x"00000000",
+3125 => x"00000000",
+3126 => x"00000000",
+3127 => x"00000000",
+3128 => x"00000000",
+3129 => x"00000000",
+3130 => x"00000000",
+3131 => x"00000000",
+3132 => x"00000000",
+3133 => x"00000000",
+3134 => x"00000000",
+3135 => x"00000000",
+3136 => x"00000000",
+3137 => x"00000000",
+3138 => x"00000000",
+3139 => x"00000000",
+3140 => x"00000000",
+3141 => x"00000000",
+3142 => x"00000000",
+3143 => x"00000000",
+3144 => x"00000000",
+3145 => x"00000000",
+3146 => x"00000000",
+3147 => x"00000000",
+3148 => x"00000000",
+3149 => x"00000000",
+3150 => x"00000000",
+3151 => x"00000000",
+3152 => x"00000000",
+3153 => x"00000000",
+3154 => x"00000000",
+3155 => x"00000000",
+3156 => x"00000000",
+3157 => x"00000000",
+3158 => x"00000000",
+3159 => x"00000000",
+3160 => x"00000000",
+3161 => x"00000000",
+3162 => x"00000000",
+3163 => x"00000000",
+3164 => x"00000000",
+3165 => x"00000000",
+3166 => x"00000000",
+3167 => x"00000000",
+3168 => x"00000000",
+3169 => x"00000000",
+3170 => x"00000000",
+3171 => x"00000000",
+3172 => x"00000000",
+3173 => x"00000000",
+3174 => x"00000000",
+3175 => x"00000000",
+3176 => x"00000000",
+3177 => x"00000000",
+3178 => x"00000000",
+3179 => x"00000000",
+3180 => x"00000000",
+3181 => x"00000000",
+3182 => x"00000000",
+3183 => x"00000000",
+3184 => x"00000000",
+3185 => x"00000000",
+3186 => x"00000000",
+3187 => x"00000000",
+3188 => x"00000000",
+3189 => x"00000000",
+3190 => x"00000000",
+3191 => x"00000000",
+3192 => x"00000000",
+3193 => x"00000000",
+3194 => x"00000000",
+3195 => x"00000000",
+3196 => x"00000000",
+3197 => x"00000000",
+3198 => x"00000000",
+3199 => x"00000000",
+3200 => x"00000000",
+3201 => x"00000000",
+3202 => x"00000000",
+3203 => x"00000000",
+3204 => x"00000000",
+3205 => x"00000000",
+3206 => x"00000000",
+3207 => x"00000000",
+3208 => x"00000000",
+3209 => x"00000000",
+3210 => x"00000000",
+3211 => x"00000000",
+3212 => x"00000000",
+3213 => x"00000000",
+3214 => x"00000000",
+3215 => x"00000000",
+3216 => x"00000000",
+3217 => x"00000000",
+3218 => x"00000000",
+3219 => x"00000000",
+3220 => x"00000000",
+3221 => x"00000000",
+3222 => x"00000000",
+3223 => x"00000000",
+3224 => x"00000000",
+3225 => x"00000000",
+3226 => x"00000000",
+3227 => x"00000000",
+3228 => x"00000000",
+3229 => x"00000000",
+3230 => x"00000000",
+3231 => x"00000000",
+3232 => x"00000000",
+3233 => x"00000000",
+3234 => x"00000000",
+3235 => x"00000000",
+3236 => x"00000000",
+3237 => x"00000000",
+3238 => x"00000000",
+3239 => x"00000000",
+3240 => x"00000000",
+3241 => x"00000000",
+3242 => x"00000000",
+3243 => x"00000000",
+3244 => x"00000000",
+3245 => x"00000000",
+3246 => x"00000000",
+3247 => x"00000000",
+3248 => x"00000000",
+3249 => x"00000000",
+3250 => x"00000000",
+3251 => x"00002ad4",
+3252 => x"ffffffff",
+3253 => x"00000000",
+3254 => x"ffffffff",
+3255 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
+
+process (clk, areset)
+begin
+ if areset = '1' then
+ elsif (clk'event and clk = '1') then
+ if (mem_writeEnable = '1') then
+ ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
+ end if;
+ if (mem_readEnable = '1') then
+ mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/example_medium/dram_hello.vhd b/zpu/hdl/example_medium/dram_hello.vhd
new file mode 100644
index 0000000..aae18fd
--- /dev/null
+++ b/zpu/hdl/example_medium/dram_hello.vhd
@@ -0,0 +1,3107 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+areset : std_logic;
+ mem_writeEnable : in std_logic;
+ mem_readEnable : in std_logic;
+ mem_addr : in std_logic_vector(maxAddrBit downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_busy : out std_logic;
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"c4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"9f2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"e32d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfd40c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6d93f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc0",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c0085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"d408802e",
+299 => x"a43880cf",
+300 => x"d808822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc00c",
+304 => x"82a0800b",
+305 => x"80dfc40c",
+306 => x"8290800b",
+307 => x"80dfc80c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc0",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfc40cf8",
+314 => x"80808480",
+315 => x"0b80dfc8",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c00c80c0",
+320 => x"a880940b",
+321 => x"80dfc40c",
+322 => x"0b0b80cf",
+323 => x"8c0b80df",
+324 => x"c80c0470",
+325 => x"7080dfcc",
+326 => x"335170a7",
+327 => x"3880cfe0",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe00c",
+332 => x"702d80cf",
+333 => x"e0087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfcc3450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"bc08802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
+342 => x"802e0981",
+343 => x"06833850",
+344 => x"040b0b80",
+345 => x"dfbc510b",
+346 => x"0b0bf594",
+347 => x"3f500404",
+348 => x"fe3d0d89",
+349 => x"5380cf90",
+350 => x"5182c13f",
+351 => x"80cfa051",
+352 => x"82ba3f81",
+353 => x"0a0b80df",
+354 => x"d80cff0b",
+355 => x"80dfdc0c",
+356 => x"ff135372",
+357 => x"8025de38",
+358 => x"72800c84",
+359 => x"3d0d04fb",
+360 => x"3d0d7779",
+361 => x"55558056",
+362 => x"757524ab",
+363 => x"38807424",
+364 => x"9d388053",
+365 => x"73527451",
+366 => x"80e13f80",
+367 => x"08547580",
+368 => x"2e853880",
+369 => x"08305473",
+370 => x"800c873d",
+371 => x"0d047330",
+372 => x"76813257",
+373 => x"54dc3974",
+374 => x"30558156",
+375 => x"738025d2",
+376 => x"38ec39fa",
+377 => x"3d0d787a",
+378 => x"57558057",
+379 => x"767524a4",
+380 => x"38759f2c",
+381 => x"54815375",
+382 => x"74327431",
+383 => x"5274519b",
+384 => x"3f800854",
+385 => x"76802e85",
+386 => x"38800830",
+387 => x"5473800c",
+388 => x"883d0d04",
+389 => x"74305581",
+390 => x"57d739fc",
+391 => x"3d0d7678",
+392 => x"53548153",
+393 => x"80747326",
+394 => x"52557280",
+395 => x"2e983870",
+396 => x"802eab38",
+397 => x"807224a6",
+398 => x"38711073",
+399 => x"10757226",
+400 => x"53545272",
+401 => x"ea387351",
+402 => x"78833874",
+403 => x"5170800c",
+404 => x"863d0d04",
+405 => x"720a100a",
+406 => x"720a100a",
+407 => x"53537280",
+408 => x"2ee43871",
+409 => x"7426ed38",
+410 => x"73723175",
+411 => x"7407740a",
+412 => x"100a740a",
+413 => x"100a5555",
+414 => x"5654e339",
+415 => x"f73d0d7c",
+416 => x"70525380",
+417 => x"f93f7254",
+418 => x"80085580",
+419 => x"cfb05681",
+420 => x"57800881",
+421 => x"055a8b3d",
+422 => x"e4115953",
+423 => x"8259f413",
+424 => x"527b8811",
+425 => x"08525381",
+426 => x"b23f8008",
+427 => x"30708008",
+428 => x"079f2c8a",
+429 => x"07800c53",
+430 => x"8b3d0d04",
+431 => x"f63d0d7c",
+432 => x"80cfe408",
+433 => x"71535553",
+434 => x"b53f7255",
+435 => x"80085680",
+436 => x"cfb05781",
+437 => x"58800881",
+438 => x"055b8c3d",
+439 => x"e4115a53",
+440 => x"825af413",
+441 => x"52881408",
+442 => x"5180f03f",
+443 => x"80083070",
+444 => x"8008079f",
+445 => x"2c8a0780",
+446 => x"0c548c3d",
+447 => x"0d047070",
+448 => x"70707570",
+449 => x"71830653",
+450 => x"555270b4",
+451 => x"38717008",
+452 => x"7009f7fb",
+453 => x"fdff1206",
+454 => x"f8848281",
+455 => x"80065452",
+456 => x"53719b38",
+457 => x"84137008",
+458 => x"7009f7fb",
+459 => x"fdff1206",
+460 => x"f8848281",
+461 => x"80065452",
+462 => x"5371802e",
+463 => x"e7387252",
+464 => x"71335372",
+465 => x"802e8a38",
+466 => x"81127033",
+467 => x"545272f8",
+468 => x"38717431",
+469 => x"800c5050",
+470 => x"505004f2",
+471 => x"3d0d6062",
+472 => x"88110870",
+473 => x"58565f5a",
+474 => x"73802e81",
+475 => x"8c388c1a",
+476 => x"2270832a",
+477 => x"81328106",
+478 => x"56587486",
+479 => x"38901a08",
+480 => x"91387951",
+481 => x"90b73fff",
+482 => x"55800880",
+483 => x"ec388c1a",
+484 => x"22587d08",
+485 => x"55807883",
+486 => x"ffff0670",
+487 => x"0a100a81",
+488 => x"06415c57",
+489 => x"7e772e80",
+490 => x"d7387690",
+491 => x"38740884",
+492 => x"16088817",
+493 => x"57585676",
+494 => x"802ef238",
+495 => x"76548880",
+496 => x"77278438",
+497 => x"88805473",
+498 => x"5375529c",
+499 => x"1a0851a4",
+500 => x"1a085877",
+501 => x"2d800b80",
+502 => x"082582e0",
+503 => x"38800816",
+504 => x"77800831",
+505 => x"7f880508",
+506 => x"80083170",
+507 => x"6188050c",
+508 => x"5b585678",
+509 => x"ffb43880",
+510 => x"5574800c",
+511 => x"903d0d04",
+512 => x"7a813281",
+513 => x"06774056",
+514 => x"75802e81",
+515 => x"bd387690",
+516 => x"38740884",
+517 => x"16088817",
+518 => x"57585976",
+519 => x"802ef238",
+520 => x"881a0878",
+521 => x"83ffff06",
+522 => x"70892a81",
+523 => x"06565956",
+524 => x"73802e82",
+525 => x"f8387577",
+526 => x"278b3877",
+527 => x"872a8106",
+528 => x"5c7b82b5",
+529 => x"38767627",
+530 => x"83387656",
+531 => x"75537852",
+532 => x"79085185",
+533 => x"833f881a",
+534 => x"08763188",
+535 => x"1b0c7908",
+536 => x"167a0c76",
+537 => x"56751977",
+538 => x"77317f88",
+539 => x"05087831",
+540 => x"70618805",
+541 => x"0c415859",
+542 => x"7e802efe",
+543 => x"fa388c1a",
+544 => x"2258ff8a",
+545 => x"39787954",
+546 => x"7c537b52",
+547 => x"5684c93f",
+548 => x"881a0879",
+549 => x"31881b0c",
+550 => x"7908197a",
+551 => x"0c7c7631",
+552 => x"5d7c8e38",
+553 => x"79518ff2",
+554 => x"3f800881",
+555 => x"8f388008",
+556 => x"5f751c77",
+557 => x"77317f88",
+558 => x"05087831",
+559 => x"70618805",
+560 => x"0c5d585c",
+561 => x"7a802efe",
+562 => x"ae387681",
+563 => x"83387408",
+564 => x"84160888",
+565 => x"1757585c",
+566 => x"76802ef2",
+567 => x"3876538a",
+568 => x"527b5182",
+569 => x"d33f8008",
+570 => x"7c318105",
+571 => x"5d800884",
+572 => x"3881175d",
+573 => x"815f7c59",
+574 => x"767d2783",
+575 => x"38765994",
+576 => x"1a08881b",
+577 => x"08115758",
+578 => x"807a085c",
+579 => x"54901a08",
+580 => x"7b278338",
+581 => x"81547579",
+582 => x"25843873",
+583 => x"ba387779",
+584 => x"24fee238",
+585 => x"77537b52",
+586 => x"9c1a0851",
+587 => x"a41a0859",
+588 => x"782d8008",
+589 => x"56800880",
+590 => x"24fee238",
+591 => x"8c1a2280",
+592 => x"c0075e7d",
+593 => x"8c1b23ff",
+594 => x"5574800c",
+595 => x"903d0d04",
+596 => x"7effa338",
+597 => x"ff873975",
+598 => x"537b527a",
+599 => x"5182f93f",
+600 => x"7908167a",
+601 => x"0c79518e",
+602 => x"b13f8008",
+603 => x"cf387c76",
+604 => x"315d7cfe",
+605 => x"bc38feac",
+606 => x"39901a08",
+607 => x"7a087131",
+608 => x"78117056",
+609 => x"5a575280",
+610 => x"cfe40851",
+611 => x"84943f80",
+612 => x"08802eff",
+613 => x"a7388008",
+614 => x"901b0c80",
+615 => x"08167a0c",
+616 => x"77941b0c",
+617 => x"76881b0c",
+618 => x"7656fd99",
+619 => x"39790858",
+620 => x"901a0878",
+621 => x"27833881",
+622 => x"54757727",
+623 => x"843873b3",
+624 => x"38941a08",
+625 => x"54737726",
+626 => x"80d33873",
+627 => x"5378529c",
+628 => x"1a0851a4",
+629 => x"1a085877",
+630 => x"2d800856",
+631 => x"80088024",
+632 => x"fd83388c",
+633 => x"1a2280c0",
+634 => x"075e7d8c",
+635 => x"1b23ff55",
+636 => x"fed73975",
+637 => x"53785277",
+638 => x"5181dd3f",
+639 => x"7908167a",
+640 => x"0c79518d",
+641 => x"953f8008",
+642 => x"802efcd9",
+643 => x"388c1a22",
+644 => x"80c0075e",
+645 => x"7d8c1b23",
+646 => x"ff55fead",
+647 => x"39767754",
+648 => x"79537852",
+649 => x"5681b13f",
+650 => x"881a0877",
+651 => x"31881b0c",
+652 => x"7908177a",
+653 => x"0cfcae39",
+654 => x"fa3d0d7a",
+655 => x"79028805",
+656 => x"a7053355",
+657 => x"53548374",
+658 => x"2780df38",
+659 => x"71830651",
+660 => x"7080d738",
+661 => x"71715755",
+662 => x"83517582",
+663 => x"802913ff",
+664 => x"12525670",
+665 => x"8025f338",
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+2532 => x"48656c6c",
+2533 => x"6f20776f",
+2534 => x"726c6420",
+2535 => x"310a0000",
+2536 => x"48656c6c",
+2537 => x"6f20776f",
+2538 => x"726c6420",
+2539 => x"320a0000",
+2540 => x"0a000000",
+2541 => x"43000000",
+2542 => x"64756d6d",
+2543 => x"792e6578",
+2544 => x"65000000",
+2545 => x"00ffffff",
+2546 => x"ff00ffff",
+2547 => x"ffff00ff",
+2548 => x"ffffff00",
+2549 => x"00000000",
+2550 => x"00000000",
+2551 => x"00000000",
+2552 => x"00002fb8",
+2553 => x"000027e8",
+2554 => x"00000000",
+2555 => x"00002a50",
+2556 => x"00002aac",
+2557 => x"00002b08",
+2558 => x"00000000",
+2559 => x"00000000",
+2560 => x"00000000",
+2561 => x"00000000",
+2562 => x"00000000",
+2563 => x"00000000",
+2564 => x"00000000",
+2565 => x"00000000",
+2566 => x"00000000",
+2567 => x"000027b4",
+2568 => x"00000000",
+2569 => x"00000000",
+2570 => x"00000000",
+2571 => x"00000000",
+2572 => x"00000000",
+2573 => x"00000000",
+2574 => x"00000000",
+2575 => x"00000000",
+2576 => x"00000000",
+2577 => x"00000000",
+2578 => x"00000000",
+2579 => x"00000000",
+2580 => x"00000000",
+2581 => x"00000000",
+2582 => x"00000000",
+2583 => x"00000000",
+2584 => x"00000000",
+2585 => x"00000000",
+2586 => x"00000000",
+2587 => x"00000000",
+2588 => x"00000000",
+2589 => x"00000000",
+2590 => x"00000000",
+2591 => x"00000000",
+2592 => x"00000000",
+2593 => x"00000000",
+2594 => x"00000000",
+2595 => x"00000000",
+2596 => x"00000001",
+2597 => x"330eabcd",
+2598 => x"1234e66d",
+2599 => x"deec0005",
+2600 => x"000b0000",
+2601 => x"00000000",
+2602 => x"00000000",
+2603 => x"00000000",
+2604 => x"00000000",
+2605 => x"00000000",
+2606 => x"00000000",
+2607 => x"00000000",
+2608 => x"00000000",
+2609 => x"00000000",
+2610 => x"00000000",
+2611 => x"00000000",
+2612 => x"00000000",
+2613 => x"00000000",
+2614 => x"00000000",
+2615 => x"00000000",
+2616 => x"00000000",
+2617 => x"00000000",
+2618 => x"00000000",
+2619 => x"00000000",
+2620 => x"00000000",
+2621 => x"00000000",
+2622 => x"00000000",
+2623 => x"00000000",
+2624 => x"00000000",
+2625 => x"00000000",
+2626 => x"00000000",
+2627 => x"00000000",
+2628 => x"00000000",
+2629 => x"00000000",
+2630 => x"00000000",
+2631 => x"00000000",
+2632 => x"00000000",
+2633 => x"00000000",
+2634 => x"00000000",
+2635 => x"00000000",
+2636 => x"00000000",
+2637 => x"00000000",
+2638 => x"00000000",
+2639 => x"00000000",
+2640 => x"00000000",
+2641 => x"00000000",
+2642 => x"00000000",
+2643 => x"00000000",
+2644 => x"00000000",
+2645 => x"00000000",
+2646 => x"00000000",
+2647 => x"00000000",
+2648 => x"00000000",
+2649 => x"00000000",
+2650 => x"00000000",
+2651 => x"00000000",
+2652 => x"00000000",
+2653 => x"00000000",
+2654 => x"00000000",
+2655 => x"00000000",
+2656 => x"00000000",
+2657 => x"00000000",
+2658 => x"00000000",
+2659 => x"00000000",
+2660 => x"00000000",
+2661 => x"00000000",
+2662 => x"00000000",
+2663 => x"00000000",
+2664 => x"00000000",
+2665 => x"00000000",
+2666 => x"00000000",
+2667 => x"00000000",
+2668 => x"00000000",
+2669 => x"00000000",
+2670 => x"00000000",
+2671 => x"00000000",
+2672 => x"00000000",
+2673 => x"00000000",
+2674 => x"00000000",
+2675 => x"00000000",
+2676 => x"00000000",
+2677 => x"00000000",
+2678 => x"00000000",
+2679 => x"00000000",
+2680 => x"00000000",
+2681 => x"00000000",
+2682 => x"00000000",
+2683 => x"00000000",
+2684 => x"00000000",
+2685 => x"00000000",
+2686 => x"00000000",
+2687 => x"00000000",
+2688 => x"00000000",
+2689 => x"00000000",
+2690 => x"00000000",
+2691 => x"00000000",
+2692 => x"00000000",
+2693 => x"00000000",
+2694 => x"00000000",
+2695 => x"00000000",
+2696 => x"00000000",
+2697 => x"00000000",
+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000000",
+2707 => x"00000000",
+2708 => x"00000000",
+2709 => x"00000000",
+2710 => x"00000000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"ffffffff",
+2790 => x"00000000",
+2791 => x"00020000",
+2792 => x"00000000",
+2793 => x"00000000",
+2794 => x"00002ba0",
+2795 => x"00002ba0",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
+
+process (clk, areset)
+begin
+ if areset = '1' then
+ elsif (clk'event and clk = '1') then
+ if (mem_writeEnable = '1') then
+ ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
+ end if;
+ if (mem_readEnable = '1') then
+ mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/example_medium/sim_fpga_top.vhd b/zpu/hdl/example_medium/sim_fpga_top.vhd
new file mode 100644
index 0000000..962caad
--- /dev/null
+++ b/zpu/hdl/example_medium/sim_fpga_top.vhd
@@ -0,0 +1,194 @@
+--------------------------------------------------------------------------------
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.zpu_config.all;
+
+
+entity fpga_top is
+end fpga_top;
+
+use work.zpupkg.all;
+
+architecture behave of fpga_top is
+
+
+ signal clk : std_logic;
+
+ signal areset : std_logic := '1';
+
+
+ component zpu_io is
+ generic (
+ log_file: string := "log.txt"
+ );
+ port (
+ clk : in std_logic;
+ areset : in std_logic;
+ busy : out std_logic;
+ writeEnable : in std_logic;
+ readEnable : in std_logic;
+ write : in std_logic_vector(wordSize-1 downto 0);
+ read : out std_logic_vector(wordSize-1 downto 0);
+ addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+ );
+ end component;
+
+
+ signal mem_busy : std_logic;
+ signal mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+ signal mem_writeEnable : std_logic;
+ signal mem_readEnable : std_logic;
+ signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal enable : std_logic;
+
+ signal dram_mem_busy : std_logic;
+ signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_writeEnable : std_logic;
+ signal dram_mem_readEnable : std_logic;
+ signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal io_busy : std_logic;
+
+ signal io_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal io_mem_writeEnable : std_logic;
+ signal io_mem_readEnable : std_logic;
+
+ signal dram_ready : std_logic;
+ signal io_ready : std_logic;
+ signal io_reading : std_logic;
+
+ signal break : std_logic;
+
+begin
+
+ zpu: zpu_core
+ port map (
+ clk => clk,
+ reset => areset,
+ enable => enable,
+ in_mem_busy => mem_busy,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => mem_addr,
+ out_mem_writeEnable => mem_writeEnable,
+ out_mem_readEnable => mem_readEnable,
+ mem_writeMask => mem_writeMask,
+ interrupt => '0',
+ break => break
+ );
+
+ dram_imp: dram
+ port map (
+ clk => clk ,
+ areset => areset,
+ mem_busy => dram_mem_busy,
+ mem_read => dram_mem_read,
+ mem_write => mem_write,
+ mem_addr => mem_addr(maxAddrBit downto 0),
+ mem_writeEnable => dram_mem_writeEnable,
+ mem_readEnable => dram_mem_readEnable,
+ mem_writeMask => mem_writeMask
+ );
+
+
+ ioMap: zpu_io
+ port map (
+ clk => clk,
+ areset => areset,
+ busy => io_busy,
+ writeEnable => io_mem_writeEnable,
+ readEnable => io_mem_readEnable,
+ write => mem_write(wordSize-1 downto 0),
+ read => io_mem_read,
+ addr => mem_addr(maxAddrBit downto minAddrBit)
+ );
+
+ dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+ dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+ io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+ io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+ mem_busy <= io_busy or dram_mem_busy or io_busy;
+
+
+ -- Memory reads either come from IO or DRAM. We need to pick the right one.
+ memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+ begin
+ mem_read <= (others => 'U');
+ if dram_ready='1' then
+ mem_read <= dram_mem_read;
+ end if;
+
+ if io_ready='1' then
+ mem_read <= io_mem_read;
+ end if;
+ end process;
+
+
+ io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+ memoryControlSync: process(clk, areset)
+ begin
+ if areset = '1' then
+ enable <= '0';
+ io_reading <= '0';
+ dram_ready <= '0';
+ elsif rising_edge(clk) then
+ enable <= '1';
+ io_reading <= io_busy or io_mem_readEnable;
+ dram_ready <= dram_mem_readEnable;
+ end if;
+ end process;
+
+ -- wiggle the clock @ 100MHz
+ clock : process
+ begin
+ clk <= '0';
+ wait for 5 ns;
+ clk <= '1';
+ wait for 5 ns;
+ areset <= '0';
+ end process clock;
+
+
+end architecture behave;
diff --git a/zpu/hdl/example_medium/simzpu_medium.do b/zpu/hdl/example_medium/simzpu_medium.do
new file mode 100644
index 0000000..2b77ba6
--- /dev/null
+++ b/zpu/hdl/example_medium/simzpu_medium.do
@@ -0,0 +1,28 @@
+# Xilinx WebPack modelsim script
+#
+# cd C:/workspace/zpu/zpu/hdl/example_medium
+# do simzpu_medium.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config_trace.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core.vhd
+vcom -93 -explicit dram_hello.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 1000 ms
diff --git a/zpu/hdl/example_medium/zpu_config_trace.vhd b/zpu/hdl/example_medium/zpu_config_trace.vhd
new file mode 100644
index 0000000..a5b9192
--- /dev/null
+++ b/zpu/hdl/example_medium/zpu_config_trace.vhd
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package zpu_config is
+
+ constant Generate_Trace : boolean := true;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
+ constant maxAddrBitIncIO : integer := 27;
+ constant maxAddrBitDRAM : integer := 16;
+ constant maxAddrBitBRAM : integer := 16;
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8";
+
+end zpu_config;
diff --git a/zpu/hdl/sim/dmipssmalltrace.do b/zpu/hdl/sim/dmipssmalltrace.do
new file mode 100644
index 0000000..eb4c6fe
--- /dev/null
+++ b/zpu/hdl/sim/dmipssmalltrace.do
@@ -0,0 +1,26 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config_trace.vhd
+vcom -93 -explicit zpupkg.vhd
+vcom -93 -explicit txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit zpu_core_small.vhd
+vcom -93 -explicit bram_dmips.vhd
+vcom -93 -explicit dram_dmips.vhd
+vcom -93 -explicit timer.vhd
+vcom -93 -explicit io.vhd
+vcom -93 -explicit trace.vhd
+
+
+vsim fpga_top
+view wave
+
+add wave -recursive fpga_top/zpu/*
+#--add wave -recursive fpga_top/ioMap/*
+#add wave -recursive fpga_top/*
+view structure
+
+
+# run ZPU
+run 5 ms
diff --git a/zpu/hdl/sim/dmipstrace.do b/zpu/hdl/sim/dmipstrace.do
new file mode 100644
index 0000000..64cf8fd
--- /dev/null
+++ b/zpu/hdl/sim/dmipstrace.do
@@ -0,0 +1,30 @@
+# Xilinx WebPack modelsim script
+#
+# cd C:/workspace/zpu/zpu/hdl/zpu4/src
+# do dmipstrace.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config_trace.vhd
+vcom -93 -explicit zpupkg.vhd
+vcom -93 -explicit txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit zpu_core.vhd
+vcom -93 -explicit dram_dmips.vhd
+vcom -93 -explicit timer.vhd
+vcom -93 -explicit io.vhd
+vcom -93 -explicit trace.vhd
+
+
+vsim fpga_top
+view wave
+
+add wave -recursive fpga_top/zpu/*
+#--add wave -recursive fpga_top/ioMap/*
+#add wave -recursive fpga_top/*
+view structure
+
+
+# run ZPU
+run 5 ms
diff --git a/zpu/hdl/spi/spi_controller.v b/zpu/hdl/spi/spi_controller.v
new file mode 100644
index 0000000..b22f294
--- /dev/null
+++ b/zpu/hdl/spi/spi_controller.v
@@ -0,0 +1,235 @@
+/*
+ SPI flash read-only controller
+
+ Copyright 2008 Álvaro Lopes <alvieboy@alvie.com>
+
+ Version: 1.3
+
+ The FreeBSD license
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials
+ provided with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Changelog:
+
+ 1.3: Remove async reset from spi_data shift register
+ Fix indentation of code
+
+ 1.2: Fix read count for sequential fetch
+
+ 1.1: Move port types outside module declaration.
+ Fix state machine to handle clock stop
+ Remove err out report
+ Fix SPI_CLK generation.
+*/
+
+module spi_controller (
+ clk, // Clock
+ rst, // Reset
+ ce, // Chip Enable
+ ack, // Acknowledge
+
+ adr, // Address in
+ dat_o, // Data out
+
+ SPI_MOSI, // Master Out/Slave In for SPI
+ SPI_MISO, // Master In/Slave Out for SPI
+ SPI_CLK, // SPI clock
+ SPI_SELN // SPI nSEL
+);
+
+parameter Tp = 0; // Propagation delay - for simulation
+parameter INIT_CLOCK_CYCLE_WAIT = 2; // Clock cycles to wait before init
+parameter DESELECT_CYCLES = 3; // Clock cycles to wait after deselection - should give 100ns at least
+parameter SPI_REGISTER_SIZE = 40;
+parameter SPI_ADDRESS_SIZE = 24;
+
+input clk;
+input rst;
+input ce;
+output reg ack;
+
+input [SPI_ADDRESS_SIZE-1:0] adr;
+output reg [31:0] dat_o;
+
+output reg SPI_MOSI;
+input SPI_MISO;
+output SPI_CLK;
+output reg SPI_SELN;
+
+
+// FSM states
+localparam SPI_STATE_WAIT = 7'b0000001,
+ SPI_STATE_IDLE = 7'b0000010,
+ SPI_STATE_WACK = 7'b0000100,
+ SPI_STATE_SEND = 7'b0001000,
+ SPI_STATE_BREAD = 7'b0010000,
+ SPI_STATE_READ = 7'b0100000,
+ SPI_STATE_WDES = 7'b1000000;
+
+// SPI commands
+localparam SPI_CMD_READ_FAST = 8'b00001011;
+
+
+// Shift register to hold command to be sent to SPI
+reg [SPI_REGISTER_SIZE-1:0] spi_shift_register_out;
+
+integer spi_reg_count;
+
+reg [8:0] spi_read_count;
+reg [7:0] spi_data;
+reg [3:0] data_valid_window;
+reg [SPI_REGISTER_SIZE-1:0] next_address;
+
+integer dsel_dly;
+integer spi_init_count;
+reg spi_start_count;
+reg spi_enable_clock; // Enable SPI clock
+reg [6:0] spi_state; // SPI state machine
+
+/*
+ SPI clock generation
+*/
+
+assign SPI_CLK = spi_enable_clock?~clk:1'b0;
+
+reg seq_read; // Sequential read in progress
+
+always @(posedge clk or posedge rst)
+begin
+ if ( rst ) begin
+ spi_enable_clock <= #Tp 1'b0;
+ spi_state <= #Tp SPI_STATE_WAIT;
+ spi_init_count <= #Tp INIT_CLOCK_CYCLE_WAIT;
+ SPI_SELN <= #Tp 1'b1;
+ ack <= #Tp 1'b0;
+ spi_start_count <= #Tp 1'b0;
+ next_address <= #Tp 32'hFFFFFFFF;
+ end else begin
+
+ case (spi_state)
+ SPI_STATE_WAIT:
+ begin
+ if ( spi_init_count == 0 ) begin
+ spi_state <= SPI_STATE_IDLE;
+ end else begin
+ spi_init_count <= #Tp spi_init_count - 1;
+ end
+ end
+ SPI_STATE_IDLE:
+ begin
+
+ if ( ce ) begin
+ next_address <= { adr[SPI_ADDRESS_SIZE-1:2], 2'b0 } + 4;
+ seq_read = adr[SPI_ADDRESS_SIZE-1:2] == next_address[SPI_ADDRESS_SIZE-1:2];
+ // Latch address (24 bit wordsize)
+ spi_shift_register_out <= #Tp { SPI_CMD_READ_FAST, adr[SPI_ADDRESS_SIZE-1:2], 2'b0, 8'b0 };
+
+ spi_enable_clock <= #Tp 1'b1;
+
+ if ( seq_read ) begin
+ spi_state <= #Tp SPI_STATE_BREAD;
+ end else