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| author | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
| commit | a1c964908b51599bf624bd2d253419c7e629f195 (patch) | |
| tree | 06125d59e83b7dde82d1bb57bc0e09ca83451b98 /zpu/hdl | |
| parent | bbfe29a15f11548eb7c9fa71dcb4d2d18c164a53 (diff) | |
| parent | 8679e4f91dcae05aef40f96629f33f0f4161f14a (diff) | |
| download | zpu-a1c964908b51599bf624bd2d253419c7e629f195.zip zpu-a1c964908b51599bf624bd2d253419c7e629f195.tar.gz | |
Merge branch 'master' of https://github.com/zylin/zpu
Diffstat (limited to 'zpu/hdl')
142 files changed, 60334 insertions, 0 deletions
diff --git a/zpu/hdl/avalanche/core/zpu_core.v b/zpu/hdl/avalanche/core/zpu_core.v new file mode 100644 index 0000000..e704fbc --- /dev/null +++ b/zpu/hdl/avalanche/core/zpu_core.v @@ -0,0 +1,749 @@ +`timescale 1ns / 1ps +`include "zpu_core_defines.v" + +/* MODULE: zpu_core + DESCRIPTION: Contains ZPU cpu + AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com) + +REVISION HISTORY: +Revision 1.0, 14/09/2009 +Initial public release + +COPYRIGHT: +Copyright (c) 2009 Antonio J. Anton + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +of the Software, and to permit persons to whom the Software is furnished to do +so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE.*/ + +// --------- MICROPROGRAMMED ZPU CORE --------------- +// all signals are polled on clk rising edge +// all signals positive + +module zpu_core ( +`ifdef ENABLE_CPU_INTERRUPTS + interrupt, // interrupt request +`endif + clk, // clock on rising edge + reset, // reset on rising edge + mem_read, // request memory read + mem_write, // request memory write + mem_done, // memory operation completed + mem_addr, // memory address + mem_data_read, // data readed + mem_data_write, // data written + byte_select // byte select on memory operation +); + +input clk; +input reset; +output mem_read; +output mem_write; +input mem_done; +input [31:0] mem_data_read; +output [31:0] mem_data_write; +output [31:0] mem_addr; +output [3:0] byte_select; +`ifdef ENABLE_CPU_INTERRUPTS +input interrupt; +`endif + +wire clk; +wire reset; +wire mem_read; +wire mem_write; +wire mem_done; +wire [31:0] mem_data_read; +wire [31:0] mem_data_write; +wire [31:0] mem_addr; +`ifdef ENABLE_CPU_INTERRUPTS +wire interrupt; +`endif + +`ifdef ENABLE_BYTE_SELECT +// ------ unaligned byte/halfword memory operations ----- +/// TODO: think rewriting into microcode or in a less resource wasting way + +reg [3:0] byte_select; +wire byte_op; +wire halfw_op; + +reg [31:0] mem_data_read_int; // aligned data from memory +reg [31:0] mem_data_write_out; // write data already aligned +wire [31:0] mem_data_write_int; // write data from cpu to be aligned + +// --- byte select logic --- +always @(mem_addr[1:0] or byte_op or halfw_op) +begin + casez( { mem_addr[1:0], byte_op, halfw_op } ) + 4'b00_1_? : byte_select <= 4'b0001; // byte select + 4'b01_1_? : byte_select <= 4'b0010; + 4'b10_1_? : byte_select <= 4'b0100; + 4'b11_1_? : byte_select <= 4'b1000; + 4'b0?_0_1 : byte_select <= 4'b0011; // half word select + 4'b1?_0_1 : byte_select <= 4'b1100; + default : byte_select <= 4'b1111; // word select + endcase +end + +// --- input data to cpu --- +always @(mem_data_read or mem_addr[1:0] or byte_op or halfw_op) +begin + casez( { mem_addr[1:0], byte_op, halfw_op } ) + 4'b00_1_? : mem_data_read_int <= { 24'b0, mem_data_read[7:0] }; // 8 bit read + 4'b01_1_? : mem_data_read_int <= { 24'b0, mem_data_read[15:8] }; + 4'b10_1_? : mem_data_read_int <= { 24'b0, mem_data_read[23:16] }; + 4'b11_1_? : mem_data_read_int <= { 24'b0, mem_data_read[31:24] }; + 4'b0?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[7:0], mem_data_read[15:8] }; // 16 bit read + 4'b1?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[23:16], mem_data_read[31:24] }; + default : mem_data_read_int <= { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] }; // 32 bit access (default) + endcase +end + +// --- output data from cpu --- +assign mem_data_write = mem_data_write_out; + +always @(mem_data_write_int or mem_addr[1:0] or byte_op or halfw_op) +begin + casez( {mem_addr[1:0], byte_op, halfw_op } ) + 4'b00_1_? : mem_data_write_out <= { 24'bX, mem_data_write_int[7:0] }; // 8 bit write + 4'b01_1_? : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], 8'bX }; + 4'b10_1_? : mem_data_write_out <= { 8'bX, mem_data_write_int[7:0], 16'bX }; + 4'b11_1_? : mem_data_write_out <= { mem_data_write_int[7:0], 24'bX }; + 4'b0?_0_1 : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], mem_data_write_int[15:8] }; // 16 bit write + 4'b1?_0_1 : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], 16'bX }; + default : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] }; + endcase +end +`else +// -------- only 32 bit memory access -------- +wire [3:0] byte_select = 4'b1111; // all memory operations are 32 bit wide +wire [31:0] mem_data_read_int; // no byte/halfword memory access by HW +wire [31:0] mem_data_write_int; // byte and halfword memory access must be emulated + +// ----- reorder bytes due to MSB-LSB configuration ----- +assign mem_data_read_int = { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] }; +assign mem_data_write = { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] }; +`endif + +// ------ datapath registers and connections ----------- +reg [31:0] pc; // program counter (byte align) +reg [31:0] sp; // stack counter (word align) +reg [31:0] a; // operand (address_out, data_out, alu_in) +reg [31:0] b; // operand (address_out) +reg idim; // im opcode being processed +reg [7:0] opcode; // opcode being processed +reg [31:2] pc_cached; // cached PC +reg [31:0] opcode_cache; // cached opcodes (current word) +`ifdef ENABLE_CPU_INTERRUPTS + reg int_requested; // interrupt has been requested + reg on_interrupt; // serving interrupt + wire exit_interrupt; // microcode says this is poppc_interrupt + wire enter_interrupt; // microcode says we are entering interrupt +`endif +wire [1:0] sel_opcode = pc[1:0]; // which opcode is selected +wire sel_read; // mux for data-in +wire [1:0] sel_alu; // mux for alu +wire [1:0] sel_addr; // mux for addr +wire w_pc; // write PC +`ifdef ENABLE_PC_INCREMENT + wire w_pc_increment; // write PC+1 +`endif +wire w_sp; // write SP +wire w_a; // write A (from ALU result) +wire w_a_mem; // write A (from MEM read) +wire w_b; // write B +wire w_op; // write OPCODE (opcode cache) +wire set_idim; // set IDIM +wire clear_idim; // clear IDIM +wire is_op_cached = (pc[31:2] == pc_cached) ? 1'b1 : 1'b0; // is opcode available? +wire a_is_zero; // A == 0 +wire a_is_neg; // A[31] == 1 +wire busy; // busy signal to microcode sequencer (stalls cpu) + +reg [`MC_MEM_BITS-1:0] mc_pc; // microcode PC +initial mc_pc <= `MC_ADDR_RESET-1; +wire [`MC_BITS-1:0] mc_op; // current microcode operation + +// memory addr / write ports +assign mem_addr = (sel_addr == `SEL_ADDR_SP) ? sp : + (sel_addr == `SEL_ADDR_A) ? a : + (sel_addr == `SEL_ADDR_B) ? b : pc; +assign mem_data_write_int = a; // only A can be written to memory + +// ------- alu instantiation ------- +wire [31:0] alu_a; +wire [31:0] alu_b; +wire [31:0] alu_r; +wire [`ALU_OP_WIDTH-1:0] alu_op; +wire alu_done; + +// alu inputs multiplexors +// constant in microcode is sign extended (in order to implement substractions like adds) +assign alu_a = (sel_read == `SEL_READ_DATA) ? mem_data_read_int : mem_addr; +assign alu_b = (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } : // most priority + (sel_alu == `SEL_ALU_A) ? a : + (sel_alu == `SEL_ALU_B) ? b : { {24{1'b0}} , opcode }; // `SEL_ALU_OPCODE is less priority + +zpu_core_alu alu( + .alu_a(alu_a), + .alu_b(alu_b), + .alu_r(alu_r), + .alu_op(alu_op), + .flag_idim(idim), + .clk(clk), + .done(alu_done) +); + +// -------- pc : program counter -------- +always @(posedge clk) +begin + if(w_pc) pc <= alu_r; +`ifdef ENABLE_PC_INCREMENT // microcode optimization + else if(w_pc_increment) pc <= pc + 1; // usually pc=pc+1 +`endif +end + +// -------- sp : stack pointer -------- +always @(posedge clk) +begin + if(w_sp) sp <= alu_r; +end + +// -------- a : acumulator register --------- +always @(posedge clk) +begin + if(w_a) a <= alu_r; + else if(w_a_mem) a <= mem_data_read_int; +end + +// alu results over a register instead of alu result +// in order to improve speed +assign a_is_zero = (a == 0); +assign a_is_neg = a[31]; + +// -------- b : auxiliary register --------- +always @(posedge clk) +begin + if(w_b) b <= alu_r; +end + +// -------- opcode and opcode_cache -------- +always @(posedge clk) +begin + if(w_op) + begin + opcode_cache <= alu_r; // store all opcodes in the word + pc_cached <= pc[31:2]; // store PC address of cached opcodes + end +end + +// -------- opcode : based on pc[1:0] --------- +always @(sel_opcode or opcode_cache) // select current opcode from +begin // the cached opcode word + case(sel_opcode) + 0 : opcode <= opcode_cache[31:24]; + 1 : opcode <= opcode_cache[23:16]; + 2 : opcode <= opcode_cache[15:8]; + 3 : opcode <= opcode_cache[7:0]; + endcase +end + +// ------- idim : immediate opcode handling ---------- +always @(posedge clk) +begin + if(set_idim) idim <= 1'b1; + else if(clear_idim) idim <= 1'b0; +end + +`ifdef ENABLE_CPU_INTERRUPTS +// ------ on interrupt status bit ----- +always @(posedge clk) +begin + if(reset | exit_interrupt) on_interrupt <= 1'b0; + else if(enter_interrupt) on_interrupt <= 1'b1; +end +`endif + +// ------ microcode execution unit -------- +assign sel_read = mc_op[`P_SEL_READ]; // map datapath signals with microcode program bits +assign sel_alu = mc_op[`P_SEL_ALU+1:`P_SEL_ALU]; +assign sel_addr = mc_op[`P_SEL_ADDR+1:`P_SEL_ADDR]; +assign alu_op = mc_op[`P_ALU+3:`P_ALU]; +assign w_sp = mc_op[`P_W_SP] & ~busy; +assign w_pc = mc_op[`P_W_PC] & ~busy; +assign w_a = mc_op[`P_W_A] & ~busy; +assign w_a_mem = mc_op[`P_W_A_MEM] & ~busy; +assign w_b = mc_op[`P_W_B] & ~busy; +assign w_op = mc_op[`P_W_OPCODE] & ~busy; +assign mem_read = mc_op[`P_MEM_R]; +assign mem_write = mc_op[`P_MEM_W]; +assign set_idim = mc_op[`P_SET_IDIM] & ~busy; +assign clear_idim= mc_op[`P_CLEAR_IDIM] & ~busy; +`ifdef ENABLE_BYTE_SELECT +assign byte_op = mc_op[`P_BYTE]; +assign halfw_op = mc_op[`P_HALFWORD]; +`endif +`ifdef ENABLE_PC_INCREMENT + assign w_pc_increment = mc_op[`P_PC_INCREMENT] & ~busy; +`endif +`ifdef ENABLE_CPU_INTERRUPTS + assign exit_interrupt = mc_op[`P_EXIT_INT] & ~busy; + assign enter_interrupt = mc_op[`P_ENTER_INT] & ~busy; +`endif + +wire cond_op_not_cached = mc_op[`P_OP_NOT_CACHED]; // conditional: true if opcode not cached +wire cond_a_zero = mc_op[`P_A_ZERO]; // conditional: true if A is zero +wire cond_a_neg = mc_op[`P_A_NEG]; // conditional: true if A is negative +wire decode = mc_op[`P_DECODE]; // decode means jumps to apropiate microcode based on zpu opcode +wire branch = mc_op[`P_BRANCH]; // unconditional jump inside microcode + +wire [`MC_MEM_BITS-1:0] mc_goto = { mc_op[`P_ADDR+6:`P_ADDR], 2'b00 }; // microcode goto (goto = high 7 bits) +wire [`MC_MEM_BITS-1:0] mc_entry = { opcode[6:0], 2'b00 }; // microcode entry point for opcode +reg [`MC_MEM_BITS-1:0] next_mc_pc; // next microcode operation to be executed +initial next_mc_pc <= `MC_ADDR_RESET-1; + +wire cond_branch = (cond_op_not_cached & ~is_op_cached) | // sum of all conditionals + (cond_a_zero & a_is_zero) | + (cond_a_neg & a_is_neg); + +assign busy = ((mem_read | mem_write) & ~mem_done) | ~alu_done; // busy signal for microcode sequencer + +// ------- handle interrupts --------- +`ifdef ENABLE_CPU_INTERRUPTS +always @(posedge clk) +begin + if(reset | on_interrupt) int_requested <= 0; + else if(interrupt & ~on_interrupt & ~int_requested) int_requested <= 1; // interrupt requested +end +`endif + +// ----- calculate next microcode address (next, decode, branch, specific opcode, etc.) ----- +always @(reset or mc_pc or mc_goto or opcode[7:4] or idim or + decode or branch or cond_branch or mc_entry or busy +`ifdef ENABLE_CPU_INTERRUPTS + or int_requested +`endif +) +begin + // default, next microcode instruction + next_mc_pc <= mc_pc + 1; + if(reset) next_mc_pc <= `MC_ADDR_RESET; + else if(~busy) + begin + // get next microcode instruction + if(branch | cond_branch) next_mc_pc <= mc_goto; + else if(decode) // decode: entry point of a new zpu opcode + begin +`ifdef ENABLE_CPU_INTERRUPTS + if(int_requested & ~idim) next_mc_pc <= `MC_ADDR_INTERRUPT; // microde to enter interrupt mode + else +`endif + if(opcode[7] == `OP_IM) next_mc_pc <= (idim ? `MC_ADDR_IM_IDIM : `MC_ADDR_IM_NOIDIM); + else if(opcode[7:5] == `OP_STORESP) next_mc_pc <= `MC_ADDR_STORESP; + else if(opcode[7:5] == `OP_LOADSP) next_mc_pc <= `MC_ADDR_LOADSP; + else if(opcode[7:4] == `OP_ADDSP) next_mc_pc <= `MC_ADDR_ADDSP; + else next_mc_pc <= mc_entry; // includes EMULATE opcodes + end + end + else next_mc_pc <= mc_pc; // in case of cpu stalled (busy=1) +end + +// set microcode program counter +always @(posedge clk) mc_pc <= next_mc_pc; + +// ----- microcode program ------ +zpu_core_rom microcode ( + .addr(next_mc_pc), + .data(mc_op), + .clk(clk) +); + +// -------------- ZPU debugger -------------------- +`ifdef ZPU_CORE_DEBUG +//synthesis translate_off +// ---- register operation dump ---- +always @(posedge clk) +begin + if(~reset) + begin + if(w_pc) $display("zpu_core: set PC=0x%h", alu.alu_r); +`ifdef ENABLE_PC_INCREMENT + if(w_pc_increment) $display("zpu_core: set PC=0x%h (PC+1)", pc); +`endif + if(w_sp) $display("zpu_core: set SP=0x%h", alu.alu_r); + if(w_a) $display("zpu_core: set A=0x%h", alu.alu_r); + if(w_a_mem) $display("zpu_core: set A=0x%h (from MEM)", mem_data_read_int); + if(w_b) $display("zpu_core: set B=0x%h", alu.alu_r); + if(w_op & ~is_op_cached) $display("zpu_core: set opcode_cache=0x%h, pc_cached=0x%h", alu.alu_r, {pc[31:2], 2'b0}); +`ifdef ENABLE_CPU_INTERRUPTS + if(~busy & mc_pc == `MC_ADDR_INTERRUPT) $display("zpu_core: ***** ENTERING INTERRUPT MICROCODE ******"); + if(~busy & exit_interrupt) $display("zpu_core: ***** INTERRUPT FLAG CLEARED *****"); + if(~busy & enter_interrupt) $display("zpu_core: ***** INTERRUPT FLAG SET *****"); +`endif + if(set_idim & ~idim) $display("zpu_core: IDIM=1"); + if(clear_idim & idim) $display("zpu_core: IDIM=0"); + +// ---- microcode debug ---- +`ifdef ZPU_CORE_DEBUG_MICROCODE + if(~busy) + begin + $display("zpu_core: mc_op[%d]=0b%b", mc_pc, mc_op); + if(branch) $display("zpu_core: microcode: branch=%d", mc_goto); + if(cond_branch) $display("zpu_core: microcode: CONDITION branch=%d", mc_goto); + if(decode) $display("zpu_core: decoding opcode=0x%h (0b%b) : branch to=%d ", opcode, opcode, mc_entry); + end + else $display("zpu_core: busy"); +`endif + +// ---- cpu abort in case of unaligned memory access --- +`ifdef ASSERT_NON_ALIGNMENT + /* unaligned word access (except PC) */ + if(sel_addr != `SEL_ADDR_PC & mem_addr[1:0] != 2'b00 & (mem_read | mem_write) & !byte_op & !halfw_op) + begin + $display("zpu_core: unaligned word operation at addr=0x%x", mem_addr); + $finish; + end + + /* unaligned halfword access */ + if(mem_addr[0] & (mem_read | mem_write) & !byte_op & halfw_op) + begin + $display("zpu_core: unaligned halfword operation at addr=0x%x", mem_addr); + $finish; + end +`endif + + end +end + +// ----- opcode dissasembler ------ +always @(posedge clk) +begin +if(~busy) +case(mc_pc) +0 : begin + $display("zpu_core: ------ breakpoint ------"); + $finish; + end +4 : $display("zpu_core: ------ shiftleft ------"); +8 : $display("zpu_core: ------ pushsp ------"); +12 : $display("zpu_core: ------ popint ------"); +16 : $display("zpu_core: ------ poppc ------"); +20 : $display("zpu_core: ------ add ------"); +24 : $display("zpu_core: ------ and ------"); +28 : $display("zpu_core: ------ or ------"); +32 : $display("zpu_core: ------ load ------"); +36 : $display("zpu_core: ------ not ------"); +40 : $display("zpu_core: ------ flip ------"); +44 : $display("zpu_core: ------ nop ------"); +48 : $display("zpu_core: ------ store ------"); +52 : $display("zpu_core: ------ popsp ------"); +56 : $display("zpu_core: ------ ipsum ------"); +60 : $display("zpu_core: ------ sncpy ------"); + +`MC_ADDR_IM_NOIDIM : $display("zpu_core: ------ im 0x%h (1st) ------", opcode[6:0] ); +`MC_ADDR_IM_IDIM : $display("zpu_core: ------ im 0x%h (cont) ------", opcode[6:0] ); +`MC_ADDR_STORESP : $display("zpu_core: ------ storesp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } ); +`MC_ADDR_LOADSP : $display("zpu_core: ------ loadsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } ); +`MC_ADDR_ADDSP : $display("zpu_core: ------ addsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } ); +`MC_ADDR_EMULATE : $display("zpu_core: ------ emulate 0x%h ------", b[2:0]); // opcode[5:0] ); + +128 : $display("zpu_core: ------ mcpy ------"); +132 : $display("zpu_core: ------ mset ------"); +136 : $display("zpu_core: ------ loadh ------"); +140 : $display("zpu_core: ------ storeh ------"); +144 : $display("zpu_core: ------ lessthan ------"); +148 : $display("zpu_core: ------ lessthanorequal ------"); +152 : $display("zpu_core: ------ ulessthan ------"); +156 : $display("zpu_core: ------ ulessthanorequal ------"); +160 : $display("zpu_core: ------ swap ------"); +164 : $display("zpu_core: ------ mult ------"); +168 : $display("zpu_core: ------ lshiftright ------"); +172 : $display("zpu_core: ------ ashiftleft ------"); +176 : $display("zpu_core: ------ ashiftright ------"); +180 : $display("zpu_core: ------ call ------"); +184 : $display("zpu_core: ------ eq ------"); +188 : $display("zpu_core: ------ neq ------"); +192 : $display("zpu_core: ------ neg ------"); +196 : $display("zpu_core: ------ sub ------"); +200 : $display("zpu_core: ------ xor ------"); +204 : $display("zpu_core: ------ loadb ------"); +208 : $display("zpu_core: ------ storeb ------"); +212 : $display("zpu_core: ------ div ------"); +216 : $display("zpu_core: ------ mod ------"); +220 : $display("zpu_core: ------ eqbranch ------"); +224 : $display("zpu_core: ------ neqbranch ------"); +228 : $display("zpu_core: ------ poppcrel ------"); +232 : $display("zpu_core: ------ config ------"); +236 : $display("zpu_core: ------ pushpc ------"); +240 : $display("zpu_core: ------ syscall_emulate ------"); +244 : $display("zpu_core: ------ pushspadd ------"); +248 : $display("zpu_core: ------ halfmult ------"); +252 : $display("zpu_core: ------ callpcrel ------"); +//default : $display("zpu_core: mc_pc=0x%h", decode_mcpc); +endcase +end +//synthesis translate_on +`endif +endmodule + +// --------- ZPU CORE ALU UNIT --------------- +module zpu_core_alu( + alu_a, // parameter A + alu_b, // parameter B + alu_r, // computed result + flag_idim, // for IMM alu op + alu_op, // ALU operation + clk, // clock for syncronous multicycle operations + done // done signal for alu operation +); + +input [31:0] alu_a; +input [31:0] alu_b; +input [`ALU_OP_WIDTH-1:0] alu_op; +input flag_idim; +output [31:0] alu_r; +input clk; +output done; + +wire [31:0] alu_a; +wire [31:0] alu_b; +wire [`ALU_OP_WIDTH-1:0] alu_op; +wire flag_idim; +reg [31:0] alu_r; +wire clk; +reg done; + +`ifdef ENABLE_MULT +// implement 32 bit pipeline multiplier +reg mul_running; +reg [2:0] mul_counter; +wire mul_done = (mul_counter == 3); +reg [31:0] mul_result, mul_tmp1; +reg [31:0] a_in, b_in; + +always@(posedge clk) +begin + a_in <= 0; + b_in <= 0; + mul_tmp1 <= 0; + mul_result <= 0; + mul_counter <= 0; + if(mul_running) + begin // infer pipeline multiplier + a_in <= alu_a; + b_in <= alu_b; + mul_tmp1 <= a_in * b_in; + mul_result <= mul_tmp1; + mul_counter <= mul_counter + 1; + end +end +`endif + +`ifdef ENABLE_DIV +// implement 32 bit divider +// Unsigned/Signed division based on Patterson and Hennessy's algorithm. +// Description: Calculates quotient. The "sign" input determines whether +// signs (two's complement) should be taken into consideration. +// references: http://www.ece.lsu.edu/ee3755/2002/l07.html +reg [63:0] qr; +wire [33:0] diff; +wire [31:0] quotient; +wire [31:0] dividend; +wire [31:0] divider; +reg [6:0] bit; +wire div_done; +reg div_running; +reg divide_sign; +reg negative_output; + +assign div_done = !bit; +assign diff = qr[63:31] - {1'b0, divider}; +assign quotient = (!negative_output) ? qr[31:0] : ~qr[31:0] + 1'b1; +assign dividend = (!divide_sign || !alu_a[31]) ? alu_a : ~alu_a + 1'b1; +assign divider = (!divide_sign || !alu_b[31]) ? alu_b : ~alu_b + 1'b1; + +always@(posedge clk) +begin + bit <= 7'b1_000000; // divider stopped + if(div_running) + begin + if(bit[6]) // divider started: initialize registers + begin + bit <= 7'd32; + qr <= { 32'd0, dividend }; + negative_output <= divide_sign && ((alu_b[31] && !alu_a[31]) || (!alu_b[31] && alu_a[31])); + end + else // step by step divide + begin + if( diff[32] ) qr <= { qr[62:0], 1'd0 }; + else qr <= { diff[31:0], qr[30:0], 1'd1 }; + bit <= bit - 1; + end + end +end +`endif + +`ifdef ENABLE_BARREL +// implement 32 bit barrel shift +// alu_b[6] == 1 ? left(only arithmetic) : right +// alu_b[5] == 1 ? logical : arithmetic +reg bs_running; +reg [31:0] bs_result; +reg [4:0] bs_counter; // 5 bits +wire bs_left = alu_b[6]; +wire bs_logical = alu_b[5]; +wire [4:0] bs_moves = alu_b[4:0]; +wire bs_done = (bs_counter == bs_moves); + +always @(posedge clk) +begin + bs_counter <= 0; + bs_result <= alu_a; + if(bs_running) + begin + if(bs_left) bs_result <= { bs_result[30:0], 1'b0 }; // shift left + else + begin + if(bs_logical) bs_result <= { 1'b0, bs_result[31:1] }; // shift logical right + else bs_result <= { bs_result[31], bs_result[31], bs_result[30:1] };// shift arithmetic right + end + bs_counter <= bs_counter + 1; + end +end +`endif + +// ----- alu add/sub ----- +reg [31:0] alu_b_tmp; +always @(alu_b or alu_op) +begin + alu_b_tmp <= alu_b; // by default, ALU_B as is + if(alu_op == `ALU_PLUS_OFFSET) alu_b_tmp <= { {25{1'b0}}, ~alu_b[4], alu_b[3:0], 2'b0 }; // ALU_B is an offset if ALU_PLUS_OFFSET operation +end + +reg [31:0] alu_r_addsub; // compute R=A+B or A-B based on opcode (ALU_PLUSxx / ALU_SUB-CMP) +always @(alu_a or alu_b_tmp or alu_op) +begin +`ifdef ENABLE_CMP + if(alu_op == `ALU_CMP_SIGNED || alu_op == `ALU_CMP_UNSIGNED) // in case of sub or cmp --> operation is '-' + begin + alu_r_addsub <= alu_a - alu_b_tmp; + end + else +`endif + begin + alu_r_addsub <= alu_a + alu_b_tmp; // by default '+' operation + end +end + +`ifdef ENABLE_CMP +// handle overflow/underflow exceptions in ALU_CMP_SIGNED +reg cmp_exception; +always @(alu_a[31] or alu_b[31] or alu_r_addsub[31]) +begin + cmp_exception <= 0; + if( (alu_a[31] == 0 && alu_b[31] == 1 && alu_r_addsub[31] == 1) || + (alu_a[31] == 1 && alu_b[31] == 0 && alu_r_addsub[31] == 0) ) cmp_exception <= 1; +end +`endif + +// ----- alu operation selection ----- +always @(alu_a or alu_b or alu_op or flag_idim or alu_r_addsub +`ifdef ENABLE_CMP + or cmp_exception +`endif +`ifdef ENABLE_MULT + or mul_done or mul_result +`endif +`ifdef ENABLE_BARREL + or bs_done or bs_result +`endif +`ifdef ENABLE_DIV + or div_done or div_result +`endif +) +begin + done <= 1; // default alu operations are 1 cycle +`ifdef ENABLE_MULT + mul_running <= 0; +`endif +`ifdef ENABLE_BARREL + bs_running <= 0; +`endif +`ifdef ENABLE_DIV + div_running <= 0; +`endif + alu_r <= alu_r_addsub; // ALU_PLUS, ALU_PLUS_OFFSET, ALU_SUB and part of ALU_CMP + case(alu_op) + `ALU_NOP : alu_r <= alu_a; + `ALU_NOP_B : alu_r <= alu_b; + `ALU_AND : alu_r <= alu_a & alu_b; + `ALU_OR : alu_r <= alu_a | alu_b; + `ALU_NOT : alu_r <= ~alu_a; + `ALU_FLIP : alu_r <= { alu_a[0], alu_a[1], alu_a[2], alu_a[3], alu_a[4], alu_a[5], alu_a[6], alu_a[7], + alu_a[8],alu_a[9],alu_a[10],alu_a[11],alu_a[12],alu_a[13],alu_a[14],alu_a[15], + alu_a[16],alu_a[17],alu_a[18],alu_a[19],alu_a[20],alu_a[21],alu_a[22],alu_a[23], + alu_a[24],alu_a[25],alu_a[26],alu_a[27],alu_a[28],alu_a[29],alu_a[30],alu_a[31] }; + `ALU_IM : if(flag_idim) alu_r <= { alu_a[24:0], alu_b[6:0] }; + else alu_r <= { {25{alu_b[6]}}, alu_b[6:0] }; +`ifdef ENABLE_CMP + `ALU_CMP_UNSIGNED:if( (alu_a[31] == alu_b[31] && cmp_exception) || + (alu_a[31] != alu_b[31] && ~cmp_exception) ) + begin + alu_r[31] <= ~alu_r_addsub[31]; + end + `ALU_CMP_SIGNED : if(cmp_exception) + begin + alu_r[31] <= ~alu_r_addsub[31]; + end +`endif +`ifdef ENABLE_XOR + `ALU_XOR : alu_r <= alu_a ^ alu_b; +`endif +`ifdef ENABLE_A_SHIFT + `ALU_A_SHIFT_RIGHT: alu_r <= { alu_a[31], alu_a[31], alu_a[30:1] }; // arithmetic shift left +`endif +`ifdef ENABLE_MULT + `ALU_MULT : begin + mul_running <= ~mul_done; + done <= mul_done; + alu_r <= mul_result; + end +`endif +`ifdef ENABLE_BARREL + `ALU_BARREL : begin + bs_running <= ~bs_done; + done <= bs_done; + alu_r <= bs_result; + end +`endif +`ifdef ENABLE_DIV + `ALU_DIV : begin + div_running<= ~div_done; + done <= div_done; + alu_r <= quotient; + end + `ALU_MOD : begin + div_running<= ~div_done; + done <= div_done; + alu_r <= qr[31:0]; + end +`endif + endcase +end + +endmodule diff --git a/zpu/hdl/avalanche/core/zpu_core_defines.v b/zpu/hdl/avalanche/core/zpu_core_defines.v new file mode 100644 index 0000000..228f46b --- /dev/null +++ b/zpu/hdl/avalanche/core/zpu_core_defines.v @@ -0,0 +1,322 @@ +/* MODULE: zpu_core_defines + DESCRIPTION: Contains ZPU parameters and other cpu related definitions + AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com) + +REVISION HISTORY: +Revision 1.0, 14/09/2009 +Initial public release + +COPYRIGHT: +Copyright (c) 2009 Antonio J. Anton + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +of the Software, and to permit persons to whom the Software is furnished to do +so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE.*/ + +/* --------------- ISA DOCUMENTATION ------------------ + stack: top of stack = sp, mem[sp]=valid data + push: sp=sp-1, then mem[sp]=data + pop: data=mem[sp], then sp=sp+1 + + immediates: any opcode instead of im sets idim=0 + + MNEMONIC OPCODE HEX OPERATION +- im x 1_xxxxxxx if(~idim) { idim=1; sp=sp-1; mem[sp]={{25{b[6]}},b[6:0]} } + else { idim=1; mem[sp]={mem[sp][24:0], b[6:0]} } +- emulate x 001_xxxxx sp=sp-1; mem[sp]=pc+1; pc=mem[@VECTOR_EMULATE + <b>]; fetch (used only by microcode) +- storesp x 010_xxxxx mem[sp+x<<2] = mem[sp]; sp=sp+1 +- loadsp x 011_xxxxx mem[sp-1] = mem [sp+x<<2]; sp=sp-1 +- addsp x 0001_xxxx (1x) mem[sp] = mem[sp]+mem[sp+x<<2] + +- breakpoint 0000_0000 (00) call exception vector + shiftleft 0000_0001 (01) +- pushsp 0000_0010 (02) mem[sp-1] = sp; sp = sp - 1 +- popint 0000_0011 (03) pc=mem[sp]; sp = sp + 1 ; fetch ; decode ; clear_interrupt_flag +- poppc 0000_0100 (04) pc=mem[sp]; sp = sp + 1 +- add 0000_0101 (05) mem[sp+1] = mem[sp+1] + mem[sp]; sp = sp + 1 +- and 0000_0110 (06) mem[sp+1] = mem[sp+1] & mem[sp]; sp = sp + 1 +- or 0000_0111 (07) mem[sp+1] = mem[sp+1] | mem[sp]; sp = sp + 1 +- load 0000_1000 (08) mem[sp] = mem[ mem[sp] ] +- not 0000_1001 (09) mem[sp] = ~mem[sp] +- flip 0000_1010 (0a) mem[sp] = flip(mem[sp]) +- nop 0000_1011 (0b) - +- store 0000_1100 (0c) mem[mem[sp]] = mem[sp+1]; sp = sp + 2 +- popsp 0000_1101 (0d) sp = mem[sp] + compare 0000_1110 (0e) ???? --> opcode recycled (see below) + popint 0000_1111 (0f) duplicated of 0x03 ????? --> opcode recycled (see below) + +- ipsum 0000_1110 (0e) c=mem[sp],s=mem[sp+1]; sum=0; while(c-->0) {sum+=halfword(mem[s],s);s+=2}; sp=sp+1; mem[sp]=sum (overwrites mem[0] & mem[4] words) +- sncpy 0000_1111 (0f) c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while( *(char*)s != 0 && c>0 ) {*((char*)d++)=*((char*)s++));c--}; sp=sp+3 (overwrites mem[0] & mem[4] words) +- wcpy 001_00000 (20) c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while(c-->0) mem[d++]=mem[s++]; sp=sp+3 (overwrites mem[0] & mem[4] words) +- wset 001_00001 (21) v=mem[sp],c=mem[sp+1],d=mem[sp+2]; while(c-->0) mem[d++]=v; sp=sp+3 (overwrites mem[0] & mem[4] words) + +- loadh 001_00010 (22) mem[sp] = halfword[ mem[sp] ] +- storeh 001_00011 (23) halfword[mem[sp]] = (mem[sp+1] & 0xFFFF); sp = sp + 2 +- lessthan 001_00100 (24) (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1 +- lessthanorequal 001_00101 (25) (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1 +- ulessthan 001_00110 (26) (unsigned(mem[sp])-unsigned(mem[sp+1])) < 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1 +- ulessthanorequal 001_00111 (27) (unsigned(mem[sp])-unsigned(mem[sp+1])) <= 0 || == 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1 + swap 001_01000 (28) +- mult 001_01001 (29) mem[sp+1] = mem[sp+1] * mem[sp]; sp = sp + 1 +- lshiftright 001_01010 (2a) mem[sp+1] = mem[sp+1] >> (mem[sp] & 0x1f); sp = sp + 1 +- ashiftleft 001_01011 (2b) mem[sp+1] = mem[sp+1] << (mem[sp] & 0x1f); sp = sp + 1 +- ashiftright 001_01100 (2c) mem[sp+1] = mem[sp+1] signed>> (mem[sp] & 0x1f); sp = sp + 1 +- call 001_01101 (2d) a = mem[sp]; mem[sp]=pc + 1; pc = a +- eq 001_01110 (2e) mem[sp+1] = (mem[sp] == mem[sp+1]) ? 1 : 0; sp = sp + 1 +- neq 001_01111 (2f) mem[sp+1] = (mem[sp] != mem[sp+1]) ? 1 : 0; sp = sp + 1 +- neg 001_10000 (30) mem[sp] = NOT(mem[sp])+1 +- sub 001_10001 (31) mem[sp+1]=mem[sp+1]-mem[sp]; sp=sp+1 +- xor 001_10010 (32) mem[sp+1]=mem[sp] ^ mem[sp+1]; sp=sp+1 +- loadb 001_10011 (33) mem[sp] = byte[ mem[sp] ] +- storeb 001_10100 (34) byte[mem[sp]] = (mem[sp+1] & 0xFF); sp = sp + 2 + div 001_10101 (35) + mod 001_10110 (36) +- eqbranch 001_10111 (37) mem[sp+1] == 0 ? pc = pc + mem[sp]; sp = sp + 2 +- neqbranch 001_11000 (38) mem[sp+1] != 0 ? pc = pc + mem[sp]; sp = sp + 2 +- poppcrel 001_11001 (39) pc = pc + mem[sp]; sp = sp + 1 + config 001_11010 (3a) +- pushpc 001_11011 (3b) sp=sp-1; mem[sp]=pc + syscall 001_11100 (3c) +- pushspadd 001_11101 (3d) mem[sp] = sp + (mem[sp] << 2) +- halfmult 001_11110 (3e) mem[sp+1] = 16bits(mem[sp]) * 16bits(mem[sp+1]); sp = sp + 1 +- callpcrel 001_11111 (3f) a = mem[sp]; mem[sp]=pc+1; pc = pc + a; + + gcc seems to be using only: + + add, addsp, and, ashiftleft, ashiftright, call, callpcrel, div, eq, flip, im, lessthan, + lessthanorequal, loadb, loadh, load, loadsp, lshiftright, mod, mult, neg, neqbranch, + not, or, poppc, poppcrel, popsp, pushpc, pushspadd, pushsp, storeb, storeh, store, storesp, + sub, ulessthan, ulessthanorequal, xor + + --------- memory access ---------------------------- + + data is stored in big-endian format into memory: + 00 MSB .. .. LSB + 05 .. .. .. .. + + ---------------------------------------------------- */ +`define SP_START 32'h10 // after reset change in startup code +`define EMULATION_VECTOR 32'h10 // table of emulated opcodes (interrupt & exception vectors plus up to 5 emulated opcodes) +`define RESET_VECTOR 32'h20 // reset entry point (can be moved up to 0x3c as per emulation table needs) + +// ---- zpu core optimizations/features ---- +`define ZPU_CORE_DEBUG +//`define ZPU_CORE_DEBUG_MICROCODE +`define ASSERT_NON_ALIGNMENT /* abort cpu in case of non-aligned memory access (only simulation) */ + +`define ENABLE_BYTE_SELECT /* allow byte / halfword memory accesses */ +`define ENABLE_CPU_INTERRUPTS /* enable interrupts to cpu */ +//`define ENABLE_PC_INCREMENT /* gain 1 clk per opcode but requires microcode changes ** not done at the moment ** */ +//`define ENABLE_A_SHIFT /* 1 bit arithmetic shift (right) mutual exclusive with barrel shift */ +//`define ENABLE_XOR /* 1 cycle x-or */ +//`define ENABLE_MULT /* 32 bit pipelined (3 stages) multiplier */ +//`define ENABLE_DIV /* 32 bit, up to 32 cycles serial divider */ +`define ENABLE_BARREL /* n bit logical & arithmetic shift mutual exclusive with 1 bit shift */ +`define ENABLE_CMP /* enable ALU_CMP_SIGNED and ALU_CMP_UNSIGNED */ + +// ------- microcode zpu core datapath selectors -------- +`define SEL_READ_DATA 0 +`define SEL_READ_ADDR 1 + +`define SEL_ALU_A 0 +`define SEL_ALU_OPCODE 1 +`define SEL_ALU_MC_CONST 2 +`define SEL_ALU_B 3 + +`define SEL_ADDR_PC 0 +`define SEL_ADDR_SP 1 +`define SEL_ADDR_A 2 +`define SEL_ADDR_B 3 + +`define ALU_OP_WIDTH 4 // alu operation is 4 bits + +`define ALU_NOP 0 // r = a +`define ALU_NOP_B 1 // r = b +`define ALU_PLUS 2 // r = a + b +`define ALU_PLUS_OFFSET 3 // r = a + { 27'b0, ~b[4], b[3:0] } +`define ALU_AND 4 // r = a AND b +`define ALU_OR 5 // r = a OR b +`define ALU_NOT 6 // r = NOT a +`define ALU_FLIP 7 // r = FLIP a +`define ALU_IM 8 // r = IDIM ? { a[24:0], b[6:0] } : { 25{b[6]}, b[6:0] } +`ifdef ENABLE_CMP + `define ALU_CMP_UNSIGNED 9 // r = (unsigned)a - (unsigned)b (r[31] is overflow/underflow adjusted) + `define ALU_CMP_SIGNED 10 // r = (signed)a - (signed)b (r[31] is overflow/underflow adjusted) +`endif +`ifdef ENABLE_BARREL + `define ALU_BARREL 11 // r = a <<|>> b (logical, arithmetical) +`endif +`ifdef ENABLE_A_SHIFT + `define ALU_A_SHIFT_RIGHT 11 // r = { a[31], a[31], a[30:29] } = (signed)a >> 1 +`endif +`ifdef ENABLE_XOR + `define ALU_XOR 12 // r = a XOR b +`endif +`ifdef ENABLE_MULT + `define ALU_MULT 13 // r = a * b +`endif +`ifdef ENABLE_DIV + `define ALU_DIV 14 // r = a / b + `define ALU_MOD 15 // r = a mod b +`endif + +// ------- special zpu opcodes ------ +`define OP_NOP 8'b0000_1011 // default value for opcode cache on reset +`define OP_IM 1'b1 +`define OP_EMULATE 3'b001 +`define OP_STORESP 3'b010 +`define OP_LOADSP 3'b011 +`define OP_ADDSP 4'b0001 + +// ------- microcode memory settings ------ +`define MC_MEM_BITS 9 // 512 microcode operations +`define MC_BITS 36 // microcode opcode width + +// ------- microcode labels for opcode execution ------- +// based on microcode program +`define MC_ADDR_IM_NOIDIM 488 +`define MC_ADDR_IM_IDIM 491 +`define MC_ADDR_STORESP 493 +`define MC_ADDR_LOADSP 496 +`define MC_ADDR_ADDSP 500 +`define MC_ADDR_EMULATE 504 +`define MC_ADDR_INTERRUPT 484 +`define MC_ADDR_FETCH_NEXT 480 +`define MC_ADDR_FETCH 476 +`define MC_ADDR_RESET 474 + +// ---------- microcode settings -------------------- +`define P_SEL_READ 0 // alu-A multiplexor between data-in and addr-out (1 bit) +`define P_SEL_ALU 1 // alu-B multiplexor between a, b, mc_const or opcode (2 bits) +`define P_SEL_ADDR 3 // addr-out multiplexor between sp, pc, a, b (2 bits) +`define P_ALU 5 // alu operation (4 bits) +`define P_W_SP 9 // write sp (from alu-out) +`define P_W_PC 10 // write pc (from alu-out) +`define P_W_A 11 // write a (from alu-out) +`define P_W_B 12 // write b (from alu-out) +`define P_SET_IDIM 13 // set idim flag +`define P_CLEAR_IDIM 14 // clear idim flag +`define P_W_OPCODE 15 // write opcode (from alu-out) : check if can be written directly from data-in +`define P_DECODE 16 // jump to microcode entry point based on current opcode +`define P_MEM_R 17 // request memory read +`define P_MEM_W 18 // request memory write +`define P_ADDR 19 // microcode address (7 bits (granularity is 4 words)) or constant to be used at microcode level +`define P_BRANCH 26 // microcode inconditional branch to address +`define P_OP_NOT_CACHED 27 // microcode branch if byte[pc] is not cached at opcode +`define P_A_ZERO 28 // microcode branch if a is zero +`define P_A_NEG 29 // microcode branch if a is negative a[31]=1 +`define P_W_A_MEM 30 // write a directly from data-in (alu datapath is free to perform any other operation in parallel) +`ifdef ENABLE_BYTE_SELECT + `define P_BYTE 31 // byte memory operation + `define P_HALFWORD 32 // half word memory operation +`endif +`ifdef ENABLE_PC_INCREMENT + `define P_PC_INCREMENT 33 // autoincrement PC bypassing ALU (1 clock gain per opcode) : not implemented at microcode level +`endif +`ifdef ENABLE_CPU_INTERRUPTS + `define P_EXIT_INT 34 // clear interrupt flag (exit from interrupt) + `define P_ENTER_INT 35 // set interrupt flag (enter interrupt) +`endif + +`define MC_SEL_READ_DATA (`SEL_READ_DATA << `P_SEL_READ) // 1 bit +`define MC_SEL_READ_ADDR (`SEL_READ_ADDR << `P_SEL_READ) + +`define MC_SEL_ALU_A (`SEL_ALU_A << `P_SEL_ALU) // 2 bit +`define MC_SEL_ALU_OPCODE (`SEL_ALU_OPCODE << `P_SEL_ALU) +`define MC_SEL_ALU_MC_CONST (`SEL_ALU_MC_CONST << `P_SEL_ALU) +`define MC_SEL_ALU_B (`SEL_ALU_B << `P_SEL_ALU) + +`define MC_SEL_ADDR_PC (`SEL_ADDR_PC << `P_SEL_ADDR) // 2 bits +`define MC_SEL_ADDR_SP (`SEL_ADDR_SP << `P_SEL_ADDR) +`define MC_SEL_ADDR_A (`SEL_ADDR_A << `P_SEL_ADDR) +`define MC_SEL_ADDR_B (`SEL_ADDR_B << `P_SEL_ADDR) + +`define MC_ALU_NOP (`ALU_NOP << `P_ALU) // 4 bits +`define MC_ALU_NOP_B (`ALU_NOP_B << `P_ALU) +`define MC_ALU_PLUS (`ALU_PLUS << `P_ALU) +`define MC_ALU_AND (`ALU_AND << `P_ALU) +`define MC_ALU_OR (`ALU_OR << `P_ALU) +`define MC_ALU_NOT (`ALU_NOT << `P_ALU) +`define MC_ALU_FLIP (`ALU_FLIP << `P_ALU) +`define MC_ALU_IM (`ALU_IM << `P_ALU) +`define MC_ALU_PLUS_OFFSET (`ALU_PLUS_OFFSET << `P_ALU) +`ifdef ENABLE_CMP + `define MC_ALU_CMP_SIGNED (`ALU_CMP_SIGNED << `P_ALU) + `define MC_ALU_CMP_UNSIGNED (`ALU_CMP_UNSIGNED << `P_ALU) +`endif +`ifdef ENABLE_XOR + `define MC_ALU_XOR (`ALU_XOR << `P_ALU) +`endif +`ifdef ENABLE_A_SHIFT + `define MC_ALU_A_SHIFT_RIGHT (`ALU_A_SHIFT_RIGHT << `P_ALU) +`endif +`ifdef ENABLE_MULT + `define MC_ALU_MULT (`ALU_MULT << `P_ALU) +`endif +`ifdef ENABLE_DIV + `define MC_ALU_DIV (`ALU_DIV << `P_ALU) + `define MC_ALU_MOD (`ALU_MOD << `P_ALU) +`endif +`ifdef ENABLE_BARREL + `define MC_ALU_BARREL (`ALU_BARREL << `P_ALU) +`endif + +`define MC_W_SP (1 << `P_W_SP) +`define MC_W_PC (1 << `P_W_PC) +`define MC_W_A (1 << `P_W_A) +`define MC_W_A_MEM (1 << `P_W_A_MEM) +`define MC_W_B (1 << `P_W_B) +`define MC_W_OPCODE (1 << `P_W_OPCODE) +`define MC_SET_IDIM (1 << `P_SET_IDIM) +`define MC_CLEAR_IDIM (1 << `P_CLEAR_IDIM) +`ifdef ENABLE_BYTE_SELECT + `define MC_BYTE (1 << `P_BYTE) + `define MC_HALFWORD (1 << `P_HALFWORD) +`endif +`ifdef ENABLE_PC_INCREMENT + `define MC_PC_INCREMENT (1 << `P_PC_INCREMENT) +`endif +`ifdef ENABLE_CPU_INTERRUPTS + `define MC_EXIT_INTERRUPT (1 << `P_EXIT_INT) + `define MC_ENTER_INTERRUPT (1 << `P_ENTER_INT) +`endif + +`define MC_MEM_R (1 << `P_MEM_R) +`define MC_MEM_W (1 << `P_MEM_W) + +`define MC_DECODE (1 << `P_DECODE) +`define MC_BRANCH (1 << `P_BRANCH) +`define MC_BRANCHIF_OP_NOT_CACHED (1 << `P_OP_NOT_CACHED) +`define MC_BRANCHIF_A_ZERO (1 << `P_A_ZERO) +`define MC_BRANCHIF_A_NEG (1 << `P_A_NEG) + +// microcode common operations + +`define MC_ADDR_FETCH_OP ( (`MC_ADDR_FETCH >> 2) << `P_ADDR) // fetch opcode from memory then decode +`define MC_ADDR_NEXT_OP ( (`MC_ADDR_FETCH_NEXT >> 2) << `P_ADDR) // go to next opcode +`define MC_ADDR_EMULATE_OP ( (`MC_ADDR_EMULATE >> 2) << `P_ADDR) // EMULATE opcode + +`define MC_PC_PLUS_1 (`MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS | (1 << `P_ADDR) | `MC_W_PC) +`define MC_SP_MINUS_4 (`MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS | ((-4 & 127) << `P_ADDR) | `MC_W_SP) +`define MC_SP_PLUS_4 (`MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS | (4 << `P_ADDR) | `MC_W_SP) +`define MC_EMULATE (`MC_BRANCH | `MC_ADDR_EMULATE_OP) + +`define MC_FETCH (`MC_BRANCHIF_OP_NOT_CACHED | `MC_ADDR_FETCH_OP | `MC_DECODE) // fetch and decode current PC opcode +`define MC_GO_NEXT (`MC_BRANCH | `MC_ADDR_NEXT_OP) // go to next opcode (PC=PC+1, fetch, decode) +`define MC_GO_FETCH (`MC_BRANCH | `MC_ADDR_FETCH_OP) // go to fetch opcode at PC, then decode +`define MC_GO_BREAKPOINT (`MC_BRANCH | ((0 >> 2) << `P_ADDR)) // go to breakpoint opcode + diff --git a/zpu/hdl/avalanche/core/zpu_core_rom.v b/zpu/hdl/avalanche/core/zpu_core_rom.v new file mode 100644 index 0000000..62b7229 --- /dev/null +++ b/zpu/hdl/avalanche/core/zpu_core_rom.v @@ -0,0 +1,1017 @@ +`timescale 1ns / 1ps +`include "zpu_core_defines.v" + +/* MODULE: zpu_core_rom + DESCRIPTION: Contains microcode program + AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com) + +REVISION HISTORY: +Revision 1.0, 14/09/2009 +Initial public release + +COPYRIGHT: +Copyright (c) 2009 Antonio J. Anton + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +of the Software, and to permit persons to whom the Software is furnished to do +so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE.*/ + +module zpu_core_rom ( + clk, + addr, + data +); + +input [`MC_MEM_BITS-1:0] addr; +output [`MC_BITS-1:0] data; +input clk; + +wire [`MC_MEM_BITS-1:0] addr; +reg [`MC_BITS-1:0] data; +reg [`MC_BITS-1:0] memory[(1<<`MC_MEM_BITS)-1:0]; + +initial data <= 0; +always @(posedge clk) data <= memory[addr]; + +// --- clear all memory at startup; for any reason, xilinx xst +// will not syntetize as block ram if not all memory is initialized --- +integer n; +initial begin +// initialize all memory array +for(n = 0; n < (1<<`MC_MEM_BITS); n = n + 1) memory[n] = 0; + +// ------------------------- MICROCODE MEMORY START ----------------------------------- + +// As per zpu_core.v, each opcode is executed by microcode. Each opcode microcode entry point +// is at <opcode> << 2 (example pushsp = 0x02 has microcode entry point of 0x08); this leaves +// room of 4 microcode operations per opcode; if the opcode microcode needs more space, +// it can jump & link to other microcode address (with the two lower bits at 0). The lower 256 addresses +// of microcode memory are entry points and code for 0..127 opcodes; other specific opcodes like im, storesp, etc. +// are directly hardwired to specific microcode addresses at the memory end. Upper 256 addresses are +// used by microcode continuation (eg. opcodes which needs more microcode operations), entry points, initializations, etc. +// the idea is to fit the microcode program in a xilinx blockram 512x36. + +// ----- OPCODES WITHOUT CONSTANT ------ + +// 0000_0000 (00) breakpoint ------------------------------------- +memory[0] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | // b = 4 (#1 in emulate table) + `MC_W_B; +memory[1] = `MC_EMULATE; // emulate #1 (exception) + +// 0000_0001 (01) shiftleft ------------------------------------- +memory[4] = `MC_GO_BREAKPOINT; + +// 0000_0010 (02) pushsp ------------------------------------- +// mem[sp-1] = sp +// sp = sp - 1 +memory[8] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + `MC_ALU_NOP | `MC_W_A; +memory[9] = `MC_SP_MINUS_4; // sp = sp - 1 +memory[10] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp]=a + +// 0000_0011 (03) popint ------------------------------------- +`ifdef ENABLE_CPU_INTERRUPTS +// pc=mem[sp]-1 (emulate stores pc+1 but we must return to +// sp=sp+1 pc because interrupt takes precedence to decode) +// fetch & decode, then clear_interrupt_flag +// this guarantees that a continous interrupt allows to execute at least one +// opcode of mainstream program before reentry to interrupt handler +memory[12] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // pc = mem[sp]-1 + `MC_MEM_R | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | + ((-1 & 127) << `P_ADDR) | `MC_W_PC; +memory[13] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R | // opcode_cache = mem[pc] + `MC_W_OPCODE; +memory[14] = `MC_SP_PLUS_4 | `MC_DECODE | `MC_EXIT_INTERRUPT; // sp=sp+1, decode opcode, exit_interrupt +`else +memory[12] = `MC_GO_BREAKPOINT; +`endif + +// 0000_0100 (04) poppc ------------------------------------- +// pc=mem[sp] +// sp = sp + 1 +memory[16] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // pc = mem[sp] + `MC_MEM_R | `MC_W_PC; +memory[17] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[18] = `MC_FETCH; // opcode cached ? decode : fetch,decode + +// 0000_0101 (05) add ------------------------------------- +// mem[sp+1] = mem[sp+1] + mem[sp] +// sp = sp + 1 +memory[20] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1 + `MC_W_A_MEM | `MC_SP_PLUS_4; +memory[21] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a + mem[sp] + `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A; +memory[22] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 0000_0110 (06) and ------------------------------------- +// mem[sp+1] = mem[sp+1] & mem[sp] +// sp = sp + 1 +memory[24] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1 + `MC_W_A_MEM | `MC_SP_PLUS_4; +memory[25] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a & mem[sp] + `MC_ALU_AND |`MC_SEL_ALU_A | `MC_W_A; +memory[26] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 0000_0111 (07) or ------------------------------------- +// mem[sp+1] = mem[sp+1] | mem[sp] +// sp = sp + 1 +memory[28] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1 + `MC_W_A_MEM | `MC_SP_PLUS_4; +memory[29] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a | mem[sp] + `MC_ALU_OR | `MC_SEL_ALU_A | `MC_W_A; +memory[30] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 0000_1000 (08) load ------------------------------------- +// mem[sp] = mem[ mem[sp] ] +memory[32] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] + `MC_MEM_R | `MC_W_A; +memory[33] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a] +memory[34] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 0000_1001 (09) not ------------------------------------- +// mem[sp] = ~mem[sp] +memory[36] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = ~mem[sp] + `MC_MEM_R | `MC_ALU_NOT | `MC_W_A; +memory[37] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 0000_1010 (0a) flip ------------------------------------- +// mem[sp] = flip(mem[sp]) +memory[40] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = FLIP(mem[sp]) + `MC_MEM_R | `MC_ALU_FLIP | `MC_W_A; +memory[41] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 0000_1011 (0b) nop ------------------------------------- +memory[44] = `MC_CLEAR_IDIM | `MC_PC_PLUS_1; // IDIM=0 +memory[45] = `MC_FETCH; + +// 0000_1100 (0c) store ------------------------------------- +// mem[mem[sp]] <= mem[sp+1] +// sp = sp + 2 +memory[48] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] + `MC_MEM_R | `MC_W_B; +memory[49] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[50] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | `MC_SP_PLUS_4; // a = mem[sp] || sp = sp + 1 +memory[51] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT; // mem[b] = a + +// 0000_1101 (0d) popsp ------------------------------------- +// sp = mem[sp] +memory[52] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // sp = mem[sp] + `MC_W_SP | `MC_GO_NEXT; + +// 0000_1110 (0e) ipsum ------------------------------------ +// compare: opcode recycled --> ipsum +// c=mem[sp];s=mem[sp+1]; sum=0; +// while(c-->0) {sum+=halfword(mem[s],s);s++}; +// sp=sp+1; mem[sp]=sum (overwrites mem[0] & mem[4] words) +// requires HALFWORD memory access +`ifdef ENABLE_BYTE_SELECT +memory[56] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0 + (0 << `P_ADDR) | `MC_W_B; +memory[57] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1 save next pc on mem[0] + `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; +memory[58] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4 + `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR); +memory[59] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @ipsum_continue1 + `MC_BRANCH | ((116 >> 2) << `P_ADDR); +`else +memory[56] = `MC_GO_BREAKPOINT; +`endif + +// 0000_1111 (0f) sncpy --------------------------------------- +// c=mem[sp],d=mem[sp+1],s=mem[sp+2]; +// while( *(char*)s != 0 && c>0 ) { *((char*)d++)=*((char*)s++)); c-- }; +// sp=sp+1; mem[sp+1]=d; mem[sp]=c +// (overwrites mem[0] & mem[4] words) +// requires BYTE memory access +`ifdef ENABLE_BYTE_SELECT +memory[60] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0 + (0 << `P_ADDR) | `MC_W_B; +memory[61] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1 save next pc on mem[0] + `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; +memory[62] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4 + `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR); +memory[63] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @sncpy_continue1 + `MC_BRANCH | ((100 >> 2) << `P_ADDR); +`else +memory[60] = `MC_GO_BREAKPOINT; +`endif + +// ------------- microcode opcode continuations --------------- +// wset_continue1: ------------------------ +memory[64] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+12 save clear stack on mem[4] + `MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A; +memory[65] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a +memory[66] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (data) +memory[67] = `MC_SP_PLUS_4; // sp=sp+4 +memory[68] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B; // b=mem[sp] (count) +memory[69] = `MC_SP_PLUS_4; // sp=sp+4 +memory[70] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (destination @) +memory[71] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (count) +// wset_loop: +memory[72] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @wset_end +memory[73] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b=b-1 (count) + `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B; +memory[74] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_W_A; // a=pc (data) +memory[75] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SP_PLUS_4; // mem[sp]=a || sp=sp+4 (sp=destination@) +memory[76] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | // a=b (count) || goto @wset_loop + `MC_BRANCH | ((72 >> 2) << `P_ADDR); +// wset_end: wcpy_end: sncpy_end: +memory[80] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC; // pc=mem[a] (a is 0) +memory[81] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | // b=4 + `MC_W_B; +memory[82] = `MC_SEL_ADDR_B | `MC_MEM_R | `MC_SEL_READ_DATA | // sp=mem[b] || goto @fetch + `MC_W_SP | `MC_FETCH; + +// wcpy_continue1: ------------------------ +memory[84] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+12 save clear stack on mem[4] + `MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A; +memory[85] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a +memory[86] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B; // b=mem[sp] (count) +memory[87] = `MC_SP_PLUS_4; // sp=sp+4 +memory[88] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (destination @) +memory[89] = `MC_SP_PLUS_4; // sp=sp+4 +memory[90] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (source @) +memory[91] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (count) +// wcpy_loop: +memory[92] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @wcpy_end +memory[93] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b=b-1 (count) + `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B; +memory[94] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+4 (sp=source@) + `MC_SP_PLUS_4; +memory[95] = `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR | // mem[pc]=a || pc=pc+4 (pc=destination@) + `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_PC; +memory[96] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | // a=b (count) || goto @wcpy_loop + `MC_BRANCH | ((92 >> 2) << `P_ADDR); + +`ifdef ENABLE_BYTE_SELECT +// sncpy_continue1: --------------------- +memory[100] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+12 + `MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A; +memory[101] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a +memory[102] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;// b=mem[sp] (count) +memory[103] = `MC_SP_PLUS_4; // sp=sp+4 +memory[104] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (destination @) +memory[105] = `MC_SP_PLUS_4; // sp=sp+4 +memory[106] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (source @) +memory[107] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (count) +// sncpy_loop: +memory[108] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @sncpy_end (count==0?) +memory[109] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_BYTE | `MC_W_A_MEM | // a=BYTE(mem[sp],sp) || sp=sp+1 (sp=source@) + `MC_SEL_READ_ADDR | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | + (1 << `P_ADDR) | `MC_W_SP; +memory[110] = `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR | // BYTE(mem[pc],pc)=a || pc=pc+1 (pc=destination@) + `MC_BYTE | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | + (1 << `P_ADDR) | `MC_W_PC; +memory[111] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @sncpy_end (mem[src]==0?) +memory[112] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b=b-1 (count) + `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B; +memory[113] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | // a=b (count) || goto @sncpy_loop + `MC_BRANCH | ((108 >> 2) << `P_ADDR); + +// ipsum_continue1: ------------------- +memory[116] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+4 + `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_A; +memory[117] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a save return sp on mem[4] +memory[118] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // pc=mem[sp] (count) + `MC_W_PC; +memory[119] = `MC_SP_PLUS_4; // sp=sp+4 +memory[120] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // sp=mem[sp] (start @) + `MC_W_SP; +memory[121] = `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | `MC_W_B | // b=0 (sum) + `MC_ALU_NOP_B; +memory[122] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_W_A; // a=pc (count) +// ipsum_loop: +memory[124] = `MC_BRANCHIF_A_ZERO | ((392 >> 2) << `P_ADDR); // a == 0 ? goto @ipsum_end + +memory[125] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_HALFWORD | // b=mem[sp]+b + `MC_SEL_READ_DATA | `MC_ALU_PLUS | `MC_SEL_ALU_B | `MC_W_B; +memory[126] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // sp=sp+2 + `MC_SEL_ALU_MC_CONST | (2 << `P_ADDR) | `MC_W_SP; +memory[127] = `MC_BRANCH | ((408 >> 2) << `P_ADDR); // goto @ipsum_continue2 +`endif + +// ------------------------------------------------------------- + +// 001_00000 (20) wcpy ----------------------------------------- +// before using this opcode you must save mem[0] & mem[4] words, then wcpy, then restore mems +// c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while(c-->0) mem[d++]=mem[s++]; sp=sp+3 +memory[128] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0 + (0 << `P_ADDR) | `MC_W_B; +memory[129] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1 + `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; +memory[130] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4 + `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR); +memory[131] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @wcpy_continue1 + `MC_BRANCH | ((84 >> 2) << `P_ADDR); + +// 001_00001 (21) wset ---------------------------------------- +// before using this opcode you must save mem[0] & mem[4] words, then wset, then restore mems +// v=mem[sp],c=mem[sp+1],d=mem[sp+2]; while(c-->0) mem[d++]=v; sp=sp+3 +memory[132] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0 + (0 << `P_ADDR) | `MC_W_B; +memory[133] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1 + `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; +memory[134] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4 + `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR); +memory[135] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @wset_continue1 + `MC_BRANCH | ((64 >> 2) << `P_ADDR); + +// 001_00010 (22) loadh ------------------------------------- +`ifdef ENABLE_BYTE_SELECT +// mem[sp] = HALFWORD(mem[sp], mem[mem[sp]]) +memory[136] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] + `MC_MEM_R | `MC_W_A; +memory[137] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | // a = halfword(a, mem[a]) + `MC_W_A | `MC_HALFWORD; +memory[138] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`else +memory[136] = `MC_GO_BREAKPOINT; +`endif + +// 001_00011 (23) storeh ------------------------------------- +`ifdef ENABLE_BYTE_SELECT +// HALFWORD( mem[mem[sp]] <= mem[sp+1] ) +// sp = sp + 2 +memory[140] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] + `MC_MEM_R | `MC_W_B; +memory[141] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[142] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a = mem[sp] || sp=sp+1 + `MC_SP_PLUS_4; +memory[143] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_HALFWORD | `MC_GO_NEXT; // HALFWORD(mem[b] = a) +`else +memory[140] = `MC_GO_BREAKPOINT; +`endif + +// 001_00100 (24) lessthan ------------------------------------- +// (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0 +// sp=sp+1 +`ifdef ENABLE_CMP +memory[144] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1 + `MC_SP_PLUS_4; +memory[145] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B; // b=mem[sp] +memory[146] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthan_check + `MC_ALU_CMP_SIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH; +`else +memory[144] = `MC_GO_BREAKPOINT; +`endif + +// 001_00101 (25) lessthanorequal ------------------------------------- +// (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0 +// sp=sp+1 +`ifdef ENABLE_CMP +memory[148] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1 + `MC_SP_PLUS_4; +memory[149] = `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B; // b=mem[sp] +memory[150] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthanorequal_check + `MC_ALU_CMP_SIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH; +`else +memory[148] = `MC_GO_BREAKPOINT; +`endif + +// 001_00110 (26) ulessthan ------------------------------------- +// signA!=signB -> (unsigA < unsigB) == ~(sigA < sigA) +// signA==signB -> (unsigA < unsigB) == (sigA < sigB) +// (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0 +// sp=sp+1 +`ifdef ENABLE_CMP +memory[152] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1 + `MC_SP_PLUS_4; +memory[153] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B; // b=mem[sp] +memory[154] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthan_check + `MC_ALU_CMP_UNSIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH; +`else +memory[152] = `MC_GO_BREAKPOINT; +`endif + +// 001_00111 (27) ulessthanorequal ------------------------------------- +// (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0 +// sp=sp+1 +`ifdef ENABLE_CMP +memory[156] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1 + `MC_SP_PLUS_4; +memory[157] = `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B; // b=mem[sp] +memory[158] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthanorequal_check + `MC_ALU_CMP_UNSIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH; +`else +memory[156] = `MC_GO_BREAKPOINT; +`endif + +// 001_01000 (28) swap ------------------------------------- +memory[160] = `MC_GO_BREAKPOINT; + +// 001_01001 (29) mult ------------------------------------- +`ifdef ENABLE_MULT +// mem[sp+1] = mem[sp+1] * mem[sp] +// sp = sp + 1 +memory[164] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1 + `MC_W_A_MEM | `MC_SP_PLUS_4; +memory[165] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp] + `MC_W_B; +memory[166] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = a * b DON'T COMBINE MULTICYCLE ALU + `MC_ALU_MULT | `MC_W_A; // OPERATIONS WITH MEMORY READ/WRITE +memory[167] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`else +memory[164] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | // b = 8 (#2 in emulate table) + `MC_W_B; +memory[165] = `MC_EMULATE; // emulate #2 (mult opcode) +`endif + +// 001_01010 (2a) lshiftright ------------------------------------- +`ifdef ENABLE_BARREL +// b = mem[sp] & 5'b1111 : limit to 5 bits (max 31 shifts) +// b = b | 7'b01_00000 : shift right, logical +// sp=sp+1 +// a = mem[sp] +// a = a >> b +// mem[sp] = a +memory[168] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] & 5'b11111 + `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B; +memory[169] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR | // b = b | 7'b01_00000 (shift right, logical) + `MC_SEL_ALU_MC_CONST | (32 << `P_ADDR) | `MC_W_B; +memory[170] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[171] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] | goto @shift_cont + `MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR); +`else + `ifdef ENABLE_A_SHIFT +// a = mem[sp] & 5'b11111 +// sp=sp+1 +// b = FLIP(mem[sp]) +// label: a <= 0 ? goto @fin +// b = b << 1 +// a = a - 1 || goto @label +// fin: a = FLIP(b) +// mem[sp]=a +memory[168] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] & 5'b11111 + `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | + (31 << `P_ADDR) | `MC_W_A; +memory[169] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[170] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = FLIP(mem[sp]) + `MC_ALU_FLIP | `MC_W_B; +memory[171] = `MC_BRANCH | ((448 >> 2) << `P_ADDR); // goto @lshiftleft_loop + `else + memory[168] = `MC_GO_BREAKPOINT; + `endif +`endif + +// 001_01011 (2b) ashiftleft ------------------------------------- +`ifdef ENABLE_BARREL +// b = mem[sp] & 5'b11111 : 5 bit shift +// b = b | 7'b10_00000 : shift left, arithmetic +// sp=sp+1 +// a = mem[sp] +// a = a <<signed b +// mem[sp] = a +memory[172] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] & 5'b11111 + `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B; +memory[173] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR | // b = b | 7'b10_00000 (shift left, arithmetic) + `MC_SEL_ALU_MC_CONST | (64 << `P_ADDR) | `MC_W_B; +memory[174] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[175] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] | goto @shift_cont + `MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR); +`else +// a = mem[sp] & 5'b11111 +// sp = sp + 1 +// b = mem[sp] +// label: a <= 0 ? goto @fin +// b = b << 1 +// a = a - 1 || goto @label +// fin: a = b +// mem[sp] = a +memory[172] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] & 5'b11111 + `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | + (31 << `P_ADDR) | `MC_W_A; +memory[173] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[174] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp] + `MC_W_B; +memory[175] = `MC_BRANCH | ((440 >> 2) << `P_ADDR); // goto @ashiftleft_loop +`endif + +// 001_01100 (2c) ashiftright ------------------------------------- +`ifdef ENABLE_BARREL +// b = mem[sp] & 5'b11111 : 5 bit shift +// b = b | 7'b00_00000 : shift right, arithmetic +// sp=sp+1 +// a = mem[sp] +// a = a >>signed b +// mem[sp] = a +memory[176] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] & 5'b11111 + `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B; +memory[177] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[178] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] | goto @shift_cont + `MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR); +`else + `ifdef ENABLE_A_SHIFT +// a = mem[sp] & 5'b11111 +// sp = sp + 1 +// b = FLIP(mem[sp]) +// label: a <= 0 ? goto @fin +// b = b signed_<< 1 +// a = a - 1 || goto @label +// fin: a = FLIP(b) +// mem[sp] = a +memory[176] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] & 5'b11111 + `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | + (31 << `P_ADDR) | `MC_W_A; +memory[177] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[178] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = FLIP(mem[sp]) + `MC_ALU_FLIP | `MC_W_B; +memory[179] = `MC_BRANCH | ((432 >> 2) << `P_ADDR); // goto @ashiftright_loop + `else +memory[176] = `MC_GO_BREAKPOINT; + `endif +`endif + +// 001_01101 (2d) call ------------------------------------- +// a = mem[sp] +// mem[sp]=pc+1 +// pc = a +memory[180] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] + `MC_MEM_R | `MC_W_B; +memory[181] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | + `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; // a = pc + 1 +memory[182] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_ALU_NOP_B | // mem[sp] = a || pc = b + `MC_SEL_ALU_B | `MC_W_PC; +memory[183] = `MC_FETCH; // op_cached? decode : goto next + +// 001_01110 (2e) eq ------------------------------------- +// a = mem[sp] +// sp = sp + 1 +// (mem[sp] - a == 0) ? mem[sp] = 1 : mem[sp] = 0 +memory[184] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = NOT(mem[sp]) + `MC_SEL_READ_DATA | `MC_ALU_NOT | `MC_W_A; +memory[185] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS | // a = a + 1 + `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; +memory[186] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[187] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] + a || goto @eq_check + `MC_ALU_PLUS |`MC_SEL_ALU_A | `MC_W_A | + ( (416 >> 2) << `P_ADDR) | `MC_BRANCH; + +// 001_01111 (2f) neq ------------------------------------- +// a = mem[sp] +// sp = sp + 1 +// (mem[sp] - a != 0) ? mem[sp] = 1 : mem[sp] = 0 +memory[188] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = NOT(mem[sp]) + `MC_MEM_R | `MC_ALU_NOT | `MC_W_A; +memory[189] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS | // a = a + 1 + `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; +memory[190] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[191] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] + a || goto @neq_check + `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | + ( (412 >> 2) << `P_ADDR) | `MC_BRANCH; + +// 001_10000 (30) neg ------------------------------------- +// a = NOT(mem[sp]) +// a = a + 1 +// mem[sp] = a +memory[192] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = NOT(mem[sp]) + `MC_MEM_R | `MC_ALU_NOT | `MC_W_A; +memory[193] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + 1 + (1 << `P_ADDR) | `MC_SEL_ALU_MC_CONST | `MC_W_A; +memory[194] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 001_10001 (31) sub ------------------------------------- +// mem[sp+1] = mem[sp+1] - mem[sp] +// sp = sp + 1 +memory[196] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = NOT(mem[sp]) + `MC_MEM_R | `MC_ALU_NOT | `MC_W_A; +memory[197] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + 1 + `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; +memory[198] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[199] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] + a || goto @sub_cont (set_mem[sp]=a) + `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | ((400>>2) << `P_ADDR) | + `MC_BRANCH; + +// 001_10010 (32) xor ------------------------------------- +`ifdef ENABLE_XOR +// mem[sp+1] = mem[sp+1] ^ mem[sp] +// sp = sp + 1 +memory[200] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1 + `MC_W_A_MEM | `MC_SP_PLUS_4; +memory[201] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a ^ mem[sp] + `MC_ALU_XOR |`MC_SEL_ALU_A | `MC_W_A; +memory[202] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`else +// ALU doesn't perform XOR operation +// mem[sp+1] = mem[sp] ^ mem[sp+1] -> A^B=(A&~B)|(~A&B) +// a = ~mem[sp] --> a = ~A +// sp = sp + 1 +// a = mem[sp] & a --> a = ~A&B +// b = ~a --> b = A&~B +// a = a | b --> a = ~A&B | A&~B +// mem[sp] = a +memory[200] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = ~mem[sp] --> a=~A + `MC_ALU_NOT | `MC_W_A; +memory[201] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[202] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] & a --> a = ~A&B + `MC_ALU_AND | `MC_SEL_ALU_A | `MC_W_A; +memory[203] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_NOT | // b = ~a || goto @xor_cont --> b = A&~B + `MC_W_B | `MC_BRANCH | ((428 >> 2) << `P_ADDR); +`endif + +// 001_10011 (33) loadb ------------------------------------- +`ifdef ENABLE_BYTE_SELECT +// mem[sp] = BYTE(mem[sp], mem[mem[sp]]) +memory[204] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] + `MC_MEM_R | `MC_W_A; +memory[205] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | // a = byte(a, mem[a]) + `MC_W_A | `MC_BYTE; +memory[206] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`else +// b=pc +// pc = mem[sp] +// opcode_cache=mem[pc] +// a = opcode +// mem[sp]=a +// pc=b +// fetch +memory[204] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | // b = pc + `MC_W_B; +memory[205] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // pc = mem[sp] + `MC_W_PC; +memory[206] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R | // opcode_cache = mem[pc] + `MC_W_OPCODE; +memory[207] = `MC_SEL_ALU_OPCODE | `MC_ALU_NOP_B | `MC_W_A | // a = opcode -> byte(pc, mem[pc]) || goto @loadb_continued + `MC_BRANCH | ( (396 >> 2) << `P_ADDR); +`endif + +// 001_10100 (34) storeb ------------------------------------- +`ifdef ENABLE_BYTE_SELECT +// BYTE( mem[mem[sp]] <= mem[sp+1] ) +// sp = sp + 2 +memory[208] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] + `MC_MEM_R | `MC_W_B; +memory[209] = `MC_SP_PLUS_4; // sp = sp + 1 +memory[210] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a = mem[sp] || sp=sp+1 + `MC_SP_PLUS_4; +memory[211] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_BYTE | `MC_GO_NEXT; // BYTE(mem[b] = a) +`else +memory[208] = `MC_GO_BREAKPOINT; +`endif + +// 001_10101 (35) div ------------------------------------- +`ifdef ENABLE_DIV +// *** TODO: CHECK IF DIVIDE BY ZERO AND RAISE EXCEPTION *** +// mem[sp+1] = mem[sp+1] / mem[sp] +// sp = sp + 1 +memory[212] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1 + `MC_W_A_MEM | `MC_SP_PLUS_4; +memory[213] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp] + `MC_W_B; +memory[214] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = a / b DON'T COMBINE MULTICYCLE ALU + `MC_ALU_DIV | `MC_W_A; // OPERATIONS WITH MEMORY READ/WRITE +memory[215] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`else +memory[212] = `MC_GO_BREAKPOINT; +`endif + +// 001_10110 (36) mod ------------------------------------- +`ifdef ENABLE_DIV +// mem[sp+1] = mem[sp+1] % mem[sp] +// sp = sp + 1 +memory[216] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1 + `MC_W_A_MEM | `MC_SP_PLUS_4; +memory[217] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp] + `MC_W_B; +memory[218] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = a % b DON'T COMBINE MULTICYCLE ALU + `MC_ALU_MOD | `MC_W_A; // OPERATIONS WITH MEMORY READ/WRITE +memory[219] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`else +memory[216] = `MC_GO_BREAKPOINT; +`endif + +// 001_10111 (37) eqbranch ------------------------------------- +// a = sp + 1 +// a = mem[a] +// a = mem[sp] || a == 0 ? { pc = pc + a; sp = sp + 2 } +// else { sp = sp + 2, pc = pc + 1 } +memory[220] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + 1 + `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | + `MC_W_A; +memory[221] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A; // a = mem[a] +memory[222] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A | // a = mem[sp] || a == 0 ? goto 456 (sp=sp+2, pc=pc+a) + `MC_BRANCHIF_A_ZERO | ((456>>2) << `P_ADDR); +memory[223] = `MC_BRANCH | ((460>>2) << `P_ADDR); // else goto 460 (sp=sp+2, pc=pc+1) + +// 001_11000 (38) neqbranch ------------------------------------- +// a = sp + 1 +// a = mem[a] +// a = mem[sp] || a == 0 ? { sp = sp + 2, pc = pc + 1 } +// else { sp = sp + 2, pc = pc + a } +memory[224] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + 1 + `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | + `MC_W_A; +memory[225] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A; // a = mem[a] +memory[226] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A | // a = mem[sp] || a == 0 ? goto 460 (sp=sp+2, pc=pc+1) + `MC_BRANCHIF_A_ZERO | ((460>>2) << `P_ADDR); +memory[227] = `MC_BRANCH | ((456>>2) << `P_ADDR); // else goto 456 (sp=sp+2, pc=pc+a) + +// 001_11001 (39) poppcrel ------------------------------------- +// a = mem[sp] +// sp = sp + 1 +// pc = pc + a +memory[228] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a=mem[sp] || sp=sp+1 + `MC_W_A_MEM | `MC_SP_PLUS_4; +memory[229] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // pc = pc + a + `MC_ALU_PLUS | `MC_W_PC; +memory[230] = `MC_FETCH; // op_cached? decode : goto next + +// 001_11010 (3a) config ------------------------------------- +memory[232] = `MC_GO_BREAKPOINT; + +// 001_11011 (3b) pushpc ------------------------------------- +// sp = sp - 1 +// mem[sp] = pc +memory[236] = `MC_CLEAR_IDIM | `MC_SP_MINUS_4 | `MC_W_A; // a = sp = sp - 1 +memory[237] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 001_11100 (3c) syscall_emulate ------------------------------ +memory[240] = `MC_GO_BREAKPOINT; + +// 001_11101 (3d) pushspadd ------------------------------------- +// a = mem[sp] << 2 +// mem[sp] = a + sp +`ifdef ENABLE_BARREL +memory[244] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] + `MC_W_A_MEM; +memory[245] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL | // a = a << 2 (left,arithmetic->10_00010) + `MC_SEL_ALU_MC_CONST | ( 66 << `P_ADDR) | `MC_W_A; +memory[246] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + sp + `MC_ALU_PLUS | `MC_W_A; +memory[247] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`else +memory[244] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM; // a = mem[sp] +memory[245] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + a + `MC_ALU_PLUS | `MC_W_A; +memory[246] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + a + `MC_ALU_PLUS | `MC_W_A; +memory[247] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + sp || goto @cont (->mem[sp] = a) + `MC_ALU_PLUS | `MC_W_A | ((400>>2) << `P_ADDR) | `MC_BRANCH; +`endif + +// 001_11110 (3e) halfmult ------------------------------------- +memory[248] = `MC_GO_BREAKPOINT; + +// 001_11111 (3f) callpcrel ------------------------------------- +// a = mem[sp] +// mem[sp]=pc+1 +// pc = pc + a +memory[252] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] + `MC_MEM_R | `MC_W_B; +memory[253] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = pc + 1 + `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; +memory[254] = `MC_SEL_ADDR_SP | `MC_MEM_W; // mem[sp] = a; +memory[255] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // pc = pc + b, goto @fetch + `MC_ALU_PLUS | `MC_W_PC | `MC_GO_FETCH; + +// --------------------- MICROCODE HOLE ----------------------------------- + + + + +// --------------------- CONTINUATION OF COMPLEX OPCODES ------------------ + +`ifdef ENABLE_BYTE_SELECT +// ipsum_end: ---------- +memory[392] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | // sp=0 + `MC_W_SP; +memory[393] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // pc=mem[sp] restore next pc + `MC_W_PC; +memory[394] = `MC_SP_PLUS_4; // sp=sp+4 +memory[395] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // sp=mem[sp] restore sp + `MC_W_SP; +memory[396] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (sum) +memory[397] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_FETCH; // mem[sp]=a || fetch (return sum) +`endif + +`ifndef ENABLE_BYTE_SELECT +// loadb continued microcode ----- +// mem[sp]=a || pc=b +// opcode_cache=mem[pc] || go next +memory[396] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SEL_ALU_B | // mem[sp]=a || pc=b + `MC_ALU_NOP_B | `MC_W_PC; +memory[397] = `MC_SEL_ADDR_PC | `MC_MEM_R | `MC_W_OPCODE | `MC_GO_NEXT; // opcode_cache=mem[pc] || go next +`endif + +// sub/pushspadd continued microcode ---------------- +memory[400] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// ----- hole ------ + +`ifdef ENABLE_BYTE_SELECT +// ipsum_continue2: ------------ +memory[408] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // pc=pc-1; a=pc + `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_PC | + `MC_W_A; +memory[409] = `MC_BRANCH | ((124 >> 2) << `P_ADDR); // goto @ipsum_loop +`endif + +// neqcheck ---------- +memory[412] = `MC_BRANCHIF_A_ZERO | ((468 >> 2) << `P_ADDR); // a == 0 ? goto @set_mem[sp]=0 +memory[413] = `MC_BRANCH | ((464 >> 2) << `P_ADDR); // else goto @set_mem[sp]=1 + +// eqcheck ---------- +memory[416] = `MC_BRANCHIF_A_ZERO | ((464 >> 2) << `P_ADDR); // a == 0 ? goto @set_mem[sp]=1 +memory[417] = `MC_BRANCH | ((468 >> 2) << `P_ADDR); // else goto @set_mem[sp]=0 + +// lessthanorequal_check ---- +memory[420] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR); // a <= 0 ? goto @set_mem[sp]=1 +memory[421] = `MC_BRANCH | ((468 >> 2) << `P_ADDR); // else goto @set_mem[sp]=0 + +// lessthan_check ---- +memory[424] = `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR); // a < 0 ? goto @set_mem[sp]=1 +memory[425] = `MC_BRANCH | ((468 >> 2) << `P_ADDR); // else goto @set_mem[sp]=0 + +// xor_cont continued microcode ----------------------------------- +`ifndef ENABLE_XOR +memory[428] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_OR | // a = a | b --> a = ~A&B | A&~B + `MC_SEL_ALU_B | `MC_W_A; +memory[429] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`endif + +// ashiftright_loop continued microcode ----------------------------------- +`ifdef ENABLE_BARREL +memory[432] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL | // a = a {<<|>>} b + `MC_SEL_ALU_B | `MC_W_A; +memory[433] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`else + `ifdef ENABLE_A_SHIFT +memory[432] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((436 >> 2) << `P_ADDR); // (a <= 0) ? goto @ashiftright_exit +memory[433] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + (-1) + `MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A; +memory[434] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b = b signed_<< 1 || goto @ashiftright_loop + `MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((432 >>2) << `P_ADDR); +// ashiftright_exit +memory[436] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP | // a = FLIP(b) + `MC_W_A; +memory[437] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + `endif +`endif + +// ashiftleft_loop continued microcode ----------------------------------- +`ifndef ENABLE_BARREL +memory[440] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((444 >> 2) << `P_ADDR);// (a <= 0) ? goto @ashiftleft_exit +memory[441] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + (-1) + `MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A; +memory[442] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b = b << 1 || goto @ashiftleft_loop + `MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((440 >>2) << `P_ADDR); +// ashiftleft_exit +memory[444] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_NOP | // a = b + `MC_W_A; +memory[445] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`endif + +// lshiftright_loop continued microcode ----------------------------------- +`ifdef ENABLE_A_SHIFT +memory[448] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((452 >> 2) << `P_ADDR);// (a <= 0) ? goto @lshiftright_exit +memory[449] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + (-1) + `MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A; +memory[450] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b = b << 1 || goto @lshiftright_loop + `MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((448 >>2) << `P_ADDR); +// lshiftright_exit +memory[452] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP | // a = FLIP(b) + `MC_W_A; +memory[453] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a +`endif + +// neqbranch / eqbranch --- continued microcode ------------------------------------- +// sp = sp + 2 +// pc = pc + a +memory[456] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // sp = sp + 2 + `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP; +memory[457] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // pc = pc + a + `MC_ALU_PLUS | `MC_W_PC; +memory[458] = `MC_FETCH; // op_cached? decode : goto fetch + +// neqbranch / eqbranch --- continued microcode ------------------------------------- +// sp = sp + 2 +// pc = pc + 1 +memory[460] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // sp = sp + 2 + `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP; +memory[461] = `MC_PC_PLUS_1; // pc = pc + 1 +memory[462] = `MC_FETCH; // op_cached? decode : goto fetch + +// neq / eq / lessthan_1 --- continued microcode -------------------- +// mem[sp] = 1 +memory[464] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (1 << `P_ADDR) | // a = 1 + `MC_W_A; +memory[465] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// neq / eq / lessthan_0 --- continued microcode -------------------- +// mem[sp] = 0 +memory[468] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (0 << `P_ADDR) | // a = 0 + `MC_W_A; +memory[469] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// MICROCODE ENTRY POINT AFTER RESET ------------------------------- +// initialize cpu registers +// sp = @SP_START +// pc = @RESET_VECTOR +memory[473] = 0; // reserved and empty for correct cpu startup +memory[474] = `MC_CLEAR_IDIM |`MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | // sp = @SP_START + (`SP_START << `P_ADDR) | `MC_W_SP; +memory[475] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | `MC_W_PC | // pc = @RESET + (`RESET_VECTOR << `P_ADDR) | `MC_EXIT_INTERRUPT; // enable interrupts on reset +// fall throught fetch/decode + +// FETCH / DECODE ------------------------------------- +// opcode=mem[pc] +// decode (goto microcode entry point for opcode) +memory[476] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R | // opcode_cache = mem[pc] + `MC_W_OPCODE; +memory[477] = `MC_DECODE; // decode jump to microcode + +// NEXT OPCODE ------------------------------------- +// pc = pc + 1 +// opcode cached ? decode : goto fetch +memory[480] = `MC_PC_PLUS_1; // pc = pc + 1 +memory[481] = `MC_FETCH; // pc_cached ? decode else fetch,decode + +// INTERRUPT REQUEST ------------------------------------- +// sp = sp - 1 +// mem[sp] = pc +// pc = mem[EMULATED_VECTORS + 0] +memory[484] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | // b = 0 (#0 in emulate table) || disable interrupts + `MC_W_B | `MC_ENTER_INTERRUPT; +memory[485] = `MC_EMULATE; // emulate #0 (interrupt) + +// ---------------- OPCODES WITH PARAMETER IN OPCODE ---------------- + +// im x (idim=0) 1_xxxxxxx ------------------------------------- +// sp = sp - 1 +// mem[sp] = IMM(IDIM, opcode) +// idim = 1 +memory[488] = `MC_SP_MINUS_4; // sp = sp - 1 +memory[489] = `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A; // a = IMM(IDIM, opcode) +memory[490] = `MC_SET_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_W | // MEM[sp] = a; IDIM=1 + `MC_GO_NEXT; + +// 1_xxxxxxx im x (idim=1) ------------------------------------- +// mem[sp] = IMM(IDIM, mem[sp], opcode) +memory[491] = `MC_SET_IDIM | `MC_SEL_READ_DATA | `MC_SEL_ADDR_SP | // a = IMM(IDIM, MEM[sp], opcode) + `MC_MEM_R | `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A; +memory[492] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // MEM[sp] = a + +// 010_xxxxx storesp x +// mem[sp + x<<2] = mem[sp] +// sp = sp + 1 +memory[493] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // b = sp + offset + `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_B; +memory[494] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1 + `MC_SP_PLUS_4; +memory[495] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT; // mem[b] = a + +// 011_xxxxx loadsp x ------------------------------------- +// mem[sp-1] = mem [sp + x<<2] +// sp = sp - 1 +memory[496] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + offset + `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A; +memory[497] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a] +memory[498] = `MC_SP_MINUS_4; // sp = sp - 1 +memory[499] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 0001_xxxx addsp x ------------------------------------- +// mem[sp] = mem[sp] + mem[sp + x<<2] +memory[500] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + offset + `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A; +memory[501] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a] +memory[502] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | + `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A; // a = a + mem[sp] +memory[503] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a + +// 001_xxxxx emulate x ------------------------------------- +// <expects b = offset into table for emulated opcode> +// sp = sp - 1 +// mem[sp] = pc + 1 emulated opcode microcode must set b to +// a=@EMULATION_TABLE offset inside emulated_table prior to +// pc = mem[a + b] calling the emulate microcode +// fetch +memory[504] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | // a = pc + 1 + `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; +memory[505] = `MC_SP_MINUS_4; // sp = sp - 1 +memory[506] = `MC_SEL_ADDR_SP | `MC_MEM_W; // mem[sp] = a +memory[507] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | `MC_W_A | // a = @vector_emulated + (`EMULATION_VECTOR << `P_ADDR); +memory[508] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + b + `MC_SEL_ALU_B | `MC_W_A; +memory[509] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | // pc = mem[a] + `MC_ALU_NOP | `MC_W_PC; +memory[510] = `MC_FETCH; + +// --------------------- END OF MICROCODE PROGRAM -------------------------- +end + +endmodule diff --git a/zpu/hdl/avalanche/readme.txt b/zpu/hdl/avalanche/readme.txt new file mode 100644 index 0000000..3eb1baf --- /dev/null +++ b/zpu/hdl/avalanche/readme.txt @@ -0,0 +1,91 @@ +This ZPU implementation, codenamed "avalanche" was +contributed by Antonio Anton <antonio.anton@anro-ingenieros.com>. + +It's most interesting aspects are it's implementation using +microcode, small size, reduced code size overhead and that +it's implemented in Verilog. + +Please direct any questions to the zylin-zpu mailing list. + +The most urgently needed patches would be to provide working +simulation examples and improved documentation. + + +Ãyvind Harboe + + +Notes from Antonio: + +Hi, + +attached goes my zpu implementation in verilog in case anybody is +interested in. Code is quite commented. Also microcode and opcodes are +exhaustive commented (and more accurate that the HTML documentation in +some cases :-) ). + +At the moment I have no time to send a working environment but I will +get some time in next days and prepare a clean environment +(software/hardware) and send to the list. The target HW is spartan3 +starter kit board (all peripherals working: vga, sram, uarts, etc.). + +Feel free to ask any question to the list I will do my best to answer +quickly. + +Regards +Antonio + +Hi, + +the zpu_core is complete and lot of bugs has been solved in the past but +extensive testing and a complete test program has not been +defined/executed; anyway I'm quite confident it works: this core +executes eCos, FreeRTOS, Forth and other applications. + +Regarding FPGA resources for a "balanced" implementation (not the +smallest, not the fastest): + +-cpu+alu+microcode rom: 671 LUT + 239 FF + 1 BRAM (50% of LUT is ALU) +-complete soc (cpu, vga, uart, memory controller, interrupt controller, +timers, gpio, spi, etc.): 1317 LUT + 716 FF + 1 BRAM + +Regarding "modelsim hello world"; I'm sorry but I don't modelsim; +instead I use Icarus Verilog & gtkwave. The core has a "debug" facility +which displays all opcode and registers (memory changes, sp, pc, etc..) +during simulation execution. + +Regards +Antonio + + +> > Regarding FPGA resources for a "balanced" implementation (not the +> > smallest, not the fastest): +> > +> > -cpu+alu+microcode rom: 671 LUT + 239 FF + 1 BRAM (50% of LUT is ALU) +> +> Are there any emulated instructions not implemented in +> microcode? +> + +*All* zpu opcodes are microcoded. For some opcodes (like *shift*), +there are two versions; 32 bit barrel shift in HDL (up to 32 clocks) or +1 bit shift in HDL microcode drived (up to ~130 clocks). They are +selectable via `DEFINES in the zpu_core_defines.v + +Other opcodes like mult and div are 32 bit HDL only at the moment (there +are enough room in microcode memory to implement as microcode) and +software emulable as well. + +For the above figures (671 LUT + 239 FF): *shift* are 32 bit HDL and +mult/div are software implemented. + +There are new opcodes (as per my needs) like memory bulk copy (sncpy, +wcpy, wset) and ip checksum calculation (ipsum). There are room in +microccode memory to define new opcodes using the holes in the ISA (for +a complete list of opcodes and its function please see +zpu_core_defines.v). + +Some future ideas (easy to implement in microcode) +-on-chip debug +-microcode update via software + +Regards diff --git a/zpu/hdl/example/.cvsignore b/zpu/hdl/example/.cvsignore new file mode 100644 index 0000000..8238018 --- /dev/null +++ b/zpu/hdl/example/.cvsignore @@ -0,0 +1,3 @@ +work +vsim.wlf +install diff --git a/zpu/hdl/example/bram_dmips.vhd b/zpu/hdl/example/bram_dmips.vhd new file mode 100644 index 0000000..07b19f4 --- /dev/null +++ b/zpu/hdl/example/bram_dmips.vhd @@ -0,0 +1,3356 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80d5f40c", + 3 => x"3a0b0b80", + 4 => x"c4fb0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80c5c22d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c3040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a6", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80d5", + 162 => x"e0738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88a90400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b0bad", + 171 => x"aa2d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"80088408", + 177 => x"88087575", + 178 => x"0b0b0bad", + 179 => x"ee2d5050", + 180 => x"80085688", + 181 => x"0c840c80", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"810b0b0b", + 209 => x"80d5f00c", + 210 => x"51040000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"00000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"82fd3fbf", + 257 => x"a03f0410", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10105351", + 266 => x"047381ff", + 267 => x"06738306", + 268 => x"09810583", + 269 => x"05101010", + 270 => x"2b0772fc", + 271 => x"060c5151", + 272 => x"043c0472", + 273 => x"72807281", + 274 => x"06ff0509", + 275 => x"72060571", + 276 => x"1052720a", + 277 => x"100a5372", + 278 => x"ed385151", + 279 => x"535104ff", + 280 => x"3d0d0b0b", + 281 => x"80e5e408", + 282 => x"52710870", + 283 => x"882a8132", + 284 => x"70810651", + 285 => x"515170f1", + 286 => x"3873720c", + 287 => x"833d0d04", + 288 => x"80d5f008", + 289 => x"802ea438", + 290 => x"80d5f408", + 291 => x"822ebd38", + 292 => x"8380800b", + 293 => x"0b0b80e5", + 294 => x"e40c82a0", + 295 => x"800b80e5", + 296 => x"e80c8290", + 297 => x"800b80e5", + 298 => x"ec0c04f8", + 299 => x"808080a4", + 300 => x"0b0b0b80", + 301 => x"e5e40cf8", + 302 => x"80808280", + 303 => x"0b80e5e8", + 304 => x"0cf88080", + 305 => x"84800b80", + 306 => x"e5ec0c04", + 307 => x"80c0a880", + 308 => x"8c0b0b0b", + 309 => x"80e5e40c", + 310 => x"80c0a880", + 311 => x"940b80e5", + 312 => x"e80c0b0b", + 313 => x"80c7d00b", + 314 => x"80e5ec0c", + 315 => x"04f23d0d", + 316 => x"6080e5e8", + 317 => x"08565d82", + 318 => x"750c8059", + 319 => x"805a800b", + 320 => x"8f3d5d5b", + 321 => x"7a101015", + 322 => x"70087108", + 323 => x"719f2c7e", + 324 => x"852b5855", + 325 => x"557d5359", + 326 => x"5799993f", + 327 => x"7d7f7a72", + 328 => x"077c7207", + 329 => x"71716081", + 330 => x"05415f5d", + 331 => x"5b595755", + 332 => x"817b278f", + 333 => x"38767d0c", + 334 => x"77841e0c", + 335 => x"7c800c90", + 336 => x"3d0d0480", + 337 => x"e5e80855", + 338 => x"ffba3970", + 339 => x"7080e5f0", + 340 => x"335170a7", + 341 => x"3880d5fc", + 342 => x"08700852", + 343 => x"5270802e", + 344 => x"94388412", + 345 => x"80d5fc0c", + 346 => x"702d80d5", + 347 => x"fc087008", + 348 => x"525270ee", + 349 => x"38810b80", + 350 => x"e5f03450", + 351 => x"50040470", + 352 => x"0b0b80e5", + 353 => x"e008802e", + 354 => x"8e380b0b", + 355 => x"0b0b800b", + 356 => x"802e0981", + 357 => x"06833850", + 358 => x"040b0b80", + 359 => x"e5e0510b", + 360 => x"0b0bf4dc", + 361 => x"3f500404", + 362 => x"ff3d0d02", + 363 => x"8f053352", + 364 => x"718a2e8a", + 365 => x"387151fd", + 366 => x"a63f833d", + 367 => x"0d048d51", + 368 => x"fd9d3f71", + 369 => x"51fd983f", + 370 => x"833d0d04", + 371 => x"ce3d0db5", + 372 => x"3d707084", + 373 => x"0552088b", + 374 => x"a85c56a5", + 375 => x"3d5e5c80", + 376 => x"75708105", + 377 => x"5733765b", + 378 => x"55587378", + 379 => x"2e80c138", + 380 => x"8e3d5b73", + 381 => x"a52e0981", + 382 => x"0680c538", + 383 => x"78708105", + 384 => x"5a335473", + 385 => x"80e42e81", + 386 => x"b6387380", + 387 => x"e42480c6", + 388 => x"387380e3", + 389 => x"2ea13880", + 390 => x"52a55179", + 391 => x"2d805273", + 392 => x"51792d82", + 393 => x"18587870", + 394 => x"81055a33", + 395 => x"5473c438", + 396 => x"77800cb4", + 397 => x"3d0d047b", + 398 => x"841d8312", + 399 => x"33565d57", + 400 => x"80527351", + 401 => x"792d8118", + 402 => x"79708105", + 403 => x"5b335558", + 404 => x"73ffa038", + 405 => x"db397380", + 406 => x"f32e0981", + 407 => x"06ffb838", + 408 => x"7b841d71", + 409 => x"08595d56", + 410 => x"80773355", + 411 => x"5673762e", + 412 => x"8d388116", + 413 => x"70187033", + 414 => x"57555674", + 415 => x"f538ff16", + 416 => x"55807625", + 417 => x"ffa03876", + 418 => x"70810558", + 419 => x"33548052", + 420 => x"7351792d", + 421 => x"811875ff", + 422 => x"17575758", + 423 => x"807625ff", + 424 => x"85387670", + 425 => x"81055833", + 426 => x"54805273", + 427 => x"51792d81", + 428 => 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x"00002e04", + 2949 => x"00002e0c", + 2950 => x"00002e0c", + 2951 => x"00002e14", + 2952 => x"00002e14", + 2953 => x"00002e1c", + 2954 => x"00002e1c", + 2955 => x"00002e24", + 2956 => x"00002e24", + 2957 => x"00002e2c", + 2958 => x"00002e2c", + 2959 => x"00002e34", + 2960 => x"00002e34", + 2961 => x"00002e3c", + 2962 => x"00002e3c", + 2963 => x"00002e44", + 2964 => x"00002e44", + 2965 => x"00002e4c", + 2966 => x"00002e4c", + 2967 => x"00002e54", + 2968 => x"00002e54", + 2969 => x"00002e5c", + 2970 => x"00002e5c", + 2971 => x"00002e64", + 2972 => x"00002e64", + 2973 => x"00002e6c", + 2974 => x"00002e6c", + 2975 => x"00002e74", + 2976 => x"00002e74", + 2977 => x"00002e7c", + 2978 => x"00002e7c", + 2979 => x"00002e84", + 2980 => x"00002e84", + 2981 => x"00002e8c", + 2982 => x"00002e8c", + 2983 => x"00002e94", + 2984 => x"00002e94", + 2985 => x"00002e9c", + 2986 => x"00002e9c", + 2987 => x"00002ea4", + 2988 => x"00002ea4", + 2989 => x"00002eac", + 2990 => x"00002eac", + 2991 => x"00002eb4", + 2992 => x"00002eb4", + 2993 => x"00002ebc", + 2994 => x"00002ebc", + 2995 => x"00002ec4", + 2996 => x"00002ec4", + 2997 => x"00002ecc", + 2998 => x"00002ecc", + 2999 => x"00002ed4", + 3000 => x"00002ed4", + 3001 => x"00002edc", + 3002 => x"00002edc", + 3003 => x"00002ee4", + 3004 => x"00002ee4", + 3005 => x"00002eec", + 3006 => x"00002eec", + 3007 => x"00002ef4", + 3008 => x"00002ef4", + 3009 => x"00002efc", + 3010 => x"00002efc", + 3011 => x"00002f04", + 3012 => x"00002f04", + 3013 => x"00002f0c", + 3014 => x"00002f0c", + 3015 => x"00002f14", + 3016 => x"00002f14", + 3017 => x"00002f1c", + 3018 => x"00002f1c", + 3019 => x"00002f24", + 3020 => x"00002f24", + 3021 => x"00002f2c", + 3022 => x"00002f2c", + 3023 => x"00002f34", + 3024 => x"00002f34", + 3025 => x"00002f3c", + 3026 => x"00002f3c", + 3027 => x"00002f50", + 3028 => x"00000000", + 3029 => x"000031b8", + 3030 => x"00003214", + 3031 => x"00003270", + 3032 => x"00000000", + 3033 => x"00000000", + 3034 => x"00000000", + 3035 => x"00000000", + 3036 => x"00000000", + 3037 => x"00000000", + 3038 => x"00000000", + 3039 => x"00000000", + 3040 => x"00000000", + 3041 => x"00002ad0", + 3042 => x"00000000", + 3043 => x"00000000", + 3044 => x"00000000", + 3045 => x"00000000", + 3046 => x"00000000", + 3047 => x"00000000", + 3048 => x"00000000", + 3049 => x"00000000", + 3050 => x"00000000", + 3051 => x"00000000", + 3052 => x"00000000", + 3053 => x"00000000", + 3054 => x"00000000", + 3055 => x"00000000", + 3056 => x"00000000", + 3057 => x"00000000", + 3058 => x"00000000", + 3059 => x"00000000", + 3060 => x"00000000", + 3061 => x"00000000", + 3062 => x"00000000", + 3063 => x"00000000", + 3064 => x"00000000", + 3065 => x"00000000", + 3066 => x"00000000", + 3067 => x"00000000", + 3068 => x"00000000", + 3069 => x"00000000", + 3070 => x"00000001", + 3071 => x"330eabcd", + 3072 => x"1234e66d", + 3073 => x"deec0005", + 3074 => x"000b0000", + 3075 => x"00000000", + 3076 => x"00000000", + 3077 => x"00000000", + 3078 => x"00000000", + 3079 => x"00000000", + 3080 => x"00000000", + 3081 => x"00000000", + 3082 => x"00000000", + 3083 => x"00000000", + 3084 => x"00000000", + 3085 => x"00000000", + 3086 => x"00000000", + 3087 => x"00000000", + 3088 => x"00000000", + 3089 => x"00000000", + 3090 => x"00000000", + 3091 => x"00000000", + 3092 => x"00000000", + 3093 => x"00000000", + 3094 => x"00000000", + 3095 => x"00000000", + 3096 => x"00000000", + 3097 => x"00000000", + 3098 => x"00000000", + 3099 => x"00000000", + 3100 => x"00000000", + 3101 => x"00000000", + 3102 => x"00000000", + 3103 => x"00000000", + 3104 => x"00000000", + 3105 => x"00000000", + 3106 => x"00000000", + 3107 => x"00000000", + 3108 => x"00000000", + 3109 => x"00000000", + 3110 => x"00000000", + 3111 => x"00000000", + 3112 => x"00000000", + 3113 => x"00000000", + 3114 => x"00000000", + 3115 => x"00000000", + 3116 => x"00000000", + 3117 => x"00000000", + 3118 => x"00000000", + 3119 => x"00000000", + 3120 => x"00000000", + 3121 => x"00000000", + 3122 => x"00000000", + 3123 => x"00000000", + 3124 => x"00000000", + 3125 => x"00000000", + 3126 => x"00000000", + 3127 => x"00000000", + 3128 => x"00000000", + 3129 => x"00000000", + 3130 => x"00000000", + 3131 => x"00000000", + 3132 => x"00000000", + 3133 => x"00000000", + 3134 => x"00000000", + 3135 => x"00000000", + 3136 => x"00000000", + 3137 => x"00000000", + 3138 => x"00000000", + 3139 => x"00000000", + 3140 => x"00000000", + 3141 => x"00000000", + 3142 => x"00000000", + 3143 => x"00000000", + 3144 => x"00000000", + 3145 => x"00000000", + 3146 => x"00000000", + 3147 => x"00000000", + 3148 => x"00000000", + 3149 => x"00000000", + 3150 => x"00000000", + 3151 => x"00000000", + 3152 => x"00000000", + 3153 => x"00000000", + 3154 => x"00000000", + 3155 => x"00000000", + 3156 => x"00000000", + 3157 => x"00000000", + 3158 => x"00000000", + 3159 => x"00000000", + 3160 => x"00000000", + 3161 => x"00000000", + 3162 => x"00000000", + 3163 => x"00000000", + 3164 => x"00000000", + 3165 => x"00000000", + 3166 => x"00000000", + 3167 => x"00000000", + 3168 => x"00000000", + 3169 => x"00000000", + 3170 => x"00000000", + 3171 => x"00000000", + 3172 => x"00000000", + 3173 => x"00000000", + 3174 => x"00000000", + 3175 => x"00000000", + 3176 => x"00000000", + 3177 => x"00000000", + 3178 => x"00000000", + 3179 => x"00000000", + 3180 => x"00000000", + 3181 => x"00000000", + 3182 => x"00000000", + 3183 => x"00000000", + 3184 => x"00000000", + 3185 => x"00000000", + 3186 => x"00000000", + 3187 => x"00000000", + 3188 => x"00000000", + 3189 => x"00000000", + 3190 => x"00000000", + 3191 => x"00000000", + 3192 => x"00000000", + 3193 => x"00000000", + 3194 => x"00000000", + 3195 => x"00000000", + 3196 => x"00000000", + 3197 => x"00000000", + 3198 => x"00000000", + 3199 => x"00000000", + 3200 => x"00000000", + 3201 => x"00000000", + 3202 => x"00000000", + 3203 => x"00000000", + 3204 => x"00000000", + 3205 => x"00000000", + 3206 => x"00000000", + 3207 => x"00000000", + 3208 => x"00000000", + 3209 => x"00000000", + 3210 => x"00000000", + 3211 => x"00000000", + 3212 => x"00000000", + 3213 => x"00000000", + 3214 => x"00000000", + 3215 => x"00000000", + 3216 => x"00000000", + 3217 => x"00000000", + 3218 => x"00000000", + 3219 => x"00000000", + 3220 => x"00000000", + 3221 => x"00000000", + 3222 => x"00000000", + 3223 => x"00000000", + 3224 => x"00000000", + 3225 => x"00000000", + 3226 => x"00000000", + 3227 => x"00000000", + 3228 => x"00000000", + 3229 => x"00000000", + 3230 => x"00000000", + 3231 => x"00000000", + 3232 => x"00000000", + 3233 => x"00000000", + 3234 => x"00000000", + 3235 => x"00000000", + 3236 => x"00000000", + 3237 => x"00000000", + 3238 => x"00000000", + 3239 => x"00000000", + 3240 => x"00000000", + 3241 => x"00000000", + 3242 => x"00000000", + 3243 => x"00000000", + 3244 => x"00000000", + 3245 => x"00000000", + 3246 => x"00000000", + 3247 => x"00000000", + 3248 => x"00000000", + 3249 => x"00000000", + 3250 => x"00000000", + 3251 => x"00002ad4", + 3252 => x"ffffffff", + 3253 => x"00000000", + 3254 => x"ffffffff", + 3255 => x"00000000", + 3256 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr))); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd new file mode 100644 index 0000000..cc8d8c6 --- /dev/null +++ b/zpu/hdl/example/helloworld.vhd @@ -0,0 +1,3154 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfd80c", +3 => x"3a0b0b80", +4 => x"c6d00400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c7972d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80cf", +162 => x"c4738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8b", +171 => x"9f2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8b", +179 => x"e32d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80cfd40c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82c53f80", +257 => x"c6d93f04", +258 => x"10101010", +259 => x"10101010", +260 => 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x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"000027b8", +3051 => x"ffffffff", +3052 => x"00000000", +3053 => x"ffffffff", +3054 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr))); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/example/interrupt.vhd b/zpu/hdl/example/interrupt.vhd new file mode 100644 index 0000000..d2bc709 --- /dev/null +++ b/zpu/hdl/example/interrupt.vhd @@ -0,0 +1,3156 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfe00c", +3 => x"3a0b0b80", +4 => x"c6e00400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0b8af02d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80cf", +162 => x"cc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8b", +171 => x"ab2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8b", +179 => x"ef2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80cfdc0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82c53f80", +257 => x"c6e63f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51047381", +267 => x"ff067383", +268 => x"06098105", +269 => x"83051010", +270 => x"102b0772", +271 => x"fc060c51", +272 => x"51043c04", +273 => x"72728072", +274 => x"8106ff05", +275 => x"09720605", +276 => x"71105272", +277 => x"0a100a53", +278 => x"72ed3851", +279 => x"51535104", +280 => x"fe3d0d0b", +281 => x"0b80dfc8", +282 => x"08538413", +283 => x"0870882a", +284 => x"70810651", +285 => x"52527080", +286 => x"2ef03871", +287 => x"81ff0680", +288 => x"0c843d0d", +289 => x"04ff3d0d", +290 => x"0b0b80df", +291 => x"c8085271", +292 => x"0870882a", +293 => x"81327081", +294 => x"06515151", +295 => x"70f13873", +296 => x"720c833d", +297 => x"0d0480cf", +298 => x"dc08802e", +299 => x"a43880cf", +300 => x"e008822e", +301 => x"bd388380", +302 => x"800b0b0b", +303 => x"80dfc80c", +304 => x"82a0800b", +305 => x"80dfcc0c", +306 => x"8290800b", +307 => x"80dfd00c", +308 => x"04f88080", +309 => x"80a40b0b", +310 => x"0b80dfc8", +311 => x"0cf88080", +312 => x"82800b80", +313 => x"dfcc0cf8", +314 => x"80808480", +315 => x"0b80dfd0", +316 => x"0c0480c0", +317 => x"a8808c0b", +318 => x"0b0b80df", +319 => x"c80c80c0", +320 => x"a880940b", +321 => x"80dfcc0c", +322 => x"0b0b80cf", +323 => x"980b80df", +324 => x"d00c0470", +325 => x"7080dfd4", +326 => x"335170a7", +327 => x"3880cfe8", +328 => x"08700852", +329 => x"5270802e", +330 => x"94388412", +331 => x"80cfe80c", +332 => x"702d80cf", +333 => x"e8087008", +334 => x"525270ee", +335 => x"38810b80", +336 => x"dfd43450", +337 => x"50040470", +338 => x"0b0b80df", +339 => x"c408802e", +340 => x"8e380b0b", +341 => x"0b0b800b", +342 => x"802e0981", +343 => x"06833850", +344 => x"040b0b80", +345 => x"dfc4510b", +346 => x"0b0bf594", +347 => x"3f500404", +348 => x"803d0d80", +349 => x"dfe00881", +350 => x"1180dfe0", +351 => x"0c51823d", +352 => x"0d04fe3d", +353 => x"0d80dfe0", +354 => x"085380df", +355 => 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x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"000027c0", +3053 => x"ffffffff", +3054 => x"00000000", +3055 => x"ffffffff", +3056 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr))); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/example/log.txt b/zpu/hdl/example/log.txt new file mode 100644 index 0000000..6ee1d94 --- /dev/null +++ b/zpu/hdl/example/log.txt @@ -0,0 +1,20 @@ +Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd new file mode 100644 index 0000000..909ea21 --- /dev/null +++ b/zpu/hdl/example/sim_small_fpga_top.vhd @@ -0,0 +1,197 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity fpga_top is +end fpga_top; + + +architecture behave of fpga_top is + + + signal clk : std_logic; + + signal areset : std_logic := '1'; + + + component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port ( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); + end component; + + + signal mem_busy : std_logic; + signal mem_read : std_logic_vector(wordSize-1 downto 0); + signal mem_write : std_logic_vector(wordSize-1 downto 0); + signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); + signal mem_writeEnable : std_logic; + signal mem_readEnable : std_logic; + signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + + signal enable : std_logic; + + signal dram_mem_busy : std_logic; + signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_writeEnable : std_logic; + signal dram_mem_readEnable : std_logic; + signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + + signal io_busy : std_logic; + + signal io_mem_read : std_logic_vector(wordSize-1 downto 0); + signal io_mem_writeEnable : std_logic; + signal io_mem_readEnable : std_logic; + + signal dram_ready : std_logic; + signal io_ready : std_logic; + signal io_reading : std_logic; + signal interruptcounter : unsigned(15 downto 0); + signal interrupt : std_logic; + + signal break : std_logic; + +begin + + zpu: zpu_core + port map ( + clk => clk, + reset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => interrupt, + break => break + ); + + + ioMap: zpu_io + port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + + interruptcounter <= to_unsigned(0, 16); + interrupt <= '0'; + + elsif rising_edge(clk) then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready <= dram_mem_readEnable; + + -- keep interrupt signal high for 16 cycles + interruptcounter <= interruptcounter + 1; + if (interruptcounter < 16) then + report "Interrupt asserted!" severity note; + interrupt <='1'; + else + interrupt <='0'; + end if; + end if; + end process; + + -- wiggle the clock @ 100MHz + clock: process + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + areset <= '0'; + end process clock; + + +end architecture behave; diff --git a/zpu/hdl/example/sim_small_fpga_top_noint.vhd b/zpu/hdl/example/sim_small_fpga_top_noint.vhd new file mode 100644 index 0000000..23b92cc --- /dev/null +++ b/zpu/hdl/example/sim_small_fpga_top_noint.vhd @@ -0,0 +1,184 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity fpga_top is +end fpga_top; + + +architecture behave of fpga_top is + + + signal clk : std_logic; + + signal areset : std_logic := '1'; + + + component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port ( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); + end component; + + + signal mem_busy : std_logic; + signal mem_read : std_logic_vector(wordSize-1 downto 0); + signal mem_write : std_logic_vector(wordSize-1 downto 0); + signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); + signal mem_writeEnable : std_logic; + signal mem_readEnable : std_logic; + signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + + signal enable : std_logic; + + signal dram_mem_busy : std_logic; + signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_writeEnable : std_logic; + signal dram_mem_readEnable : std_logic; + signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + + signal io_busy : std_logic; + + signal io_mem_read : std_logic_vector(wordSize-1 downto 0); + signal io_mem_writeEnable : std_logic; + signal io_mem_readEnable : std_logic; + + signal dram_ready : std_logic; + signal io_ready : std_logic; + signal io_reading : std_logic; + + signal break : std_logic; + + +begin + + zpu: zpu_core + port map ( + clk => clk, + reset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break + ); + + + ioMap: zpu_io + port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + + elsif rising_edge(clk) then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready <= dram_mem_readEnable; + end if; + end process; + + -- wiggle the clock @ 100MHz + clock: process + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + areset <= '0'; + end process clock; + + +end architecture behave; diff --git a/zpu/hdl/example/simzpu_dmips.do b/zpu/hdl/example/simzpu_dmips.do new file mode 100644 index 0000000..883259e --- /dev/null +++ b/zpu/hdl/example/simzpu_dmips.do @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script
+#
+#
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_dmips.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_small_fpga_top_noint.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit bram_dmips.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/simzpu_interrupt.do b/zpu/hdl/example/simzpu_interrupt.do new file mode 100644 index 0000000..864bf76 --- /dev/null +++ b/zpu/hdl/example/simzpu_interrupt.do @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script
+#
+#
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_interrupt.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_small_fpga_top.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit interrupt.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do new file mode 100644 index 0000000..2b64926 --- /dev/null +++ b/zpu/hdl/example/simzpu_small.do @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script
+#
+#
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_small.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_small_fpga_top_noint.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit helloworld.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd new file mode 100644 index 0000000..cd4163d --- /dev/null +++ b/zpu/hdl/example/zpu_config.vhd @@ -0,0 +1,55 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package zpu_config is + -- generate trace output + constant Generate_Trace : boolean := true; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 27; + constant maxAddrBitBRAM : integer := 16; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := + std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1)); +end zpu_config; diff --git a/zpu/hdl/example/zpuromgen.c b/zpu/hdl/example/zpuromgen.c new file mode 100644 index 0000000..fb8c4ba --- /dev/null +++ b/zpu/hdl/example/zpuromgen.c @@ -0,0 +1,59 @@ +// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+// by Adam Pierce
+// 29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef uint8_t BYTE;
+
+main(int argc, char **argv)
+{
+ BYTE opcode[4];
+ int fd;
+ int addr = 0;
+ ssize_t s;
+
+// Check the user has given us an input file.
+ if(argc < 2)
+ {
+ printf("Usage: %s <binary_file>\n\n", argv[0]);
+ return 1;
+ }
+
+// Open the input file.
+ fd = open(argv[1], 0);
+ if(fd == -1)
+ {
+ perror("File Open");
+ return 2;
+ }
+
+ while(1)
+ {
+ // Read 32 bits.
+ s = read(fd, opcode, 4);
+ if(s == -1)
+ {
+ perror("File read");
+ return 3;
+ }
+
+ if(s == 0)
+ break; // End of file.
+
+ // Output to STDOUT.
+ printf("%6d => x\"%02x%02x%02x%02x\",\n",
+ addr++, opcode[0], opcode[1],
+ opcode[2], opcode[3]);
+ }
+
+ close(fd);
+ return 0;
+}
+
diff --git a/zpu/hdl/example/zpuromgen.exe b/zpu/hdl/example/zpuromgen.exe Binary files differnew file mode 100644 index 0000000..6655412 --- /dev/null +++ b/zpu/hdl/example/zpuromgen.exe diff --git a/zpu/hdl/example_ghdl/README b/zpu/hdl/example_ghdl/README new file mode 100644 index 0000000..a098c0c --- /dev/null +++ b/zpu/hdl/example_ghdl/README @@ -0,0 +1,44 @@ +This directory contains a quick setup of the helloworld example for
+the GHDL simulator.
+
+ http://ghdl.free.fr/
+
+Compiled by Arnim Laeuger, 17-Apr-2008.
+Removed ROC/unisim dependency 16-Jun-2008.
+
+Compiling the example
+---------------------
+
+Make all shell scripts executable:
+ $ chmod +x *.sh
+
+On Linux, convert files from DOS format:
+ $ dos2unix *.sh
+
+You need to import the project sources once by running
+ $ ./ghdl_import.sh
+
+Compilation (using GHDL's make feature) is invoked by
+ $ ./ghdl_make.sh
+
+Whenever the VHDL sources change, it's enough to execute ghdl_make.sh. GHDL
+will trace the dependencies and will rebuild only the modified sources.
+
+
+Simulation
+----------
+
+Simulation finally happens by running the fpga_top executable generated by the
+compilation step. Don't forget to set a stop time or the testbench might run
+forever:
+
+ $ ./fpga_top --stop-time=2100us
+
+The log.txt and trace.txt files are generated as simulation progresses. They
+should be compared to the files given in the example directory.
+
+Waveforms can be obtained by specifying the ghw file name:
+
+ $ ./fpga_top --stop-time=1ms --wave=zpu.ghw
+
+They can be inspected with gtkwave from http://home.nc.rr.com/gtkwave/.
diff --git a/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh new file mode 100644 index 0000000..b3be1a6 --- /dev/null +++ b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh @@ -0,0 +1,24 @@ +#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/bram_dmips.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=1ms"
+fi
diff --git a/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh new file mode 100644 index 0000000..53474d4 --- /dev/null +++ b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh @@ -0,0 +1,24 @@ +#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_dmips.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=2500us"
+fi
diff --git a/zpu/hdl/example_ghdl/ghdl_import.sh b/zpu/hdl/example_ghdl/ghdl_import.sh new file mode 100644 index 0000000..b1c2713 --- /dev/null +++ b/zpu/hdl/example_ghdl/ghdl_import.sh @@ -0,0 +1,16 @@ +#!/bin/sh
+. ghdl_options.sh
+
+mkdir -p work
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/interrupt.vhd
+# to execute helloworld comment interrupt.vhd above
+# and edit sim_small_fpga_top.vhd to never assert interrupts
+#ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/helloworld.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd
diff --git a/zpu/hdl/example_ghdl/ghdl_make.sh b/zpu/hdl/example_ghdl/ghdl_make.sh new file mode 100644 index 0000000..948b100 --- /dev/null +++ b/zpu/hdl/example_ghdl/ghdl_make.sh @@ -0,0 +1,4 @@ +#!/bin/sh
+. ghdl_options.sh
+
+ghdl -m ${MAKE_OPTIONS} fpga_top
diff --git a/zpu/hdl/example_ghdl/ghdl_options.sh b/zpu/hdl/example_ghdl/ghdl_options.sh new file mode 100644 index 0000000..aba231c --- /dev/null +++ b/zpu/hdl/example_ghdl/ghdl_options.sh @@ -0,0 +1,2 @@ +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
diff --git a/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh new file mode 100644 index 0000000..8ba5078 --- /dev/null +++ b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh @@ -0,0 +1,24 @@ +#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_hello.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=1ms"
+fi
diff --git a/zpu/hdl/example_medium/.cvsignore b/zpu/hdl/example_medium/.cvsignore new file mode 100644 index 0000000..3add443 --- /dev/null +++ b/zpu/hdl/example_medium/.cvsignore @@ -0,0 +1,4 @@ +vsim.wlf +work +log.txt +trace.txt diff --git a/zpu/hdl/example_medium/dram_dmips.vhd b/zpu/hdl/example_medium/dram_dmips.vhd new file mode 100644 index 0000000..0437adc --- /dev/null +++ b/zpu/hdl/example_medium/dram_dmips.vhd @@ -0,0 +1,3308 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dram is +port (clk : in std_logic; +areset : std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80d5f40c", +3 => x"3a0b0b80", +4 => x"c4fb0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c5c22d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c3040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a6", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80d5", +162 => x"e0738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88a90400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0bad", +171 => x"aa2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0bad", +179 => x"ee2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80d5f00c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82fd3fbf", +257 => x"a03f0410", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10105351", +266 => x"047381ff", +267 => x"06738306", +268 => x"09810583", +269 => x"05101010", +270 => x"2b0772fc", +271 => x"060c5151", +272 => x"043c0472", +273 => x"72807281", +274 => x"06ff0509", +275 => x"72060571", +276 => x"1052720a", +277 => x"100a5372", +278 => x"ed385151", +279 => x"535104ff", +280 => x"3d0d0b0b", +281 => x"80e5e408", +282 => x"52710870", +283 => x"882a8132", +284 => x"70810651", +285 => x"515170f1", +286 => x"3873720c", +287 => x"833d0d04", +288 => x"80d5f008", +289 => x"802ea438", +290 => x"80d5f408", +291 => x"822ebd38", +292 => x"8380800b", +293 => x"0b0b80e5", +294 => x"e40c82a0", +295 => x"800b80e5", +296 => x"e80c8290", +297 => x"800b80e5", +298 => x"ec0c04f8", +299 => x"808080a4", +300 => x"0b0b0b80", +301 => x"e5e40cf8", +302 => x"80808280", +303 => x"0b80e5e8", +304 => x"0cf88080", +305 => x"84800b80", +306 => x"e5ec0c04", +307 => x"80c0a880", +308 => x"8c0b0b0b", +309 => x"80e5e40c", +310 => x"80c0a880", +311 => x"940b80e5", +312 => x"e80c0b0b", +313 => x"80c7d00b", +314 => x"80e5ec0c", +315 => x"04f23d0d", +316 => x"6080e5e8", +317 => x"08565d82", +318 => x"750c8059", +319 => x"805a800b", +320 => x"8f3d5d5b", +321 => x"7a101015", +322 => x"70087108", +323 => x"719f2c7e", +324 => x"852b5855", +325 => x"557d5359", +326 => x"5799993f", +327 => x"7d7f7a72", +328 => x"077c7207", +329 => x"71716081", +330 => x"05415f5d", +331 => x"5b595755", +332 => x"817b278f", +333 => x"38767d0c", +334 => x"77841e0c", +335 => x"7c800c90", +336 => x"3d0d0480", +337 => x"e5e80855", +338 => x"ffba3970", +339 => x"7080e5f0", +340 => x"335170a7", +341 => x"3880d5fc", +342 => x"08700852", +343 => x"5270802e", +344 => x"94388412", +345 => x"80d5fc0c", +346 => x"702d80d5", +347 => x"fc087008", +348 => x"525270ee", +349 => x"38810b80", +350 => x"e5f03450", +351 => x"50040470", +352 => x"0b0b80e5", +353 => x"e008802e", +354 => x"8e380b0b", +355 => x"0b0b800b", +356 => x"802e0981", +357 => x"06833850", +358 => x"040b0b80", +359 => x"e5e0510b", +360 => x"0b0bf4dc", +361 => x"3f500404", +362 => x"ff3d0d02", +363 => x"8f053352", +364 => x"718a2e8a", +365 => x"387151fd", +366 => x"a63f833d", +367 => x"0d048d51", +368 => x"fd9d3f71", +369 => x"51fd983f", +370 => x"833d0d04", +371 => x"ce3d0db5", +372 => x"3d707084", +373 => x"0552088b", +374 => x"a85c56a5", +375 => x"3d5e5c80", +376 => x"75708105", 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x"00002e74", +2976 => x"00002e74", +2977 => x"00002e7c", +2978 => x"00002e7c", +2979 => x"00002e84", +2980 => x"00002e84", +2981 => x"00002e8c", +2982 => x"00002e8c", +2983 => x"00002e94", +2984 => x"00002e94", +2985 => x"00002e9c", +2986 => x"00002e9c", +2987 => x"00002ea4", +2988 => x"00002ea4", +2989 => x"00002eac", +2990 => x"00002eac", +2991 => x"00002eb4", +2992 => x"00002eb4", +2993 => x"00002ebc", +2994 => x"00002ebc", +2995 => x"00002ec4", +2996 => x"00002ec4", +2997 => x"00002ecc", +2998 => x"00002ecc", +2999 => x"00002ed4", +3000 => x"00002ed4", +3001 => x"00002edc", +3002 => x"00002edc", +3003 => x"00002ee4", +3004 => x"00002ee4", +3005 => x"00002eec", +3006 => x"00002eec", +3007 => x"00002ef4", +3008 => x"00002ef4", +3009 => x"00002efc", +3010 => x"00002efc", +3011 => x"00002f04", +3012 => x"00002f04", +3013 => x"00002f0c", +3014 => x"00002f0c", +3015 => x"00002f14", +3016 => x"00002f14", +3017 => x"00002f1c", +3018 => x"00002f1c", +3019 => x"00002f24", +3020 => x"00002f24", +3021 => x"00002f2c", +3022 => x"00002f2c", +3023 => x"00002f34", +3024 => x"00002f34", +3025 => x"00002f3c", +3026 => x"00002f3c", +3027 => x"00002f50", +3028 => x"00000000", +3029 => x"000031b8", +3030 => x"00003214", +3031 => x"00003270", +3032 => x"00000000", +3033 => x"00000000", +3034 => x"00000000", +3035 => x"00000000", +3036 => x"00000000", +3037 => x"00000000", +3038 => x"00000000", +3039 => x"00000000", +3040 => x"00000000", +3041 => x"00002ad0", +3042 => x"00000000", +3043 => x"00000000", +3044 => x"00000000", +3045 => x"00000000", +3046 => x"00000000", +3047 => x"00000000", +3048 => x"00000000", +3049 => x"00000000", +3050 => x"00000000", +3051 => x"00000000", +3052 => x"00000000", +3053 => x"00000000", +3054 => x"00000000", +3055 => x"00000000", +3056 => x"00000000", +3057 => x"00000000", +3058 => x"00000000", +3059 => x"00000000", +3060 => x"00000000", +3061 => x"00000000", +3062 => x"00000000", +3063 => x"00000000", +3064 => x"00000000", +3065 => x"00000000", +3066 => x"00000000", +3067 => x"00000000", +3068 => x"00000000", +3069 => x"00000000", +3070 => x"00000001", +3071 => x"330eabcd", +3072 => x"1234e66d", +3073 => x"deec0005", +3074 => x"000b0000", +3075 => x"00000000", +3076 => x"00000000", +3077 => x"00000000", +3078 => x"00000000", +3079 => x"00000000", +3080 => x"00000000", +3081 => x"00000000", +3082 => x"00000000", +3083 => x"00000000", +3084 => x"00000000", +3085 => x"00000000", +3086 => x"00000000", +3087 => x"00000000", +3088 => x"00000000", +3089 => x"00000000", +3090 => x"00000000", +3091 => x"00000000", +3092 => x"00000000", +3093 => x"00000000", +3094 => x"00000000", +3095 => x"00000000", +3096 => x"00000000", +3097 => x"00000000", +3098 => x"00000000", +3099 => x"00000000", +3100 => x"00000000", +3101 => x"00000000", +3102 => x"00000000", +3103 => x"00000000", +3104 => x"00000000", +3105 => x"00000000", +3106 => x"00000000", +3107 => x"00000000", +3108 => x"00000000", +3109 => x"00000000", +3110 => x"00000000", +3111 => x"00000000", +3112 => x"00000000", +3113 => x"00000000", +3114 => x"00000000", +3115 => x"00000000", +3116 => x"00000000", +3117 => x"00000000", +3118 => x"00000000", +3119 => x"00000000", +3120 => x"00000000", +3121 => x"00000000", +3122 => x"00000000", +3123 => x"00000000", +3124 => x"00000000", +3125 => x"00000000", +3126 => x"00000000", +3127 => x"00000000", +3128 => x"00000000", +3129 => x"00000000", +3130 => x"00000000", +3131 => x"00000000", +3132 => x"00000000", +3133 => x"00000000", +3134 => x"00000000", +3135 => x"00000000", +3136 => x"00000000", +3137 => x"00000000", +3138 => x"00000000", +3139 => x"00000000", +3140 => x"00000000", +3141 => x"00000000", +3142 => x"00000000", +3143 => x"00000000", +3144 => x"00000000", +3145 => x"00000000", +3146 => x"00000000", +3147 => x"00000000", +3148 => x"00000000", +3149 => x"00000000", +3150 => x"00000000", +3151 => x"00000000", +3152 => x"00000000", +3153 => x"00000000", +3154 => x"00000000", +3155 => x"00000000", +3156 => x"00000000", +3157 => x"00000000", +3158 => x"00000000", +3159 => x"00000000", +3160 => x"00000000", +3161 => x"00000000", +3162 => x"00000000", +3163 => x"00000000", +3164 => x"00000000", +3165 => x"00000000", +3166 => x"00000000", +3167 => x"00000000", +3168 => x"00000000", +3169 => x"00000000", +3170 => x"00000000", +3171 => x"00000000", +3172 => x"00000000", +3173 => x"00000000", +3174 => x"00000000", +3175 => x"00000000", +3176 => x"00000000", +3177 => x"00000000", +3178 => x"00000000", +3179 => x"00000000", +3180 => x"00000000", +3181 => x"00000000", +3182 => x"00000000", +3183 => x"00000000", +3184 => x"00000000", +3185 => x"00000000", +3186 => x"00000000", +3187 => x"00000000", +3188 => x"00000000", +3189 => x"00000000", +3190 => x"00000000", +3191 => x"00000000", +3192 => x"00000000", +3193 => x"00000000", +3194 => x"00000000", +3195 => x"00000000", +3196 => x"00000000", +3197 => x"00000000", +3198 => x"00000000", +3199 => x"00000000", +3200 => x"00000000", +3201 => x"00000000", +3202 => x"00000000", +3203 => x"00000000", +3204 => x"00000000", +3205 => x"00000000", +3206 => x"00000000", +3207 => x"00000000", +3208 => x"00000000", +3209 => x"00000000", +3210 => x"00000000", +3211 => x"00000000", +3212 => x"00000000", +3213 => x"00000000", +3214 => x"00000000", +3215 => x"00000000", +3216 => x"00000000", +3217 => x"00000000", +3218 => x"00000000", +3219 => x"00000000", +3220 => x"00000000", +3221 => x"00000000", +3222 => x"00000000", +3223 => x"00000000", +3224 => x"00000000", +3225 => x"00000000", +3226 => x"00000000", +3227 => x"00000000", +3228 => x"00000000", +3229 => x"00000000", +3230 => x"00000000", +3231 => x"00000000", +3232 => x"00000000", +3233 => x"00000000", +3234 => x"00000000", +3235 => x"00000000", +3236 => x"00000000", +3237 => x"00000000", +3238 => x"00000000", +3239 => x"00000000", +3240 => x"00000000", +3241 => x"00000000", +3242 => x"00000000", +3243 => x"00000000", +3244 => x"00000000", +3245 => x"00000000", +3246 => x"00000000", +3247 => x"00000000", +3248 => x"00000000", +3249 => x"00000000", +3250 => x"00000000", +3251 => x"00002ad4", +3252 => x"ffffffff", +3253 => x"00000000", +3254 => x"ffffffff", +3255 => x"00000000", + others => x"00000000" +); + +begin + +mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request + +process (clk, areset) +begin + if areset = '1' then + elsif (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; + end if; + if (mem_readEnable = '1') then + mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); + end if; + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/example_medium/dram_hello.vhd b/zpu/hdl/example_medium/dram_hello.vhd new file mode 100644 index 0000000..aae18fd --- /dev/null +++ b/zpu/hdl/example_medium/dram_hello.vhd @@ -0,0 +1,3107 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dram is +port (clk : in std_logic; +areset : std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfd80c", +3 => x"3a0b0b80", +4 => x"c6d00400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c7972d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80cf", +162 => x"c4738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8b", +171 => x"9f2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8b", +179 => x"e32d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80cfd40c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82c53f80", +257 => x"c6d93f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51047381", +267 => x"ff067383", +268 => x"06098105", +269 => x"83051010", +270 => x"102b0772", +271 => x"fc060c51", +272 => x"51043c04", +273 => x"72728072", +274 => x"8106ff05", +275 => x"09720605", +276 => x"71105272", +277 => x"0a100a53", +278 => x"72ed3851", +279 => x"51535104", +280 => x"fe3d0d0b", +281 => x"0b80dfc0", +282 => x"08538413", +283 => x"0870882a", +284 => x"70810651", +285 => x"52527080", +286 => x"2ef03871", +287 => x"81ff0680", +288 => x"0c843d0d", +289 => x"04ff3d0d", +290 => x"0b0b80df", +291 => x"c0085271", +292 => x"0870882a", +293 => x"81327081", +294 => x"06515151", +295 => x"70f13873", +296 => x"720c833d", +297 => x"0d0480cf", +298 => x"d408802e", +299 => x"a43880cf", +300 => x"d808822e", +301 => x"bd388380", +302 => x"800b0b0b", +303 => x"80dfc00c", +304 => x"82a0800b", +305 => x"80dfc40c", +306 => x"8290800b", +307 => x"80dfc80c", +308 => x"04f88080", +309 => x"80a40b0b", +310 => x"0b80dfc0", +311 => x"0cf88080", +312 => x"82800b80", +313 => x"dfc40cf8", +314 => x"80808480", +315 => x"0b80dfc8", +316 => x"0c0480c0", +317 => x"a8808c0b", +318 => x"0b0b80df", +319 => x"c00c80c0", +320 => x"a880940b", +321 => x"80dfc40c", +322 => x"0b0b80cf", +323 => x"8c0b80df", +324 => x"c80c0470", +325 => x"7080dfcc", +326 => x"335170a7", +327 => x"3880cfe0", +328 => x"08700852", +329 => x"5270802e", +330 => x"94388412", +331 => x"80cfe00c", +332 => x"702d80cf", +333 => x"e0087008", +334 => x"525270ee", +335 => x"38810b80", +336 => x"dfcc3450", +337 => x"50040470", +338 => x"0b0b80df", +339 => x"bc08802e", +340 => x"8e380b0b", +341 => x"0b0b800b", +342 => x"802e0981", +343 => x"06833850", +344 => x"040b0b80", +345 => x"dfbc510b", +346 => x"0b0bf594", +347 => x"3f500404", +348 => x"fe3d0d89", +349 => x"5380cf90", +350 => x"5182c13f", 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x"00002d58", +2906 => x"00002d60", +2907 => x"00002d60", +2908 => x"00002d68", +2909 => x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"000027b8", +3051 => x"ffffffff", +3052 => x"00000000", +3053 => x"ffffffff", +3054 => x"00000000", + others => x"00000000" +); + +begin + +mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request + +process (clk, areset) +begin + if areset = '1' then + elsif (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; + end if; + if (mem_readEnable = '1') then + mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); + end if; + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/example_medium/sim_fpga_top.vhd b/zpu/hdl/example_medium/sim_fpga_top.vhd new file mode 100644 index 0000000..962caad --- /dev/null +++ b/zpu/hdl/example_medium/sim_fpga_top.vhd @@ -0,0 +1,194 @@ +-------------------------------------------------------------------------------- +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Ãyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.zpu_config.all; + + +entity fpga_top is +end fpga_top; + +use work.zpupkg.all; + +architecture behave of fpga_top is + + + signal clk : std_logic; + + signal areset : std_logic := '1'; + + + component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port ( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); + end component; + + + signal mem_busy : std_logic; + signal mem_read : std_logic_vector(wordSize-1 downto 0); + signal mem_write : std_logic_vector(wordSize-1 downto 0); + signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); + signal mem_writeEnable : std_logic; + signal mem_readEnable : std_logic; + signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + + signal enable : std_logic; + + signal dram_mem_busy : std_logic; + signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_writeEnable : std_logic; + signal dram_mem_readEnable : std_logic; + signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + + signal io_busy : std_logic; + + signal io_mem_read : std_logic_vector(wordSize-1 downto 0); + signal io_mem_writeEnable : std_logic; + signal io_mem_readEnable : std_logic; + + signal dram_ready : std_logic; + signal io_ready : std_logic; + signal io_reading : std_logic; + + signal break : std_logic; + +begin + + zpu: zpu_core + port map ( + clk => clk, + reset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break + ); + + dram_imp: dram + port map ( + clk => clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask + ); + + + ioMap: zpu_io + port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write(wordSize-1 downto 0), + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or io_busy; + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif rising_edge(clk) then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready <= dram_mem_readEnable; + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : process + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + areset <= '0'; + end process clock; + + +end architecture behave; diff --git a/zpu/hdl/example_medium/simzpu_medium.do b/zpu/hdl/example_medium/simzpu_medium.do new file mode 100644 index 0000000..2b77ba6 --- /dev/null +++ b/zpu/hdl/example_medium/simzpu_medium.do @@ -0,0 +1,28 @@ +# Xilinx WebPack modelsim script
+#
+# cd C:/workspace/zpu/zpu/hdl/example_medium
+# do simzpu_medium.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config_trace.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core.vhd
+vcom -93 -explicit dram_hello.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 1000 ms
diff --git a/zpu/hdl/example_medium/zpu_config_trace.vhd b/zpu/hdl/example_medium/zpu_config_trace.vhd new file mode 100644 index 0000000..a5b9192 --- /dev/null +++ b/zpu/hdl/example_medium/zpu_config_trace.vhd @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; + +package zpu_config is + + constant Generate_Trace : boolean := true; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + constant maxAddrBitIncIO : integer := 27; + constant maxAddrBitDRAM : integer := 16; + constant maxAddrBitBRAM : integer := 16; + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; + +end zpu_config; diff --git a/zpu/hdl/sim/dmipssmalltrace.do b/zpu/hdl/sim/dmipssmalltrace.do new file mode 100644 index 0000000..eb4c6fe --- /dev/null +++ b/zpu/hdl/sim/dmipssmalltrace.do @@ -0,0 +1,26 @@ +set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config_trace.vhd
+vcom -93 -explicit zpupkg.vhd
+vcom -93 -explicit txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit zpu_core_small.vhd
+vcom -93 -explicit bram_dmips.vhd
+vcom -93 -explicit dram_dmips.vhd
+vcom -93 -explicit timer.vhd
+vcom -93 -explicit io.vhd
+vcom -93 -explicit trace.vhd
+
+
+vsim fpga_top
+view wave
+
+add wave -recursive fpga_top/zpu/*
+#--add wave -recursive fpga_top/ioMap/*
+#add wave -recursive fpga_top/*
+view structure
+
+
+# run ZPU
+run 5 ms
diff --git a/zpu/hdl/sim/dmipstrace.do b/zpu/hdl/sim/dmipstrace.do new file mode 100644 index 0000000..64cf8fd --- /dev/null +++ b/zpu/hdl/sim/dmipstrace.do @@ -0,0 +1,30 @@ +# Xilinx WebPack modelsim script
+#
+# cd C:/workspace/zpu/zpu/hdl/zpu4/src
+# do dmipstrace.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config_trace.vhd
+vcom -93 -explicit zpupkg.vhd
+vcom -93 -explicit txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit zpu_core.vhd
+vcom -93 -explicit dram_dmips.vhd
+vcom -93 -explicit timer.vhd
+vcom -93 -explicit io.vhd
+vcom -93 -explicit trace.vhd
+
+
+vsim fpga_top
+view wave
+
+add wave -recursive fpga_top/zpu/*
+#--add wave -recursive fpga_top/ioMap/*
+#add wave -recursive fpga_top/*
+view structure
+
+
+# run ZPU
+run 5 ms
diff --git a/zpu/hdl/spi/spi_controller.v b/zpu/hdl/spi/spi_controller.v new file mode 100644 index 0000000..b22f294 --- /dev/null +++ b/zpu/hdl/spi/spi_controller.v @@ -0,0 +1,235 @@ +/*
+ SPI flash read-only controller
+
+ Copyright 2008 Álvaro Lopes <alvieboy@alvie.com>
+
+ Version: 1.3
+
+ The FreeBSD license
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials
+ provided with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Changelog:
+
+ 1.3: Remove async reset from spi_data shift register
+ Fix indentation of code
+
+ 1.2: Fix read count for sequential fetch
+
+ 1.1: Move port types outside module declaration.
+ Fix state machine to handle clock stop
+ Remove err out report
+ Fix SPI_CLK generation.
+*/
+
+module spi_controller (
+ clk, // Clock
+ rst, // Reset
+ ce, // Chip Enable
+ ack, // Acknowledge
+
+ adr, // Address in
+ dat_o, // Data out
+
+ SPI_MOSI, // Master Out/Slave In for SPI
+ SPI_MISO, // Master In/Slave Out for SPI
+ SPI_CLK, // SPI clock
+ SPI_SELN // SPI nSEL
+);
+
+parameter Tp = 0; // Propagation delay - for simulation
+parameter INIT_CLOCK_CYCLE_WAIT = 2; // Clock cycles to wait before init
+parameter DESELECT_CYCLES = 3; // Clock cycles to wait after deselection - should give 100ns at least
+parameter SPI_REGISTER_SIZE = 40;
+parameter SPI_ADDRESS_SIZE = 24;
+
+input clk;
+input rst;
+input ce;
+output reg ack;
+
+input [SPI_ADDRESS_SIZE-1:0] adr;
+output reg [31:0] dat_o;
+
+output reg SPI_MOSI;
+input SPI_MISO;
+output SPI_CLK;
+output reg SPI_SELN;
+
+
+// FSM states
+localparam SPI_STATE_WAIT = 7'b0000001,
+ SPI_STATE_IDLE = 7'b0000010,
+ SPI_STATE_WACK = 7'b0000100,
+ SPI_STATE_SEND = 7'b0001000,
+ SPI_STATE_BREAD = 7'b0010000,
+ SPI_STATE_READ = 7'b0100000,
+ SPI_STATE_WDES = 7'b1000000;
+
+// SPI commands
+localparam SPI_CMD_READ_FAST = 8'b00001011;
+
+
+// Shift register to hold command to be sent to SPI
+reg [SPI_REGISTER_SIZE-1:0] spi_shift_register_out;
+
+integer spi_reg_count;
+
+reg [8:0] spi_read_count;
+reg [7:0] spi_data;
+reg [3:0] data_valid_window;
+reg [SPI_REGISTER_SIZE-1:0] next_address;
+
+integer dsel_dly;
+integer spi_init_count;
+reg spi_start_count;
+reg spi_enable_clock; // Enable SPI clock
+reg [6:0] spi_state; // SPI state machine
+
+/*
+ SPI clock generation
+*/
+
+assign SPI_CLK = spi_enable_clock?~clk:1'b0;
+
+reg seq_read; // Sequential read in progress
+
+always @(posedge clk or posedge rst)
+begin
+ if ( rst ) begin
+ spi_enable_clock <= #Tp 1'b0;
+ spi_state <= #Tp SPI_STATE_WAIT;
+ spi_init_count <= #Tp INIT_CLOCK_CYCLE_WAIT;
+ SPI_SELN <= #Tp 1'b1;
+ ack <= #Tp 1'b0;
+ spi_start_count <= #Tp 1'b0;
+ next_address <= #Tp 32'hFFFFFFFF;
+ end else begin
+
+ case (spi_state)
+ SPI_STATE_WAIT:
+ begin
+ if ( spi_init_count == 0 ) begin
+ spi_state <= SPI_STATE_IDLE;
+ end else begin
+ spi_init_count <= #Tp spi_init_count - 1;
+ end
+ end
+ SPI_STATE_IDLE:
+ begin
+
+ if ( ce ) begin
+ next_address <= { adr[SPI_ADDRESS_SIZE-1:2], 2'b0 } + 4;
+ seq_read = adr[SPI_ADDRESS_SIZE-1:2] == next_address[SPI_ADDRESS_SIZE-1:2];
+ // Latch address (24 bit wordsize)
+ spi_shift_register_out <= #Tp { SPI_CMD_READ_FAST, adr[SPI_ADDRESS_SIZE-1:2], 2'b0, 8'b0 };
+
+ spi_enable_clock <= #Tp 1'b1;
+
+ if ( seq_read ) begin
+ spi_state <= #Tp SPI_STATE_BREAD;
+ end else begin
+ SPI_SELN <= 1'b1 ;
+ spi_reg_count <= #Tp SPI_REGISTER_SIZE;
+ dsel_dly <= DESELECT_CYCLES;
+ spi_state <= #Tp SPI_STATE_WDES;
+ end
+ end
+ end
+ SPI_STATE_WACK:
+ begin
+ ack <= 1'b0;
+ spi_state <= SPI_STATE_IDLE;
+ end
+ SPI_STATE_SEND:
+ begin
+
+ SPI_SELN <=#Tp 1'b0;
+
+ if (spi_reg_count == 0)
+ begin
+ spi_state <= #Tp SPI_STATE_BREAD;
+ end else begin
+ SPI_MOSI <= #Tp spi_shift_register_out[SPI_REGISTER_SIZE-1];
+ spi_shift_register_out <= #Tp { spi_shift_register_out[SPI_REGISTER_SIZE-2:0], 1'b0 };
+ spi_reg_count <= #Tp spi_reg_count - 1;
+ end
+ end
+ SPI_STATE_BREAD:
+ begin
+ spi_start_count <= #Tp 1'b1;
+ spi_state <= #Tp SPI_STATE_READ;
+ end
+ SPI_STATE_READ:
+ begin
+ spi_start_count <= #Tp 1'b0;
+
+ // Stop clock a bit earlier
+ if ( data_valid_window[3] && spi_read_count[1] )
+ spi_enable_clock <= 1'b0;
+
+ if (spi_read_count[0])
+ begin
+
+ dat_o <= #Tp { dat_o[23:0], spi_data };
+
+ if ( data_valid_window[3] ) begin
+ ack <= #Tp 1'b1;
+ spi_state <= #Tp SPI_STATE_WACK;
+ end
+ end
+ end
+ SPI_STATE_WDES:
+ begin
+ if ( dsel_dly == 0 )
+ spi_state <= SPI_STATE_SEND;
+ else
+ dsel_dly <= dsel_dly -1;
+ end
+ endcase
+ end
+end
+
+always @(posedge clk)
+begin
+ if (spi_start_count) begin
+ spi_read_count <= 8'b01000000;
+ data_valid_window <= #Tp 5'b00001;
+ end else begin
+ if ( spi_read_count[0] ) begin
+ data_valid_window <= #Tp { data_valid_window[3:0], 1'b0 };
+ end
+ spi_read_count <= #Tp { spi_read_count[0] ,spi_read_count[7:1] };
+ end
+end
+
+// SPI data shift register
+
+always @(negedge clk)
+begin
+ spi_data <= #Tp { spi_data[6:0], SPI_MISO };
+end
+
+endmodule
diff --git a/zpu/hdl/wishbone/wishbone_pkg.vhd b/zpu/hdl/wishbone/wishbone_pkg.vhd new file mode 100644 index 0000000..b6d30ee --- /dev/null +++ b/zpu/hdl/wishbone/wishbone_pkg.vhd @@ -0,0 +1,86 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package wishbone_pkg is + + type wishbone_bus_in is record + adr : std_logic_vector(31 downto 0); + sel : std_logic_vector(3 downto 0); + we : std_logic; + dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we' + cyc : std_logic; + stb : std_logic; + end record; + + type wishbone_bus_out is record + dat : std_logic_vector(31 downto 0); + ack : std_logic; + end record; + + type wishbone_bus is record + insig : wishbone_bus_in; + outsig : wishbone_bus_out; + end record; + + component atomic32_access is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from CPU interface + wb_16_i : in wishbone_bus_in; + wb_16_o : out wishbone_bus_out; + -- Wishbone to FPGA registers and ethernet core + wb_32_i : in wishbone_bus_out; + wb_32_o : out wishbone_bus_in); + end component; + + component eth_access_corr is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from Wishbone MUX + eth_raw_o : out wishbone_bus_out; + eth_raw_i : in wishbone_bus_in; + + -- Wishbone ethernet core + eth_slave_i : in wishbone_bus_out; + eth_slave_o : out wishbone_bus_in); + end component; + + +end wishbone_pkg; diff --git a/zpu/hdl/wishbone/zpu_system.vhd b/zpu/hdl/wishbone/zpu_system.vhd new file mode 100644 index 0000000..07c5bdc --- /dev/null +++ b/zpu/hdl/wishbone/zpu_system.vhd @@ -0,0 +1,104 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +library work; +use work.wishbone_pkg.all; +use work.zpupkg.all; +use work.zpu_config.all; + +entity zpu_system is + generic( + simulate : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + + -- ZPU Control signals + enable : in std_logic; + interrupt : in std_logic; + + zpu_status : out std_logic_vector(63 downto 0); + + -- wishbone interfaces + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); +end zpu_system; + +architecture behave of zpu_system is + +signal mem_req : std_logic; +signal mem_we : std_logic; +signal mem_ack : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + + +begin + + my_zpu_core: + zpu_core port map ( + clk => cpu_clk, + areset => areset, + enable => enable, + mem_req => mem_req, + mem_we => mem_we, + mem_ack => mem_ack, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => out_mem_addr, + mem_writeMask => mem_writeMask, + interrupt => interrupt, + zpu_status => zpu_status, + break => open); + + my_zpu_wb_bridge: + zpu_wb_bridge port map ( + clk => cpu_clk, + areset => areset, + mem_req => mem_req, + mem_we => mem_we, + mem_ack => mem_ack, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => out_mem_addr, + mem_writeMask => mem_writeMask, + zpu_wb_i => zpu_wb_i, + zpu_wb_o => zpu_wb_o); + +end behave; diff --git a/zpu/hdl/wishbone/zpu_wb_bridge.vhd b/zpu/hdl/wishbone/zpu_wb_bridge.vhd new file mode 100644 index 0000000..086ae11 --- /dev/null +++ b/zpu/hdl/wishbone/zpu_wb_bridge.vhd @@ -0,0 +1,83 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.phi_config.all; +use work.wishbone_pkg.all; +use work.zpupkg.all; +use work.zpu_config.all; + +entity zpu_wb_bridge is + port ( -- Native ZPU interface + clk : in std_logic; + areset : in std_logic; + + mem_req : in std_logic; + mem_we : in std_logic; + mem_ack : out std_logic; + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0); + + -- Wishbone from ZPU + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); + +end zpu_wb_bridge; + +architecture behave of zpu_wb_bridge is + +begin + + mem_read <= zpu_wb_i.dat; + mem_ack <= zpu_wb_i.ack; + + zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0); + zpu_wb_o.dat <= mem_write; + zpu_wb_o.sel <= mem_writeMask; + zpu_wb_o.stb <= mem_req; + zpu_wb_o.cyc <= mem_req; + zpu_wb_o.we <= mem_we; + +end behave; + + + + + diff --git a/zpu/hdl/zealot/0README.txt b/zpu/hdl/zealot/0README.txt new file mode 100644 index 0000000..4bb4546 --- /dev/null +++ b/zpu/hdl/zealot/0README.txt @@ -0,0 +1,195 @@ +This is a test release of the ZPU. +ZPU is a 32 bits stack CPU. This package contains a VHDL implementation +suitable for FPGAs. It was tested using a Xilinx Spartan 3 1500 FPGA. + +The author of the ZPU is Øyvind Harboe (oyvind.harboe zylin.com) and the +license is the BSD one. Portions of this package were developed by Salvador E. +Tropea (salvador inti.gob.ar) and others. Some portions are under the GPL +license. + +Øyvind also added a ZPU target to the gcc/gdb. + +For more information about the ZPU core please visit: +http://www.zylin.com/zpu.htm +http://www.opencores.org/projects.cgi/web/zpu/overview + +What are the files? +------------------- + +zpu_medium.vhdl +ZPU CPU, medium version. + +zpu_small.vhdl +ZPU CPU, small version (Dual Port RAM only!). + +zpu_pkg.vhdl +Package containing the declarations for the ZPU library. + +devices/phi_io.vhdl +The very basic I/O peripherals needed for the standard C library. It includes a +timer (64 bits clock counter) and an UART (8N1 without FIFO). +This is known as the PHI I/O layout, this implementation isn't complete. Only +the above mentioned peripherals are available. + +devices/timer.vhdl +64 bits clock counter maped by the PHI I/O. + +devices/trace.vhdl +This is used for debug purposes. The ZPU have a debug port to connect this +module. It can generate an execution trace log during the simulation. + +devices/txt_util.vhdl +Useful text handling routines for the simulation. + +devices/br_gen.vhdl +Fixed baud rate generator for the UART. + +devices/rx_unit.vhdl +UART Rx module. + +devices/tx_unit.vhdl +UART Tx module. + +roms/rom_pkg.vhdl +Package containing the declarations for the memories used by the small and +medium ZPU. + +roms/dmips_bram.vhdl +A memory that maps to Xilinx BRAMs and contains the Dhrystone Benchmark, +Version 2.1 (Language: C). This memory can be connected to the ZPU for +simulation or hardware implementations. The code assumes a 50 MHz clock to +compute the benchmark. The minimum size for this block should be 32 kB. + +roms/dmips_dbram.vhdl +Same as roms/dmips_bram.vhdl, but dual ported. Suitable for the small ZPU. + +roms/hello_bram.vhdl +A memory that maps to Xilinx BRAMs and contains a simple "Hello World!" +program (C compiled). This memory can be connected to the ZPU for +simulation or hardware implementations. The minimum size for this block +should be 16 kB. + +roms/hello_dbram.vhdl +Same as roms/hello_bram.vhdl, but dual ported. Suitable for the small ZPU. +helpers/zpu_med1.vhdl +This is a helper that connects a ZPU to its memory and the PHI I/O space. + +testbenches/dmips_med1_tb.vhdl +A simple testbench to simulate the medium ZPU (behavior). + +testbenches/small1_tb.vhdl +A simple testbench to simulate the small ZPU (behavior). + +fpga/dmips_med1.vhdl +A wrapper to implement the medium ZPU in an FPGA. This example was designed +for a GR-XC3S board from Pender, but should be easily adapted to other +boards. + +fpga/hello_med1.vhdl +Same as fpga/dmips_med1.vhdl, but uses less memory, enough for the "Hello +Wold!" test. + +fpga/dmips_small1.vhdl +Same as fpga/dmips_med1.vhdl, but for the small ZPU. + +fpga/hello_small1.vhdl +Same as fpga/hello_med1.vhdl, but for the small ZPU. + + +ZPU library? +------------ + +The following files are part of a library I called ZPU: + +zpu_pkg.vhdl, zpu_medium.vhdl, zpu_small.vhdl, txt_util.vhdl, timer.vhdl, +rx_unit.vhdl, tx_unit.vhdl, br_gen.vhdl, phi_io.vhdl and trace.vhdl. + +You should group them inside a library called zpu. This procedure is +tool-chain dependent. In the ISE tool you must add a library and them move +these files to the library. + +If you don't know how to do it with your tools you can just replace all the: + +library zpu; +use zpu.xxxxxx.all; + +code by: + +library work; +use work.xxxxxx.all; + + +Which files are needed for simulation? +-------------------------------------- + +You need all the files that compose the zpu library plus: +1) A memory containing a program, i.e.: +roms/rom_pkg.vhdl and roms/dmips_bram.vhdl +2) A testbench (including the memory and I/O interconnections): +aux/zpu_med1.vhdl and testbenches/dmips_med1_tb.vhdl +3) Be careful to include only the medium or the small ZPU. Also note that +the small uses dual port BRAMs, i.e. roms/dmips_dbram.vhdl The testbench +for the small ZPU is small1_tb.vhdl + + +Which files are needed for synthesis? +------------------------------------- + +This is similar to simulation, but: +1) You should avoid trace.vhdl. +2) The top level should connect to the FPGA pins, replace dmips_med1_tb.vhdl +by fpga/dmips_med1.vhdl or fpga/hello_med1.vhdl + + +What resources are needed in the FPGA? +-------------------------------------- + +The DMIPS benchmarks needs aprox (Xilinx Spartan 3): + +Medium ZPU: + +Flip Flops: 498 +LUTs: 1877 +Slices: 1032 +BRAMs: 16 +Multipliers: 3 + +The hello world example needs less memory: + +Flip Flops: 496 +LUTs: 1871 +Slices: 1027 +BRAMs: 8 +Multipliers: 3 + + +Small ZPU: + +Flip Flops: 373 +LUTs: 706 +Slices: 434 +BRAMs: 16 + +The hello world example needs less memory: + +Flip Flops: 371 +LUTs: 701 +Slices: 431 +BRAMs: 8 + + +The board should contain an RS-232 transceiver. A push button (active when +pressed) is also used, for reset. + + +Ok, I synthetized it and put in the FPGA, what now? +--------------------------------------------------- + +Connect the RS-232 board output to a terminal (a PC). Setup the terminal for +115200 8N1 reception and press the reset push button. You should get the +program output. You can change the baudrate in the toplevel VHDL. + + +Please tell me if you succeed or failed! +Enjoy, Salvador E. Tropea + diff --git a/zpu/hdl/zealot/BSD b/zpu/hdl/zealot/BSD new file mode 100644 index 0000000..cca2a5c --- /dev/null +++ b/zpu/hdl/zealot/BSD @@ -0,0 +1,20 @@ +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + <one line to give the program's name and a brief idea of what it does.> + Copyright (C) 19yy <name of author> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/zpu/hdl/zealot/devices/br_gen.vhdl b/zpu/hdl/zealot/devices/br_gen.vhdl new file mode 100644 index 0000000..d14440e --- /dev/null +++ b/zpu/hdl/zealot/devices/br_gen.vhdl @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------ +---- ---- +---- RS-232 baudrate generator ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This counter is a parametrizable clock divider. The count value is ---- +---- the generic parameter COUNT. It has a chip enable ce_i input. ---- +---- (will count only if CE is high). ---- +---- When it overflows, will emit a pulse on o_o. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Philippe Carton, philippe.carton2 libertysurf.fr ---- +---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2001-2003 Philippe Carton ---- +---- Copyright (c) 2005 Juan Pablo Daniel Borgna ---- +---- Copyright (c) 2005-2008 Salvador E. Tropea ---- +---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: BRGen(Behaviour) (Entity and architecture) ---- +---- File name: br_gen.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- Target FPGA: Spartan ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity BRGen is + generic( + COUNT : integer range 0 to 65535);-- Count revolution + port ( + clk_i : in std_logic; -- Clock + reset_i : in std_logic; -- Reset input + ce_i : in std_logic; -- Chip Enable + o_o : out std_logic); -- Output +end entity BRGen; + +architecture Behaviour of BRGen is + +begin + CountGen: + if COUNT/=1 generate + Counter: + process (clk_i) + variable cnt : integer range 0 to COUNT-1; + begin + if rising_edge(clk_i) then + o_o <= '0'; + if reset_i='1' then + cnt:=COUNT-1; + elsif ce_i='1' then + if cnt=0 then + o_o <= '1'; + cnt:=COUNT-1; + else + cnt:=cnt-1; + end if; -- cnt/=0 + end if; -- ce_i='1' + end if; -- rising_edge(clk_i) + end process Counter; + end generate CountGen; + + CountWire: + if COUNT=1 generate + o_o <= '0' when reset_i='1' else ce_i; + end generate CountWire; +end architecture Behaviour; -- Entity: BRGen + diff --git a/zpu/hdl/zealot/devices/gpio.vhdl b/zpu/hdl/zealot/devices/gpio.vhdl new file mode 100644 index 0000000..fc66bde --- /dev/null +++ b/zpu/hdl/zealot/devices/gpio.vhdl @@ -0,0 +1,107 @@ +-- +-- this module desribes a simple GPIO interface +-- +-- data on port_in is synhronized to clk_i and can be read at +-- address 0 +-- +-- any write to address 0 is mapped to port_out +-- +-- at address 1 is a direction register (port_dir) +-- initialized with '1's, what mean direction = in +-- this register is useful for bidirectional pins, e.g. headers +-- +-- +-- some examples: +-- +-- to connect 4 buttons: +-- port_in( 3 downto 0) <= gpio_button; +-- +-- +-- to connect 8 LEDs: +-- gpio_led <= port_out(7 downto 0); +-- +-- +-- to connect 2 bidirectional header pins: +-- port_in(8) <= gpio_pin(0); +-- gpio_pin(0) <= port_out(8) when port_dir(8) = '0' else 'Z'; +-- +-- port_in(9) <= gpio_pin(1); +-- gpio_pin(1) <= port_out(9) when port_dir(9) = '0' else 'Z'; +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity gpio is + port( + clk_i : in std_logic; + reset_i : in std_logic; + -- + we_i : in std_logic; + data_i : in unsigned(31 downto 0); + addr_i : in unsigned( 0 downto 0); + data_o : out unsigned(31 downto 0); + -- + port_in : in std_logic_vector(31 downto 0); + port_out : out std_logic_vector(31 downto 0); + port_dir : out std_logic_vector(31 downto 0) + ); +end entity gpio; + + +architecture rtl of gpio is + + signal port_in_reg : std_logic_vector(31 downto 0); + signal port_in_sync : std_logic_vector(31 downto 0); + -- + signal direction : std_logic_vector(31 downto 0) := (others => '1'); + +begin + + process + begin + wait until rising_edge( clk_i); + + -- synchronize all inputs with two registers + -- to avoid metastability + port_in_reg <= port_in; + port_in_sync <= port_in_reg; + + -- write access to gpio + if we_i = '1' then + -- data + if addr_i = "0" then + port_out <= std_logic_vector( data_i); + end if; + -- direction + if addr_i = "1" then + direction <= std_logic_vector( data_i); + end if; + end if; + + -- read access to gpio + -- data + if addr_i = "0" then + data_o <= unsigned( port_in_sync); + end if; + -- direction + if addr_i = "1" then + data_o <= unsigned( direction); + end if; + + -- outputs + port_dir <= direction; + + -- sync reset + if reset_i = '1' then + direction <= (others => '1'); + port_in_reg <= (others => '0'); + port_in_sync <= (others => '0'); + end if; + + end process; + + +end architecture rtl; diff --git a/zpu/hdl/zealot/devices/phi_io.vhdl b/zpu/hdl/zealot/devices/phi_io.vhdl new file mode 100644 index 0000000..6e40d1d --- /dev/null +++ b/zpu/hdl/zealot/devices/phi_io.vhdl @@ -0,0 +1,257 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Phi I/O ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is the minimum I/O devices ---- +---- assumed by the libc. They are a timer and an UART.@p ---- +---- Important! this is currently a simulation only model, no UART ---- +---- provided and it unconditionally generates a log. ---- +---- Important! not all peripherals implemented! ---- +---- Important! The enable signals assumes this is mapped @ 0x80A00xx. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPUPhiIO(Behave) (Entity and architecture) ---- +---- File name: phi_io.vhdl ---- +---- Note: None ---- +---- Limitations: Only for simulation. ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- std.textio ---- +---- zpu.zpupkg ---- +---- zpu.txt_util ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: N/A ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use std.textio.all; + +library zpu; +use zpu.zpupkg.timer; +use zpu.zpupkg.gpio; +use zpu.UART.all; +use zpu.txt_util.all; + +entity ZPUPhiIO is + generic( + BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4 + ENA_LOG : boolean:=true; -- Enable log + LOG_FILE : string:="log.txt"); -- Name for the log file + port( + clk_i : in std_logic; -- System Clock + reset_i : in std_logic; -- Synchronous Reset + busy_o : out std_logic; -- I/O is busy + we_i : in std_logic; -- Write Enable + re_i : in std_logic; -- Read Enable + data_i : in unsigned(31 downto 0); + data_o : out unsigned(31 downto 0); + addr_i : in unsigned(2 downto 0); -- Address bits 4-2 + -- + rs232_rx_i : in std_logic; -- UART Rx input + rs232_tx_o : out std_logic; -- UART Tx output + br_clk_i : in std_logic; -- UART base clock (enable) + -- + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); +end entity ZPUPhiIO; + + +architecture Behave of ZPUPhiIO is + constant LOW_BITS : unsigned(1 downto 0):=(others=>'0'); + constant TX_FULL : std_logic:='0'; + constant RX_EMPTY : std_logic:='1'; + + -- "000" 0x00 is CPU enable ... useful? + constant IO_DATA : unsigned(2 downto 0):="001"; -- 0x04 + constant IO_DIR : unsigned(2 downto 0):="010"; -- 0x08 + constant UART_TX : unsigned(2 downto 0):="011"; -- 0x0C + constant UART_RX : unsigned(2 downto 0):="100"; -- 0x10 + constant CNT_1 : unsigned(2 downto 0):="101"; -- 0x14 + constant CNT_2 : unsigned(2 downto 0):="110"; -- 0x18 + -- "111" 0x1C Unused + -- Unimplemented: Interrupt control and timer (not counter ...?) + + signal timer_read : unsigned(31 downto 0); + signal timer_we : std_logic; + signal is_timer : std_logic; + + -- UART + -- Rx + signal rx_br : std_logic; -- Rx timing + signal uart_read : std_logic; -- ZPU read the value + signal rx_avail : std_logic; -- Rx data available + signal rx_data : std_logic_vector(7 downto 0); -- Rx data + -- Tx + signal tx_br : std_logic; -- Tx timing + signal uart_write : std_logic; -- ZPU is writing + signal tx_busy : std_logic; -- Tx can't get a new value + + -- GPIO + signal gpio_we : std_logic; + signal is_gpio : std_logic; + signal gpio_read : unsigned(31 downto 0); + + file l_file : text open write_mode is LOG_FILE; + +begin + ----------- + -- Timer -- + ----------- + timerinst: Timer + port map( + clk_i => clk_i, reset_i => reset_i, we_i => timer_we, + data_i => data_i, addr_i => addr_i(1 downto 1), + data_o => timer_read); + + busy_o <= we_i or re_i; + is_timer <= '1' when to_01(addr_i)=CNT_1 or to_01(addr_i)=CNT_2 else '0'; -- 0x80A0014/8 + timer_we <= we_i and is_timer; + + ---------- + -- UART -- + ---------- + -- Rx section + rx_core : RxUnit + port map( + clk_i => clk_i, reset_i => reset_i, enable_i => rx_br, + read_i => uart_read, rxd_i => rs232_rx_i, rxav_o => rx_avail, + datao_o => rx_data); + uart_read <= '1' when re_i='1' and addr_i=UART_RX else '0'; + + -- Tx section + tx_core : TxUnit + port map( + clk_i => clk_i, reset_i => reset_i, enable_i => tx_br, + load_i => uart_write, txd_o => rs232_tx_o, busy_o => tx_busy, + datai_i => std_logic_vector(data_i(7 downto 0))); + uart_write <= '1' when we_i='1' and addr_i=UART_TX else '0'; + + -- Rx timing + rx_timer : BRGen + generic map(COUNT => BRDIVISOR) + port map( + clk_i => clk_i, reset_i => reset_i, ce_i => br_clk_i, o_o => rx_br); + + -- Tx timing + tx_timer : BRGen -- 4 Divider for Tx + generic map(COUNT => 4) + port map( + clk_i => clk_i, reset_i => reset_i, ce_i => rx_br, o_o => tx_br); + + ---------- + -- GPIO -- + ---------- + gpio_i0: gpio + port map( + clk_i => clk_i, -- : in std_logic; + reset_i => reset_i, -- : in std_logic; + -- + we_i => gpio_we, -- : in std_logic; + data_i => data_i, -- : in unsigned(31 downto 0); + addr_i => addr_i(1 downto 1), -- : in unsigned( 0 downto 0); + data_o => gpio_read, -- : out unsigned(31 downto 0); + -- + port_in => gpio_in, -- : std_logic_vector(31 downto 0); + port_out => gpio_out, -- : std_logic_vector(31 downto 0); + port_dir => gpio_dir -- : std_logic_vector(31 downto 0); + ); + is_gpio <= '1' when to_01(addr_i) = IO_DATA or to_01(addr_i) = IO_DIR else '0'; -- 0x80A0004/8 + gpio_we <= we_i and is_gpio; + + + do_io: + process(clk_i) + --synopsys translate off + variable line_out : line := new string'(""); + variable char : character; + --synopsys translate on + begin + if rising_edge(clk_i) then + if reset_i/='1' then + --synopsys translate off + if we_i='1' then + if addr_i=UART_TX and ENA_LOG then -- 0x80a000c + -- Write to UART + print("- Write to UART Tx: 0x" &hstr(data_i)&" ("& + character'val(to_integer(data_i) mod 256)&")"); + char := character'val(to_integer(data_i)); + if char = lf then + std.textio.writeline(l_file, line_out); + else + std.textio.write(line_out, char); + end if; + elsif is_gpio = '1' and ENA_LOG then + print("- Write GPIO: 0x" & hstr(data_i)); + elsif is_timer='1' and ENA_LOG then + print("- Write to TIMER: 0x" & hstr(data_i)); + else + --print(l_file,character'val(to_integer(data_i))); + report "Illegal IO data_i=0x"&hstr(data_i)&" @0x"& + hstr(x"80a00"&"000"&addr_i&"00") severity warning; + end if; + end if; + --synopsys translate on + data_o <= (others => '0'); + if re_i='1' then + if is_gpio = '1' then + if ENA_LOG then + print("- Read GPIO: 0x" & hstr(gpio_read)); + end if; + data_o <= gpio_read; + elsif addr_i=UART_TX then + if ENA_LOG then + print("- Read UART Tx"); + end if; + data_o(8) <= not(tx_busy); -- output fifo not full + elsif addr_i=UART_RX then + if ENA_LOG then + print("- Read UART Rx"); + end if; + data_o(8) <= rx_avail; -- receiver not empty + data_o(7 downto 0) <= unsigned(rx_data); + elsif is_timer='1' then + if ENA_LOG then + print("- Read TIMER: 0x" & hstr(timer_read)); + end if; + data_o <= timer_read; + else + report "Illegal IO data_o @0x"& + hstr(x"80a00"&"000"&addr_i&"00") severity warning; + end if; + end if; -- re_i='1' + end if; -- reset_i/='1' + end if; -- rising_edge(clk_i) + end process do_io; +end Behave; + diff --git a/zpu/hdl/zealot/devices/rx_unit.vhdl b/zpu/hdl/zealot/devices/rx_unit.vhdl new file mode 100644 index 0000000..e9b3251 --- /dev/null +++ b/zpu/hdl/zealot/devices/rx_unit.vhdl @@ -0,0 +1,108 @@ +------------------------------------------------------------------------------ +---- ---- +---- RS-232 simple Rx module ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- Implements a simple 8N1 rx module for RS-232. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Philippe Carton, philippe.carton2 libertysurf.fr ---- +---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2001-2003 Philippe Carton ---- +---- Copyright (c) 2005 Juan Pablo Daniel Borgna ---- +---- Copyright (c) 2005-2008 Salvador E. Tropea ---- +---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: RxUnit(Behaviour) (Entity and architecture) ---- +---- File name: rx_unit.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- Target FPGA: Spartan ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity RxUnit is + port( + clk_i : in std_logic; -- System clock signal + reset_i : in std_logic; -- Reset input (sync) + enable_i : in std_logic; -- Enable input (rate*4) + read_i : in std_logic; -- Received Byte Read + rxd_i : in std_logic; -- RS-232 data input + rxav_o : out std_logic; -- Byte available + datao_o : out std_logic_vector(7 downto 0)); -- Byte received +end entity RxUnit; + +architecture Behaviour of RxUnit is + signal r_r : std_logic_vector(7 downto 0); -- Receive register + signal bavail_r : std_logic:='0'; -- Byte received +begin + rxav_o <= bavail_r; + -- Rx Process + RxProc: + process (clk_i) + variable bitpos : integer range 0 to 10; -- Position of the bit in the frame + variable samplecnt : integer range 0 to 3; -- Count from 0 to 3 in each bit + begin + if rising_edge(clk_i) then + if reset_i='1' then + bavail_r <= '0'; + bitpos:=0; + else -- reset_i='0' + if read_i='1' then + bavail_r <= '0'; + end if; + if enable_i='1' then + case bitpos is + when 0 => -- idle + bavail_r <= '0'; + if rxd_i='0' then -- Start Bit + samplecnt:=0; + bitpos:=1; + end if; + when 10 => -- Stop Bit + bitpos:=0; -- next is idle + bavail_r <= '1'; -- Indicate byte received + datao_o <= r_r; -- Store received byte + when others => + if samplecnt=1 and bitpos>=2 then -- Sample RxD on 1 + r_r(bitpos-2) <= rxd_i; -- Deserialisation + end if; + if samplecnt=3 then -- Increment BitPos on 3 + bitpos:=bitpos+1; + end if; + end case; + if samplecnt=3 then + samplecnt:=0; + else + samplecnt:=samplecnt+1; + end if; + end if; -- enable_i='1' + end if; -- reset_i='0' + end if; -- rising_edge(clk_i) + end process RxProc; +end architecture Behaviour; + diff --git a/zpu/hdl/zealot/devices/timer.vhdl b/zpu/hdl/zealot/devices/timer.vhdl new file mode 100644 index 0000000..389868c --- /dev/null +++ b/zpu/hdl/zealot/devices/timer.vhdl @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------ +---- ---- +---- 64 bits clock counter ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a peripheral used by the PHI I/O layout. It just counts the ---- +---- elapsed number of clocks. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Timer(Behave) (Entity and architecture) ---- +---- File name: timer.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity Timer is + port( + clk_i : in std_logic; + reset_i : in std_logic; + we_i : in std_logic; + data_i : in unsigned(31 downto 0); + addr_i : in unsigned(0 downto 0); + data_o : out unsigned(31 downto 0)); +end entity Timer; + +architecture Behave of Timer is + signal sample : std_logic; + signal reset : std_logic; + + signal cnt : unsigned(63 downto 0); + signal cnt_smp : unsigned(63 downto 0); +begin + reset <= '1' when (we_i='1' and data_i(0)='1') else '0'; + sample <= '1' when (we_i='1' and data_i(1)='1') else '0'; + + -- Carry generation + do_timer: + process (clk_i) + begin + if rising_edge(clk_i) then + if reset_i='1' or reset='1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + else + cnt <= cnt+1; + if sample='1' then + -- report "sampling" severity failure; + cnt_smp <= cnt; + end if; + end if; -- else reset_i='1' + end if; -- rising_edge(clk_i) + end process do_timer; + + data_o <= cnt_smp(31 downto 0) when to_01(addr_i)="0" else + cnt_smp(63 downto 32); +end architecture Behave; -- Entity: Timer + diff --git a/zpu/hdl/zealot/devices/trace.vhdl b/zpu/hdl/zealot/devices/trace.vhdl new file mode 100644 index 0000000..83d3782 --- /dev/null +++ b/zpu/hdl/zealot/devices/trace.vhdl @@ -0,0 +1,258 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Trace Module ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is a module to log an ---- +---- execution trace. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Trace(Behave) (Entity and architecture) ---- +---- File name: trace.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- std.textio ---- +---- zpu.zpupkg ---- +---- zpu.txt_util ---- +---- Target FPGA: N/A ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: N/A ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use std.textio.all; + +library zpu; +use zpu.zpupkg.all; +use zpu.txt_util.all; + +entity Trace is + generic( + LOG_FILE : string:="trace.txt"; -- Name of the trace file + ADDR_W : integer:=16; -- Address width + WORD_SIZE : integer:=32); -- 16/32 + port( + clk_i : in std_logic; + dbg_i : in zpu_dbgo_t; + stop_i : in std_logic; + busy_i : in std_logic + ); +end entity Trace; + +architecture Behave of Trace is + file l_file : text open write_mode is LOG_FILE; + signal counter : unsigned(63 downto 0); +begin + -- write data and control information to a file + receive_data: + process + variable l : line; + variable stk_min : unsigned(31 downto 0):=(others => '1'); + variable stk_ini : unsigned(31 downto 0); + variable first : boolean:=true; + variable sp_off : unsigned(4 downto 0); + variable idim : boolean:=false; + variable im_val : unsigned(31 downto 0):=(others => '0'); + begin + counter <= to_unsigned(1,64); + -- print header for the logfile + print(l_file,"#PC Opcode SP A=[SP] B=[SP+1] Clk Counter Assembler"); + print(l_file,"#---------------------------------------------------------------------------"); + print(l_file," "); + + wait until clk_i='1'; + wait until clk_i='0'; + + while true loop + counter <= counter+1; + if dbg_i.b_inst='1' then + write(l, "0x"&hstr(dbg_i.pc(ADDR_W-1 downto 0))& + " 0x"&hstr(dbg_i.opcode)& + " 0x"&hstr(dbg_i.sp)& + " 0x"&hstr(dbg_i.stk_a)& + " 0x"&hstr(dbg_i.stk_b)& + " 0x"&hstr(counter)&" "); + -------------------------- + -- Instruction Decoder -- + -------------------------- + sp_off(4):=not dbg_i.opcode(4); + sp_off(3 downto 0):=dbg_i.opcode(3 downto 0); + if dbg_i.opcode(7 downto 7)=OPCODE_IM then + if idim then + im_val(31 downto 7):=im_val(24 downto 0); + im_val(6 downto 0):=dbg_i.opcode(6 downto 0); + else + im_val:=unsigned(resize(signed(dbg_i.opcode(6 downto 0)),32)); + end if; + idim:=true; + write(l,"im 0x"&hstr(dbg_i.opcode(6 downto 0))&" ; 0x"&hstr(im_val)); + elsif dbg_i.opcode(7 downto 5)=OPCODE_STORESP then + if sp_off=0 then + write(l,string'("storesp 0 ; pop")); + elsif sp_off=1 then + write(l,string'("storesp 4 ; 1*4 = popdown")); + else + write(l,"storesp "&integer'image(to_integer(sp_off)*4)&" ; "& + integer'image(to_integer(sp_off))&"*4"); + end if; + elsif dbg_i.opcode(7 downto 5)=OPCODE_LOADSP then + if sp_off=0 then + write(l,string'("loadsp 0 ; dup")); + elsif sp_off=1 then + write(l,string'("loadsp 4 ; 1*4 = dupstkb")); + else + write(l,"loadsp "&integer'image(to_integer(sp_off)*4)&" ; "& + integer'image(to_integer(sp_off))&"*4"); + end if; + elsif dbg_i.opcode(7 downto 5)=OPCODE_EMULATE then + if dbg_i.opcode(5 downto 0)=OPCODE_EQ then + write(l,string'("eq")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADB then + write(l,string'("loadb")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQBRANCH then + write(l,string'("neqbranch")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHSPADD then + write(l,string'("pushspadd")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHAN then + write(l,string'("lessthan")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHAN then + write(l,string'("ulessthan")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_MULT then + write(l,string'("mult")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREB then + write(l,string'("storeb")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_CALLPCREL then + write(l,string'("callpcrel")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_SUB then + write(l,string'("sub")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then + write(l,string'("lessthanorequal")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then + write(l,string'("ulessthanorequal")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_CALL then + write(l,string'("call")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_POPPCREL then + write(l,string'("poppcrel")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LSHIFTRIGHT then + write(l,string'("lshiftright")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADH then + write(l,string'("loadh")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREH then + write(l,string'("storeh")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTLEFT then + write(l,string'("ashiftleft")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTRIGHT then + write(l,string'("ashiftright")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQ then + write(l,string'("neq")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_NEG then + write(l,string'("neg")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_XOR then + write(l,string'("xor")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_DIV then + write(l,string'("div")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_MOD then + write(l,string'("mod")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_EQBRANCH then + write(l,string'("eqbranch")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_CONFIG then + write(l,string'("config")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHPC then + write(l,string'("pushpc")); + else + write(l,integer'image(to_integer(dbg_i.opcode(5 downto 0)))& + " ; invalid emulated instruction"); + end if; + elsif dbg_i.opcode(7 downto 4)=OPCODE_ADDSP then + if sp_off=0 then + write(l,string'("addsp 0 ; shift")); + elsif sp_off=1 then + write(l,string'("addsp 4 ; 1*4 = addtop")); + else + write(l,"addsp "&integer'image(to_integer(sp_off)*4)&" ; "& + integer'image(to_integer(sp_off))&"*4"); + end if; + else -- OPCODE_SHORT + case dbg_i.opcode(3 downto 0) is + when OPCODE_BREAK => + write(l,string'("break")); + when OPCODE_PUSHSP => + write(l,string'("pushsp")); + when OPCODE_POPPC => + write(l,string'("poppc")); + when OPCODE_ADD => + write(l,string'("add")); + when OPCODE_OR => + write(l,string'("or")); + when OPCODE_AND => + write(l,string'("and")); + when OPCODE_LOAD => + write(l,string'("load")); + when OPCODE_NOT => + write(l,string'("not")); + when OPCODE_FLIP => + write(l,string'("flip")); + when OPCODE_STORE => + write(l,string'("store")); + when OPCODE_POPSP => + write(l,string'("popsp")); + when OPCODE_NOP => + write(l,string'("nop")); + when others => + write(l,integer'image(to_integer(dbg_i.opcode))& + " ; invalid instruction"); + end case; + end if; + if dbg_i.opcode(7 downto 7)/=OPCODE_IM then + idim:=false; + end if; + ----------------------------- + -- End Instruction Decoder -- + ----------------------------- + writeline(l_file,l); + if dbg_i.sp<stk_min then + stk_min:=dbg_i.sp; + end if; + if first then + stk_ini:=dbg_i.sp+8; + first:=false; + end if; + end if; + wait until clk_i='0' or stop_i='1'; + if stop_i='1' then + print(output,"Minimum SP: 0x"&hstr(stk_min)&" Size: 0x"&hstr(stk_ini-stk_min)); + wait; + end if; + end loop; + end process receive_data; +end Behave; + diff --git a/zpu/hdl/zealot/devices/tx_unit.vhdl b/zpu/hdl/zealot/devices/tx_unit.vhdl new file mode 100644 index 0000000..73293f6 --- /dev/null +++ b/zpu/hdl/zealot/devices/tx_unit.vhdl @@ -0,0 +1,109 @@ +------------------------------------------------------------------------------ +---- ---- +---- RS-232 simple Tx module ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- Implements a simple 8N1 tx module for RS-232. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Philippe Carton, philippe.carton2 libertysurf.fr ---- +---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2001-2003 Philippe Carton ---- +---- Copyright (c) 2005 Juan Pablo Daniel Borgna ---- +---- Copyright (c) 2005-2008 Salvador E. Tropea ---- +---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: TxUnit(Behaviour) (Entity and architecture) ---- +---- File name: Txunit.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- zpu.UART ---- +---- Target FPGA: Spartan ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +library zpu; +use zpu.UART.all; + +entity TxUnit is + port ( + clk_i : in std_logic; -- Clock signal + reset_i : in std_logic; -- Reset input + enable_i : in std_logic; -- Enable input + load_i : in std_logic; -- Load input + txd_o : out std_logic; -- RS-232 data output + busy_o : out std_logic; -- Tx Busy + datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit +end entity TxUnit; + +architecture Behaviour of TxUnit is + signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer + signal t_r : std_logic_vector(7 downto 0); -- transmit register + signal loaded_r : std_logic:='0'; -- Buffer loaded + signal txd_r : std_logic:='1'; -- Tx buffer ready +begin + busy_o <= load_i or loaded_r; + txd_o <= txd_r; + + -- Tx process + TxProc: + process (clk_i) + variable bitpos : integer range 0 to 10; -- Bit position in the frame + begin + if rising_edge(clk_i) then + if reset_i='1' then + loaded_r <= '0'; + bitpos:=0; + txd_r <= '1'; + else -- reset_i='0' + if load_i='1' then + tbuff_r <= datai_i; + loaded_r <= '1'; + end if; + if enable_i='1' then + case bitpos is + when 0 => -- idle or stop bit + txd_r <= '1'; + if loaded_r='1' then -- start transmit. next is start bit + t_r <= tbuff_r; + loaded_r <= '0'; + bitpos:=1; + end if; + when 1 => -- Start bit + txd_r <= '0'; + bitpos:=2; + when others => + txd_r <= t_r(bitpos-2); -- Serialisation of t_r + bitpos:=bitpos+1; + end case; + if bitpos=10 then -- bit8. next is stop bit + bitpos:=0; + end if; + end if; -- enable_i='1' + end if; -- reset_i='0' + end if; -- rising_edge(clk_i) + end process TxProc; +end architecture Behaviour; diff --git a/zpu/hdl/zealot/devices/txt_util.vhdl b/zpu/hdl/zealot/devices/txt_util.vhdl new file mode 100644 index 0000000..862611c --- /dev/null +++ b/zpu/hdl/zealot/devices/txt_util.vhdl @@ -0,0 +1,541 @@ +------------------------------------------------------------------------------ +---- ---- +---- Text Utils ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- Utils to handle text. Used for the testbenches. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: txt_util (Package) ---- +---- File name: txt_util.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- std.textio ---- +---- Target FPGA: N/A ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use std.textio.all; + +library zpu; + +package txt_util is + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + function hstr(slv: unsigned) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + procedure str_write(file out_file: TEXT; + new_string: in string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); +end package txt_util; + + + + +package body txt_util is + -- prints text to the screen + procedure print(text: string) is + variable msg_line: line; + begin + --synopsys translate off + write(msg_line, text); + writeline(output, msg_line); + --synopsys translate on + end procedure print; + + -- prints text to the screen when active + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end procedure print; + + -- converts std_logic into a character + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end function chr; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1):=chr(sl); + return s; + end function str; + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r:=1; + for i in slv'range loop + result(r) := chr(slv(i)); + r:=r+1; + end loop; + return result; + end function str; + + + function str(b: boolean) return string is + begin + if b then + return "true"; + else + return "false"; + end if; + end function str; + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end function chr; + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + function str(int: integer; base: integer) return string is + variable temp : string(1 to 10); + variable num : integer; + variable abs_int : integer; + variable len : integer:=1; + variable power : integer:=1; + begin + -- bug fix for negative numbers + abs_int:=abs(int); + + num :=abs_int; + + while num>=base loop -- Determine how many + len:=len+1; -- characters required + num:=num/base; -- to represent the + end loop; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i):=chr(abs_int/power mod base); -- a string starting + power:=power*base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int<0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + end function str; + + -- convert integer to string, using base 10 + function str(int: integer) return string is + begin + return str(int, 10) ; + end function str; + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0):=(others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen:=(slv'left+1)/4; + if (slv'left+1) mod 4/=0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen-1) downto 0 loop + fourbit:=longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen-I):='0'; + when "0001" => hex(hexlen-I):='1'; + when "0010" => hex(hexlen-I):='2'; + when "0011" => hex(hexlen-I):='3'; + when "0100" => hex(hexlen-I):='4'; + when "0101" => hex(hexlen-I):='5'; + when "0110" => hex(hexlen-I):='6'; + when "0111" => hex(hexlen-I):='7'; + when "1000" => hex(hexlen-I):='8'; + when "1001" => hex(hexlen-I):='9'; + when "1010" => hex(hexlen-I):='A'; + when "1011" => hex(hexlen-I):='B'; + when "1100" => hex(hexlen-I):='C'; + when "1101" => hex(hexlen-I):='D'; + when "1110" => hex(hexlen-I):='E'; + when "1111" => hex(hexlen-I):='F'; + when "ZZZZ" => hex(hexlen-I):='z'; + when "UUUU" => hex(hexlen-I):='u'; + when "XXXX" => hex(hexlen-I):='x'; + when others => hex(hexlen-I):='?'; + end case; + end loop; + return hex(1 to hexlen); + end function hstr; + + function hstr(slv: unsigned) return string is + begin + return hstr(std_logic_vector(slv)); + end function hstr; + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + function to_upper(c: character) return character is + variable u: character; + begin + case c is + when 'a' => u:='A'; + when 'b' => u:='B'; + when 'c' => u:='C'; + when 'd' => u:='D'; + when 'e' => u:='E'; + when 'f' => u:='F'; + when 'g' => u:='G'; + when 'h' => u:='H'; + when 'i' => u:='I'; + when 'j' => u:='J'; + when 'k' => u:='K'; + when 'l' => u:='L'; + when 'm' => u:='M'; + when 'n' => u:='N'; + when 'o' => u:='O'; + when 'p' => u:='P'; + when 'q' => u:='Q'; + when 'r' => u:='R'; + when 's' => u:='S'; + when 't' => u:='T'; + when 'u' => u:='U'; + when 'v' => u:='V'; + when 'w' => u:='W'; + when 'x' => u:='X'; + when 'y' => u:='Y'; + when 'z' => u:='Z'; + when others => u:=c; + end case; + return u; + end function to_upper; + + + -- convert a character to lower case + function to_lower(c: character) return character is + variable l: character; + begin + case c is + when 'A' => l:='a'; + when 'B' => l:='b'; + when 'C' => l:='c'; + when 'D' => l:='d'; + when 'E' => l:='e'; + when 'F' => l:='f'; + when 'G' => l:='g'; + when 'H' => l:='h'; + when 'I' => l:='i'; + when 'J' => l:='j'; + when 'K' => l:='k'; + when 'L' => l:='l'; + when 'M' => l:='m'; + when 'N' => l:='n'; + when 'O' => l:='o'; + when 'P' => l:='p'; + when 'Q' => l:='q'; + when 'R' => l:='r'; + when 'S' => l:='s'; + when 'T' => l:='t'; + when 'U' => l:='u'; + when 'V' => l:='v'; + when 'W' => l:='w'; + when 'X' => l:='x'; + when 'Y' => l:='y'; + when 'Z' => l:='z'; + when others => l:=c; + end case; + return l; + end function to_lower; + + -- convert a string to upper case + function to_upper(s: string) return string is + variable uppercase: string (s'range); + begin + for i in s'range loop + uppercase(i):=to_upper(s(i)); + end loop; + return uppercase; + end to_upper; + + -- convert a string to lower case + function to_lower(s: string) return string is + variable lowercase: string (s'range); + begin + for i in s'range loop + lowercase(i):=to_lower(s(i)); + end loop; + return lowercase; + end to_lower; + + -- functions to convert strings into other types + + -- converts a character into a std_logic + + function to_std_logic(c: character) return std_logic is + variable sl : std_logic; + begin + case c is + when 'U' => + sl:='U'; + when 'X' => + sl:='X'; + when '0' => + sl:='0'; + when '1' => + sl:='1'; + when 'Z' => + sl:='Z'; + when 'W' => + sl:='W'; + when 'L' => + sl:='L'; + when 'H' => + sl:='H'; + when '-' => + sl:='-'; + when others => + sl:='X'; + end case; + return sl; + end function to_std_logic; + + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector is + variable slv : std_logic_vector(s'high-s'low downto 0); + variable k : integer; + begin + k:=s'high-s'low; + for i in s'range loop + slv(k):=to_std_logic(s(i)); + k :=k-1; + end loop; + return slv; + end function to_std_logic_vector; + + + ---------------- + -- file I/O -- + ---------------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string) is + variable l : line; + variable c : character; + variable is_string : boolean; + begin + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i):=' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l,c,is_string); + res_string(i):=c; + if not is_string then -- found end of line + exit; + end if; + end loop; + end procedure str_read; + + -- print string to a file + procedure print(file out_file: TEXT; + new_string: in string) is + variable l: line; + begin + write(l,new_string); + writeline(out_file,l); + end procedure print; + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character) is + variable l: line; + begin + write(l,char); + writeline(out_file,l); + end procedure print; + + -- appends contents of a string to a file until line feed occurs + -- (LF is considered to be the end of the string) + procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + for i in new_string'range loop + print(out_file,new_string(i)); + if new_string(i)=LF then -- end of string + exit; + end if; + end loop; + end str_write; +end package body txt_util; + diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh new file mode 100755 index 0000000..d525737 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/gpio.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do new file mode 100644 index 0000000..acc1710 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do +run -all diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do new file mode 100644 index 0000000..3f5d4fe --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /top_tb/tb_reset_n +add wave -noupdate /top_tb/tb_clk +add wave -noupdate -divider <NULL> +add wave -noupdate /top_tb/tb_rs232_rx +add wave -noupdate /top_tb/tb_rs232_tx +add wave -noupdate /top_tb/tb_rs232_rts +add wave -noupdate /top_tb/tb_rs232_cts +add wave -noupdate -divider Buttons +add wave -noupdate /top_tb/tb_button_n +add wave -noupdate -divider LEDs +add wave -noupdate /top_tb/tb_led +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 2 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {1294218073 ps} {1421130628 ps} diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh new file mode 100755 index 0000000..a7180fc --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/altium-livedesign-xc3s1000.ucf -p xc3s1000-fg456-4 top.ngc top.ngd +map -p xc3s1000-fg456-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf +par -w -ol high -t 1 top_map.ncd top.ncd top.pcf +trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf new file mode 100644 index 0000000..ba22ee9 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf @@ -0,0 +1,397 @@ +############################################################ +# Altium Livedesign Evaluation Board constraints file +# +# Familiy: Spartan-3 +# Device: XC3S1000 +# Package: FG456C +# Speed: -4 +# +# all banks are powered with 3.3V +# +# config pins (M2, M1, M0): 101 + +############################################################ +## clock/timing constraints +############################################################ + +NET "clk_50" period = 50 MHz ; + + +############################################################ +## pin placement constraints +############################################################ + +NET "clk_50" LOC = AA12 | IOSTANDARD = LVCMOS33; +NET "reset_n" LOC = Y17 | IOSTANDARD = LVCMOS33; # low active + +# Soft JTAG +NET "soft_tdo" LOC = D22 | IOSTANDARD = LVCMOS33; +NET "soft_tms" LOC = E21 | IOSTANDARD = LVCMOS33; +NET "soft_tdi" LOC = E22 | IOSTANDARD = LVCMOS33; +NET "soft_tck" LOC = F21 | IOSTANDARD = LVCMOS33; + +# SRAM 0 +NET "sram0_a<0>" LOC = L6 | IOSTANDARD = LVCMOS33; +NET "sram0_a<1>" LOC = K4 | IOSTANDARD = LVCMOS33; +NET "sram0_a<2>" LOC = H5 | IOSTANDARD = LVCMOS33; +NET "sram0_a<3>" LOC = G6 | IOSTANDARD = LVCMOS33; +NET "sram0_a<4>" LOC = F3 | IOSTANDARD = LVCMOS33; +NET "sram0_a<5>" LOC = G1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<6>" LOC = G2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<7>" LOC = K3 | IOSTANDARD = LVCMOS33; +NET "sram0_a<8>" LOC = T2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<9>" LOC = T1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<10>" LOC = U2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<11>" LOC = V3 | IOSTANDARD = LVCMOS33; +NET "sram0_a<12>" LOC = V1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<13>" LOC = W1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<14>" LOC = V2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<15>" LOC = V5 | IOSTANDARD = LVCMOS33; +NET "sram0_a<16>" LOC = V4 | IOSTANDARD = LVCMOS33; +NET "sram0_a<17>" LOC = U5 | IOSTANDARD = LVCMOS33; +NET "sram0_a<18>" LOC = U6 | IOSTANDARD = LVCMOS33; # n.c. +NET "sram0_d<0>" LOC = L4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<1>" LOC = L3 | IOSTANDARD = LVCMOS33; +NET "sram0_d<2>" LOC = M5 | IOSTANDARD = LVCMOS33; +NET "sram0_d<3>" LOC = M4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<4>" LOC = M3 | IOSTANDARD = LVCMOS33; +NET "sram0_d<5>" LOC = N4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<6>" LOC = N3 | IOSTANDARD = LVCMOS33; +NET "sram0_d<7>" LOC = T5 | IOSTANDARD = LVCMOS33; +NET "sram0_d<8>" LOC = T4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<9>" LOC = T6 | IOSTANDARD = LVCMOS33; +NET "sram0_d<10>" LOC = M6 | IOSTANDARD = LVCMOS33; +NET "sram0_d<11>" LOC = N2 | IOSTANDARD = LVCMOS33; +NET "sram0_d<12>" LOC = N1 | IOSTANDARD = LVCMOS33; +NET "sram0_d<13>" LOC = M2 | IOSTANDARD = LVCMOS33; +NET "sram0_d<14>" LOC = M1 | IOSTANDARD = LVCMOS33; +NET "sram0_d<15>" LOC = L2 | IOSTANDARD = LVCMOS33; +NET "sram0_cs_n" LOC = L5 | IOSTANDARD = LVCMOS33; +NET "sram0_lb_n" LOC = L1 | IOSTANDARD = LVCMOS33; +NET "sram0_ub_n" LOC = K2 | IOSTANDARD = LVCMOS33; +NET "sram0_we_n" LOC = U4 | IOSTANDARD = LVCMOS33; +NET "sram0_oe_n" LOC = K1 | IOSTANDARD = LVCMOS33; + +# SRAM 1 +NET "sram1_a<0>" LOC = K21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<1>" LOC = K22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<2>" LOC = K20 | IOSTANDARD = LVCMOS33; +NET "sram1_a<3>" LOC = G21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<4>" LOC = G22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<5>" LOC = M17 | IOSTANDARD = LVCMOS33; +NET "sram1_a<6>" LOC = L18 | IOSTANDARD = LVCMOS33; +NET "sram1_a<7>" LOC = K19 | IOSTANDARD = LVCMOS33; +NET "sram1_a<8>" LOC = V19 | IOSTANDARD = LVCMOS33; +NET "sram1_a<9>" LOC = W20 | IOSTANDARD = LVCMOS33; +NET "sram1_a<10>" LOC = W19 | IOSTANDARD = LVCMOS33; +NET "sram1_a<11>" LOC = Y20 | IOSTANDARD = LVCMOS33; +NET "sram1_a<12>" LOC = Y21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<13>" LOC = Y22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<14>" LOC = W21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<15>" LOC = W22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<16>" LOC = V21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<17>" LOC = V22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<18>" LOC = V20 | IOSTANDARD = LVCMOS33; # n.c. +NET "sram1_d<0>" LOC = L21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<1>" LOC = M22 | IOSTANDARD = LVCMOS33; +NET "sram1_d<2>" LOC = M21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<3>" LOC = N22 | IOSTANDARD = LVCMOS33; +NET "sram1_d<4>" LOC = N21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<5>" LOC = U20 | IOSTANDARD = LVCMOS33; +NET "sram1_d<6>" LOC = T22 | IOSTANDARD = LVCMOS33; +NET "sram1_d<7>" LOC = T21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<8>" LOC = V18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<9>" LOC = U19 | IOSTANDARD = LVCMOS33; +NET "sram1_d<10>" LOC = U18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<11>" LOC = T18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<12>" LOC = R18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<13>" LOC = T17 | IOSTANDARD = LVCMOS33; +NET "sram1_d<14>" LOC = M18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<15>" LOC = M20 | IOSTANDARD = LVCMOS33; +NET "sram1_cs_n" LOC = L22 | IOSTANDARD = LVCMOS33; +NET "sram1_lb_n" LOC = M19 | IOSTANDARD = LVCMOS33; +NET "sram1_ub_n" LOC = L20 | IOSTANDARD = LVCMOS33; +NET "sram1_we_n" LOC = U21 | IOSTANDARD = LVCMOS33; +NET "sram1_oe_n" LOC = L19 | IOSTANDARD = LVCMOS33; + +# RS232 +NET "rs232_rx" LOC = A5 | IOSTANDARD = LVCMOS33; +NET "rs232_tx" LOC = F7 | IOSTANDARD = LVCMOS33; +NET "rs232_cts" LOC = F2 | IOSTANDARD = LVCMOS33; +NET "rs232_rts" LOC = E1 | IOSTANDARD = LVCMOS33; + +# 2x PS2 connectors +NET "mouse_clk" LOC = L17 | IOSTANDARD = LVCMOS33; +NET "mouse_data" LOC = G18 | IOSTANDARD = LVCMOS33; +NET "kbd_clk" LOC = F20 | IOSTANDARD = LVCMOS33; +NET "kbd_data" LOC = G19 | IOSTANDARD = LVCMOS33; + + +# VGA output (2**9 = 512 colors) +NET "vga_blue<7>" LOC = E14 | IOSTANDARD = LVCMOS33; +NET "vga_blue<6>" LOC = A13 | IOSTANDARD = LVCMOS33; +NET "vga_blue<5>" LOC = C13 | IOSTANDARD = LVCMOS33; +NET "vga_green<7>" LOC = E11 | IOSTANDARD = LVCMOS33; +NET "vga_green<6>" LOC = C11 | IOSTANDARD = LVCMOS33; +NET "vga_green<5>" LOC = D10 | IOSTANDARD = LVCMOS33; +NET "vga_red<7>" LOC = D6 | IOSTANDARD = LVCMOS33; +NET "vga_red<6>" LOC = D7 | IOSTANDARD = LVCMOS33; +NET "vga_red<5>" LOC = D9 | IOSTANDARD = LVCMOS33; +NET "vga_hsync" LOC = A8 | IOSTANDARD = LVCMOS33; +NET "vga_vsync" LOC = B14 | IOSTANDARD = LVCMOS33; + + +# Stereo Audio out +NET "audio_r" LOC = U3 | IOSTANDARD = LVCMOS33; +NET "audio_l" LOC = W3 | IOSTANDARD = LVCMOS33; + + +# GPIO DIP switches 7..0 left..right, low active +NET "switch_n<0>" LOC = Y6 | IOSTANDARD = LVCMOS33; +NET "switch_n<1>" LOC = V6 | IOSTANDARD = LVCMOS33; +NET "switch_n<2>" LOC = U7 | IOSTANDARD = LVCMOS33; +NET "switch_n<3>" LOC = AA4 | IOSTANDARD = LVCMOS33; +NET "switch_n<4>" LOC = AB4 | IOSTANDARD = LVCMOS33; +NET "switch_n<5>" LOC = AA5 | IOSTANDARD = LVCMOS33; +NET "switch_n<6>" LOC = AB5 | IOSTANDARD = LVCMOS33; +NET "switch_n<7>" LOC = AA6 | IOSTANDARD = LVCMOS33; + +# GPIO push buttons, low active +NET "button_n<5>" LOC = C21 | IOSTANDARD = LVCMOS33; +NET "button_n<4>" LOC = B20 | IOSTANDARD = LVCMOS33; +NET "button_n<3>" LOC = A15 | IOSTANDARD = LVCMOS33; +NET "button_n<2>" LOC = B6 | IOSTANDARD = LVCMOS33; +NET "button_n<1>" LOC = C1 | IOSTANDARD = LVCMOS33; +NET "button_n<0>" LOC = D1 | IOSTANDARD = LVCMOS33; + +# GPIO LEDs +NET "led<7>" LOC = W6 | IOSTANDARD = LVCMOS33; +NET "led<6>" LOC = Y5 | IOSTANDARD = LVCMOS33; +NET "led<5>" LOC = W5 | IOSTANDARD = LVCMOS33; +NET "led<4>" LOC = W4 | IOSTANDARD = LVCMOS33; +NET "led<3>" LOC = Y3 | IOSTANDARD = LVCMOS33; +NET "led<2>" LOC = Y2 | IOSTANDARD = LVCMOS33; +NET "led<1>" LOC = Y1 | IOSTANDARD = LVCMOS33; +NET "led<0>" LOC = W2 | IOSTANDARD = LVCMOS33; + +# seven segment display (5=left 0=right) +# +# segment assignment: +# .ABCDEFG +# 76543210 +NET "dig0_seg<7>" LOC = E20 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<6>" LOC = C22 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<5>" LOC = E18 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<4>" LOC = D20 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<3>" LOC = D21 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<2>" LOC = E19 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<1>" LOC = G17 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<0>" LOC = F19 | IOSTANDARD = LVCMOS33; + +NET "dig1_seg<7>" LOC = F17 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<6>" LOC = D18 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<5>" LOC = B19 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<4>" LOC = C18 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<3>" LOC = C19 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<2>" LOC = C20 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<1>" LOC = F18 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<0>" LOC = D19 | IOSTANDARD = LVCMOS33; + +NET "dig2_seg<7>" LOC = A19 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<6>" LOC = E17 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<5>" LOC = C17 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<4>" LOC = D17 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<3>" LOC = B15 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<2>" LOC = A18 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<1>" LOC = B18 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<0>" LOC = B17 | IOSTANDARD = LVCMOS33; + +NET "dig3_seg<7>" LOC = D15 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<6>" LOC = E13 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<5>" LOC = B13 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<4>" LOC = D13 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<3>" LOC = D14 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<2>" LOC = A14 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<1>" LOC = E16 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<0>" LOC = E15 | IOSTANDARD = LVCMOS33; + +NET "dig4_seg<7>" LOC = D11 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<6>" LOC = E9 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<5>" LOC = A10 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<4>" LOC = B9 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<3>" LOC = A9 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<2>" LOC = C10 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<1>" LOC = A12 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<0>" LOC = B10 | IOSTANDARD = LVCMOS33; + +NET "dig5_seg<7>" LOC = C7 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<6>" LOC = A4 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<5>" LOC = B5 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<4>" LOC = E6 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<3>" LOC = C5 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<2>" LOC = E7 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<1>" LOC = B8 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<0>" LOC = C6 | IOSTANDARD = LVCMOS33; + + +# Header A (left) +NET "header_a<2>" LOC = V7 | IOSTANDARD = LVCMOS33; +NET "header_a<3>" LOC = AA8 | IOSTANDARD = LVCMOS33; +NET "header_a<4>" LOC = AB8 | IOSTANDARD = LVCMOS33; +NET "header_a<5>" LOC = V8 | IOSTANDARD = LVCMOS33; +NET "header_a<6>" LOC = Y10 | IOSTANDARD = LVCMOS33; +NET "header_a<7>" LOC = V9 | IOSTANDARD = LVCMOS33; +NET "header_a<8>" LOC = W9 | IOSTANDARD = LVCMOS33; +NET "header_a<9>" LOC = AA10 | IOSTANDARD = LVCMOS33; +NET "header_a<10>" LOC = AB10 | IOSTANDARD = LVCMOS33; +NET "header_a<11>" LOC = W10 | IOSTANDARD = LVCMOS33; +NET "header_a<12>" LOC = AB11 | IOSTANDARD = LVCMOS33; +NET "header_a<13>" LOC = U11 | IOSTANDARD = LVCMOS33; +NET "header_a<14>" LOC = AB13 | IOSTANDARD = LVCMOS33; +NET "header_a<15>" LOC = AA13 | IOSTANDARD = LVCMOS33; +NET "header_a<16>" LOC = V10 | IOSTANDARD = LVCMOS33; +NET "header_a<17>" LOC = U10 | IOSTANDARD = LVCMOS33; +NET "header_a<18>" LOC = W13 | IOSTANDARD = LVCMOS33; +NET "header_a<19>" LOC = Y13 | IOSTANDARD = LVCMOS33; + +# Header B (right) +NET "header_b<2>" LOC = V14 | IOSTANDARD = LVCMOS33; +NET "header_b<3>" LOC = V13 | IOSTANDARD = LVCMOS33; +NET "header_b<4>" LOC = AA15 | IOSTANDARD = LVCMOS33; +NET "header_b<5>" LOC = W14 | IOSTANDARD = LVCMOS33; +NET "header_b<6>" LOC = AB15 | IOSTANDARD = LVCMOS33; +NET "header_b<7>" LOC = Y16 | IOSTANDARD = LVCMOS33; +NET "header_b<8>" LOC = AA17 | IOSTANDARD = LVCMOS33; +NET "header_b<9>" LOC = AA18 | IOSTANDARD = LVCMOS33; +NET "header_b<10>" LOC = AB18 | IOSTANDARD = LVCMOS33; +NET "header_b<11>" LOC = Y18 | IOSTANDARD = LVCMOS33; +NET "header_b<12>" LOC = Y19 | IOSTANDARD = LVCMOS33; +NET "header_b<13>" LOC = AB20 | IOSTANDARD = LVCMOS33; +NET "header_b<14>" LOC = AA20 | IOSTANDARD = LVCMOS33; +NET "header_b<15>" LOC = U16 | IOSTANDARD = LVCMOS33; +NET "header_b<16>" LOC = V16 | IOSTANDARD = LVCMOS33; +NET "header_b<17>" LOC = V17 | IOSTANDARD = LVCMOS33; +NET "header_b<18>" LOC = W16 | IOSTANDARD = LVCMOS33; +NET "header_b<19>" LOC = W17 | IOSTANDARD = LVCMOS33; + +# usused pins +CONFIG PROHIBIT = A3; +CONFIG PROHIBIT = A7; +CONFIG PROHIBIT = A11; +CONFIG PROHIBIT = A16; +CONFIG PROHIBIT = AA3; +CONFIG PROHIBIT = AA7; +CONFIG PROHIBIT = AA9; +CONFIG PROHIBIT = AA11; +CONFIG PROHIBIT = AA14; +CONFIG PROHIBIT = AA16; +CONFIG PROHIBIT = AA19; +CONFIG PROHIBIT = AB7; +CONFIG PROHIBIT = AB9; +CONFIG PROHIBIT = AB12; +CONFIG PROHIBIT = AB14; +CONFIG PROHIBIT = AB16; +CONFIG PROHIBIT = AB19; +CONFIG PROHIBIT = B4; +CONFIG PROHIBIT = B7; +CONFIG PROHIBIT = B12; +CONFIG PROHIBIT = B11; +CONFIG PROHIBIT = B16; +CONFIG PROHIBIT = C2; +CONFIG PROHIBIT = C3; +CONFIG PROHIBIT = C4; +CONFIG PROHIBIT = C12; +CONFIG PROHIBIT = C16; +CONFIG PROHIBIT = D2; +CONFIG PROHIBIT = D3; +CONFIG PROHIBIT = D4; +CONFIG PROHIBIT = D5; +CONFIG PROHIBIT = D8; +CONFIG PROHIBIT = D12; +CONFIG PROHIBIT = D16; +CONFIG PROHIBIT = E2; +CONFIG PROHIBIT = E3; +CONFIG PROHIBIT = E8; +CONFIG PROHIBIT = E4; +CONFIG PROHIBIT = E5; +CONFIG PROHIBIT = F4; +CONFIG PROHIBIT = E10; +CONFIG PROHIBIT = E12; +CONFIG PROHIBIT = F12; +CONFIG PROHIBIT = F5; +CONFIG PROHIBIT = F13; +CONFIG PROHIBIT = F6; +CONFIG PROHIBIT = F9; +CONFIG PROHIBIT = F10; +CONFIG PROHIBIT = F16; +CONFIG PROHIBIT = F11; +CONFIG PROHIBIT = F14; +CONFIG PROHIBIT = G3; +CONFIG PROHIBIT = G4; +CONFIG PROHIBIT = G5; +CONFIG PROHIBIT = G20; +CONFIG PROHIBIT = H1; +CONFIG PROHIBIT = H2; +CONFIG PROHIBIT = H4; +CONFIG PROHIBIT = H18; +CONFIG PROHIBIT = H19; +CONFIG PROHIBIT = H21; +CONFIG PROHIBIT = H22; +CONFIG PROHIBIT = J1; +CONFIG PROHIBIT = J2; +CONFIG PROHIBIT = J4; +CONFIG PROHIBIT = J5; +CONFIG PROHIBIT = J6; +CONFIG PROHIBIT = J17; +CONFIG PROHIBIT = J18; +CONFIG PROHIBIT = J19; +CONFIG PROHIBIT = J21; +CONFIG PROHIBIT = J22; +CONFIG PROHIBIT = K5; +CONFIG PROHIBIT = K6; +CONFIG PROHIBIT = K17; +CONFIG PROHIBIT = K18; +CONFIG PROHIBIT = N5; +CONFIG PROHIBIT = N6; +CONFIG PROHIBIT = N17; +CONFIG PROHIBIT = N18; +CONFIG PROHIBIT = N19; +CONFIG PROHIBIT = N20; +CONFIG PROHIBIT = P1; +CONFIG PROHIBIT = P2; +CONFIG PROHIBIT = P4; +CONFIG PROHIBIT = P5; +CONFIG PROHIBIT = P6; +CONFIG PROHIBIT = P17; +CONFIG PROHIBIT = P18; +CONFIG PROHIBIT = P19; +CONFIG PROHIBIT = P21; +CONFIG PROHIBIT = P22; +CONFIG PROHIBIT = R1; +CONFIG PROHIBIT = R2; +CONFIG PROHIBIT = R4; +CONFIG PROHIBIT = R5; +CONFIG PROHIBIT = R19; +CONFIG PROHIBIT = R21; +CONFIG PROHIBIT = R22; +CONFIG PROHIBIT = T3; +CONFIG PROHIBIT = T19; +CONFIG PROHIBIT = T20; +CONFIG PROHIBIT = U9; +CONFIG PROHIBIT = U12; +CONFIG PROHIBIT = U13; +CONFIG PROHIBIT = U14; +CONFIG PROHIBIT = U17; +CONFIG PROHIBIT = V11; +CONFIG PROHIBIT = V12; +CONFIG PROHIBIT = V15; +CONFIG PROHIBIT = W7; +CONFIG PROHIBIT = W8; +CONFIG PROHIBIT = W11; +CONFIG PROHIBIT = W12; +CONFIG PROHIBIT = W15; +CONFIG PROHIBIT = W18; +CONFIG PROHIBIT = Y4; +CONFIG PROHIBIT = Y7; +CONFIG PROHIBIT = Y11; +CONFIG PROHIBIT = Y12; diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj new file mode 100644 index 0000000..24120d5 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj @@ -0,0 +1,19 @@ +vhdl work ../top.vhd +vhdl zpu ../../../zpu_pkg.vhdl +vhdl zpu ../../../zpu_small.vhdl +vhdl zpu ../../../zpu_medium.vhdl +vhdl zpu ../../../roms/rom_pkg.vhdl +#vhdl zpu ../../../roms/hello_dbram.vhdl +#vhdl zpu ../../../roms/hello_bram.vhdl +vhdl zpu ../../../roms/dmips_dbram.vhdl +vhdl zpu ../../../roms/dmips_bram.vhdl +vhdl zpu ../../../helpers/zpu_small1.vhdl +vhdl zpu ../../../helpers/zpu_med1.vhdl +vhdl zpu ../../../devices/txt_util.vhdl +vhdl zpu ../../../devices/phi_io.vhdl +vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/gpio.vhdl +vhdl zpu ../../../devices/rx_unit.vhdl +vhdl zpu ../../../devices/tx_unit.vhdl +vhdl zpu ../../../devices/br_gen.vhdl +vhdl zpu ../../../devices/trace.vhdl diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut new file mode 100644 index 0000000..765a6f3 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:6 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g HswapenPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:Auto +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst new file mode 100644 index 0000000..14873ea --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst @@ -0,0 +1,56 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../synthesis_config/top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc3s1000-4-fg456 +-top top +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd new file mode 100644 index 0000000..4a93c4f --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd @@ -0,0 +1,372 @@ +-- top module of +-- Altium LiveDesign Board +-- +-- using following external connections: +-- test button as reset +-- LEDs and 7 segment for output +-- RS232 +-- + + +library ieee; +use ieee.std_logic_1164.all; + +library zpu; +use zpu.zpupkg.all; -- zpu_dbgo_t + +library unisim; +use unisim.vcomponents.dcm; + + +entity top is + port ( + -- pragma translate_off + stop_simulation : out std_logic; + -- pragma translate_on + clk_50 : in std_logic; + reset_n : in std_logic; + -- + -- soft JTAG + soft_tdo : out std_logic; + soft_tms : in std_logic; + soft_tdi : in std_logic; + soft_tck : in std_logic; + -- + -- SRAM 0 (256k x 16) pin connections + sram0_a : out std_logic_vector(18 downto 0); + sram0_d : inout std_logic_vector(15 downto 0); + sram0_lb_n : out std_logic; + sram0_ub_n : out std_logic; + sram0_cs_n : out std_logic; -- chip select + sram0_we_n : out std_logic; -- write-enable + sram0_oe_n : out std_logic; -- output enable + -- + -- SRAM 1 (256k x 16) pin connections + sram1_a : out std_logic_vector(18 downto 0); + sram1_d : inout std_logic_vector(15 downto 0); + sram1_lb_n : out std_logic; + sram1_ub_n : out std_logic; + sram1_cs_n : out std_logic; -- chip select + sram1_we_n : out std_logic; -- write-enable + sram1_oe_n : out std_logic; -- output enable + -- + -- RS232 + rs232_rx : in std_logic; + rs232_tx : out std_logic; + rs232_cts : in std_logic; + rs232_rts : out std_logic; + -- + -- PS2 connectors + mouse_clk : inout std_logic; + mouse_data : inout std_logic; + kbd_clk : inout std_logic; + kbd_data : inout std_logic; + -- + -- vga output + vga_red : out std_logic_vector(7 downto 5); + vga_green : out std_logic_vector(7 downto 5); + vga_blue : out std_logic_vector(7 downto 5); + vga_hsync : out std_logic; + vga_vsync : out std_logic; + -- + -- Audio out + audio_r : out std_logic; + audio_l : out std_logic; + -- + -- GPIOs + switch_n : in std_logic_vector(7 downto 0); + button_n : in std_logic_vector(5 downto 0); + led : out std_logic_vector(7 downto 0); + -- + -- seven segment display + dig0_seg : out std_logic_vector(7 downto 0); + dig1_seg : out std_logic_vector(7 downto 0); + dig2_seg : out std_logic_vector(7 downto 0); + dig3_seg : out std_logic_vector(7 downto 0); + dig4_seg : out std_logic_vector(7 downto 0); + dig5_seg : out std_logic_vector(7 downto 0); + -- + -- User Header + header_a : inout std_logic_vector(19 downto 2); + header_b : inout std_logic_vector(19 downto 2) + ); +end entity top; + + +architecture rtl of top is + + + --------------------------- + -- type declarations + type zpu_type is (zpu_small, zpu_medium); + + --------------------------- + -- constant declarations + constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE + -- modify frequency here + constant clk_multiply : positive := 3; -- 9 for small, 3 for medium + constant clk_divide : positive := 2; -- 5 for small, 2 for medium + -- + constant word_size_c : natural := 32; -- 32 bits data path + constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + + constant clk_frequency : positive := 50; -- input frequency for correct calculation + + + --------------------------- + -- component declarations + component zpu_small1 is + generic ( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port ( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_small1; + + component zpu_med1 is + generic( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_med1; + + + --------------------------- + -- signal declarations + signal dcm_i0_clk0 : std_ulogic; + signal dcm_i0_clkfx : std_ulogic; + signal clk_fb : std_ulogic; + signal clk : std_ulogic; + -- + signal reset_shift_reg : std_ulogic_vector(3 downto 0); + signal reset_sync : std_ulogic; + -- + signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info + signal zpu_i0_break : std_logic; + -- + signal gpio_in : std_logic_vector(31 downto 0) := (others => '0'); + signal zpu_i0_gpio_out : std_logic_vector(31 downto 0); + signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0); + + +begin + + -- default output drivers + -- to pass bitgen DRC + -- outputs used by design are commented + soft_tdo <= '1'; + -- + sram0_a <= (others => '1'); + sram0_d <= (others => 'Z'); + sram0_lb_n <= '1'; + sram0_ub_n <= '1'; + sram0_cs_n <= '1'; + sram0_we_n <= '1'; + sram0_oe_n <= '1'; + -- + sram1_a <= (others => '1'); + sram1_d <= (others => 'Z'); + sram1_lb_n <= '1'; + sram1_ub_n <= '1'; + sram1_cs_n <= '1'; + sram1_we_n <= '1'; + sram1_oe_n <= '1'; + -- + --rs232_tx <= '1'; + rs232_rts <= '1'; + -- + mouse_clk <= 'Z'; + mouse_data <= 'Z'; + kbd_clk <= 'Z'; + kbd_data <= 'Z'; + -- + vga_red <= (others => '1'); + vga_green <= (others => '1'); + vga_blue <= (others => '1'); + vga_hsync <= '1'; + vga_vsync <= '1'; + -- + audio_r <= '0'; + audio_l <= '0'; + -- + --led <= (others => '0'); + -- + --dig0_seg <= (others => '0'); + --dig1_seg <= (others => '0'); + dig2_seg <= (others => '0'); + dig3_seg <= (others => '0'); + dig4_seg <= (others => '0'); + dig5_seg <= (others => '0'); + -- + header_a <= (others => 'Z'); + header_b <= (others => 'Z'); + + + -- digital clock manager (DCM) + -- to generate higher/other system clock frequencys + dcm_i0 : dcm + generic map ( + startup_wait => true, -- wait with DONE till locked + clkfx_multiply => clk_multiply, + clkfx_divide => clk_divide, + clk_feedback => "1X" + ) + port map ( + clkin => clk_50, + clk0 => dcm_i0_clk0, + clkfx => dcm_i0_clkfx, + clkfb => clk_fb + ); + + clk_fb <= dcm_i0_clk0; + clk <= dcm_i0_clkfx; + + + -- reset synchronizer + -- generate synchronous reset + reset_synchronizer : process(clk, reset_n) + begin + if reset_n = '0' then + reset_shift_reg <= (others => '1'); + elsif rising_edge(clk) then + reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0'; + end if; + end process; + reset_sync <= reset_shift_reg(reset_shift_reg'high); + + + -- select instance of zpu + zpu_i0_small : if zpu_flavour = zpu_small generate + zpu_i0 : zpu_small1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; -- UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic -- UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_small; + + zpu_i0_medium : if zpu_flavour = zpu_medium generate + zpu_i0 : zpu_med1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; -- UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic -- UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_medium; + + + -- pragma translate_off + stop_simulation <= zpu_i0_break; + + + trace_mod : trace + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + log_file => "zpu_trace.log" + ) + port map ( + clk_i => clk, + dbg_i => zpu_i0_dbg, + stop_i => zpu_i0_break, + busy_i => '0' + ); + -- pragma translate_on + + + -- assign GPIOs + -- + -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 + -- + -- in header_a(19.........12) -- -- -- -- -- -- -- -- + -- out header_a(19.........12) dig1_seg(7...........0) + -- + -- + -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + -- + -- in switch_n(7...........0) -- -- button_n(5....0) + -- out dig0_seg(7...........0) led(7................0) + -- + + gpio_in(31 downto 24) <= header_a(19 downto 12); + gpio_in(15 downto 8) <= switch_n; + gpio_in( 5 downto 0) <= button_n; + + -- 3-state buffers for some headers + header_a(19) <= zpu_i0_gpio_out(31) when zpu_i0_gpio_dir(31) = '0' else 'Z'; + header_a(18) <= zpu_i0_gpio_out(30) when zpu_i0_gpio_dir(30) = '0' else 'Z'; + header_a(17) <= zpu_i0_gpio_out(29) when zpu_i0_gpio_dir(29) = '0' else 'Z'; + header_a(16) <= zpu_i0_gpio_out(28) when zpu_i0_gpio_dir(28) = '0' else 'Z'; + header_a(15) <= zpu_i0_gpio_out(27) when zpu_i0_gpio_dir(27) = '0' else 'Z'; + header_a(14) <= zpu_i0_gpio_out(26) when zpu_i0_gpio_dir(26) = '0' else 'Z'; + header_a(13) <= zpu_i0_gpio_out(25) when zpu_i0_gpio_dir(25) = '0' else 'Z'; + header_a(12) <= zpu_i0_gpio_out(24) when zpu_i0_gpio_dir(24) = '0' else 'Z'; + + -- outputs + dig1_seg <= zpu_i0_gpio_out(23 downto 16); + dig0_seg <= zpu_i0_gpio_out(15 downto 8); + + -- switch on all LEDs in case of break + process + begin + wait until rising_edge(clk); + led <= zpu_i0_gpio_out(7 downto 0); + if zpu_i0_break = '1' then + led <= (others => '1'); + end if; + end process; + + +end architecture rtl; + diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd new file mode 100644 index 0000000..e42fc20 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd @@ -0,0 +1,194 @@ +-- testbench for +-- Altium LiveDesign Board +-- +-- includes "model" for clock generation +-- simulate press on test/reset as reset +-- +-- place models for external components (SRAM, PS2) in this file +-- + + +library ieee; +use ieee.std_logic_1164.all; + + +entity top_tb is +end entity top_tb; + +architecture testbench of top_tb is + + --------------------------- + -- constant declarations + constant clk_period : time := 1 sec / 50_000_000; -- 50 MHz + + + --------------------------- + -- signal declarations + signal simulation_run : boolean := true; + signal tb_stop_simulation : std_logic; + -- + signal tb_clk : std_logic := '0'; + signal tb_reset_n : std_logic; + -- + -- soft JTAG + signal tb_soft_tdo : std_logic; + signal tb_soft_tms : std_logic := '1'; + signal tb_soft_tdi : std_logic := '1'; + signal tb_soft_tck : std_logic := '1'; + -- + -- SRAM 0 (256k x 16) pin connections + signal tb_sram0_a : std_logic_vector(18 downto 0); + signal tb_sram0_d : std_logic_vector(15 downto 0) := (others => 'Z'); + signal tb_sram0_lb_n : std_logic; + signal tb_sram0_ub_n : std_logic; + signal tb_sram0_cs_n : std_logic; -- chip select + signal tb_sram0_we_n : std_logic; -- write-enable + signal tb_sram0_oe_n : std_logic; -- output enable + -- + -- SRAM 1 (256k x 16) pin connections + signal tb_sram1_a : std_logic_vector(18 downto 0); + signal tb_sram1_d : std_logic_vector(15 downto 0) := (others => 'Z'); + signal tb_sram1_lb_n : std_logic; + signal tb_sram1_ub_n : std_logic; + signal tb_sram1_cs_n : std_logic; -- chip select + signal tb_sram1_we_n : std_logic; -- write-enable + signal tb_sram1_oe_n : std_logic; -- output enable + -- + -- RS232 + signal tb_rs232_rx : std_logic := '1'; + signal tb_rs232_tx : std_logic; + signal tb_rs232_cts : std_logic := '1'; + signal tb_rs232_rts : std_logic; + -- + -- PS2 connectors + signal tb_mouse_clk : std_logic := 'Z'; + signal tb_mouse_data : std_logic := 'Z'; + signal tb_kbd_clk : std_logic := 'Z'; + signal tb_kbd_data : std_logic := 'Z'; + -- + -- vga output + signal tb_vga_red : std_logic_vector(7 downto 5); + signal tb_vga_green : std_logic_vector(7 downto 5); + signal tb_vga_blue : std_logic_vector(7 downto 5); + signal tb_vga_hsync : std_logic; + signal tb_vga_vsync : std_logic; + -- + -- Audio out + signal tb_audio_r : std_logic; + signal tb_audio_l : std_logic; + -- + -- GPIOs + signal tb_switch_n : std_logic_vector(7 downto 0) := (others => '1'); + signal tb_button_n : std_logic_vector(5 downto 0) := (others => '1'); + signal tb_led : std_logic_vector(7 downto 0); + -- + -- seven segment display + signal tb_dig0_seg : std_logic_vector(7 downto 0); + signal tb_dig1_seg : std_logic_vector(7 downto 0); + signal tb_dig2_seg : std_logic_vector(7 downto 0); + signal tb_dig3_seg : std_logic_vector(7 downto 0); + signal tb_dig4_seg : std_logic_vector(7 downto 0); + signal tb_dig5_seg : std_logic_vector(7 downto 0); + -- + -- User Header A + signal tb_header_a : std_logic_vector(19 downto 2) := (others => 'Z'); + signal tb_header_b : std_logic_vector(19 downto 2) := (others => 'Z'); + +begin + + -- generate clock + tb_clk <= not tb_clk after clk_period / 2 when simulation_run; + + -- generate reset + tb_reset_n <= '0', '1' after 6.66 * clk_period; + + + -- simulate keypress + tb_button_n(2) <= '1', '0' after 50 us, '1' after 52 us; + + -- dut + top_i0 : entity work.top + port map ( + stop_simulation => tb_stop_simulation, -- : out std_logic; + -- + clk_50 => tb_clk, -- : in std_logic; + reset_n => tb_reset_n, -- : in std_logic; + -- + -- soft JTAG + soft_tdo => tb_soft_tdo, -- : out std_logic; + soft_tms => tb_soft_tms, -- : in std_logic; + soft_tdi => tb_soft_tdi, -- : in std_logic; + soft_tck => tb_soft_tck, -- : in std_logic; + -- + -- SRAM 0 (256k x 16) pin connections + sram0_a => tb_sram0_a, -- : out std_logic_vector(18 downto 0); + sram0_d => tb_sram0_d, -- : inout std_logic_vector(15 downto 0); + sram0_lb_n => tb_sram0_lb_n, -- : out std_logic; + sram0_ub_n => tb_sram0_ub_n, -- : out std_logic; + sram0_cs_n => tb_sram0_cs_n, -- : out std_logic; -- chip select + sram0_we_n => tb_sram0_we_n, -- : out std_logic; -- write-enable + sram0_oe_n => tb_sram0_oe_n, -- : out std_logic; -- output enable + -- + -- SRAM 1 (256k x 16) pin connections + sram1_a => tb_sram1_a, -- : out std_logic_vector(18 downto 0); + sram1_d => tb_sram1_d, -- : inout std_logic_vector(15 downto 0); + sram1_lb_n => tb_sram1_lb_n, -- : out std_logic; + sram1_ub_n => tb_sram1_ub_n, -- : out std_logic; + sram1_cs_n => tb_sram1_cs_n, -- : out std_logic; -- chip select + sram1_we_n => tb_sram1_we_n, -- : out std_logic; -- write-enable + sram1_oe_n => tb_sram1_oe_n, -- : out std_logic; -- output enable + -- + -- RS232 + rs232_rx => tb_rs232_rx, -- : in std_logic; + rs232_tx => tb_rs232_tx, -- : out std_logic; + rs232_cts => tb_rs232_cts, -- : in std_logic; + rs232_rts => tb_rs232_rts, -- : out std_logic; + -- + -- PS2 connectors + mouse_clk => tb_mouse_clk, -- : inout std_logic; + mouse_data => tb_mouse_data, -- : inout std_logic; + kbd_clk => tb_kbd_clk, -- : inout std_logic; + kbd_data => tb_kbd_data, -- : inout std_logic; + -- + -- vga output + vga_red => tb_vga_red, -- : out std_logic_vector(7 downto 5); + vga_green => tb_vga_green, -- : out std_logic_vector(7 downto 5); + vga_blue => tb_vga_blue, -- : out std_logic_vector(7 downto 5); + vga_hsync => tb_vga_hsync, -- : out std_logic; + vga_vsync => tb_vga_vsync, -- : out std_logic; + -- + -- Audio out + audio_r => tb_audio_r, -- : out std_logic; + audio_l => tb_audio_l, -- : out std_logic; + -- + -- GPIOs + switch_n => tb_switch_n, -- : in std_logic_vector(7 downto 0); + button_n => tb_button_n, -- : in std_logic_vector(5 downto 0); + led => tb_led, -- : out std_logic_vector(7 downto 0); + -- + -- seven segment display + dig0_seg => tb_dig0_seg, -- : out std_logic_vector(7 downto 0); + dig1_seg => tb_dig1_seg, -- : out std_logic_vector(7 downto 0); + dig2_seg => tb_dig2_seg, -- : out std_logic_vector(7 downto 0); + dig3_seg => tb_dig3_seg, -- : out std_logic_vector(7 downto 0); + dig4_seg => tb_dig4_seg, -- : out std_logic_vector(7 downto 0); + dig5_seg => tb_dig5_seg, -- : out std_logic_vector(7 downto 0); + -- + -- User Header + header_a => tb_header_a, -- : inout std_logic_vector(19 downto 2); + header_b => tb_header_b -- : inout std_logic_vector(19 downto 2) + ); + + + -- check for simulation stopping + process (tb_stop_simulation) + begin + if tb_stop_simulation = '1' then + report "Simulation end." severity note; + simulation_run <= false; + end if; + end process; + + +end architecture testbench; + diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh new file mode 100755 index 0000000..d525737 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/gpio.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do new file mode 100644 index 0000000..acc1710 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do +run -all diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do new file mode 100644 index 0000000..d572a06 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do @@ -0,0 +1,30 @@ +onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_gpio_button(0)
+add wave -noupdate /top_tb/tb_clk_100MHz
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_rs232_rx
+add wave -noupdate /top_tb/tb_rs232_tx
+add wave -noupdate /top_tb/tb_rs232_rts
+add wave -noupdate /top_tb/tb_rs232_cts
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_gpio_button
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/tb_gpio_led_n
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {126912555 ps}
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh new file mode 100755 index 0000000..d8d7603 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/avnet-eval-xc5vfx30t.ucf -p xc5vfx30t-ff665-1 top.ngc top.ngd +map -p xc5vfx30t-ff665-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf +par -w -ol high -mt off top_map.ncd top.ncd top.pcf +trce -v 3 -s 1 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf new file mode 100644 index 0000000..8494af3 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf @@ -0,0 +1,482 @@ +############################################################ +# Avnet Virtex 5 FX Evaluation Board constraints file +# +# Familiy: Virtex5 +# Device: XC5VFX30T +# Package: FF665 +# Speed: -1 +# +# +# Bank 0 3.3V +# Bank 1 3.3V +# Bank 2 3.3V +# Bank 3 3.3V +# Bank 4 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V +# Bank 11 1.8V +# Bank 12 3.3V +# Bank 13 1.8V +# Bank 15 3.3V +# Bank 16 2.5V or 3.3V (JP3, VIO_EXP1_SE), here 2.5V +# Bank 17 1.8V +# Bank 18 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V + + +############################################################ +## clock/timing constraints +############################################################ + +TIMESPEC "TS_clk_100" = PERIOD "clk_100" 100 MHz; + + +############################################################ +## design placement constraints +############################################################ +# +# the following constraint are need if you want to synthesize +# zpu_medium with 125 MHz +# +INST "zpu_i0_medium.zpu_i0/zpu/*" AREA_GROUP = "zpu_block"; +AREA_GROUP "zpu_block" RANGE=SLICE_X18Y0:SLICE_X55Y41; +AREA_GROUP "zpu_block" RANGE=DSP48_X0Y0:DSP48_X0Y15; +AREA_GROUP "zpu_block" RANGE=RAMB36_X1Y0:RAMB36_X3Y7; + + +############################################################ +## pin placement constraints +############################################################ + +NET "clk_100MHz" LOC= E18 | IOSTANDARD = LVCMOS33 | TNM_NET = "clk_100"; +NET "clk_socket" LOC= E13 | IOSTANDARD = LVCMOS33; +NET "user_clk_p" LOC= AB15 ; +NET "user_clk_n" LOC= AC16 ; + +# RS232 +NET "RS232_RX" LOC= K8 | IOSTANDARD = LVCMOS33; +NET "RS232_TX" LOC= L8 | IOSTANDARD = LVCMOS33; +NET "RS232_RTS" LOC= N8 | IOSTANDARD = LVCMOS33; # Jumper J3 +NET "RS232_CTS" LOC= R8 | IOSTANDARD = LVCMOS33; # Jumper J4 + +# RS232_USB +NET "RS232_USB_RX" LOC= AA10 | IOSTANDARD = LVCMOS33; +NET "RS232_USB_TX" LOC= AA19 | IOSTANDARD = LVCMOS33; +NET "RS232_USB_reset_n" LOC= Y20 | IOSTANDARD = LVCMOS33; + +# GPIO LEDs, active low +NET "GPIO_LED_n<0>" LOC= AF22 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<1>" LOC= AF23 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<2>" LOC= AF25 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<3>" LOC= AE25 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<4>" LOC= AD25 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<5>" LOC= AE26 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<6>" LOC= AD26 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<7>" LOC= AC26 | IOSTANDARD = LVCMOS18 | PULLUP; + +# GPIO DIP_Switches +NET "GPIO_DIPswitch<0>" LOC= AD13 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<1>" LOC= AE13 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<2>" LOC= AF13 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<3>" LOC= AD15 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<4>" LOC= AD14 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<5>" LOC= AF14 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<6>" LOC= AE15 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<7>" LOC= AF15 | IOSTANDARD = LVCMOS18; + +# Push Buttons +NET "GPIO_button<0>" LOC= AF20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB1 +NET "GPIO_button<1>" LOC= AE20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB2 +NET "GPIO_button<2>" LOC= AD19 | IOSTANDARD = LVCMOS18 | PULLUP; #PB3 +NET "GPIO_button<3>" LOC= AD20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB4 + +# FLASH_8Mx16 +NET "FLASH_A<31>" LOC= Y11 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<30>" LOC= H9 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<29>" LOC= G10 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<28>" LOC= H21 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<27>" LOC= G20 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<26>" LOC= H11 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<25>" LOC= G11 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<24>" LOC= H19 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<23>" LOC= H18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<22>" LOC= G12 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<21>" LOC= F13 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<20>" LOC= G19 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<19>" LOC= F18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<18>" LOC= F14 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<17>" LOC= F15 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<16>" LOC= F17 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<15>" LOC= G17 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<14>" LOC= G14 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<13>" LOC= H13 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<12>" LOC= G16 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<11>" LOC= G15 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<10>" LOC= Y18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<9>" LOC= AA18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<8>" LOC= Y10 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<7>" LOC= W11 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<0>" LOC= AA15 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<1>" LOC= Y15 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<2>" LOC= W14 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<3>" LOC= Y13 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<4>" LOC= W16 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<5>" LOC= Y16 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<6>" LOC= AA14 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<7>" LOC= AA13 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<8>" LOC= AB12 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<9>" LOC= AC11 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<10>" LOC= AB20 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<11>" LOC= AB21 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<12>" LOC= AB11 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<13>" LOC= AB10 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<14>" LOC= AA20 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<15>" LOC= Y21 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_WEN" LOC= AA17 | IOSTANDARD = LVCMOS33; +NET "FLASH_OEN<0>" LOC= AA12 | IOSTANDARD = LVCMOS33; +NET "FLASH_CEN<0>" LOC= Y12 | IOSTANDARD = LVCMOS33; +NET "FLASH_rp_n" LOC= D13 | IOSTANDARD = LVCMOS33; +NET "FLASH_byte_n" LOC= Y17 | IOSTANDARD = LVCMOS33; +NET "FLASH_adv_n" LOC= F19 | IOSTANDARD = LVCMOS33; +NET "FLASH_clk" LOC= E12 | IOSTANDARD = LVCMOS33; +NET "FLASH_wait" LOC= D16 | IOSTANDARD = LVCMOS33; + +# DDR2_SDRAM_16Mx32 +NET "DDR2_ODT<0>" LOC= AF24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<0>" LOC= U25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<1>" LOC= T25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<2>" LOC= T24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<3>" LOC= T23 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<4>" LOC= U24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<5>" LOC= V24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<6>" LOC= Y23 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<7>" LOC= W23 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<8>" LOC= AA25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<9>" LOC= AB26 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<10>" LOC= AB25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<11>" LOC= AB24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<12>" LOC= AA23 | IOSTANDARD = SSTL18_II; +NET "DDR2_BA<0>" LOC= U21 | IOSTANDARD = SSTL18_II; +NET "DDR2_BA<1>" LOC= V22 | IOSTANDARD = SSTL18_II; +NET "DDR2_CAS_N" LOC= W24 | IOSTANDARD = SSTL18_II; +NET "DDR2_CKE" LOC= T22 | IOSTANDARD = SSTL18_II; +NET "DDR2_CS_N" LOC= AD24 | IOSTANDARD = SSTL18_II; +NET "DDR2_RAS_N" LOC= Y22 | IOSTANDARD = SSTL18_II; +NET "DDR2_WE_N" LOC= AA22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<0>" LOC= U26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<1>" LOC= N24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<2>" LOC= M24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<3>" LOC= M25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<0>" LOC= W26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<1>" LOC= L23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<2>" LOC= K22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<3>" LOC= J21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<0>" LOC= W25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<1>" LOC= L22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<2>" LOC= K23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<3>" LOC= K21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<0>" LOC= R22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<1>" LOC= R23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<2>" LOC= P23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<3>" LOC= P24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<4>" LOC= R25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<5>" LOC= P25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<6>" LOC= R26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<7>" LOC= P26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<8>" LOC= M26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<9>" LOC= N26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<10>" LOC= K25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<11>" LOC= L24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<12>" LOC= K26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<13>" LOC= J26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<14>" LOC= J25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<15>" LOC= N21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<16>" LOC= M21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<17>" LOC= J23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<18>" LOC= H23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<19>" LOC= H22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<20>" LOC= G22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<21>" LOC= F22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<22>" LOC= F23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<23>" LOC= E23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<24>" LOC= G24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<25>" LOC= F24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<26>" LOC= G25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<27>" LOC= H26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<28>" LOC= G26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<29>" LOC= F25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<30>" LOC= E25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<31>" LOC= E26 | IOSTANDARD = SSTL18_II; +NET "DDR2_CK_p<0>" LOC= V21 | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CK_p<1>" LOC= N22 | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CK_n<0>" LOC= W21 | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CK_n<1>" LOC= M22 | IOSTANDARD = DIFF_SSTL18_II; + +# Ethernet MAC +NET "GMII_txer" LOC= A22 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_clk" LOC= E17 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps; +NET "GMII_rx_clk" LOC= E20 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps; +NET "GMII_gtc_clk" LOC= A19 | IOSTANDARD = LVCMOS33; +NET "GMII_crs" LOC= A25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_dv" LOC= C21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<0>" LOC= D24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<1>" LOC= D23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<2>" LOC= D21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<3>" LOC= C26 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<4>" LOC= D20 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<5>" LOC= C23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<6>" LOC= B25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<7>" LOC= C22 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_col" LOC= A24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_er" LOC= B24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_tx_en" LOC= A23 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<0>" LOC= D19 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<1>" LOC= C19 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<2>" LOC= A20 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<3>" LOC= B20 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<4>" LOC= B19 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<5>" LOC= A15 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<6>" LOC= B22 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<7>" LOC= B21 | IOSTANDARD = LVCMOS33; +NET "GBE_rst_n" LOC= B26 | IOSTANDARD = LVCMOS33; +NET "GBE_mdc" LOC= D26 | IOSTANDARD = LVCMOS33; +NET "GBE_mdio" LOC= D25 | IOSTANDARD = LVCMOS33; +NET "GBE_int_n" LOC= C24 | IOSTANDARD = LVCMOS33; +NET "GBE_mclk" LOC= F20 | IOSTANDARD = LVCMOS33; + +# SysACE CompactFlash +NET "SAM_CLK" LOC= F12 | IOSTANDARD = LVCMOS33; +NET "SAM_A<0>" LOC= Y5 | IOSTANDARD = LVCMOS33; +NET "SAM_A<1>" LOC= V7 | IOSTANDARD = LVCMOS33; +NET "SAM_A<2>" LOC= W6 | IOSTANDARD = LVCMOS33; +NET "SAM_A<3>" LOC= W5 | IOSTANDARD = LVCMOS33; +NET "SAM_A<4>" LOC= K6 | IOSTANDARD = LVCMOS33; +NET "SAM_A<5>" LOC= J5 | IOSTANDARD = LVCMOS33; +NET "SAM_A<6>" LOC= J6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<0>" LOC= F5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<1>" LOC= U7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<2>" LOC= V6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<3>" LOC= U5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<4>" LOC= U6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<5>" LOC= T5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<6>" LOC= T7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<7>" LOC= R6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<8>" LOC= R7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<9>" LOC= R5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<10>" LOC= P6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<11>" LOC= P8 | IOSTANDARD = LVCMOS33; +NET "SAM_D<12>" LOC= N6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<13>" LOC= M7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<14>" LOC= K5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<15>" LOC= L7 | IOSTANDARD = LVCMOS33; +NET "SAM_CEN" LOC= G4 | IOSTANDARD = LVCMOS33; +NET "SAM_OEN" LOC= Y6 | IOSTANDARD = LVCMOS33; +NET "SAM_WEN" LOC= Y4 | IOSTANDARD = LVCMOS33; +NET "SAM_MPIRQ" LOC= H4 | IOSTANDARD = LVCMOS33; +NET "SAM_BRDY" LOC= G5 | IOSTANDARD = LVCMOS33; +NET "SAM_RESET_n" LOC= H6 | IOSTANDARD = LVCMOS33; + +# Expansion Header +NET "EXP1_SE_IO<0>" LOC= A8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<1>" LOC= A12 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<2>" LOC= B10 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<3>" LOC= A10 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<4>" LOC= B9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<5>" LOC= A9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<6>" LOC= A5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<7>" LOC= B11 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<8>" LOC= B6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<9>" LOC= A7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<10>" LOC= D8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<11>" LOC= C9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<12>" LOC= B7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<13>" LOC= A4 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<14>" LOC= B5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<15>" LOC= C8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<16>" LOC= C7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<17>" LOC= A3 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<18>" LOC= C6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<19>" LOC= B4 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<20>" LOC= D6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<21>" LOC= D9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<22>" LOC= E8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<23>" LOC= D5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<24>" LOC= F7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<25>" LOC= E7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<26>" LOC= E5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<27>" LOC= E6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<28>" LOC= F8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<29>" LOC= H7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<30>" LOC= G7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<31>" LOC= H8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<32>" LOC= G9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<33>" LOC= J8 | IOSTANDARD = LVCMOS25; +NET "EXP1_DIFF_P<0>" LOC= AF9 ; +NET "EXP1_DIFF_N<0>" LOC= AF10 ; +NET "EXP1_DIFF_P<1>" LOC= AF12 ; +NET "EXP1_DIFF_N<1>" LOC= AE12 ; +NET "EXP1_DIFF_P<2>" LOC= AF7 ; +NET "EXP1_DIFF_N<2>" LOC= AF8 ; +NET "EXP1_DIFF_P<3>" LOC= AE11 ; +NET "EXP1_DIFF_N<3>" LOC= AD11 ; +NET "EXP1_DIFF_P<4>" LOC= AF4 ; +NET "EXP1_DIFF_N<4>" LOC= AF3 ; +NET "EXP1_DIFF_P<5>" LOC= AD10 ; +NET "EXP1_DIFF_N<5>" LOC= AE10 ; +NET "EXP1_DIFF_P<6>" LOC= AE8 ; +NET "EXP1_DIFF_N<6>" LOC= AE7 ; +NET "EXP1_DIFF_P<7>" LOC= AC8 ; +NET "EXP1_DIFF_N<7>" LOC= AD8 ; +NET "EXP1_DIFF_P<8>" LOC= AD9 ; +NET "EXP1_DIFF_N<8>" LOC= AC9 ; +NET "EXP1_DIFF_P<9>" LOC= AE6 ; +NET "EXP1_DIFF_N<9>" LOC= AF5 ; +NET "EXP1_DIFF_P<10>" LOC= AB6 ; +NET "EXP1_DIFF_N<10>" LOC= AB7 ; +NET "EXP1_DIFF_P<11>" LOC= AC6 ; +NET "EXP1_DIFF_N<11>" LOC= AD5 ; +NET "EXP1_DIFF_P<12>" LOC= AD6 ; +NET "EXP1_DIFF_N<12>" LOC= AC7 ; +NET "EXP1_DIFF_P<13>" LOC= AE5 ; +NET "EXP1_DIFF_N<13>" LOC= AD4 ; +NET "EXP1_DIFF_P<14>" LOC= AB9 ; +NET "EXP1_DIFF_N<14>" LOC= AA9 ; +NET "EXP1_DIFF_P<15>" LOC= AC12 ; +NET "EXP1_DIFF_N<15>" LOC= AC13 ; +NET "EXP1_DIFF_P<16>" LOC= AA7 ; +NET "EXP1_DIFF_N<16>" LOC= AA8 ; +NET "EXP1_DIFF_P<17>" LOC= AA5 ; +NET "EXP1_DIFF_N<17>" LOC= AB5 ; +NET "EXP1_DIFF_P<18>" LOC= AB19 ; +NET "EXP1_DIFF_N<18>" LOC= AC19 ; +NET "EXP1_DIFF_P<19>" LOC= Y7 ; +NET "EXP1_DIFF_N<19>" LOC= Y8 ; +NET "EXP1_DIFF_P<20>" LOC= W9 ; +NET "EXP1_DIFF_N<20>" LOC= W8 ; +NET "EXP1_DIFF_P<21>" LOC= V8 ; +NET "EXP1_DIFF_N<21>" LOC= V9 ; +NET "EXP1_SE_CLK_OUT" LOC= B12 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_CLK_IN" LOC= E10 | IOSTANDARD = LVCMOS33; +NET "EXP1_DIFF_CLK_OUT_P" LOC= AC18 ; +NET "EXP1_DIFF_CLK_OUT_N" LOC= AB17 ; +NET "EXP1_DIFF_CLK_IN_P" LOC= AB14 ; +NET "EXP1_DIFF_CLK_IN_N" LOC= AC14 ; +#NET "EXP1_RCLK_DIFF_P" LOC= AB6 ; +#NET "EXP1_RCLK_DIFF_N" LOC= AB7 ; + +# CPU Debug Trace +NET "ATDD<8>" LOC= C16 | IOSTANDARD = LVCMOS33; +NET "ATDD<9>" LOC= A17 | IOSTANDARD = LVCMOS33; +NET "ATDD<10>" LOC= B15 | IOSTANDARD = LVCMOS33; +NET "ATDD<11>" LOC= E15 | IOSTANDARD = LVCMOS33; +NET "ATDD<12>" LOC= A14 | IOSTANDARD = LVCMOS33; +NET "ATDD<13>" LOC= D18 | IOSTANDARD = LVCMOS33; +NET "ATDD<14>" LOC= A13 | IOSTANDARD = LVCMOS33; +NET "ATDD<15>" LOC= C13 | IOSTANDARD = LVCMOS33; +NET "ATDD<16>" LOC= D14 | IOSTANDARD = LVCMOS33; +NET "ATDD<17>" LOC= C17 | IOSTANDARD = LVCMOS33; +NET "ATDD<18>" LOC= E16 | IOSTANDARD = LVCMOS33; +NET "ATDD<19>" LOC= C14 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS10" LOC= B16 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS20" LOC= E21 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS1E" LOC= B14 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS2E" LOC= B17 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS3" LOC= C18 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS4" LOC= G21 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS5" LOC= A18 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS6" LOC= F10 | IOSTANDARD = LVCMOS33; +NET "TRACE_CLK" LOC= D15 | IOSTANDARD = LVCMOS33; +NET "CPU_HRESET" LOC= E11 | IOSTANDARD = LVCMOS33; +NET "CPU_TDO" LOC= K7 | IOSTANDARD = LVCMOS33; +NET "CPU_TMS" LOC= L5 | IOSTANDARD = LVCMOS33; +NET "CPU_TDI" LOC= M6 | IOSTANDARD = LVCMOS33; +NET "CPU_TRST" LOC= N7 | IOSTANDARD = LVCMOS33; +NET "CPU_TCK" LOC= T8 | IOSTANDARD = LVCMOS33; +NET "CPU_HALT_n" LOC= W4 | IOSTANDARD = LVCMOS33; + + +# voltage termination +CONFIG PROHIBIT = AA24; +CONFIG PROHIBIT = AE23; +CONFIG PROHIBIT = AF17; +CONFIG PROHIBIT = V26; +CONFIG PROHIBIT = E22; +CONFIG PROHIBIT = L25; + +# unused pins +CONFIG PROHIBIT = F9; +CONFIG PROHIBIT = D10; +CONFIG PROHIBIT = C12; +CONFIG PROHIBIT = C11; +CONFIG PROHIBIT = D11; +CONFIG PROHIBIT = AB16; +CONFIG PROHIBIT = AB22; +CONFIG PROHIBIT = AC17; +CONFIG PROHIBIT = AC21; +CONFIG PROHIBIT = AE22; +CONFIG PROHIBIT = AD23; +CONFIG PROHIBIT = AC24; +CONFIG PROHIBIT = AC23; +CONFIG PROHIBIT = AC22; +CONFIG PROHIBIT = AB22; +CONFIG PROHIBIT = AE21; +CONFIG PROHIBIT = AD21; +CONFIG PROHIBIT = AF19; +CONFIG PROHIBIT = AF18; +CONFIG PROHIBIT = AE18; +CONFIG PROHIBIT = AD18; +CONFIG PROHIBIT = AE17; +CONFIG PROHIBIT = AE16; +CONFIG PROHIBIT = AD16; +CONFIG PROHIBIT = G6; +CONFIG PROHIBIT = H24; +CONFIG PROHIBIT = J24; +CONFIG PROHIBIT = N23; +CONFIG PROHIBIT = N15; +CONFIG PROHIBIT = P14; +CONFIG PROHIBIT = V23; +CONFIG PROHIBIT = Y26; +CONFIG PROHIBIT = Y25; +CONFIG PROHIBIT = P21; +CONFIG PROHIBIT = R21; +CONFIG PROHIBIT = U22; + +# grounded pins from gigabit transcievers +CONFIG PROHIBIT = K4; +CONFIG PROHIBIT = K3; +CONFIG PROHIBIT = J1; +CONFIG PROHIBIT = K1; +CONFIG PROHIBIT = M1; +CONFIG PROHIBIT = L1; +CONFIG PROHIBIT = T3; +CONFIG PROHIBIT = T4; +CONFIG PROHIBIT = R1; +CONFIG PROHIBIT = T1; +CONFIG PROHIBIT = V1; +CONFIG PROHIBIT = U1; +CONFIG PROHIBIT = D3; +CONFIG PROHIBIT = D4; +CONFIG PROHIBIT = C1; +CONFIG PROHIBIT = D1; +CONFIG PROHIBIT = E1; +CONFIG PROHIBIT = F1; +CONFIG PROHIBIT = AB3; +CONFIG PROHIBIT = AB4; +CONFIG PROHIBIT = AA1; +CONFIG PROHIBIT = AB1; +CONFIG PROHIBIT = AC1; +CONFIG PROHIBIT = AD1; +CONFIG PROHIBIT = H2; +CONFIG PROHIBIT = J2; +CONFIG PROHIBIT = N2; +CONFIG PROHIBIT = M2; +CONFIG PROHIBIT = P2; +CONFIG PROHIBIT = R2; +CONFIG PROHIBIT = V2; +CONFIG PROHIBIT = W2; +CONFIG PROHIBIT = B2; +CONFIG PROHIBIT = C2; +CONFIG PROHIBIT = G2; +CONFIG PROHIBIT = F2; +CONFIG PROHIBIT = Y2; +CONFIG PROHIBIT = AA2; +CONFIG PROHIBIT = AD2; +CONFIG PROHIBIT = AE2; + diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj new file mode 100644 index 0000000..24120d5 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj @@ -0,0 +1,19 @@ +vhdl work ../top.vhd +vhdl zpu ../../../zpu_pkg.vhdl +vhdl zpu ../../../zpu_small.vhdl +vhdl zpu ../../../zpu_medium.vhdl +vhdl zpu ../../../roms/rom_pkg.vhdl +#vhdl zpu ../../../roms/hello_dbram.vhdl +#vhdl zpu ../../../roms/hello_bram.vhdl +vhdl zpu ../../../roms/dmips_dbram.vhdl +vhdl zpu ../../../roms/dmips_bram.vhdl +vhdl zpu ../../../helpers/zpu_small1.vhdl +vhdl zpu ../../../helpers/zpu_med1.vhdl +vhdl zpu ../../../devices/txt_util.vhdl +vhdl zpu ../../../devices/phi_io.vhdl +vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/gpio.vhdl +vhdl zpu ../../../devices/rx_unit.vhdl +vhdl zpu ../../../devices/tx_unit.vhdl +vhdl zpu ../../../devices/br_gen.vhdl +vhdl zpu ../../../devices/trace.vhdl diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut new file mode 100644 index 0000000..e0159fb --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut @@ -0,0 +1,39 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:2 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g HswapenPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ConfigFallback:Enable +-g SelectMAPAbort:Enable +-g BPI_page_size:1 +-g OverTempPowerDown:Disable +-g JTAG_SysMon:Enable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:Auto +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst new file mode 100644 index 0000000..7ca54bc --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst @@ -0,0 +1,60 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../synthesis_config/top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc5vfx30t-1-ff665 +-top top +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Off +-reduce_control_sets Off +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 32 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd new file mode 100644 index 0000000..560e685 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd @@ -0,0 +1,444 @@ +-- top module of +-- Avnet Virtex 5 FX Evaluation Board +-- +-- using following external connections: +-- pushbutton PB1 as reset +-- LEDs for output +-- RS232 (non USB) +-- + + +library ieee; +use ieee.std_logic_1164.all; + +library zpu; +use zpu.zpupkg.all; -- zpu_dbgo_t + +library unisim; +use unisim.vcomponents.ibufds; +use unisim.vcomponents.dcm_base; + + +entity top is + port ( + -- pragma translate_off + stop_simulation : out std_logic; + -- pragma translate_on + clk_100MHz : in std_logic; -- 100 MHz clock + clk_socket : in std_logic; -- user clock + user_clk_p : in std_logic; -- differential user clock + user_clk_n : in std_logic; -- differential user clock + -- + -- RS232 + rs232_rx : in std_logic; + rs232_tx : out std_logic; + rs232_rts : in std_logic; + rs232_cts : out std_logic; + -- RS232 USB + rs232_usb_rx : in std_logic; + rs232_usb_tx : out std_logic; + rs232_usb_reset_n : out std_logic; + -- + gpio_led_n : out std_logic_vector(7 downto 0); + gpio_dipswitch : in std_logic_vector(7 downto 0); + gpio_button : in std_logic_vector(3 downto 0); + -- + -- FLASH 8Mx16 + flash_a : out std_logic_vector(31 downto 7); + flash_dq : inout std_logic_vector(15 downto 0); + flash_wen : out std_logic; + flash_oen : out std_logic_vector(0 downto 0); + flash_cen : out std_logic_vector(0 downto 0); + flash_rp_n : out std_logic; + flash_byte_n : out std_logic; + flash_adv_n : out std_logic; + flash_clk : out std_logic; + flash_wait : in std_logic; + -- + -- DDR2 SDRAM 16Mx32 + ddr2_odt : in std_logic_vector(0 downto 0); + ddr2_a : out std_logic_vector(12 downto 0); + ddr2_ba : out std_logic_vector(1 downto 0); + ddr2_cas_n : out std_logic; + ddr2_cke : out std_logic; + ddr2_cs_n : out std_logic; + ddr2_ras_n : out std_logic; + ddr2_we_n : out std_logic; + ddr2_dm : out std_logic_vector(3 downto 0); + ddr2_dqs_p : inout std_logic_vector(3 downto 0); + ddr2_dqs_n : inout std_logic_vector(3 downto 0); + ddr2_dq : inout std_logic_vector(31 downto 0); + ddr2_ck_p : in std_logic_vector(1 downto 0); + ddr2_ck_n : in std_logic_vector(1 downto 0); + -- + -- Ethernet MAC + gmii_txer : out std_logic; + gmii_tx_clk : in std_logic; -- 25 MHz + gmii_rx_clk : in std_logic; -- 25 MHz + gmii_gtc_clk : out std_logic; + gmii_crs : in std_logic; + gmii_dv : in std_logic; + gmii_rx_data : in std_logic_vector(7 downto 0); + gmii_col : in std_logic; + gmii_rx_er : in std_logic; + gmii_tx_en : out std_logic; + gmii_tx_data : out std_logic_vector(7 downto 0); + gbe_rst_n : out std_logic; + gbe_mdc : out std_logic; + gbe_mdio : inout std_logic; + gbe_int_n : inout std_logic; + gbe_mclk : in std_logic; + -- + -- SysACE CompactFlash + sam_clk : in std_logic; + sam_a : out std_logic_vector(6 downto 0); + sam_d : inout std_logic_vector(15 downto 0); + sam_cen : out std_logic; + sam_oen : out std_logic; + sam_wen : out std_logic; + sam_mpirq : in std_logic; + sam_brdy : in std_logic; + sam_reset_n : out std_logic; + -- + -- Expansion Header + exp1_se_io : inout std_logic_vector(33 downto 0); + exp1_diff_p : inout std_logic_vector(21 downto 0); + exp1_diff_n : inout std_logic_vector(21 downto 0); + exp1_se_clk_out : out std_logic; + exp1_se_clk_in : in std_logic; + exp1_diff_clk_out_p : out std_logic; + exp1_diff_clk_out_n : out std_logic; + exp1_diff_clk_in_p : in std_logic; + exp1_diff_clk_in_n : in std_logic; + -- + -- Debug/Trace + atdd : inout std_logic_vector(19 downto 8); + trace_ts10 : inout std_logic; + trace_ts20 : inout std_logic; + trace_ts1e : inout std_logic; + trace_ts2e : inout std_logic; + trace_ts3 : inout std_logic; + trace_ts4 : inout std_logic; + trace_ts5 : inout std_logic; + trace_ts6 : inout std_logic; + trace_clk : in std_logic; + cpu_hreset : in std_logic; + cpu_tdo : out std_logic; + cpu_tms : in std_logic; + cpu_tdi : in std_logic; + cpu_trst : in std_logic; + cpu_tck : in std_logic; + cpu_halt_n : in std_logic + ); +end entity top; + + +architecture rtl of top is + + --------------------------- + -- type declarations + type zpu_type is (zpu_small, zpu_medium); + + --------------------------- + -- constant declarations + constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE + -- modify frequency here + constant clk_multiply : positive := 5; -- 7 for small, 5 for medium + constant clk_divide : positive := 4; -- 4 for small, 4 for medium + -- + -- + constant word_size_c : natural := 32; -- 32 bits data path + constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + -- + constant clk_frequency : positive := 100; -- input frequency for correct calculation + + --------------------------- + -- component declarations + component zpu_small1 is + generic ( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port ( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_small1; + + component zpu_med1 is + generic( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_med1; + + + + --------------------------- + -- signal declarations + signal sys_clk : std_ulogic; + signal dcm_base_i0_clk0 : std_ulogic; + signal dcm_base_i0_clkfx : std_ulogic; + signal clk_fb : std_ulogic; + signal clk : std_ulogic; + -- + signal reset_shift_reg : std_ulogic_vector(3 downto 0); + signal reset_sync : std_ulogic; + -- + signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info + signal zpu_i0_break : std_logic; + -- + signal ibufds_i0_o : std_ulogic; + signal ibufds_i1_o : std_ulogic; + -- + signal gpio_in : std_logic_vector(31 downto 0) := (others => '0'); + signal zpu_i0_gpio_out : std_logic_vector(31 downto 0); + signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0); + +begin + + -- default output drivers + -- to pass bitgen DRC + -- other used outputs are only commented + --rs232_tx <= '1'; + rs232_cts <= '1'; + rs232_usb_tx <= '1'; + rs232_usb_reset_n <= '1'; + -- + --gpio_led_n <= (others => '1'); + -- + flash_cen <= "1"; + flash_oen <= "1"; + flash_wen <= '1'; + flash_rp_n <= '1'; + flash_byte_n <= '1'; + flash_adv_n <= '1'; + flash_clk <= '0'; + flash_a <= (others => '0'); + flash_dq <= (others => 'Z'); + -- + ddr2_a <= (others => '0'); + ddr2_ba <= (others => '0'); + ddr2_dm <= (others => '0'); + ddr2_cs_n <= '1'; + ddr2_we_n <= '1'; + ddr2_cke <= '1'; + ddr2_cas_n <= '1'; + ddr2_ras_n <= '1'; + ddr2_dqs_p <= (others => 'Z'); + ddr2_dqs_n <= (others => 'Z'); + ddr2_dq <= (others => 'Z'); + -- + gmii_gtc_clk <= '0'; + gmii_tx_data <= (others => '0'); + gmii_tx_en <= '0'; + gmii_txer <= '0'; + gbe_rst_n <= '1'; + gbe_mdc <= '1'; + gbe_mdio <= 'Z'; + gbe_int_n <= 'Z'; + -- + sam_cen <= '1'; + sam_oen <= '1'; + sam_wen <= '1'; + sam_a <= (others => '0'); + sam_d <= (others => 'Z'); + sam_reset_n <= '1'; + -- + exp1_se_io <= (others => 'Z'); + exp1_diff_p <= (others => 'Z'); + exp1_diff_n <= (others => 'Z'); + exp1_se_clk_out <= '0'; + exp1_diff_clk_out_p <= '0'; + exp1_diff_clk_out_n <= '1'; + -- + atdd <= (others => 'Z'); + trace_ts10 <= 'Z'; + trace_ts20 <= 'Z'; + trace_ts1e <= 'Z'; + trace_ts2e <= 'Z'; + trace_ts3 <= 'Z'; + trace_ts4 <= 'Z'; + trace_ts5 <= 'Z'; + trace_ts6 <= 'Z'; + cpu_tdo <= '1'; + + + -- global differential input buffer + ibufds_i0 : ibufds + generic map ( + diff_term => true + ) + port map ( + o => ibufds_i0_o, + i => ddr2_ck_p(0), + ib => ddr2_ck_n(0) + ); + + -- global differential input buffer + ibufds_i1 : ibufds + generic map ( + diff_term => true + ) + port map ( + o => ibufds_i1_o, + i => ddr2_ck_p(1), + ib => ddr2_ck_n(1) + ); + + -- digital clock manager (DCM) + -- to generate higher/other system clock frequencys + dcm_base_i0: dcm_base + generic map ( + startup_wait => true, -- wait with DONE till locked + --dfs_frequency_mode => "HIGH", -- use this with zpu_small for 175 MHz + clkfx_multiply => clk_multiply, + clkfx_divide => clk_divide, + clk_feedback => "1X" + ) + port map ( + rst => '0', + clkin => clk_100MHz, + clk0 => dcm_base_i0_clk0, + clkfx => dcm_base_i0_clkfx, + clkfb => clk_fb + ); + + -- speaking names for dcm output + clk_fb <= dcm_base_i0_clk0; + clk <= dcm_base_i0_clkfx; + + + -- reset synchronizer + -- generate synchronous reset + reset_synchronizer : process(clk, gpio_button) + begin + if (gpio_button(0) = '1') then + reset_shift_reg <= (others => '1'); + elsif rising_edge(clk) then + reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0'; + end if; + end process; + reset_sync <= reset_shift_reg(reset_shift_reg'high); + + + + -- select instance of zpu + zpu_i0_small: if zpu_flavour = zpu_small generate + zpu_i0 : zpu_small1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; - CPU clock + rst_i => reset_sync, -- : in std_logic; - Reset + break_o => zpu_i0_break, -- : out std_logic; - Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic - UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_small; + + zpu_i0_medium: if zpu_flavour = zpu_medium generate + zpu_i0 : zpu_med1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; - CPU clock + rst_i => reset_sync, -- : in std_logic; - Reset + break_o => zpu_i0_break, -- : out std_logic; - Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic - UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_medium; + + -- pragma translate_off + stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation + + + trace_mod : trace + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + log_file => "zpu_trace.log" + ) + port map ( + clk_i => clk, + dbg_i => zpu_i0_dbg, + stop_i => zpu_i0_break, + busy_i => '0' + ); + -- pragma translate_on + + -- assign GPIOs + -- no bidirectional pins (e.g. headers), so + -- gpio_dir is unused + -- + -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 + -- + -- in -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + -- out -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + -- + -- + -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + -- + -- in gpio_dipswitch(7.....0) -- -- -- -- buttons3.0 + -- out -- -- -- -- -- -- -- -- led(7................0) + -- + + gpio_in(15 downto 8) <= gpio_dipswitch; + gpio_in( 3 downto 0) <= gpio_button; + + + -- switch on all LEDs in case of break + process + begin + wait until rising_edge(clk); + gpio_led_n <= not zpu_i0_gpio_out(7 downto 0); + if zpu_i0_break = '1' then + gpio_led_n <= (others => '0'); + end if; + end process; + + + +end architecture rtl; + diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd new file mode 100644 index 0000000..751ce22 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd @@ -0,0 +1,271 @@ +-- testbench for +-- Avnet Virtex 5 FX Evaluation Board +-- +-- includes "model" for clock generation +-- simulate press on gpio_button(0) (=PB1) as reset +-- +-- place models for external components (PHY, DDR2-RAM) in this file +-- + + +library ieee; +use ieee.std_logic_1164.all; + + +entity top_tb is +end entity top_tb; + +architecture testbench of top_tb is + + --------------------------- + -- constant declarations + constant clk_100MHz_period : time := 1 sec / 100_000_000; -- 100 MHz + + + --------------------------- + -- signal declarations + signal simulation_run : boolean := true; + signal tb_stop_simulation : std_logic; + -- + signal tb_clk_100MHz : std_logic := '0'; -- 100 MHz clock + signal tb_clk_socket : std_logic := '0'; -- user clock + signal tb_user_clk_p : std_logic := '0'; -- diff user clock + signal tb_user_clk_n : std_logic := '0'; -- diff user clock + -- + -- RS232 + signal tb_rs232_rx : std_logic := '0'; + signal tb_rs232_tx : std_logic; + signal tb_rs232_rts : std_logic := '0'; + signal tb_rs232_cts : std_logic; + -- RS232 USB + signal tb_rs232_usb_rx : std_logic := '0'; + signal tb_rs232_usb_tx : std_logic; + signal tb_rs232_usb_reset_n : std_logic; + -- + signal tb_gpio_led_n : std_logic_vector(7 downto 0); + signal tb_gpio_dipswitch : std_logic_vector(7 downto 0) := (others => '0'); + signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0'); + -- + -- FLASH 8Mx16 + signal tb_flash_a : std_logic_vector(31 downto 7); + signal tb_flash_dq : std_logic_vector(15 downto 0); + signal tb_flash_wen : std_logic; + signal tb_flash_oen : std_logic_vector(0 downto 0); + signal tb_flash_cen : std_logic_vector(0 downto 0); + signal tb_flash_rp_n : std_logic; + signal tb_flash_byte_n : std_logic; + signal tb_flash_adv_n : std_logic; + signal tb_flash_clk : std_logic; + signal tb_flash_wait : std_logic := '0'; + -- + -- DDR2 SDRAM 16Mx32 + signal tb_ddr2_odt : std_logic_vector(0 downto 0) := (others => '0'); + signal tb_ddr2_a : std_logic_vector(12 downto 0); + signal tb_ddr2_ba : std_logic_vector(1 downto 0); + signal tb_ddr2_cas_n : std_logic; + signal tb_ddr2_cke : std_logic; + signal tb_ddr2_cs_n : std_logic; + signal tb_ddr2_ras_n : std_logic; + signal tb_ddr2_we_n : std_logic; + signal tb_ddr2_dm : std_logic_vector(3 downto 0); + signal tb_ddr2_dqs_p : std_logic_vector(3 downto 0); + signal tb_ddr2_dqs_n : std_logic_vector(3 downto 0); + signal tb_ddr2_dq : std_logic_vector(31 downto 0); + signal tb_ddr2_ck_p : std_logic_vector(1 downto 0) := (others => '0'); + signal tb_ddr2_ck_n : std_logic_vector(1 downto 0) := (others => '0'); + -- + -- Ethernet MAC + signal tb_gmii_txer : std_logic; + signal tb_gmii_tx_clk : std_logic := '0'; -- 25 MHz + signal tb_gmii_rx_clk : std_logic := '0'; -- 25 MHz + signal tb_gmii_gtc_clk : std_logic; + signal tb_gmii_crs : std_logic := '0'; + signal tb_gmii_dv : std_logic := '0'; + signal tb_gmii_rx_data : std_logic_vector(7 downto 0); + signal tb_gmii_col : std_logic := '0'; + signal tb_gmii_rx_er : std_logic := '0'; + signal tb_gmii_tx_en : std_logic; + signal tb_gmii_tx_data : std_logic_vector(7 downto 0); + signal tb_gbe_rst_n : std_logic; + signal tb_gbe_mdc : std_logic; + signal tb_gbe_mdio : std_logic; + signal tb_gbe_int_n : std_logic; + signal tb_gbe_mclk : std_logic := '0'; + -- + -- SysACE CompactFlash + signal tb_sam_clk : std_logic := '0'; + signal tb_sam_a : std_logic_vector(6 downto 0); + signal tb_sam_d : std_logic_vector(15 downto 0); + signal tb_sam_cen : std_logic; + signal tb_sam_oen : std_logic; + signal tb_sam_wen : std_logic; + signal tb_sam_mpirq : std_logic := '0'; + signal tb_sam_brdy : std_logic := '0'; + signal tb_sam_reset_n : std_logic; + -- + -- Expansion Header + signal tb_exp1_se_io : std_logic_vector(33 downto 0); + signal tb_exp1_diff_p : std_logic_vector(21 downto 0); + signal tb_exp1_diff_n : std_logic_vector(21 downto 0); + signal tb_exp1_se_clk_out : std_logic; + signal tb_exp1_se_clk_in : std_logic := '0'; + signal tb_exp1_diff_clk_out_p : std_logic; + signal tb_exp1_diff_clk_out_n : std_logic; + signal tb_exp1_diff_clk_in_p : std_logic := '0'; + signal tb_exp1_diff_clk_in_n : std_logic := '0'; + -- + -- Debug/Trace + signal tb_atdd : std_logic_vector(19 downto 8); + signal tb_trace_ts10 : std_logic; + signal tb_trace_ts20 : std_logic; + signal tb_trace_ts1e : std_logic; + signal tb_trace_ts2e : std_logic; + signal tb_trace_ts3 : std_logic; + signal tb_trace_ts4 : std_logic; + signal tb_trace_ts5 : std_logic; + signal tb_trace_ts6 : std_logic; + signal tb_trace_clk : std_logic := '0'; + signal tb_cpu_hreset : std_logic := '0'; + signal tb_cpu_tdo : std_logic; + signal tb_cpu_tms : std_logic := '0'; + signal tb_cpu_tdi : std_logic := '0'; + signal tb_cpu_trst : std_logic := '0'; + signal tb_cpu_tck : std_logic := '0'; + signal tb_cpu_halt_n : std_logic := '0'; + + +begin + + + -- generate clocks + tb_clk_100MHz <= not tb_clk_100MHz after clk_100MHz_period / 2 when simulation_run; + + -- generate reset + tb_gpio_button(0) <= '1', '0' after 6.66 * clk_100MHz_period; + + + -- simulate keypress + tb_gpio_button(2) <= '0', '1' after 55 us, '0' after 56 us; + + -- dut + top_i0 : entity work.top + port map ( + stop_simulation => tb_stop_simulation, -- : out std_logic; + clk_100MHz => tb_clk_100MHz, -- : in std_logic; + clk_socket => tb_clk_socket, -- : in std_logic; + user_clk_p => tb_user_clk_p, -- : in std_logic; + user_clk_n => tb_user_clk_n, -- : in std_logic; + -- + -- RS232 + rs232_rx => tb_rs232_rx, -- : in std_logic; + rs232_tx => tb_rs232_tx, -- : out std_logic; + rs232_rts => tb_rs232_rts, -- : in std_logic; + rs232_cts => tb_rs232_cts, -- : out std_logic; + -- RS232 USB + rs232_usb_rx => tb_rs232_usb_rx, -- : in std_logic; + rs232_usb_tx => tb_rs232_usb_tx, -- : out std_logic; + rs232_usb_reset_n => tb_rs232_usb_reset_n, -- : out std_logic; + -- + gpio_led_n => tb_gpio_led_n, -- : out std_logic_vector(7 downto 0); + gpio_dipswitch => tb_gpio_dipswitch, -- : in std_logic_vector(7 downto 0); + gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0); + -- + -- FLASH 8Mx16 + flash_a => tb_flash_a, -- : out std_logic_vector(31 downto 7); + flash_dq => tb_flash_dq, -- : inout std_logic_vector(15 downto 0); + flash_wen => tb_flash_wen, -- : out std_logic; + flash_oen => tb_flash_oen, -- : out std_logic_vector(0 downto 0); + flash_cen => tb_flash_cen, -- : out std_logic_vector(0 downto 0); + flash_rp_n => tb_flash_rp_n, -- : out std_logic; + flash_byte_n => tb_flash_byte_n, -- : out std_logic; + flash_adv_n => tb_flash_adv_n, -- : out std_logic; + flash_clk => tb_flash_clk, -- : out std_logic; + flash_wait => tb_flash_wait, -- : in std_logic; + -- + -- DDR2 SDRAM 16Mx32 + ddr2_odt => tb_ddr2_odt, -- : in std_logic_vector(0 downto 0); + ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0); + ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(1 downto 0); + ddr2_cas_n => tb_ddr2_cas_n, -- : out std_logic; + ddr2_cke => tb_ddr2_cke, -- : out std_logic; + ddr2_cs_n => tb_ddr2_cs_n, -- : out std_logic; + ddr2_ras_n => tb_ddr2_ras_n, -- : out std_logic; + ddr2_we_n => tb_ddr2_we_n, -- : out std_logic; + ddr2_dm => tb_ddr2_dm, -- : out std_logic_vector(3 downto 0); + ddr2_dqs_p => tb_ddr2_dqs_p, -- : inout std_logic_vector(3 downto 0); + ddr2_dqs_n => tb_ddr2_dqs_n, -- : inout std_logic_vector(3 downto 0); + ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(31 downto 0); + ddr2_ck_p => tb_ddr2_ck_p, -- : in std_logic_vector(1 downto 0); + ddr2_ck_n => tb_ddr2_ck_n, -- : in std_logic_vector(1 downto 0); + -- + -- Ethernet MAC + gmii_txer => tb_gmii_txer, -- : out std_logic; + gmii_tx_clk => tb_gmii_tx_clk, -- : in std_logic; + gmii_rx_clk => tb_gmii_rx_clk, -- : in std_logic; + gmii_gtc_clk => tb_gmii_gtc_clk, -- : out std_logic; + gmii_crs => tb_gmii_crs, -- : in std_logic; + gmii_dv => tb_gmii_dv, -- : in std_logic; + gmii_rx_data => tb_gmii_rx_data, -- : in std_logic_vector(7 downto 0); + gmii_col => tb_gmii_col, -- : in std_logic; + gmii_rx_er => tb_gmii_rx_er, -- : in std_logic; + gmii_tx_en => tb_gmii_tx_en, -- : out std_logic; + gmii_tx_data => tb_gmii_tx_data, -- : out std_logic_vector(7 downto 0); + gbe_rst_n => tb_gbe_rst_n, -- : out std_logic; + gbe_mdc => tb_gbe_mdc, -- : out std_logic; + gbe_mdio => tb_gbe_mdio, -- : inout std_logic; + gbe_int_n => tb_gbe_int_n, -- : inout std_logic; + gbe_mclk => tb_gbe_mclk, -- : in std_logic; + -- + -- SysACE CompactFlash + sam_clk => tb_sam_clk, -- : in std_logic; + sam_a => tb_sam_a, -- : out std_logic_vector(6 downto 0); + sam_d => tb_sam_d, -- : inout std_logic_vector(15 downto 0); + sam_cen => tb_sam_cen, -- : out std_logic; + sam_oen => tb_sam_oen, -- : out std_logic; + sam_wen => tb_sam_wen, -- : out std_logic; + sam_mpirq => tb_sam_mpirq, -- : in std_logic; + sam_brdy => tb_sam_brdy, -- : in std_logic; + sam_reset_n => tb_sam_reset_n, -- : out std_logic; + -- + -- Expansion Header + exp1_se_io => tb_exp1_se_io, -- : inout std_logic_vector(33 downto 0); + exp1_diff_p => tb_exp1_diff_p, -- : inout std_logic_vector(21 downto 0); + exp1_diff_n => tb_exp1_diff_n, -- : inout std_logic_vector(21 downto 0); + exp1_se_clk_out => tb_exp1_se_clk_out, -- : out std_logic; + exp1_se_clk_in => tb_exp1_se_clk_in, -- : in std_logic; + exp1_diff_clk_out_p => tb_exp1_diff_clk_out_p, -- : out std_logic; + exp1_diff_clk_out_n => tb_exp1_diff_clk_out_n, -- : out std_logic; + exp1_diff_clk_in_p => tb_exp1_diff_clk_in_p, -- : in std_logic; + exp1_diff_clk_in_n => tb_exp1_diff_clk_in_n, -- : in std_logic; + -- + -- Debug/Trace + atdd => tb_atdd, -- : inout std_logic_vector(19 downto 8); + trace_ts10 => tb_trace_ts10, -- : inout std_logic; + trace_ts20 => tb_trace_ts20, -- : inout std_logic; + trace_ts1e => tb_trace_ts1e, -- : inout std_logic; + trace_ts2e => tb_trace_ts2e, -- : inout std_logic; + trace_ts3 => tb_trace_ts3, -- : inout std_logic; + trace_ts4 => tb_trace_ts4, -- : inout std_logic; + trace_ts5 => tb_trace_ts5, -- : inout std_logic; + trace_ts6 => tb_trace_ts6, -- : inout std_logic; + trace_clk => tb_trace_clk, -- : in std_logic; + cpu_hreset => tb_cpu_hreset, -- : in std_logic; + cpu_tdo => tb_cpu_tdo, -- : out std_logic; + cpu_tms => tb_cpu_tms, -- : in std_logic; + cpu_tdi => tb_cpu_tdi, -- : in std_logic; + cpu_trst => tb_cpu_trst, -- : in std_logic; + cpu_tck => tb_cpu_tck, -- : in std_logic; + cpu_halt_n => tb_cpu_halt_n -- : in std_logic + ); + + + -- check for simulation stopping + process (tb_stop_simulation) + begin + if tb_stop_simulation = '1' then + report "Simulation end." severity note; + simulation_run <= false; + end if; + end process; + +end architecture testbench; diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh new file mode 100755 index 0000000..d525737 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/gpio.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do new file mode 100644 index 0000000..0d29e0a --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do new file mode 100644 index 0000000..12582ce --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do @@ -0,0 +1,30 @@ +onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_rot_center
+add wave -noupdate /top_tb/tb_clk_50mhz
+add wave -noupdate /top_tb/tb_rs232_dce_rxd
+add wave -noupdate /top_tb/tb_rs232_dce_txd
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_btn_east
+add wave -noupdate /top_tb/tb_btn_north
+add wave -noupdate /top_tb/tb_btn_south
+add wave -noupdate /top_tb/tb_btn_west
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/top_i0/led
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {56714893 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {151772250 ps}
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh new file mode 100755 index 0000000..66622ea --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/digilent-starter-xc3s500e.ucf -p xc3s500e-fg320-4 top.ngc top.ngd +map -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf +par -w -ol high -t 1 top_map.ncd top.ncd top.pcf +trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf new file mode 100644 index 0000000..1007d00 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf @@ -0,0 +1,356 @@ +#####################################################
+# SPARTAN-3E Starter Kit Board Constraints File
+#
+# Family: Spartan3E
+# Device: XC3S500E
+# Package: FG320
+# Speed: -4
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
+TIMESPEC "TS_CLK_50MHZ" = PERIOD "CLK_50MHZ" 50.0 MHz HIGH 40%;
+
+# ethernet clock
+TIMESPEC "TS_E_CLK" = PERIOD "E_CLK" 25.0 MHz HIGH 50% ;
+# need because misplaced ethernet clock lines
+NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;
+NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;
+
+############################################################
+## pin placement constraints
+############################################################
+
+# Analog-to-Digital Converter (ADC)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Programmable Gain Amplifier (AMP)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
+NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Pushbuttons (BTN)
+NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+
+# Clock inputs (CLK)
+NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 | TNM_NET = "CLK_50MHZ";
+NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
+NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
+
+# Digital-to-Analog Converter (DAC)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# 1-Wire Secure EEPROM (DS)
+NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+
+# Ethernet PHY (E)
+NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
+NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
+NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";
+NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
+NET "E_RX_ER" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";
+NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TX_ER" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# FPGA Configuration Mode, INIT_B Pins (FPGA)
+NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
+
+# FX2 Connector (FX2)
+NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
+NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J1 6-pin accessory header
+NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J2 6-pin accessory header
+NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J4 6-pin accessory header
+NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# The discrete LEDs are shared with the following 8 FX2 connections
+NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#
+NET "FX2_IO<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#
+NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# 6-pin header J1
+# These are shared connections with the FX2 connector
+#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# 6-pin header J2
+# These are shared connections with the FX2 connector
+#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# 6-pin header J4
+# These are shared connections with the FX2 connector
+#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# Character LCD (LCD)
+NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# LCD data connections are shared with StrataFlash connections SF_D<11:8>
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# Discrete LEDs (LED)
+# These are shared connections with the FX2 connector
+#NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+
+# PS/2 Mouse/Keyboard Port (PS2)
+NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;
+NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;
+
+# Rotary Pushbutton Switch (ROT)
+NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+
+# RS-232 Serial Ports (RS232)
+NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL | TIG;
+NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;
+NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL | TIG;
+NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;
+
+# DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
+NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
+NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
+NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
+NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;
+NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;
+NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
+NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
+NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
+NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
+NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
+NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
+# Path to allow connection to top DCM connection
+NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
+
+# Prohibit VREF pins
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = L5;
+CONFIG PROHIBIT = R4;
+
+# Intel StrataFlash Parallel NOR Flash (SF)
+NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
+NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# STMicro SPI serial Flash (SPI)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
+NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 | PULLUP ;
+NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Slide Switches (SW)
+NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP | TIG;
+
+# VGA Port (VGA)
+NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+
+# Xilinx CPLD (XC)
+NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
+NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
+NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# prohibit unused pins
+CONFIG PROHIBIT = A3;
+CONFIG PROHIBIT = A7;
+CONFIG PROHIBIT = D13;
+CONFIG PROHIBIT = F10;
+CONFIG PROHIBIT = G10;
+CONFIG PROHIBIT = C8;
+CONFIG PROHIBIT = D8;
+CONFIG PROHIBIT = A5;
+CONFIG PROHIBIT = B5;
+#
+CONFIG PROHIBIT = P13;
+CONFIG PROHIBIT = R13;
+CONFIG PROHIBIT = T14;
+CONFIG PROHIBIT = R14;
+#
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = F5;
+CONFIG PROHIBIT = G1;
+CONFIG PROHIBIT = J7;
+CONFIG PROHIBIT = K2;
+CONFIG PROHIBIT = K7;
+CONFIG PROHIBIT = M1;
+CONFIG PROHIBIT = N1;
+CONFIG PROHIBIT = N2;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = U1;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj new file mode 100644 index 0000000..965ae4c --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj @@ -0,0 +1,19 @@ +vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut new file mode 100644 index 0000000..4bf13c6 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut @@ -0,0 +1,22 @@ +-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst new file mode 100644 index 0000000..d357860 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst @@ -0,0 +1,56 @@ +set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s500e-4-fg320
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd new file mode 100644 index 0000000..4adc18b --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd @@ -0,0 +1,464 @@ +-- top module of
+-- Spartan-3E Starter Kit Board
+--
+-- using following external connections:
+-- rotary pushbutton as reset
+-- LEDs for output
+-- RS232 (DCE, the left one)
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ --
+ -- Analog-to-Digital Converter (ADC)
+ ad_conv : out std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ amp_cs : out std_logic; -- active low chip select
+ amp_dout : in std_logic;
+ amp_shdn : out std_logic; -- active high shutdown, reset
+ -- Pushbuttons (BTN)
+ btn_east : in std_logic;
+ btn_north : in std_logic;
+ btn_south : in std_logic;
+ btn_west : in std_logic;
+ -- Clock inputs (CLK)
+ clk_50mhz : in std_logic;
+ clk_aux : in std_logic;
+ clk_sma : in std_logic;
+ -- Digital-to-Analog Converter (DAC)
+ dac_clr : out std_logic; -- async, active low reset input
+ dac_cs : out std_logic; -- active low chip select, conv start with rising edge
+ -- 1-Wire Secure EEPROM (DS)
+ ds_wire : inout std_logic;
+ -- Ethernet PHY (E)
+ e_col : in std_logic; -- MII collision detect
+ e_crs : in std_logic; -- carrier sense
+ e_mdc : out std_logic; -- management clock
+ e_mdio : inout std_logic; -- management data io
+ e_rx_clk : in std_logic; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ e_rx_dv : in std_logic; -- receive data valid
+ e_rxd : in std_logic_vector(3 downto 0);
+ e_rx_er : in std_logic;
+ e_tx_clk : in std_logic; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ e_tx_en : out std_logic; -- transmit enable
+ e_txd : out std_logic_vector(3 downto 0);
+ e_tx_er : out std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ fpga_m0 : inout std_logic;
+ fpga_m1 : inout std_logic;
+ fpga_m2 : inout std_logic;
+ fpga_init_b : inout std_logic;
+ fpga_rdwr_b : in std_logic;
+ fpga_hswap : in std_logic;
+ -- FX2 Connector (FX2)
+ fx2_clkin : inout std_logic;
+ fx2_clkio : inout std_logic;
+ fx2_clkout : inout std_logic;
+ fx2_io : inout std_logic_vector(40 downto 1);
+ -- These are shared connections with the FX2 connector
+ --j1 : inout std_logic_vector(3 downto 0);
+ --j2 : inout std_logic_vector(3 downto 0);
+ --j4 : inout std_logic_vector(3 downto 0);
+ --led : out std_logic_vector(7 downto 0);
+ -- Character LCD (LCD)
+ lcd_e : out std_logic;
+ lcd_rs : out std_logic;
+ lcd_rw : out std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ --sf_d : inout std_ulogic_vector(11 downto 8);
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ ps2_clk : inout std_logic;
+ ps2_data : inout std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ rot_a : in std_logic;
+ rot_b : in std_logic;
+ rot_center : in std_logic;
+ -- RS-232 Serial Ports (RS232)
+ rs232_dce_rxd : in std_logic;
+ rs232_dce_txd : out std_logic;
+ rs232_dte_rxd : in std_logic;
+ rs232_dte_txd : out std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ sd_a : out std_logic_vector(12 downto 0); -- address inputs
+ sd_dq : inout std_logic_vector(15 downto 0); -- data io
+ sd_ba : out std_logic_vector(1 downto 0); -- bank address inputs
+ sd_ras : out std_logic; -- command output
+ sd_cas : out std_logic; -- command output
+ sd_we : out std_logic; -- command output
+ sd_udm : out std_logic; -- data mask
+ sd_ldm : out std_logic; -- data mask
+ sd_udqs : inout std_logic; -- data strobe
+ sd_ldqs : inout std_logic; -- data strobe
+ sd_cs : out std_logic; -- active low chip select
+ sd_cke : out std_logic; -- active high clock enable
+ sd_ck_n : out std_logic; -- differential clock
+ sd_ck_p : out std_logic; -- differential clock
+ -- Path to allow connection to top DCM connection
+ sd_ck_fb : in std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ sf_a : out std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32
+ sf_byte : out std_logic;
+ sf_ce0 : out std_logic;
+ sf_d : inout std_logic_vector(15 downto 1);
+ sf_oe : out std_logic;
+ sf_sts : in std_logic;
+ sf_we : out std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ spi_mosi : out std_logic; -- master out slave in
+ spi_miso : in std_logic; -- master in slave out
+ spi_sck : out std_logic; -- clock
+ spi_ss_b : out std_logic; -- active low slave select
+ spi_alt_cs_jp11 : out std_logic;
+ -- Slide Switches (SW)
+ sw : in std_logic_vector(3 downto 0);
+ -- VGA Port (VGA)
+ vga_blue : out std_logic;
+ vga_green : out std_logic;
+ vga_hsync : out std_logic;
+ vga_red : out std_logic;
+ vga_vsync : out std_logic;
+ -- Xilinx CPLD (XC)
+ xc_cmd : out std_logic_vector(1 downto 0);
+ xc_cpld_en : out std_logic;
+ xc_d : inout std_logic_vector(2 downto 0);
+ xc_trig : in std_logic;
+ xc_gck0 : inout std_logic;
+ gclk10 : inout std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 3; -- 2 for small, 3 for medium
+ constant clk_divide : positive := 2; -- 1 for small, 2 for medium
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+
+
+ constant spi_ss_b_disable : std_ulogic := '1'; -- 1 = disable SPI serial flash
+ constant dac_cs_disable : std_ulogic := '1'; -- 1 = disable DAC
+ constant amp_cs_disable : std_ulogic := '1'; -- 1 = disable programmable pre-amplifier
+ constant ad_conv_disable : std_ulogic := '0'; -- 0 = disable ADC
+ constant sf_ce0_disable : std_ulogic := '1';
+ constant fpga_init_b_disable : std_ulogic := '1'; -- 1 = disable pflatform flash PROM
+ --
+ -- connect ldc to fpga
+ constant sf_ce0_lcd_to_fpga : std_ulogic := '1';
+ --
+ constant clk_frequency : positive := 50; -- input frequency for correct calculation
+
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+ ---------------------------
+ -- signal declarations
+ signal dcm_sp_i0_clk0 : std_ulogic;
+ signal dcm_sp_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+ ---------------------------
+ -- alias declarations
+ alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13);
+
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- outputs used by design are commented
+ --
+ ad_conv <= ad_conv_disable;
+ amp_cs <= amp_cs_disable;
+ amp_shdn <= '1';
+ --
+ dac_clr <= '0';
+ dac_cs <= dac_cs_disable;
+ --
+ ds_wire <= 'Z';
+ --
+ e_txd(3 downto 0) <= (others => '1');
+ e_tx_en <= '0';
+ e_tx_er <= '0';
+ e_mdc <= '1';
+ e_mdio <= 'Z';
+ --
+ fpga_m0 <= 'Z';
+ fpga_m1 <= 'Z';
+ fpga_m2 <= 'Z';
+ fpga_init_b <= fpga_init_b_disable;
+ --
+ fx2_clkin <= 'Z';
+ fx2_clkio <= 'Z';
+ fx2_clkout <= 'Z';
+ fx2_io <= (others => 'Z');
+ --
+ lcd_e <= '0';
+ lcd_rs <= '0';
+ lcd_rw <= '0';
+ --
+ ps2_clk <= 'Z';
+ ps2_data <= 'Z';
+ --
+ --rs232_dce_txd <= '1';
+ rs232_dte_txd <= '1';
+ --
+ sd_a <= (others => '1');
+ sd_dq <= (others => 'Z');
+ sd_ba <= (others => '1');
+ sd_ras <= '0';
+ sd_cas <= '0';
+ sd_we <= '0';
+ sd_udm <= '1';
+ sd_ldm <= '1';
+ sd_udqs <= '1';
+ sd_ldqs <= '1';
+ sd_cs <= '1';
+ sd_cke <= '1';
+ sd_ck_n <= '0';
+ sd_ck_p <= '1';
+ --
+ sf_a <= (others => '0');
+ sf_byte <= '0';
+ sf_ce0 <= sf_ce0_lcd_to_fpga;
+ sf_d <= (others => 'Z');
+ sf_oe <= '1';
+ sf_we <= '0';
+ --
+ spi_mosi <= '0';
+ spi_sck <= '0';
+ spi_ss_b <= spi_ss_b_disable;
+ spi_alt_cs_jp11 <= spi_ss_b_disable;
+ --
+ vga_red <= '0';
+ vga_green <= '0';
+ vga_blue <= '0';
+ vga_hsync <= '0';
+ vga_vsync <= '0';
+ --
+ xc_cmd <= "00";
+ xc_d <= (others => 'Z');
+ xc_cpld_en <= '0';
+ xc_gck0 <= 'Z';
+ gclk10 <= 'Z';
+ -- led out
+ --fx2_io(20 downto 13) <= (others => '0');
+
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_sp_i0 : dcm_sp
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ clkin => clk_50mhz,
+ clk0 => dcm_sp_i0_clk0,
+ clkfx => dcm_sp_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ clk_fb <= dcm_sp_i0_clk0;
+ clk <= dcm_sp_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, rot_center)
+ begin
+ if rot_center = '1' then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+ -- select instance of zpu
+ zpu_i0_small : if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_dce_rxd, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium : if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_dce_rxd, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break;
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+
+ -- assign GPIOs
+ -- no bidirectional pins (e.g. headers), so
+ -- gpio_dir is unused
+ --
+ -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+ --
+ -- in -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- out -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ --
+ --
+ -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ --
+ -- in -- -- -- -- sw(3.....0) -- ra rb rc be bn bs bw
+ -- out -- -- -- -- -- -- -- -- led(7................0)
+
+ gpio_in <= ((11) => sw(3),
+ (10) => sw(2),
+ ( 9) => sw(1),
+ ( 8) => sw(0),
+ --
+ ( 6) => rot_a,
+ ( 5) => rot_b,
+ ( 4) => rot_center,
+ --
+ ( 3) => btn_east,
+ ( 2) => btn_north,
+ ( 1) => btn_south,
+ ( 0) => btn_west,
+ others => '0');
+
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ led <= zpu_i0_gpio_out(7 downto 0);
+ if zpu_i0_break = '1' then
+ led <= (others => '1');
+ end if;
+ end process;
+
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd new file mode 100644 index 0000000..d62bed9 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd @@ -0,0 +1,281 @@ +-- testbench for
+-- Digilent Spartan 3E Starter Board
+--
+-- includes "model" for clock generation
+-- simulate press on Rotary Pushbutton Switch as reset
+--
+-- place models for external components (PHY, SDRAM) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant clk_50mhz_period : time := 1 sec / 50_000_000; -- 50 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ -- Analog-to-Digital Converter (ADC)
+ signal tb_ad_conv : std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ signal tb_amp_cs : std_logic; -- active low chip select
+ signal tb_amp_dout : std_logic := '1';
+ signal tb_amp_shdn : std_logic; -- active high shutdown, reset
+ -- Pushbuttons (BTN)
+ signal tb_btn_east : std_logic := '0';
+ signal tb_btn_north : std_logic := '0';
+ signal tb_btn_south : std_logic := '0';
+ signal tb_btn_west : std_logic := '0';
+ -- Clock inputs (CLK)
+ signal tb_clk_50mhz : std_logic := '0';
+ signal tb_clk_aux : std_logic := '0';
+ signal tb_clk_sma : std_logic := '0';
+ -- Digital-to-Analog Converter (DAC)
+ signal tb_dac_clr : std_logic; -- async, active low reset input
+ signal tb_dac_cs : std_logic; -- active low chip select, conv start with rising edge
+ -- 1-Wire Secure EEPROM (DS)
+ signal tb_ds_wire : std_logic;
+ -- Ethernet PHY (E)
+ signal tb_e_col : std_logic := '0'; -- MII collision detect
+ signal tb_e_crs : std_logic := '0'; -- carrier sense
+ signal tb_e_mdc : std_logic; -- management clock
+ signal tb_e_mdio : std_logic; -- management data io
+ signal tb_e_rx_clk : std_logic := '0'; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ signal tb_e_rx_dv : std_logic := '0'; -- receive data valid
+ signal tb_e_rxd : std_logic_vector(3 downto 0) := (others => '0');
+ signal tb_e_rx_er : std_logic := '0';
+ signal tb_e_tx_clk : std_logic := '0'; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ signal tb_e_tx_en : std_logic; -- transmit enable
+ signal tb_e_txd : std_logic_vector(3 downto 0);
+ signal tb_e_tx_er : std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ signal tb_fpga_m0 : std_logic;
+ signal tb_fpga_m1 : std_logic;
+ signal tb_fpga_m2 : std_logic;
+ signal tb_fpga_init_b : std_logic;
+ signal tb_fpga_rdwr_b : std_logic := '0';
+ signal tb_fpga_hswap : std_logic := '0';
+ -- FX2 Connector (FX2)
+ signal tb_fx2_clkin : std_logic;
+ signal tb_fx2_clkio : std_logic;
+ signal tb_fx2_clkout : std_logic;
+ signal tb_fx2_io : std_logic_vector(40 downto 1);
+ -- Character LCD (LCD)
+ signal tb_lcd_e : std_logic;
+ signal tb_lcd_rs : std_logic;
+ signal tb_lcd_rw : std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ signal tb_ps2_clk : std_logic;
+ signal tb_ps2_data : std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ signal tb_rot_a : std_logic := '0';
+ signal tb_rot_b : std_logic := '0';
+ signal tb_rot_center : std_logic; -- use as reset
+ -- RS-232 Serial Ports (RS232)
+ signal tb_rs232_dce_rxd : std_logic := '1';
+ signal tb_rs232_dce_txd : std_logic;
+ signal tb_rs232_dte_rxd : std_logic := '1';
+ signal tb_rs232_dte_txd : std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ signal tb_sd_a : std_logic_vector(12 downto 0); -- address inputs
+ signal tb_sd_dq : std_logic_vector(15 downto 0); -- data io
+ signal tb_sd_ba : std_logic_vector(1 downto 0); -- bank address inputs
+ signal tb_sd_ras : std_logic; -- command output
+ signal tb_sd_cas : std_logic; -- command output
+ signal tb_sd_we : std_logic; -- command output
+ signal tb_sd_udm : std_logic; -- data mask
+ signal tb_sd_ldm : std_logic; -- data mask
+ signal tb_sd_udqs : std_logic; -- data strobe
+ signal tb_sd_ldqs : std_logic; -- data strobe
+ signal tb_sd_cs : std_logic; -- active low chip select
+ signal tb_sd_cke : std_logic; -- active high clock enable
+ signal tb_sd_ck_n : std_logic; -- differential clock
+ signal tb_sd_ck_p : std_logic; -- differential clock
+ -- Path to allow connection to top DCM connection
+ signal tb_sd_ck_fb : std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ signal tb_sf_a : std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32 :-(
+ signal tb_sf_byte : std_logic;
+ signal tb_sf_ce0 : std_logic;
+ signal tb_sf_d : std_logic_vector(15 downto 1);
+ signal tb_sf_oe : std_logic;
+ signal tb_sf_sts : std_logic := '0';
+ signal tb_sf_we : std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ signal tb_spi_mosi : std_logic; -- master out slave in
+ signal tb_spi_miso : std_logic := '0'; -- master in slave out
+ signal tb_spi_sck : std_logic; -- clock
+ signal tb_spi_ss_b : std_logic; -- active low slave select
+ signal tb_spi_alt_cs_jp11 : std_logic;
+ -- Slide Switches (SW)
+ signal tb_sw : std_logic_vector(3 downto 0) := (others => '0');
+ -- VGA Port (VGA)
+ signal tb_vga_blue : std_logic;
+ signal tb_vga_green : std_logic;
+ signal tb_vga_hsync : std_logic;
+ signal tb_vga_red : std_logic;
+ signal tb_vga_vsync : std_logic;
+ -- Xilinx CPLD (XC)
+ signal tb_xc_cmd : std_logic_vector(1 downto 0);
+ signal tb_xc_cpld_en : std_logic;
+ signal tb_xc_d : std_logic_vector(2 downto 0);
+ signal tb_xc_trig : std_logic := '0';
+ signal tb_xc_gck0 : std_logic;
+ signal tb_gclk10 : std_logic;
+
+
+begin
+
+
+ -- generate clock
+ tb_clk_50mhz <= not tb_clk_50mhz after clk_50mhz_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_rot_center <= '1', '0' after 6.66 * clk_50mhz_period;
+
+
+ -- clock feedback for SD-RAM (on board)
+ tb_sd_ck_fb <= tb_sd_ck_p;
+
+ -- simulate keypress
+ tb_btn_north <= '0', '1' after 55 us, '0' after 56 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ -- Analog-to-Digital Converter (ADC)
+ ad_conv => tb_ad_conv, -- : out std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ amp_cs => tb_amp_cs, -- : out std_logic;
+ amp_dout => tb_amp_dout, -- : in std_logic;
+ amp_shdn => tb_amp_shdn, -- : out std_logic;
+ -- Pushbuttons (BTN)
+ btn_east => tb_btn_east, -- : in std_logic;
+ btn_north => tb_btn_north, -- : in std_logic;
+ btn_south => tb_btn_south, -- : in std_logic;
+ btn_west => tb_btn_west, -- : in std_logic;
+ -- Clock inputs (CLK)
+ clk_50mhz => tb_clk_50mhz, -- : in std_logic;
+ clk_aux => tb_clk_aux, -- : in std_logic;
+ clk_sma => tb_clk_sma, -- : in std_logic;
+ -- Digital-to-Analog Converter (DAC)
+ dac_clr => tb_dac_clr, -- : out std_logic;
+ dac_cs => tb_dac_cs, -- : out std_logic;
+ -- 1-Wire Secure EEPROM (DS)
+ ds_wire => tb_ds_wire, -- : inout std_logic;
+ -- Ethernet PHY (E)
+ e_col => tb_e_col, -- : in std_logic;
+ e_crs => tb_e_crs, -- : in std_logic;
+ e_mdc => tb_e_mdc, -- : out std_logic;
+ e_mdio => tb_e_mdio, -- : inout std_logic;
+ e_rx_clk => tb_e_rx_clk, -- : in std_logic;
+ e_rx_dv => tb_e_rx_dv, -- : in std_logic;
+ e_rxd => tb_e_rxd, -- : in std_logic_vector(3 downto 0);
+ e_rx_er => tb_e_rx_er, -- : in std_logic;
+ e_tx_clk => tb_e_tx_clk, -- : in std_logic;
+ e_tx_en => tb_e_tx_en, -- : out std_logic;
+ e_txd => tb_e_txd, -- : out std_logic_vector(3 downto 0);
+ e_tx_er => tb_e_tx_er, -- : out std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ fpga_m0 => tb_fpga_m0, -- : inout std_logic;
+ fpga_m1 => tb_fpga_m1, -- : inout std_logic;
+ fpga_m2 => tb_fpga_m2, -- : inout std_logic;
+ fpga_init_b => tb_fpga_init_b, -- : inout std_logic;
+ fpga_rdwr_b => tb_fpga_rdwr_b, -- : in std_logic;
+ fpga_hswap => tb_fpga_hswap, -- : in std_logic;
+ -- FX2 Connector (FX2)
+ fx2_clkin => tb_fx2_clkin, -- : inout std_logic;
+ fx2_clkio => tb_fx2_clkio, -- : inout std_logic;
+ fx2_clkout => tb_fx2_clkout, -- : inout std_logic;
+ fx2_io => tb_fx2_io, -- : inout std_logic_vector(40 downto 1);
+ -- Character LCD (LCD)
+ lcd_e => tb_lcd_e, -- : out std_logic;
+ lcd_rs => tb_lcd_rs, -- : out std_logic;
+ lcd_rw => tb_lcd_rw, -- : out std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ ps2_clk => tb_ps2_clk, -- : inout std_logic;
+ ps2_data => tb_ps2_data, -- : inout std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ rot_a => tb_rot_a, -- : in std_logic;
+ rot_b => tb_rot_b, -- : in std_logic;
+ rot_center => tb_rot_center, -- : in std_logic;
+ -- RS-232 Serial Ports (RS232)
+ rs232_dce_rxd => tb_rs232_dce_rxd, -- : in std_logic;
+ rs232_dce_txd => tb_rs232_dce_txd, -- : out std_logic;
+ rs232_dte_rxd => tb_rs232_dte_rxd, -- : in std_logic;
+ rs232_dte_txd => tb_rs232_dte_txd, -- : out std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ sd_a => tb_sd_a, -- : out std_logic_vector(12 downto 0);
+ sd_dq => tb_sd_dq, -- : inout std_logic_vector(15 downto 0);
+ sd_ba => tb_sd_ba, -- : out std_logic_vector(1 downto 0);
+ sd_ras => tb_sd_ras, -- : out std_logic;
+ sd_cas => tb_sd_cas, -- : out std_logic;
+ sd_we => tb_sd_we, -- : out std_logic;
+ sd_udm => tb_sd_udm, -- : out std_logic;
+ sd_ldm => tb_sd_ldm, -- : out std_logic;
+ sd_udqs => tb_sd_udqs, -- : inout std_logic;
+ sd_ldqs => tb_sd_ldqs, -- : inout std_logic;
+ sd_cs => tb_sd_cs, -- : out std_logic;
+ sd_cke => tb_sd_cke, -- : out std_logic;
+ sd_ck_n => tb_sd_ck_n, -- : out std_logic;
+ sd_ck_p => tb_sd_ck_p, -- : out std_logic;
+ -- Path to allow connection to top DCM connection
+ sd_ck_fb => tb_sd_ck_fb, -- : in std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ sf_a => tb_sf_a, -- : out std_logic_vector(23 downto 0);
+ sf_byte => tb_sf_byte, -- : out std_logic;
+ sf_ce0 => tb_sf_ce0, -- : out std_logic;
+ sf_d => tb_sf_d, -- : inout std_logic_vector(15 downto 1);
+ sf_oe => tb_sf_oe, -- : out std_logic;
+ sf_sts => tb_sf_sts, -- : in std_logic;
+ sf_we => tb_sf_we, -- : out std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ spi_mosi => tb_spi_mosi, -- : out std_logic;
+ spi_miso => tb_spi_miso, -- : in std_logic;
+ spi_sck => tb_spi_sck, -- : out std_logic;
+ spi_ss_b => tb_spi_ss_b, -- : out std_logic;
+ spi_alt_cs_jp11 => tb_spi_alt_cs_jp11, -- : out std_logic;
+ -- Slide Switches (SW)
+ sw => tb_sw, -- : in std_logic_vector(3 downto 0);
+ -- VGA Port (VGA)
+ vga_blue => tb_vga_blue, -- : out std_logic;
+ vga_green => tb_vga_green, -- : out std_logic;
+ vga_hsync => tb_vga_hsync, -- : out std_logic;
+ vga_red => tb_vga_red, -- : out std_logic;
+ vga_vsync => tb_vga_vsync, -- : out std_logic;
+ -- Xilinx CPLD (XC)
+ xc_cmd => tb_xc_cmd, -- : out std_logic_vector(1 downto 0);
+ xc_cpld_en => tb_xc_cpld_en, -- : out std_logic;
+ xc_d => tb_xc_d, -- : inout std_logic_vector(2 downto 0);
+ xc_trig => tb_xc_trig, -- : in std_logic;
+ xc_gck0 => tb_xc_gck0, -- : inout std_logic;
+ gclk10 => tb_gclk10 -- : inout std_logic
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+
+end architecture testbench;
diff --git a/zpu/hdl/zealot/fpga/dmips_med1.vhdl b/zpu/hdl/zealot/fpga/dmips_med1.vhdl new file mode 100644 index 0000000..b95016c --- /dev/null +++ b/zpu/hdl/zealot/fpga/dmips_med1.vhdl @@ -0,0 +1,119 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ---- +---- 3 1500 Xilinx FPGA available in the GR-XC3S board from Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DMIPS_Med1(FPGA) (Entity and architecture) ---- +---- File name: dmips_med1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity DMIPS_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity DMIPS_Med1; + +architecture FPGA of DMIPS_Med1 is + component ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Med1; +begin + zpu : ZPU_Med1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0')); +end architecture FPGA; -- Entity: DMIPS_Med1 + diff --git a/zpu/hdl/zealot/fpga/dmips_small1.vhdl b/zpu/hdl/zealot/fpga/dmips_small1.vhdl new file mode 100644 index 0000000..6edec00 --- /dev/null +++ b/zpu/hdl/zealot/fpga/dmips_small1.vhdl @@ -0,0 +1,120 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a ---- +---- Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from ---- +---- Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DMIPS_Small1(FPGA) (Entity and architecture) ---- +---- File name: dmips_small1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity DMIPS_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity DMIPS_Small1; + +architecture FPGA of DMIPS_Small1 is + component ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Small1; +begin + zpu : ZPU_Small1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0')); +end architecture FPGA; -- Entity: DMIPS_Small1 + diff --git a/zpu/hdl/zealot/fpga/hello_med1.vhdl b/zpu/hdl/zealot/fpga/hello_med1.vhdl new file mode 100644 index 0000000..5ffea1f --- /dev/null +++ b/zpu/hdl/zealot/fpga/hello_med1.vhdl @@ -0,0 +1,119 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ---- +---- 3 1500 Xilinx FPGA available in the GR-XC3S board from Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Hello_Med1(FPGA) (Entity and architecture) ---- +---- File name: hello_med1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity Hello_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=14); -- 14 bits RAM space=16 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity Hello_Med1; + +architecture FPGA of Hello_Med1 is + component ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Med1; +begin + zpu : ZPU_Med1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0')); +end architecture FPGA; -- Entity: Hello_Med1 + diff --git a/zpu/hdl/zealot/fpga/hello_small1.vhdl b/zpu/hdl/zealot/fpga/hello_small1.vhdl new file mode 100644 index 0000000..a7e2c21 --- /dev/null +++ b/zpu/hdl/zealot/fpga/hello_small1.vhdl @@ -0,0 +1,120 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a ---- +---- Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from ---- +---- Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Hello_Small1(FPGA) (Entity and architecture) ---- +---- File name: hello_small1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity Hello_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=14); -- 14 bits RAM space=16 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity Hello_Small1; + +architecture FPGA of Hello_Small1 is + component ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Small1; +begin + zpu : ZPU_Small1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0')); +end architecture FPGA; -- Entity: Hello_Small1 + diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh new file mode 100755 index 0000000..d525737 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/gpio.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do new file mode 100644 index 0000000..0d29e0a --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do new file mode 100644 index 0000000..6a3731d --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do @@ -0,0 +1,163 @@ +onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/simulation_run
+add wave -noupdate /top_tb/tb_cpu_reset
+add wave -noupdate /top_tb/tb_sysclk_n
+add wave -noupdate /top_tb/tb_sysclk_p
+add wave -noupdate /top_tb/tb_user_clock
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/top_i0/clk
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_gpio_button
+add wave -noupdate /top_tb/tb_gpio_header_ls
+add wave -noupdate /top_tb/tb_gpio_led
+add wave -noupdate /top_tb/tb_gpio_switch
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_cts
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rts
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rx
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_tx
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_a
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ba
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cas_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ras_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_we_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cke
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_dq
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldm
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udm
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_odt
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_a
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_d
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d0_din_miso_miso1
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d1_miso2
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d2_miso3
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_we_b
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_oe_b
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_ce_b
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_scl_main
+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_sda_main
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_prsnt_m2c_l
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_pwr_good_flash_rst_b
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_awake
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cclk
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_clk
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_mosi
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_hswapen
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_init_b
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m0_cmp_miso
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m1
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_mosi_csi_b_miso0
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term1
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term2
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_vtemp
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_spi_cs_b
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_col
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_crs
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_int
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdc
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdio
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_reset
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxctl_rxdv
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxd
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxer
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txctl_txen
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txc_gtxclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txd
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txer
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1393701250 ps} 0} {{Cursor 2} {138750 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {327615 ps}
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh new file mode 100755 index 0000000..2f89415 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/xilinx-sp601-xc6slx16.ucf -p xc6slx16-csg324-2 top.ngc top.ngd +map -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf +par -ol high -mt off top_map.ncd -w top.ncd top.pcf +trce -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj new file mode 100644 index 0000000..965ae4c --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj @@ -0,0 +1,19 @@ +vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut new file mode 100644 index 0000000..be56902 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut @@ -0,0 +1,30 @@ +-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst new file mode 100644 index 0000000..ddddddd --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst @@ -0,0 +1,53 @@ +set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc6slx16-2-csg324
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf new file mode 100644 index 0000000..a0c60e7 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf @@ -0,0 +1,303 @@ +############################################################
+# SPARTAN-6 SP601 Board Constraints File
+#
+# Family: Spartan6
+# Device: XC6SLX16
+# Package: CSG324
+# Speed: -2
+#
+#
+# Bank Voltage
+# Bank 0: 2.5 V
+# Bank 1: 2.5 V
+# Bank 2: 2.5 V
+# Bank 3: 1.8 V
+# VCCAUX: 2.5 V
+
+# following pins are connected to VCC1V8/2:
+# N3, M5, C1
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 200 MHz HIGH 50 %;
+TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 50 MHz HIGH 50 %;
+NET "USER_CLOCK" PERIOD = 27 MHz HIGH 40%;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "CPU_RESET" LOC = "N4";
+
+## 128 MB DDR2 Component Memory
+NET "DDR2_A<12>" LOC ="G6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<11>" LOC ="D3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<10>" LOC ="F4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<9>" LOC ="D1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<8>" LOC ="D2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<7>" LOC ="H6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<6>" LOC ="H3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<5>" LOC ="H4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<4>" LOC ="F3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<3>" LOC ="L7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<2>" LOC ="H5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<1>" LOC ="J6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<0>" LOC ="J7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<15>" LOC ="U1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<14>" LOC ="U2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<13>" LOC ="T1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<12>" LOC ="T2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<11>" LOC ="N1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<10>" LOC ="N2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<9>" LOC ="M1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<8>" LOC ="M3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<7>" LOC ="J1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<6>" LOC ="J3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<5>" LOC ="H1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<4>" LOC ="H2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<3>" LOC ="K1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<2>" LOC ="K2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<1>" LOC ="L1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<0>" LOC ="L2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_WE_B" LOC ="E3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_UDQS_P" LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDQS_N" LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDM" LOC ="K4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_RAS_B" LOC ="L5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_ODT" LOC ="K6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_LDQS_P" LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDQS_N" LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDM" LOC ="K3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CLK_P" LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CLK_N" LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CKE" LOC ="H7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CAS_B" LOC ="K5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<2>" LOC ="E1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<1>" LOC ="F1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<0>" LOC ="F2"; # | IOSTANDARD = SSTL18_II ;
+
+## Flash Memory
+NET "FLASH_A<0>" LOC = "K18";
+NET "FLASH_A<1>" LOC = "K17";
+NET "FLASH_A<2>" LOC = "J18";
+NET "FLASH_A<3>" LOC = "J16";
+NET "FLASH_A<4>" LOC = "G18";
+NET "FLASH_A<5>" LOC = "G16";
+NET "FLASH_A<6>" LOC = "H16";
+NET "FLASH_A<7>" LOC = "H15";
+NET "FLASH_A<8>" LOC = "H14";
+NET "FLASH_A<9>" LOC = "H13";
+NET "FLASH_A<10>" LOC = "F18";
+NET "FLASH_A<11>" LOC = "F17";
+NET "FLASH_A<12>" LOC = "K13";
+NET "FLASH_A<13>" LOC = "K12";
+NET "FLASH_A<14>" LOC = "E18";
+NET "FLASH_A<15>" LOC = "E16";
+NET "FLASH_A<16>" LOC = "G13";
+NET "FLASH_A<17>" LOC = "H12";
+NET "FLASH_A<18>" LOC = "D18";
+NET "FLASH_A<19>" LOC = "D17";
+NET "FLASH_A<20>" LOC = "G14";
+NET "FLASH_A<21>" LOC = "F14";
+NET "FLASH_A<22>" LOC = "C18";
+NET "FLASH_A<23>" LOC = "C17";
+NET "FLASH_A<24>" LOC = "F16";
+#NET "FLASH_D<0>" LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<1>" LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<2>" LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<3>" LOC = "U5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<4>" LOC = "V5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<5>" LOC = "R3" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<6>" LOC = "T3" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<7>" LOC = "R5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_OE_B" LOC = "L18";
+NET "FLASH_WE_B" LOC = "M16";
+NET "FLASH_CE_B" LOC = "L17";
+
+# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)
+NET "FMC_CLK0_M2C_N" LOC = "A10";
+NET "FMC_CLK0_M2C_P" LOC = "C10";
+NET "FMC_CLK1_M2C_N" LOC = "V9" ;
+NET "FMC_CLK1_M2C_P" LOC = "T9" ;
+NET "FMC_LA00_CC_N" LOC = "C9" ;
+NET "FMC_LA00_CC_P" LOC = "D9" ;
+NET "FMC_LA01_CC_N" LOC = "C11";
+NET "FMC_LA01_CC_P" LOC = "D11";
+NET "FMC_LA02_N" LOC = "A15";
+NET "FMC_LA02_P" LOC = "C15";
+NET "FMC_LA03_N" LOC = "A13";
+NET "FMC_LA03_P" LOC = "C13";
+NET "FMC_LA04_N" LOC = "A16";
+NET "FMC_LA04_P" LOC = "B16";
+NET "FMC_LA05_N" LOC = "A14";
+NET "FMC_LA05_P" LOC = "B14";
+NET "FMC_LA06_N" LOC = "C12";
+NET "FMC_LA06_P" LOC = "D12";
+NET "FMC_LA07_N" LOC = "E8" ;
+NET "FMC_LA07_P" LOC = "E7" ;
+NET "FMC_LA08_N" LOC = "E11";
+NET "FMC_LA08_P" LOC = "F11";
+NET "FMC_LA09_N" LOC = "F10";
+NET "FMC_LA09_P" LOC = "G11";
+NET "FMC_LA10_N" LOC = "C8" ;
+NET "FMC_LA10_P" LOC = "D8" ;
+NET "FMC_LA11_N" LOC = "A12";
+NET "FMC_LA11_P" LOC = "B12";
+NET "FMC_LA12_N" LOC = "C6" ;
+NET "FMC_LA12_P" LOC = "D6" ;
+NET "FMC_LA13_N" LOC = "A11";
+NET "FMC_LA13_P" LOC = "B11";
+NET "FMC_LA14_N" LOC = "A2" ;
+NET "FMC_LA14_P" LOC = "B2" ;
+NET "FMC_LA15_N" LOC = "F9" ;
+NET "FMC_LA15_P" LOC = "G9" ;
+NET "FMC_LA16_N" LOC = "A7" ;
+NET "FMC_LA16_P" LOC = "C7" ;
+NET "FMC_LA17_CC_N" LOC = "T8" ;
+NET "FMC_LA17_CC_P" LOC = "R8" ;
+NET "FMC_LA18_CC_N" LOC = "T10";
+NET "FMC_LA18_CC_P" LOC = "R10";
+NET "FMC_LA19_N" LOC = "P7" ;
+NET "FMC_LA19_P" LOC = "N6" ;
+NET "FMC_LA20_N" LOC = "P8" ;
+NET "FMC_LA20_P" LOC = "N7" ;
+NET "FMC_LA21_N" LOC = "V4" ;
+NET "FMC_LA21_P" LOC = "T4" ;
+NET "FMC_LA22_N" LOC = "T7" ;
+NET "FMC_LA22_P" LOC = "R7" ;
+NET "FMC_LA23_N" LOC = "P6" ;
+NET "FMC_LA23_P" LOC = "N5" ;
+NET "FMC_LA24_N" LOC = "V8" ;
+NET "FMC_LA24_P" LOC = "U8" ;
+NET "FMC_LA25_N" LOC = "N11";
+NET "FMC_LA25_P" LOC = "M11";
+NET "FMC_LA26_N" LOC = "V7" ;
+NET "FMC_LA26_P" LOC = "U7" ;
+NET "FMC_LA27_N" LOC = "T11";
+NET "FMC_LA27_P" LOC = "R11";
+NET "FMC_LA28_N" LOC = "V11";
+NET "FMC_LA28_P" LOC = "U11";
+NET "FMC_LA29_N" LOC = "N8" ;
+NET "FMC_LA29_P" LOC = "M8" ;
+NET "FMC_LA30_N" LOC = "V12";
+NET "FMC_LA30_P" LOC = "T12";
+NET "FMC_LA31_N" LOC = "V6" ;
+NET "FMC_LA31_P" LOC = "T6" ;
+NET "FMC_LA32_N" LOC = "V15";
+NET "FMC_LA32_P" LOC = "U15";
+NET "FMC_LA33_N" LOC = "N9" ;
+NET "FMC_LA33_P" LOC = "M10";
+NET "FMC_PRSNT_M2C_L" LOC = "U13";
+NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
+
+# special FPGA pins
+NET "FPGA_AWAKE" LOC = "P15"| SLEW = SLOW | DRIVE = 2;
+NET "FPGA_CCLK" LOC = "R15";
+NET "FPGA_CMP_CLK" LOC = "U16";
+NET "FPGA_CMP_MOSI" LOC = "V16";
+NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
+NET "FPGA_D1_MISO2" LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
+NET "FPGA_D2_MISO3" LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12
+NET "FPGA_HSWAPEN" LOC = "D4";
+NET "FPGA_INIT_B" LOC = "U3" | SLEW = SLOW | DRIVE = 4;
+NET "FPGA_M0_CMP_MISO" LOC = "T15";
+NET "FPGA_M1" LOC = "N12";
+NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13" | DRIVE = 4;
+NET "FPGA_ONCHIP_TERM1" LOC = "L6";
+NET "FPGA_ONCHIP_TERM2" LOC = "C2";
+NET "FPGA_VTEMP" LOC = "P3";
+
+## Pushbuttons, Bank 3, external Pulldown
+NET "GPIO_BUTTON<0>" LOC = "P4" ;
+NET "GPIO_BUTTON<1>" LOC = "F6" ;
+NET "GPIO_BUTTON<2>" LOC = "E4" ;
+NET "GPIO_BUTTON<3>" LOC = "F5" ;
+NET "GPIO_BUTTON*" TIG;
+
+## 8 Pin GPIO Header J13, Bank 0,1,2
+NET "GPIO_HEADER_LS<0>" LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<1>" LOC = "M18"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<2>" LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<3>" LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<4>" LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<5>" LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<6>" LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<7>" LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;
+
+## 4 GPIO LEDs, Bank 0
+NET "GPIO_LED<0>" LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<1>" LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<2>" LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<3>" LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED*" TIG;
+
+## GPIO Dip Switches, Bank 0,2, external Pulldown
+NET "GPIO_SWITCH<0>" LOC = "D14";
+NET "GPIO_SWITCH<1>" LOC = "E12";
+NET "GPIO_SWITCH<2>" LOC = "F12";
+NET "GPIO_SWITCH<3>" LOC = "V13";
+NET "GPIO_SWITCH*" TIG;
+
+## IIC Bus
+NET "IIC_SCL_MAIN" LOC = "P11";
+NET "IIC_SDA_MAIN" LOC = "N10";
+
+## 10/100/1000 Tri-Speed Ethernet PHY
+NET "PHY_COL" LOC = "L14";
+NET "PHY_CRS" LOC = "M13";
+NET "PHY_INT" LOC = "J13";
+NET "PHY_MDC" LOC = "N14" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_MDIO" LOC = "P16" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_RESET" LOC = "L13";
+NET "PHY_RXCLK" LOC = "L16";
+NET "PHY_RXCTL_RXDV" LOC = "N18";
+NET "PHY_RXD<0>" LOC = "M14";
+NET "PHY_RXD<1>" LOC = "U18";
+NET "PHY_RXD<2>" LOC = "U17";
+NET "PHY_RXD<3>" LOC = "T18";
+NET "PHY_RXD<4>" LOC = "T17";
+NET "PHY_RXD<5>" LOC = "N16";
+NET "PHY_RXD<6>" LOC = "N15";
+NET "PHY_RXD<7>" LOC = "P18";
+NET "PHY_RXER" LOC = "P17";
+NET "PHY_TXCLK" LOC = "B9" ;
+NET "PHY_TXCTL_TXEN" LOC = "B8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXC_GTXCLK" LOC = "A9" ;
+NET "PHY_TXD<0>" LOC = "F8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<1>" LOC = "G8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<2>" LOC = "A6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<3>" LOC = "B6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<4>" LOC = "E6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<5>" LOC = "F7" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<6>" LOC = "A5" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<7>" LOC = "C5" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXER" LOC = "A8" | SLEW = SLOW | DRIVE = 4;
+
+## SPI x4 Flash
+NET "SPI_CS_B" LOC = "V3";
+
+## 200 MHz oscillator (differential)
+NET "SYSCLK_N" LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+NET "SYSCLK_P" LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+
+## USB-UART
+## this names are real net names
+NET "USB_1_CTS" LOC = "U10"| DRIVE = 4 | SLEW = SLOW; # RTS output
+NET "USB_1_RTS" LOC = "T5" ; # CTS input
+NET "USB_1_RX" LOC = "L12"| DRIVE = 4 | SLEW = SLOW; # TX data out
+NET "USB_1_TX" LOC = "K14"; # RX data in
+
+## 27 MHz
+NET "USER_CLOCK" LOC = "V10"| IOSTANDARD = LVCMOS33 ;
+##
+NET "USER_SMA_CLOCK_N" LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";
+NET "USER_SMA_CLOCK_P" LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";
+
+# pins used for voltage termination
+CONFIG PROHIBIT = C1;
+CONFIG PROHIBIT = M5;
+CONFIG PROHIBIT = N3;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd new file mode 100644 index 0000000..27d158f --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd @@ -0,0 +1,574 @@ +-- top module of
+-- SP601 evaluation board
+--
+-- using following external connections:
+--
+-- cpu_reset (SW9) reset
+-- LEDs output
+-- USB_UART communication
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.ibufgds;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ --
+ cpu_reset : in std_logic; -- SW9 pushbutton (active-high)
+ --
+ -- DDR2 memory 128 MB
+ ddr2_a : out std_logic_vector(12 downto 0);
+ ddr2_ba : out std_logic_vector(2 downto 0);
+ ddr2_cas_b : out std_logic;
+ ddr2_ras_b : out std_logic;
+ ddr2_we_b : out std_logic;
+ ddr2_cke : out std_logic;
+ ddr2_clk_n : out std_logic;
+ ddr2_clk_p : out std_logic;
+ ddr2_dq : inout std_logic_vector(15 downto 0);
+ ddr2_ldm : out std_logic;
+ ddr2_udm : out std_logic;
+ ddr2_ldqs_n : inout std_logic;
+ ddr2_ldqs_p : inout std_logic;
+ ddr2_udqs_n : inout std_logic;
+ ddr2_udqs_p : inout std_logic;
+ ddr2_odt : out std_logic;
+ --
+ -- flash memory
+ flash_a : out std_logic_vector(24 downto 0);
+ flash_d : inout std_logic_vector(7 downto 3);
+ --
+ fpga_d0_din_miso_miso1 : inout std_logic; -- dual use
+ fpga_d1_miso2 : inout std_logic; -- dual use
+ fpga_d2_miso3 : inout std_logic; -- dual use
+ flash_we_b : out std_logic;
+ flash_oe_b : out std_logic;
+ flash_ce_b : out std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ fmc_clk0_m2c_n : in std_logic;
+ fmc_clk0_m2c_p : in std_logic;
+ fmc_clk1_m2c_n : in std_logic;
+ fmc_clk1_m2c_p : in std_logic;
+ -- IIC addresses:
+ -- M24C08: 1010100..1010111
+ -- 2kb EEPROM on FMC card: 1010010
+ iic_scl_main : inout std_logic;
+ iic_sda_main : inout std_logic;
+ fmc_la00_cc_n : inout std_logic;
+ fmc_la00_cc_p : inout std_logic;
+ fmc_la01_cc_n : inout std_logic;
+ fmc_la01_cc_p : inout std_logic;
+ fmc_la02_n : inout std_logic;
+ fmc_la02_p : inout std_logic;
+ fmc_la03_n : inout std_logic;
+ fmc_la03_p : inout std_logic;
+ fmc_la04_n : inout std_logic;
+ fmc_la04_p : inout std_logic;
+ fmc_la05_n : inout std_logic;
+ fmc_la05_p : inout std_logic;
+ fmc_la06_n : inout std_logic;
+ fmc_la06_p : inout std_logic;
+ fmc_la07_n : inout std_logic;
+ fmc_la07_p : inout std_logic;
+ fmc_la08_n : inout std_logic;
+ fmc_la08_p : inout std_logic;
+ fmc_la09_n : inout std_logic;
+ fmc_la09_p : inout std_logic;
+ fmc_la10_n : inout std_logic;
+ fmc_la10_p : inout std_logic;
+ fmc_la11_n : inout std_logic;
+ fmc_la11_p : inout std_logic;
+ fmc_la12_n : inout std_logic;
+ fmc_la12_p : inout std_logic;
+ fmc_la13_n : inout std_logic;
+ fmc_la13_p : inout std_logic;
+ fmc_la14_n : inout std_logic;
+ fmc_la14_p : inout std_logic;
+ fmc_la15_n : inout std_logic;
+ fmc_la15_p : inout std_logic;
+ fmc_la16_n : inout std_logic;
+ fmc_la16_p : inout std_logic;
+ fmc_la17_cc_n : inout std_logic;
+ fmc_la17_cc_p : inout std_logic;
+ fmc_la18_cc_n : inout std_logic;
+ fmc_la18_cc_p : inout std_logic;
+ fmc_la19_n : inout std_logic;
+ fmc_la19_p : inout std_logic;
+ fmc_la20_n : inout std_logic;
+ fmc_la20_p : inout std_logic;
+ fmc_la21_n : inout std_logic;
+ fmc_la21_p : inout std_logic;
+ fmc_la22_n : inout std_logic;
+ fmc_la22_p : inout std_logic;
+ fmc_la23_n : inout std_logic;
+ fmc_la23_p : inout std_logic;
+ fmc_la24_n : inout std_logic;
+ fmc_la24_p : inout std_logic;
+ fmc_la25_n : inout std_logic;
+ fmc_la25_p : inout std_logic;
+ fmc_la26_n : inout std_logic;
+ fmc_la26_p : inout std_logic;
+ fmc_la27_n : inout std_logic;
+ fmc_la27_p : inout std_logic;
+ fmc_la28_n : inout std_logic;
+ fmc_la28_p : inout std_logic;
+ fmc_la29_n : inout std_logic;
+ fmc_la29_p : inout std_logic;
+ fmc_la30_n : inout std_logic;
+ fmc_la30_p : inout std_logic;
+ fmc_la31_n : inout std_logic;
+ fmc_la31_p : inout std_logic;
+ fmc_la32_n : inout std_logic;
+ fmc_la32_p : inout std_logic;
+ fmc_la33_n : inout std_logic;
+ fmc_la33_p : inout std_logic;
+ fmc_prsnt_m2c_l : in std_logic;
+ fmc_pwr_good_flash_rst_b : out std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+ --
+ fpga_awake : out std_logic;
+ fpga_cclk : out std_logic;
+ fpga_cmp_clk : in std_logic;
+ fpga_cmp_mosi : in std_logic;
+ --
+ fpga_hswapen : in std_logic;
+ fpga_init_b : out std_logic; -- low active
+ fpga_m0_cmp_miso : in std_logic; -- mode DIP switch SW1 active high
+ fpga_m1 : in std_logic; -- mode DIP switch SW1 active high
+ fpga_mosi_csi_b_miso0 : inout std_logic;
+ fpga_onchip_term1 : inout std_logic;
+ fpga_onchip_term2 : inout std_logic;
+ fpga_vtemp : in std_logic;
+ --
+ -- GPIOs
+ gpio_button : in std_logic_vector(3 downto 0); -- active high
+ gpio_header_ls : inout std_logic_vector(7 downto 0);
+ gpio_led : out std_logic_vector(3 downto 0);
+ gpio_switch : in std_logic_vector(3 downto 0); -- active high
+ --
+ -- Ethernet Gigabit PHY,
+ -- default settings:
+ -- phy address = 0b00111
+ -- ANEG[3..0] = "1111"
+ -- ENA_XC = 1
+ -- DIS_125 = 1
+ -- HWCFG_MD[3..0] = "1111"
+ -- DIS_FC = 1
+ -- DIS_SLEEP = 1
+ -- SEL_BDT = 0
+ -- INT_POL = 1
+ -- 75/50Ohm = 0
+ phy_col : in std_logic;
+ phy_crs : in std_logic;
+ phy_int : in std_logic;
+ phy_mdc : out std_logic;
+ phy_mdio : inout std_logic;
+ phy_reset : out std_logic;
+ phy_rxclk : in std_logic;
+ phy_rxctl_rxdv : in std_logic;
+ phy_rxd : in std_logic_vector(7 downto 0);
+ phy_rxer : in std_logic;
+ phy_txclk : in std_logic;
+ phy_txctl_txen : out std_logic;
+ phy_txc_gtxclk : out std_logic;
+ phy_txd : out std_logic_vector(7 downto 0);
+ phy_txer : out std_logic;
+ --
+ --
+ spi_cs_b : out std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ sysclk_n : in std_logic;
+ sysclk_p : in std_logic;
+ --
+ -- RS232 via USB
+ usb_1_cts : out std_logic; -- function: RTS output
+ usb_1_rts : in std_logic; -- function: CTS input
+ usb_1_rx : out std_logic; -- function: TX data out
+ usb_1_tx : in std_logic; -- function: RX data in
+ --
+ -- 27 MHz, oscillator socket
+ user_clock : in std_logic;
+ --
+ -- user clock provided per SMA
+ user_sma_clock_p : in std_logic;
+ user_sma_clock_n : in std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 2; -- 2 for small, 2 for medium
+ constant clk_divide : positive := 5; -- 4 for small, 5 for medium
+ --
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ --
+ constant clk_frequency : positive := 200; -- input frequency for correct calculation
+
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+
+ ---------------------------
+ -- signal declarations
+ signal sys_clk : std_ulogic;
+ signal dcm_sp_i0_clk0 : std_ulogic;
+ signal dcm_sp_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0) := (others => '0');
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- outputs used by design are commented
+ --
+ ddr2_a <= (others => '1');
+ ddr2_ba <= (others => '1');
+ ddr2_cas_b <= '1';
+ ddr2_ras_b <= '1';
+ ddr2_we_b <= '1';
+ ddr2_cke <= '0';
+ ddr2_clk_n <= '0';
+ ddr2_clk_p <= '1';
+ ddr2_dq <= (others => 'Z');
+ ddr2_ldm <= '0';
+ ddr2_udm <= '0';
+ ddr2_ldqs_n <= 'Z';
+ ddr2_ldqs_p <= 'Z';
+ ddr2_udqs_n <= 'Z';
+ ddr2_udqs_p <= 'Z';
+ ddr2_odt <= '1';
+ --
+ flash_a <= (others => '1');
+ flash_d <= (others => 'Z');
+ flash_we_b <= '1';
+ flash_oe_b <= '1';
+ flash_ce_b <= '1';
+ --
+ fpga_d0_din_miso_miso1 <= 'Z';
+ fpga_d1_miso2 <= 'Z';
+ fpga_d2_miso3 <= 'Z';
+ --
+ iic_scl_main <= 'Z';
+ iic_sda_main <= 'Z';
+ fmc_la00_cc_n <= 'Z';
+ fmc_la00_cc_p <= 'Z';
+ fmc_la01_cc_n <= 'Z';
+ fmc_la01_cc_p <= 'Z';
+ fmc_la02_n <= 'Z';
+ fmc_la02_p <= 'Z';
+ fmc_la03_n <= 'Z';
+ fmc_la03_p <= 'Z';
+ fmc_la04_n <= 'Z';
+ fmc_la04_p <= 'Z';
+ fmc_la05_n <= 'Z';
+ fmc_la05_p <= 'Z';
+ fmc_la06_n <= 'Z';
+ fmc_la06_p <= 'Z';
+ fmc_la07_n <= 'Z';
+ fmc_la07_p <= 'Z';
+ fmc_la08_n <= 'Z';
+ fmc_la08_p <= 'Z';
+ fmc_la09_n <= 'Z';
+ fmc_la09_p <= 'Z';
+ fmc_la10_n <= 'Z';
+ fmc_la10_p <= 'Z';
+ fmc_la11_n <= 'Z';
+ fmc_la11_p <= 'Z';
+ fmc_la12_n <= 'Z';
+ fmc_la12_p <= 'Z';
+ fmc_la13_n <= 'Z';
+ fmc_la13_p <= 'Z';
+ fmc_la14_n <= 'Z';
+ fmc_la14_p <= 'Z';
+ fmc_la15_n <= 'Z';
+ fmc_la15_p <= 'Z';
+ fmc_la16_n <= 'Z';
+ fmc_la16_p <= 'Z';
+ fmc_la17_cc_n <= 'Z';
+ fmc_la17_cc_p <= 'Z';
+ fmc_la18_cc_n <= 'Z';
+ fmc_la18_cc_p <= 'Z';
+ fmc_la19_n <= 'Z';
+ fmc_la19_p <= 'Z';
+ fmc_la20_n <= 'Z';
+ fmc_la20_p <= 'Z';
+ fmc_la21_n <= 'Z';
+ fmc_la21_p <= 'Z';
+ fmc_la22_n <= 'Z';
+ fmc_la22_p <= 'Z';
+ fmc_la23_n <= 'Z';
+ fmc_la23_p <= 'Z';
+ fmc_la24_n <= 'Z';
+ fmc_la24_p <= 'Z';
+ fmc_la25_n <= 'Z';
+ fmc_la25_p <= 'Z';
+ fmc_la26_n <= 'Z';
+ fmc_la26_p <= 'Z';
+ fmc_la27_n <= 'Z';
+ fmc_la27_p <= 'Z';
+ fmc_la28_n <= 'Z';
+ fmc_la28_p <= 'Z';
+ fmc_la29_n <= 'Z';
+ fmc_la29_p <= 'Z';
+ fmc_la30_n <= 'Z';
+ fmc_la30_p <= 'Z';
+ fmc_la31_n <= 'Z';
+ fmc_la31_p <= 'Z';
+ fmc_la32_n <= 'Z';
+ fmc_la32_p <= 'Z';
+ fmc_la33_n <= 'Z';
+ fmc_la33_p <= 'Z';
+ fmc_pwr_good_flash_rst_b <= '1';
+ --
+ fpga_awake <= '1';
+ fpga_cclk <= '1'; -- SPI clk
+ fpga_init_b <= '1';
+ fpga_mosi_csi_b_miso0 <= 'Z';
+ fpga_onchip_term1 <= 'Z';
+ fpga_onchip_term2 <= 'Z';
+ --
+ --gpio_led <= (others => '0');
+ --gpio_header_ls <= (others => 'Z');
+ --
+ phy_mdc <= '0';
+ phy_mdio <= 'Z';
+ phy_reset <= '0';
+ phy_txc_gtxclk <= '0';
+ phy_txctl_txen <= '0';
+ phy_txd <= (others => '1');
+ phy_txer <= '0';
+ --
+ spi_cs_b <= '1';
+ --
+ --usb_1_rx <= '1'; -- function: TX data out
+ usb_1_cts <= '1'; -- function: RTS
+
+
+ -- global differential input buffer
+ ibufgds_i0 : ibufgds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ i => sysclk_p,
+ ib => sysclk_n,
+ o => sys_clk
+ );
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_sp_i0 : dcm_sp
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ clkin => sys_clk,
+ clk0 => dcm_sp_i0_clk0,
+ clkfx => dcm_sp_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ clk_fb <= dcm_sp_i0_clk0;
+ clk <= dcm_sp_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, cpu_reset)
+ begin
+ if cpu_reset = '1' then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+
+ -- select instance of zpu
+ zpu_i0_small: if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => usb_1_tx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium: if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => usb_1_tx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation
+
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+ -- assign GPIOs
+ --
+ -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+ --
+ -- in -- -- -- -- -- -- -- -- gpio_header_ls(7.....0)
+ -- out -- -- -- -- -- -- -- -- gpio_header_ls(7.....0)
+ --
+ -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ --
+ -- in -- -- -- -- switch(3.0) -- -- -- -- button(3.0)
+ -- out -- -- -- -- -- -- -- -- gpio_led(7...........0)
+ --
+ gpio_in(23 downto 16) <= gpio_header_ls;
+ gpio_in(11 downto 8) <= gpio_switch;
+ gpio_in( 3 downto 0) <= gpio_button;
+
+ -- 3-state buffers for header_ls
+ gpio_header_ls(7) <= zpu_i0_gpio_out(23) when zpu_i0_gpio_dir(23) = '0' else 'Z';
+ gpio_header_ls(6) <= zpu_i0_gpio_out(22) when zpu_i0_gpio_dir(22) = '0' else 'Z';
+ gpio_header_ls(5) <= zpu_i0_gpio_out(21) when zpu_i0_gpio_dir(21) = '0' else 'Z';
+ gpio_header_ls(4) <= zpu_i0_gpio_out(20) when zpu_i0_gpio_dir(20) = '0' else 'Z';
+ gpio_header_ls(3) <= zpu_i0_gpio_out(19) when zpu_i0_gpio_dir(19) = '0' else 'Z';
+ gpio_header_ls(2) <= zpu_i0_gpio_out(18) when zpu_i0_gpio_dir(18) = '0' else 'Z';
+ gpio_header_ls(1) <= zpu_i0_gpio_out(17) when zpu_i0_gpio_dir(17) = '0' else 'Z';
+ gpio_header_ls(0) <= zpu_i0_gpio_out(16) when zpu_i0_gpio_dir(16) = '0' else 'Z';
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ gpio_led <= zpu_i0_gpio_out(3 downto 0);
+ if zpu_i0_break = '1' then
+ gpio_led <= (others => '1');
+ end if;
+ end process;
+
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd new file mode 100644 index 0000000..f089f29 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd @@ -0,0 +1,402 @@ +-- testbench for
+-- SP601 evaluation board
+--
+-- includes "model" for clock generation
+-- simulate press on cpu_reset as reset
+--
+-- place models for external components (PHY, DDR2) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant sys_clk_period : time := 1 sec / 200_000_000; -- 200 MHz
+ constant user_clk_period : time := 1 sec / 27_000_000; -- 27 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ signal tb_cpu_reset : std_logic; -- SW9 pushbutton (active-high)
+ --
+ -- DDR2 memory 128 MB
+ signal tb_ddr2_a : std_logic_vector(12 downto 0);
+ signal tb_ddr2_ba : std_logic_vector(2 downto 0);
+ signal tb_ddr2_cas_b : std_logic;
+ signal tb_ddr2_ras_b : std_logic;
+ signal tb_ddr2_we_b : std_logic;
+ signal tb_ddr2_cke : std_logic;
+ signal tb_ddr2_clk_n : std_logic;
+ signal tb_ddr2_clk_p : std_logic;
+ signal tb_ddr2_dq : std_logic_vector(15 downto 0);
+ signal tb_ddr2_ldm : std_logic;
+ signal tb_ddr2_udm : std_logic;
+ signal tb_ddr2_ldqs_n : std_logic;
+ signal tb_ddr2_ldqs_p : std_logic;
+ signal tb_ddr2_udqs_n : std_logic;
+ signal tb_ddr2_udqs_p : std_logic;
+ signal tb_ddr2_odt : std_logic;
+ --
+ -- flash memory
+ signal tb_flash_a : std_logic_vector(24 downto 0);
+ signal tb_flash_d : std_logic_vector(7 downto 3);
+ signal tb_fpga_d0_din_miso_miso1 : std_logic; -- dual use
+ signal tb_fpga_d1_miso2 : std_logic; -- dual use
+ signal tb_fpga_d2_miso3 : std_logic; -- dual use
+ signal tb_flash_we_b : std_logic;
+ signal tb_flash_oe_b : std_logic;
+ signal tb_flash_ce_b : std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ signal tb_fmc_clk0_m2c_n : std_logic := '1';
+ signal tb_fmc_clk0_m2c_p : std_logic := '0';
+ signal tb_fmc_clk1_m2c_n : std_logic := '1';
+ signal tb_fmc_clk1_m2c_p : std_logic := '0';
+ -- IIC addresses:
+ -- M24C08: 1010100..1010111
+ -- 2kb EEPROM on FMC card: 1010010
+ signal tb_iic_scl_main : std_logic;
+ signal tb_iic_sda_main : std_logic;
+ signal tb_fmc_la00_cc_n : std_logic;
+ signal tb_fmc_la00_cc_p : std_logic;
+ signal tb_fmc_la01_cc_n : std_logic;
+ signal tb_fmc_la01_cc_p : std_logic;
+ signal tb_fmc_la02_n : std_logic;
+ signal tb_fmc_la02_p : std_logic;
+ signal tb_fmc_la03_n : std_logic;
+ signal tb_fmc_la03_p : std_logic;
+ signal tb_fmc_la04_n : std_logic;
+ signal tb_fmc_la04_p : std_logic;
+ signal tb_fmc_la05_n : std_logic;
+ signal tb_fmc_la05_p : std_logic;
+ signal tb_fmc_la06_n : std_logic;
+ signal tb_fmc_la06_p : std_logic;
+ signal tb_fmc_la07_n : std_logic;
+ signal tb_fmc_la07_p : std_logic;
+ signal tb_fmc_la08_n : std_logic;
+ signal tb_fmc_la08_p : std_logic;
+ signal tb_fmc_la09_n : std_logic;
+ signal tb_fmc_la09_p : std_logic;
+ signal tb_fmc_la10_n : std_logic;
+ signal tb_fmc_la10_p : std_logic;
+ signal tb_fmc_la11_n : std_logic;
+ signal tb_fmc_la11_p : std_logic;
+ signal tb_fmc_la12_n : std_logic;
+ signal tb_fmc_la12_p : std_logic;
+ signal tb_fmc_la13_n : std_logic;
+ signal tb_fmc_la13_p : std_logic;
+ signal tb_fmc_la14_n : std_logic;
+ signal tb_fmc_la14_p : std_logic;
+ signal tb_fmc_la15_n : std_logic;
+ signal tb_fmc_la15_p : std_logic;
+ signal tb_fmc_la16_n : std_logic;
+ signal tb_fmc_la16_p : std_logic;
+ signal tb_fmc_la17_cc_n : std_logic;
+ signal tb_fmc_la17_cc_p : std_logic;
+ signal tb_fmc_la18_cc_n : std_logic;
+ signal tb_fmc_la18_cc_p : std_logic;
+ signal tb_fmc_la19_n : std_logic;
+ signal tb_fmc_la19_p : std_logic;
+ signal tb_fmc_la20_n : std_logic;
+ signal tb_fmc_la20_p : std_logic;
+ signal tb_fmc_la21_n : std_logic;
+ signal tb_fmc_la21_p : std_logic;
+ signal tb_fmc_la22_n : std_logic;
+ signal tb_fmc_la22_p : std_logic;
+ signal tb_fmc_la23_n : std_logic;
+ signal tb_fmc_la23_p : std_logic;
+ signal tb_fmc_la24_n : std_logic;
+ signal tb_fmc_la24_p : std_logic;
+ signal tb_fmc_la25_n : std_logic;
+ signal tb_fmc_la25_p : std_logic;
+ signal tb_fmc_la26_n : std_logic;
+ signal tb_fmc_la26_p : std_logic;
+ signal tb_fmc_la27_n : std_logic;
+ signal tb_fmc_la27_p : std_logic;
+ signal tb_fmc_la28_n : std_logic;
+ signal tb_fmc_la28_p : std_logic;
+ signal tb_fmc_la29_n : std_logic;
+ signal tb_fmc_la29_p : std_logic;
+ signal tb_fmc_la30_n : std_logic;
+ signal tb_fmc_la30_p : std_logic;
+ signal tb_fmc_la31_n : std_logic;
+ signal tb_fmc_la31_p : std_logic;
+ signal tb_fmc_la32_n : std_logic;
+ signal tb_fmc_la32_p : std_logic;
+ signal tb_fmc_la33_n : std_logic;
+ signal tb_fmc_la33_p : std_logic;
+ signal tb_fmc_prsnt_m2c_l : std_logic := '0';
+ signal tb_fmc_pwr_good_flash_rst_b : std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+ --
+ signal tb_fpga_awake : std_logic;
+ signal tb_fpga_cclk : std_logic;
+ signal tb_fpga_cmp_clk : std_logic := '0';
+ signal tb_fpga_cmp_mosi : std_logic := '0';
+ signal tb_fpga_hswapen : std_logic := '0';
+ signal tb_fpga_init_b : std_logic; -- low active
+ signal tb_fpga_m0_cmp_miso : std_logic := '0'; -- mode DIP switch SW1 active high
+ signal tb_fpga_m1 : std_logic := '0'; -- mode DIP switch SW1 active high
+ signal tb_fpga_mosi_csi_b_miso0 : std_logic;
+ signal tb_fpga_onchip_term1 : std_logic;
+ signal tb_fpga_onchip_term2 : std_logic;
+ signal tb_fpga_vtemp : std_logic := '0';
+ --
+ -- GPIOs
+ signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0'); -- active high
+ signal tb_gpio_header_ls : std_logic_vector(7 downto 0); --
+ signal tb_gpio_led : std_logic_vector(3 downto 0);
+ signal tb_gpio_switch : std_logic_vector(3 downto 0) := (others => '0'); -- active high
+ --
+ -- Ethernet Gigabit PHY
+ signal tb_phy_col : std_logic := '0';
+ signal tb_phy_crs : std_logic := '0';
+ signal tb_phy_int : std_logic := '0';
+ signal tb_phy_mdc : std_logic;
+ signal tb_phy_mdio : std_logic;
+ signal tb_phy_reset : std_logic;
+ signal tb_phy_rxclk : std_logic := '0';
+ signal tb_phy_rxctl_rxdv : std_logic := '0';
+ signal tb_phy_rxd : std_logic_vector(7 downto 0);
+ signal tb_phy_rxer : std_logic := '0';
+ signal tb_phy_txclk : std_logic := '0';
+ signal tb_phy_txctl_txen : std_logic;
+ signal tb_phy_txc_gtxclk : std_logic;
+ signal tb_phy_txd : std_logic_vector(7 downto 0);
+ signal tb_phy_txer : std_logic;
+ --
+ --
+ signal tb_spi_cs_b : std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ signal tb_sysclk_n : std_logic := '1';
+ signal tb_sysclk_p : std_logic := '0';
+ --
+ -- RS232 via USB
+ signal tb_usb_1_cts : std_logic; -- function: RTS output
+ signal tb_usb_1_rts : std_logic := '0'; -- function: CTS input
+ signal tb_usb_1_rx : std_logic; -- function: TX data out
+ signal tb_usb_1_tx : std_logic := '0'; -- function: RX data in
+ --
+ -- 27 MHz, oscillator socket
+ signal tb_user_clock : std_logic := '0';
+ --
+ -- user clock provided per SMA
+ signal tb_user_sma_clock_p : std_logic := '0';
+ signal tb_user_sma_clock_n : std_logic := '0';
+
+
+
+begin
+
+ -- generate clocks
+ tb_sysclk_p <= not tb_sysclk_p after sys_clk_period / 2 when simulation_run;
+ tb_sysclk_n <= not tb_sysclk_n after sys_clk_period / 2 when simulation_run;
+ tb_user_clock <= not tb_user_clock after user_clk_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_cpu_reset <= '1', '0' after 6.66 * sys_clk_period;
+
+
+ -- simulate keypress
+ tb_gpio_button(2) <= '0', '1' after 50 us, '0' after 52 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ --
+ cpu_reset => tb_cpu_reset, -- : in std_logic;
+ --
+ -- DDR2 memory 128 MB
+ ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0);
+ ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(2 downto 0);
+ ddr2_cas_b => tb_ddr2_cas_b, -- : out std_logic;
+ ddr2_ras_b => tb_ddr2_ras_b, -- : out std_logic;
+ ddr2_we_b => tb_ddr2_we_b, -- : out std_logic;
+ ddr2_cke => tb_ddr2_cke, -- : out std_logic;
+ ddr2_clk_n => tb_ddr2_clk_n, -- : out std_logic;
+ ddr2_clk_p => tb_ddr2_clk_p, -- : out std_logic;
+ ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(15 downto 0);
+ ddr2_ldm => tb_ddr2_ldm, -- : out std_logic;
+ ddr2_udm => tb_ddr2_udm, -- : out std_logic;
+ ddr2_ldqs_n => tb_ddr2_ldqs_n, -- : inout std_logic;
+ ddr2_ldqs_p => tb_ddr2_ldqs_p, -- : inout std_logic;
+ ddr2_udqs_n => tb_ddr2_udqs_n, -- : inout std_logic;
+ ddr2_udqs_p => tb_ddr2_udqs_p, -- : inout std_logic;
+ ddr2_odt => tb_ddr2_odt, -- : out std_logic;
+ --
+ -- flash memory
+ flash_a => tb_flash_a, -- : out std_logic_vector(24 downto 0);
+ flash_d => tb_flash_d, -- : inout std_logic_vector(7 downto 3);
+ -- --
+ fpga_d0_din_miso_miso1 => tb_fpga_d0_din_miso_miso1, -- : inout std_logic;
+ fpga_d1_miso2 => tb_fpga_d1_miso2, -- : inout std_logic;
+ fpga_d2_miso3 => tb_fpga_d2_miso3, -- : inout std_logic;
+ flash_we_b => tb_flash_we_b, -- : out std_logic;
+ flash_oe_b => tb_flash_oe_b, -- : out std_logic;
+ flash_ce_b => tb_flash_ce_b, -- : out std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ fmc_clk0_m2c_n => tb_fmc_clk0_m2c_n, -- : in std_logic;
+ fmc_clk0_m2c_p => tb_fmc_clk0_m2c_p, -- : in std_logic;
+ fmc_clk1_m2c_n => tb_fmc_clk1_m2c_n, -- : in std_logic;
+ fmc_clk1_m2c_p => tb_fmc_clk1_m2c_p, -- : in std_logic;
+ iic_scl_main => tb_iic_scl_main, -- : inout std_logic;
+ iic_sda_main => tb_iic_sda_main, -- : inout std_logic;
+ fmc_la00_cc_n => tb_fmc_la00_cc_n, -- : inout std_logic;
+ fmc_la00_cc_p => tb_fmc_la00_cc_p, -- : inout std_logic;
+ fmc_la01_cc_n => tb_fmc_la01_cc_n, -- : inout std_logic;
+ fmc_la01_cc_p => tb_fmc_la01_cc_p, -- : inout std_logic;
+ fmc_la02_n => tb_fmc_la02_n, -- : inout std_logic;
+ fmc_la02_p => tb_fmc_la02_p, -- : inout std_logic;
+ fmc_la03_n => tb_fmc_la03_n, -- : inout std_logic;
+ fmc_la03_p => tb_fmc_la03_p, -- : inout std_logic;
+ fmc_la04_n => tb_fmc_la04_n, -- : inout std_logic;
+ fmc_la04_p => tb_fmc_la04_p, -- : inout std_logic;
+ fmc_la05_n => tb_fmc_la05_n, -- : inout std_logic;
+ fmc_la05_p => tb_fmc_la05_p, -- : inout std_logic;
+ fmc_la06_n => tb_fmc_la06_n, -- : inout std_logic;
+ fmc_la06_p => tb_fmc_la06_p, -- : inout std_logic;
+ fmc_la07_n => tb_fmc_la07_n, -- : inout std_logic;
+ fmc_la07_p => tb_fmc_la07_p, -- : inout std_logic;
+ fmc_la08_n => tb_fmc_la08_n, -- : inout std_logic;
+ fmc_la08_p => tb_fmc_la08_p, -- : inout std_logic;
+ fmc_la09_n => tb_fmc_la09_n, -- : inout std_logic;
+ fmc_la09_p => tb_fmc_la09_p, -- : inout std_logic;
+ fmc_la10_n => tb_fmc_la10_n, -- : inout std_logic;
+ fmc_la10_p => tb_fmc_la10_p, -- : inout std_logic;
+ fmc_la11_n => tb_fmc_la11_n, -- : inout std_logic;
+ fmc_la11_p => tb_fmc_la11_p, -- : inout std_logic;
+ fmc_la12_n => tb_fmc_la12_n, -- : inout std_logic;
+ fmc_la12_p => tb_fmc_la12_p, -- : inout std_logic;
+ fmc_la13_n => tb_fmc_la13_n, -- : inout std_logic;
+ fmc_la13_p => tb_fmc_la13_p, -- : inout std_logic;
+ fmc_la14_n => tb_fmc_la14_n, -- : inout std_logic;
+ fmc_la14_p => tb_fmc_la14_p, -- : inout std_logic;
+ fmc_la15_n => tb_fmc_la15_n, -- : inout std_logic;
+ fmc_la15_p => tb_fmc_la15_p, -- : inout std_logic;
+ fmc_la16_n => tb_fmc_la16_n, -- : inout std_logic;
+ fmc_la16_p => tb_fmc_la16_p, -- : inout std_logic;
+ fmc_la17_cc_n => tb_fmc_la17_cc_n, -- : inout std_logic;
+ fmc_la17_cc_p => tb_fmc_la17_cc_p, -- : inout std_logic;
+ fmc_la18_cc_n => tb_fmc_la18_cc_n, -- : inout std_logic;
+ fmc_la18_cc_p => tb_fmc_la18_cc_p, -- : inout std_logic;
+ fmc_la19_n => tb_fmc_la19_n, -- : inout std_logic;
+ fmc_la19_p => tb_fmc_la19_p, -- : inout std_logic;
+ fmc_la20_n => tb_fmc_la20_n, -- : inout std_logic;
+ fmc_la20_p => tb_fmc_la20_p, -- : inout std_logic;
+ fmc_la21_n => tb_fmc_la21_n, -- : inout std_logic;
+ fmc_la21_p => tb_fmc_la21_p, -- : inout std_logic;
+ fmc_la22_n => tb_fmc_la22_n, -- : inout std_logic;
+ fmc_la22_p => tb_fmc_la22_p, -- : inout std_logic;
+ fmc_la23_n => tb_fmc_la23_n, -- : inout std_logic;
+ fmc_la23_p => tb_fmc_la23_p, -- : inout std_logic;
+ fmc_la24_n => tb_fmc_la24_n, -- : inout std_logic;
+ fmc_la24_p => tb_fmc_la24_p, -- : inout std_logic;
+ fmc_la25_n => tb_fmc_la25_n, -- : inout std_logic;
+ fmc_la25_p => tb_fmc_la25_p, -- : inout std_logic;
+ fmc_la26_n => tb_fmc_la26_n, -- : inout std_logic;
+ fmc_la26_p => tb_fmc_la26_p, -- : inout std_logic;
+ fmc_la27_n => tb_fmc_la27_n, -- : inout std_logic;
+ fmc_la27_p => tb_fmc_la27_p, -- : inout std_logic;
+ fmc_la28_n => tb_fmc_la28_n, -- : inout std_logic;
+ fmc_la28_p => tb_fmc_la28_p, -- : inout std_logic;
+ fmc_la29_n => tb_fmc_la29_n, -- : inout std_logic;
+ fmc_la29_p => tb_fmc_la29_p, -- : inout std_logic;
+ fmc_la30_n => tb_fmc_la30_n, -- : inout std_logic;
+ fmc_la30_p => tb_fmc_la30_p, -- : inout std_logic;
+ fmc_la31_n => tb_fmc_la31_n, -- : inout std_logic;
+ fmc_la31_p => tb_fmc_la31_p, -- : inout std_logic;
+ fmc_la32_n => tb_fmc_la32_n, -- : inout std_logic;
+ fmc_la32_p => tb_fmc_la32_p, -- : inout std_logic;
+ fmc_la33_n => tb_fmc_la33_n, -- : inout std_logic;
+ fmc_la33_p => tb_fmc_la33_p, -- : inout std_logic;
+ fmc_prsnt_m2c_l => tb_fmc_prsnt_m2c_l, -- : in std_logic;
+ fmc_pwr_good_flash_rst_b => tb_fmc_pwr_good_flash_rst_b, -- : out std_logic;
+ --
+ fpga_awake => tb_fpga_awake, -- : out std_logic;
+ fpga_cclk => tb_fpga_cclk, -- : out std_logic;
+ fpga_cmp_clk => tb_fpga_cmp_clk, -- : in std_logic;
+ fpga_cmp_mosi => tb_fpga_cmp_mosi, -- : in std_logic;
+ -- --
+ fpga_hswapen => tb_fpga_hswapen, -- : in std_logic;
+ fpga_init_b => tb_fpga_init_b, -- : out std_logic;
+ fpga_m0_cmp_miso => tb_fpga_m0_cmp_miso, -- : in std_logic;
+ fpga_m1 => tb_fpga_m1, -- : in std_logic;
+ fpga_mosi_csi_b_miso0 => tb_fpga_mosi_csi_b_miso0, -- : inout std_logic;
+ fpga_onchip_term1 => tb_fpga_onchip_term1, -- : inout std_logic;
+ fpga_onchip_term2 => tb_fpga_onchip_term2, -- : inout std_logic;
+ fpga_vtemp => tb_fpga_vtemp, -- : in std_logic;
+ --
+ -- GPIOs
+ gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0);
+ gpio_header_ls => tb_gpio_header_ls, -- : inout std_logic_vector(7 downto 0);
+ gpio_led => tb_gpio_led, -- : out std_logic_vector(3 downto 0);
+ gpio_switch => tb_gpio_switch, -- : in std_logic_vector(3 downto 0);
+ --
+ -- Ethernet Gigabit PHY
+ phy_col => tb_phy_col, -- : in std_logic;
+ phy_crs => tb_phy_crs, -- : in std_logic;
+ phy_int => tb_phy_int, -- : in std_logic;
+ phy_mdc => tb_phy_mdc, -- : out std_logic;
+ phy_mdio => tb_phy_mdio, -- : inout std_logic;
+ phy_reset => tb_phy_reset, -- : out std_logic;
+ phy_rxclk => tb_phy_rxclk, -- : in std_logic;
+ phy_rxctl_rxdv => tb_phy_rxctl_rxdv, -- : in std_logic;
+ phy_rxd => tb_phy_rxd, -- : in std_logic_vector(7 downto 0);
+ phy_rxer => tb_phy_rxer, -- : in std_logic;
+ phy_txclk => tb_phy_txclk, -- : in std_logic;
+ phy_txctl_txen => tb_phy_txctl_txen, -- : out std_logic;
+ phy_txc_gtxclk => tb_phy_txc_gtxclk, -- : out std_logic;
+ phy_txd => tb_phy_txd, -- : out std_logic_vector(7 downto 0);
+ phy_txer => tb_phy_txer, -- : out std_logic;
+ --
+ --
+ spi_cs_b => tb_spi_cs_b, -- : out std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ sysclk_n => tb_sysclk_n, -- : in std_logic;
+ sysclk_p => tb_sysclk_p, -- : in std_logic;
+ --
+ -- RS232 via USB
+ usb_1_cts => tb_usb_1_cts, -- : out std_logic;
+ usb_1_rts => tb_usb_1_rts, -- : in std_logic;
+ usb_1_rx => tb_usb_1_rx, -- : out std_logic;
+ usb_1_tx => tb_usb_1_tx, -- : in std_logic;
+ --
+ -- 27 MHz, oscillator socket
+ user_clock => tb_user_clock, -- : in std_logic;
+ --
+ -- user clock provided per SMA
+ user_sma_clock_p => tb_user_sma_clock_p, -- : in std_logic;
+ user_sma_clock_n => tb_user_sma_clock_n -- : in std_logic
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+
+end architecture testbench;
+
diff --git a/zpu/hdl/zealot/helpers/zpu_med1.vhdl b/zpu/hdl/zealot/helpers/zpu_med1.vhdl new file mode 100644 index 0000000..a0cbcb2 --- /dev/null +++ b/zpu/hdl/zealot/helpers/zpu_med1.vhdl @@ -0,0 +1,187 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium + PHI I/O + BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ---- +---- medium version, the PHI I/O basic layout and a program BRAM. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPU_Med1(Structural) (Entity and architecture) ---- +---- File name: zpu_med1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- work.zpu_memory ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +-- RAM declaration +library work; +use work.zpu_memory.all; + +entity ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); +end entity ZPU_Med1; + +architecture Structural of ZPU_Med1 is + constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes + constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O + constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4; + + -- I/O & memory (ZPU) + signal mem_busy : std_logic; + signal mem_read : unsigned(WORD_SIZE-1 downto 0); + signal mem_write : unsigned(WORD_SIZE-1 downto 0); + signal mem_addr : unsigned(ADDR_W-1 downto 0); + signal mem_we : std_logic; + signal mem_re : std_logic; + + -- Memory (SinglePort_RAM) + signal ram_busy : std_logic; + signal ram_read : unsigned(WORD_SIZE-1 downto 0); + signal ram_addr : unsigned(BRAM_W-1 downto BYTE_BITS); + signal ram_we : std_logic; + signal ram_re : std_logic; + signal ram_ready_r : std_logic:='0'; + + -- I/O (ZPU_IO) + signal io_busy : std_logic; + signal io_re : std_logic; + signal io_we : std_logic; + signal io_read : unsigned(WORD_SIZE-1 downto 0); + signal io_ready : std_logic; + signal io_reading_r : std_logic:='0'; + signal io_addr : unsigned(2 downto 0); +begin + memory: SinglePortRAM + generic map( + WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W) + port map( + clk_i => clk_i, + we_i => ram_we, re_i => ram_re, addr_i => ram_addr, + write_i => mem_write, read_o => ram_read, busy_o => ram_busy); + ram_addr <= mem_addr(BRAM_W-1 downto BYTE_BITS); + ram_we <= mem_we and not(mem_addr(IO_BIT)); + ram_re <= mem_re and not(mem_addr(IO_BIT)); + + -- I/O: Phi layout + io_map: ZPUPhiIO + generic map( + BRDIVISOR => BRDIVISOR, + LOG_FILE => "zpu_med1_io.log" + ) + port map( + clk_i => clk_i, + reset_i => rst_i, + busy_o => io_busy, + we_i => io_we, + re_i => io_re, + data_i => mem_write, + data_o => io_read, + addr_i => io_addr, + rs232_rx_i => rs232_rx_i, + rs232_tx_o => rs232_tx_o, + br_clk_i => '1', + gpio_in => gpio_in, + gpio_out => gpio_out, + gpio_dir => gpio_dir + ); + io_addr <= mem_addr(4 downto 2); + -- Here we decode 0x8xxxx as I/O and not just 0x80A00xx + -- Note: We define the address space as 256 kB, so writing to 0x80A00xx + -- will be as wrting to 0x200xx and hence we decode it as I/O space. + io_we <= mem_we and mem_addr(IO_BIT); + io_re <= mem_re and mem_addr(IO_BIT); + io_ready <= (io_reading_r or io_re) and not io_busy; + + zpu : ZPUMediumCore + generic map( + WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W, + D_CARE_VAL => D_CARE_VAL) + port map( + clk_i => clk_i, reset_i => rst_i, enable_i => '1', + break_o => break_o, dbg_o => dbg_o, + -- Memory + mem_busy_i => mem_busy, data_i => mem_read, data_o => mem_write, + addr_o => mem_addr, write_en_o => mem_we, read_en_o => mem_re); + mem_busy <= io_busy or ram_busy; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memory_control: + process (ram_read, ram_ready_r, io_ready, io_read) + begin + mem_read <= (others => '0'); + if ram_ready_r='1' then + mem_read <= ram_read; + end if; + if io_ready='1' then + mem_read <= io_read; + end if; + end process memory_control; + + memory_control_sync: + process (clk_i) + begin + if rising_edge(clk_i) then + if rst_i='1' then + io_reading_r <= '0'; + ram_ready_r <= '0'; + else + io_reading_r <= io_busy or io_re; + ram_ready_r <= ram_re; + end if; + end if; + end process memory_control_sync; +end architecture Structural; -- Entity: ZPU_Med1 + diff --git a/zpu/hdl/zealot/helpers/zpu_small1.vhdl b/zpu/hdl/zealot/helpers/zpu_small1.vhdl new file mode 100644 index 0000000..52006e4 --- /dev/null +++ b/zpu/hdl/zealot/helpers/zpu_small1.vhdl @@ -0,0 +1,153 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small + PHI I/O + BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ---- +---- small version, the PHI I/O basic layout and a program BRAM. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPU_Small1(Structural) (Entity and architecture) ---- +---- File name: zpu_small1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- work.zpu_memory ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +-- RAM declaration +library work; +use work.zpu_memory.all; + +entity ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); +end entity ZPU_Small1; + +architecture Structural of ZPU_Small1 is + constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes + constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O + constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4; + + -- Program+data+stack BRAM + -- Port A + signal a_we : std_logic; + signal a_addr : unsigned(BRAM_W-1 downto BYTE_BITS); + signal a_write : unsigned(WORD_SIZE-1 downto 0); + signal a_read : unsigned(WORD_SIZE-1 downto 0); + -- Port B + signal b_we : std_logic; + signal b_addr : unsigned(BRAM_W-1 downto BYTE_BITS); + signal b_write : unsigned(WORD_SIZE-1 downto 0); + signal b_read : unsigned(WORD_SIZE-1 downto 0); + + -- I/O space + signal io_busy : std_logic; + signal io_write : unsigned(WORD_SIZE-1 downto 0); + signal io_read : unsigned(WORD_SIZE-1 downto 0); + signal io_addr : unsigned(ADDR_W-1 downto 0); + signal phi_addr : unsigned(2 downto 0); + signal io_we : std_logic; + signal io_re : std_logic; +begin + memory: DualPortRAM + generic map( + WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W) + port map( + clk_i => clk_i, + -- Port A + a_we_i => a_we, a_addr_i => a_addr, a_write_i => a_write, + a_read_o => a_read, + -- Port B + b_we_i => b_we, b_addr_i => b_addr, b_write_i => b_write, + b_read_o => b_read); + + -- I/O: Phi layout + io_map: ZPUPhiIO + generic map( + BRDIVISOR => BRDIVISOR, + LOG_FILE => "zpu_small1_io.log" + ) + port map( + clk_i => clk_i, + reset_i => rst_i, + busy_o => io_busy, + we_i => io_we, + re_i => io_re, + data_i => io_write, + data_o => io_read, + addr_i => phi_addr, + rs232_rx_i => rs232_rx_i, + rs232_tx_o => rs232_tx_o, + br_clk_i => '1', + gpio_in => gpio_in, + gpio_out => gpio_out, + gpio_dir => gpio_dir + ); + phi_addr <= io_addr(4 downto 2); + + zpu : ZPUSmallCore + generic map( + WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W, + D_CARE_VAL => D_CARE_VAL) + port map( + clk_i => clk_i, reset_i => rst_i, interrupt_i => '0', + break_o => break_o, dbg_o => dbg_o, + -- BRAM (text, data, bss and stack) + a_we_o => a_we, a_addr_o => a_addr, a_o => a_write, a_i => a_read, + b_we_o => b_we, b_addr_o => b_addr, b_o => b_write, b_i => b_read, + -- Memory mapped I/O + mem_busy_i => io_busy, data_i => io_read, data_o => io_write, + addr_o => io_addr, write_en_o => io_we, read_en_o => io_re); +end architecture Structural; -- Entity: ZPU_Small1 + diff --git a/zpu/hdl/zealot/roms/dmips_bram.vhdl b/zpu/hdl/zealot/roms/dmips_bram.vhdl new file mode 100644 index 0000000..977626c --- /dev/null +++ b/zpu/hdl/zealot/roms/dmips_bram.vhdl @@ -0,0 +1,4462 @@ +------------------------------------------------------------------------------ +---- ---- +---- Single Port RAM that maps to a Xilinx BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ---- +---- File name: rom_s.in.vhdl (template used) ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity SinglePortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + we_i : in std_logic; + re_i : in std_logic; + addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + write_i : in unsigned(WORD_SIZE-1 downto 0); + read_o : out unsigned(WORD_SIZE-1 downto 0); + busy_o : out std_logic); +end entity SinglePortRAM; + +architecture Xilinx of SinglePortRAM is + type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0); + signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS); + + signal ram : ram_type := +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80f8ec0c", + 3 => x"3a0b0b80", + 4 => x"e7ea0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80e8b72d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80f8", + 162 => x"d8738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88aa0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b80ce", + 171 => x"b62d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"80088408", + 177 => x"88087575", + 178 => x"0b0b80cf", + 179 => x"e82d5050", + 180 => x"80085688", + 181 => x"0c840c80", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"810b0b0b", + 209 => x"80f8e80c", + 210 => x"51040000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"00000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"83803f80", + 257 => x"e2953f04", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10101053", + 266 => x"51047381", + 267 => x"ff067383", + 268 => x"06098105", + 269 => x"83051010", + 270 => x"102b0772", + 271 => x"fc060c51", + 272 => x"51043c04", + 273 => x"72728072", + 274 => x"8106ff05", + 275 => x"09720605", + 276 => x"71105272", + 277 => x"0a100a53", + 278 => x"72ed3851", + 279 => x"51535104", + 280 => x"ff3d0d0b", + 281 => x"0b8188e0", + 282 => x"08527108", + 283 => x"70882a81", + 284 => x"32708106", + 285 => x"51515170", + 286 => x"f1387372", + 287 => x"0c833d0d", + 288 => x"0480f8e8", + 289 => x"08802ea4", + 290 => x"3880f8ec", + 291 => x"08822ebd", + 292 => x"38838080", + 293 => x"0b0b0b81", + 294 => x"88e00c82", + 295 => x"a0800b81", + 296 => x"88e40c82", + 297 => x"90800b81", + 298 => x"88e80c04", + 299 => x"f8808080", + 300 => x"a40b0b0b", + 301 => x"8188e00c", + 302 => x"f8808082", + 303 => x"800b8188", + 304 => x"e40cf880", + 305 => x"8084800b", + 306 => x"8188e80c", + 307 => x"0480c0a8", + 308 => x"808c0b0b", + 309 => x"0b8188e0", + 310 => x"0c80c0a8", + 311 => x"80940b81", + 312 => x"88e40c0b", + 313 => x"0b80eac8", + 314 => x"0b8188e8", + 315 => x"0c04f23d", + 316 => x"0d608188", + 317 => x"e408565d", + 318 => x"82750c80", + 319 => x"59805a80", + 320 => x"0b8f3d5d", + 321 => x"5b7a1010", + 322 => x"15700871", + 323 => x"08719f2c", + 324 => x"7e852b58", + 325 => x"55557d53", + 326 => x"59579d94", + 327 => x"3f7d7f7a", + 328 => x"72077c72", + 329 => x"07717160", + 330 => x"8105415f", + 331 => x"5d5b5957", + 332 => x"55817b27", + 333 => x"8f38767d", + 334 => x"0c77841e", + 335 => x"0c7c800c", + 336 => x"903d0d04", + 337 => x"8188e408", + 338 => x"55ffba39", + 339 => x"ff3d0d81", + 340 => x"88ec3351", + 341 => x"70a73880", + 342 => x"f8f40870", + 343 => x"08525270", + 344 => x"802e9438", + 345 => x"841280f8", + 346 => x"f40c702d", + 347 => x"80f8f408", + 348 => x"70085252", + 349 => x"70ee3881", + 350 => x"0b8188ec", + 351 => x"34833d0d", + 352 => x"0404803d", + 353 => x"0d0b0b81", + 354 => x"88dc0880", + 355 => x"2e8e380b", + 356 => x"0b0b0b80", + 357 => x"0b802e09", + 358 => x"81068538", + 359 => x"823d0d04", + 360 => x"0b0b8188", + 361 => x"dc510b0b", + 362 => x"0bf4d53f", + 363 => x"823d0d04", + 364 => x"04ff3d0d", + 365 => x"028f0533", + 366 => x"52718a2e", + 367 => x"8a387151", + 368 => x"fd9e3f83", + 369 => x"3d0d048d", + 370 => x"51fd953f", + 371 => x"7151fd90", + 372 => x"3f833d0d", + 373 => x"04ce3d0d", + 374 => x"b53d7070", + 375 => x"84055208", + 376 => x"8bb15c56", + 377 => x"a53d5e5c", + 378 => x"80757081", + 379 => x"05573376", + 380 => x"5b555873", + 381 => x"782e80c1", + 382 => x"388e3d5b", + 383 => x"73a52e09", + 384 => x"810680c5", + 385 => x"38787081", + 386 => x"055a3354", + 387 => x"7380e42e", + 388 => x"81b63873", + 389 => x"80e42480", + 390 => x"c6387380", + 391 => x"e32ea138", + 392 => x"8052a551", + 393 => x"792d8052", + 394 => x"7351792d", + 395 => x"82185878", + 396 => x"7081055a", + 397 => x"335473c4", + 398 => x"3877800c", + 399 => x"b43d0d04", + 400 => x"7b841d83", + 401 => x"1233565d", + 402 => x"57805273", + 403 => x"51792d81", + 404 => x"18797081", + 405 => x"055b3355", + 406 => x"5873ffa0", + 407 => x"38db3973", + 408 => x"80f32e09", + 409 => x"8106ffb8", + 410 => x"387b841d", + 411 => x"7108595d", + 412 => x"56807733", + 413 => x"55567376", + 414 => x"2e8d3881", + 415 => x"16701870", + 416 => x"33575556", + 417 => x"74f538ff", + 418 => x"16558076", + 419 => x"25ffa038", + 420 => x"76708105", + 421 => x"58335480", + 422 => x"52735179", + 423 => x"2d811875", + 424 => x"ff175757", + 425 => x"58807625", + 426 => x"ff853876", + 427 => x"70810558", + 428 => x"33548052", + 429 => x"7351792d", + 430 => x"811875ff", + 431 => x"17575758", + 432 => x"758024cc", + 433 => x"38fee839", + 434 => x"7b841d71", + 435 => x"0870719f", + 436 => x"2c595359", + 437 => x"5d568075", + 438 => x"24819338", + 439 => x"757d7c58", + 440 => x"56548057", + 441 => x"73772e09", + 442 => x"8106b638", + 443 => x"b07b3402", + 444 => x"b505567a", + 445 => x"762e9738", + 446 => x"ff165675", + 447 => x"33757081", + 448 => x"05573481", + 449 => x"17577a76", + 450 => x"2e098106", + 451 => x"eb388075", + 452 => x"34767dff", + 453 => x"12575856", + 454 => x"758024fe", + 455 => x"f338fe8f", + 456 => x"398a5273", + 457 => x"5180c1c0", + 458 => x"3f800880", + 459 => x"eacc0533", + 460 => x"76708105", + 461 => x"58348a52", + 462 => x"7351bffa", + 463 => x"3f800854", + 464 => x"8008802e", + 465 => x"ffad388a", + 466 => x"52735180", + 467 => x"c19a3f80", + 468 => x"0880eacc", + 469 => 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x"00000000", + 4235 => x"00000000", + 4236 => x"00000000", + 4237 => x"00000000", + 4238 => x"00000000", + 4239 => x"00000000", + 4240 => x"00000000", + 4241 => x"00000000", + 4242 => x"00000000", + 4243 => x"00000000", + 4244 => x"00000000", + 4245 => x"00000000", + 4246 => x"00000000", + 4247 => x"00000000", + 4248 => x"00000000", + 4249 => x"00000000", + 4250 => x"00000000", + 4251 => x"00000000", + 4252 => x"00000000", + 4253 => x"00000000", + 4254 => x"00000000", + 4255 => x"00000000", + 4256 => x"00000000", + 4257 => x"00000000", + 4258 => x"00000000", + 4259 => x"00000000", + 4260 => x"00000000", + 4261 => x"00000000", + 4262 => x"00000000", + 4263 => x"00000000", + 4264 => x"00000000", + 4265 => x"00000000", + 4266 => x"00000000", + 4267 => x"00000000", + 4268 => x"00000000", + 4269 => x"00000000", + 4270 => x"00000000", + 4271 => x"00000000", + 4272 => x"00000000", + 4273 => x"00000000", + 4274 => x"00000000", + 4275 => x"00000000", + 4276 => x"00000000", + 4277 => x"00000000", + 4278 => x"00000000", + 4279 => x"00000000", + 4280 => x"00000000", + 4281 => x"00000000", + 4282 => x"00000000", + 4283 => x"00000000", + 4284 => x"00000000", + 4285 => x"00000000", + 4286 => x"00000000", + 4287 => x"00000000", + 4288 => x"00000000", + 4289 => x"00000000", + 4290 => x"00000000", + 4291 => x"00000000", + 4292 => x"00000000", + 4293 => x"00000000", + 4294 => x"00000000", + 4295 => x"00000000", + 4296 => x"00000000", + 4297 => x"00000000", + 4298 => x"00000000", + 4299 => x"00000000", + 4300 => x"00000000", + 4301 => x"00000000", + 4302 => x"00000000", + 4303 => x"00000000", + 4304 => x"00000000", + 4305 => x"00000000", + 4306 => x"00000000", + 4307 => x"00000000", + 4308 => x"00000000", + 4309 => x"00000000", + 4310 => x"00000000", + 4311 => x"00000000", + 4312 => x"00000000", + 4313 => x"00000000", + 4314 => x"00000000", + 4315 => x"00000000", + 4316 => x"00000000", + 4317 => x"00000000", + 4318 => x"00000000", + 4319 => x"00000000", + 4320 => x"00000000", + 4321 => x"00000000", + 4322 => x"00000000", + 4323 => x"00000000", + 4324 => x"00000000", + 4325 => x"00000000", + 4326 => x"00000000", + 4327 => x"00000000", + 4328 => x"00000000", + 4329 => x"00000000", + 4330 => x"00000000", + 4331 => x"00000000", + 4332 => x"00000000", + 4333 => x"00000000", + 4334 => x"00000000", + 4335 => x"00000000", + 4336 => x"00000000", + 4337 => x"00000000", + 4338 => x"00000000", + 4339 => x"00000000", + 4340 => x"00000000", + 4341 => x"00000000", + 4342 => x"00000000", + 4343 => x"00000000", + 4344 => x"00000000", + 4345 => x"00000000", + 4346 => x"00000000", + 4347 => x"00000000", + 4348 => x"00000000", + 4349 => x"00000000", + 4350 => x"00000000", + 4351 => x"00000000", + 4352 => x"00000000", + 4353 => x"00000000", + 4354 => x"00000000", + 4355 => x"00000000", + 4356 => x"00000000", + 4357 => x"00000000", + 4358 => x"00000000", + 4359 => x"00000000", + 4360 => x"00000000", + 4361 => x"00000000", + 4362 => x"00000000", + 4363 => x"00000000", + 4364 => x"00000000", + 4365 => x"00000000", + 4366 => x"00000000", + 4367 => x"00000000", + 4368 => x"00000000", + 4369 => x"00000000", + 4370 => x"00003c4c", + 4371 => x"ffffffff", + 4372 => x"00000000", + 4373 => x"ffffffff", + 4374 => x"00000000", + 4375 => x"00000000", + +others => x"00000000" +); +begin + busy_o <= re_i; -- we're done on the cycle after we serve the read request + + do_ram: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + if we_i='1' then + ram(to_integer(addr_i)) <= write_i; + end if; + addr_r <= addr_i; + end if; + end process do_ram; + read_o <= ram(to_integer(addr_r)); +end architecture Xilinx; -- Entity: SinglePortRAM + diff --git a/zpu/hdl/zealot/roms/dmips_dbram.vhdl b/zpu/hdl/zealot/roms/dmips_dbram.vhdl new file mode 100644 index 0000000..32b6947 --- /dev/null +++ b/zpu/hdl/zealot/roms/dmips_dbram.vhdl @@ -0,0 +1,4485 @@ +------------------------------------------------------------------------------ +---- ---- +---- Dual Port RAM that maps to a Xilinx BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DualPortRAM(Xilinx) (Entity and architecture) ---- +---- File name: rom.in.vhdl (template used) ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity DualPortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + -- Port A + a_we_i : in std_logic; + a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + a_write_i : in unsigned(WORD_SIZE-1 downto 0); + a_read_o : out unsigned(WORD_SIZE-1 downto 0); + -- Port B + b_we_i : in std_logic; + b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + b_write_i : in unsigned(WORD_SIZE-1 downto 0); + b_read_o : out unsigned(WORD_SIZE-1 downto 0)); +end entity DualPortRAM; + +architecture Xilinx of DualPortRAM is + type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0); + + shared variable ram : ram_type:= +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80f8ec0c", + 3 => x"3a0b0b80", + 4 => x"e7ea0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80e8b72d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80f8", + 162 => x"d8738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88aa0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b80ce", + 171 => x"b62d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"80088408", + 177 => x"88087575", + 178 => x"0b0b80cf", + 179 => x"e82d5050", + 180 => x"80085688", + 181 => x"0c840c80", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"810b0b0b", + 209 => x"80f8e80c", + 210 => x"51040000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"00000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"83803f80", + 257 => x"e2953f04", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10101053", + 266 => x"51047381", + 267 => x"ff067383", + 268 => x"06098105", + 269 => x"83051010", + 270 => x"102b0772", + 271 => x"fc060c51", + 272 => x"51043c04", + 273 => x"72728072", + 274 => x"8106ff05", + 275 => x"09720605", + 276 => x"71105272", + 277 => x"0a100a53", + 278 => x"72ed3851", + 279 => x"51535104", + 280 => x"ff3d0d0b", + 281 => x"0b8188e0", + 282 => x"08527108", + 283 => x"70882a81", + 284 => x"32708106", + 285 => x"51515170", + 286 => x"f1387372", + 287 => x"0c833d0d", + 288 => x"0480f8e8", + 289 => x"08802ea4", + 290 => x"3880f8ec", + 291 => x"08822ebd", + 292 => x"38838080", + 293 => x"0b0b0b81", + 294 => x"88e00c82", + 295 => x"a0800b81", + 296 => x"88e40c82", + 297 => x"90800b81", + 298 => x"88e80c04", + 299 => x"f8808080", + 300 => x"a40b0b0b", + 301 => x"8188e00c", + 302 => x"f8808082", + 303 => x"800b8188", + 304 => x"e40cf880", + 305 => x"8084800b", + 306 => x"8188e80c", + 307 => x"0480c0a8", + 308 => x"808c0b0b", + 309 => x"0b8188e0", + 310 => x"0c80c0a8", + 311 => x"80940b81", + 312 => x"88e40c0b", + 313 => x"0b80eac8", + 314 => x"0b8188e8", + 315 => x"0c04f23d", + 316 => x"0d608188", + 317 => x"e408565d", + 318 => x"82750c80", + 319 => x"59805a80", + 320 => x"0b8f3d5d", + 321 => x"5b7a1010", + 322 => x"15700871", + 323 => x"08719f2c", + 324 => x"7e852b58", + 325 => x"55557d53", + 326 => x"59579d94", + 327 => x"3f7d7f7a", + 328 => x"72077c72", + 329 => x"07717160", + 330 => x"8105415f", + 331 => x"5d5b5957", + 332 => x"55817b27", + 333 => x"8f38767d", + 334 => x"0c77841e", + 335 => x"0c7c800c", + 336 => x"903d0d04", + 337 => x"8188e408", + 338 => x"55ffba39", + 339 => x"ff3d0d81", + 340 => x"88ec3351", + 341 => x"70a73880", + 342 => x"f8f40870", + 343 => x"08525270", + 344 => x"802e9438", + 345 => x"841280f8", + 346 => x"f40c702d", + 347 => x"80f8f408", + 348 => x"70085252", + 349 => x"70ee3881", + 350 => x"0b8188ec", + 351 => x"34833d0d", + 352 => x"0404803d", + 353 => x"0d0b0b81", + 354 => x"88dc0880", + 355 => x"2e8e380b", + 356 => x"0b0b0b80", + 357 => x"0b802e09", + 358 => x"81068538", + 359 => x"823d0d04", + 360 => x"0b0b8188", + 361 => x"dc510b0b", + 362 => x"0bf4d53f", + 363 => x"823d0d04", + 364 => x"04ff3d0d", + 365 => x"028f0533", + 366 => x"52718a2e", + 367 => x"8a387151", + 368 => x"fd9e3f83", + 369 => x"3d0d048d", + 370 => x"51fd953f", + 371 => x"7151fd90", + 372 => x"3f833d0d", + 373 => x"04ce3d0d", + 374 => x"b53d7070", + 375 => x"84055208", + 376 => x"8bb15c56", + 377 => x"a53d5e5c", + 378 => x"80757081", + 379 => x"05573376", + 380 => x"5b555873", + 381 => x"782e80c1", + 382 => x"388e3d5b", + 383 => x"73a52e09", + 384 => x"810680c5", + 385 => x"38787081", + 386 => x"055a3354", + 387 => x"7380e42e", + 388 => x"81b63873", + 389 => x"80e42480", + 390 => x"c6387380", + 391 => x"e32ea138", + 392 => x"8052a551", + 393 => x"792d8052", + 394 => x"7351792d", + 395 => x"82185878", + 396 => x"7081055a", + 397 => x"335473c4", + 398 => x"3877800c", + 399 => x"b43d0d04", + 400 => x"7b841d83", + 401 => x"1233565d", + 402 => x"57805273", + 403 => x"51792d81", + 404 => x"18797081", + 405 => x"055b3355", + 406 => x"5873ffa0", + 407 => x"38db3973", + 408 => x"80f32e09", + 409 => x"8106ffb8", + 410 => x"387b841d", + 411 => x"7108595d", + 412 => x"56807733", + 413 => x"55567376", + 414 => x"2e8d3881", + 415 => x"16701870", + 416 => x"33575556", + 417 => x"74f538ff", + 418 => x"16558076", + 419 => x"25ffa038", + 420 => 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x"00000000", + 4231 => x"00000000", + 4232 => x"00000000", + 4233 => x"00000000", + 4234 => x"00000000", + 4235 => x"00000000", + 4236 => x"00000000", + 4237 => x"00000000", + 4238 => x"00000000", + 4239 => x"00000000", + 4240 => x"00000000", + 4241 => x"00000000", + 4242 => x"00000000", + 4243 => x"00000000", + 4244 => x"00000000", + 4245 => x"00000000", + 4246 => x"00000000", + 4247 => x"00000000", + 4248 => x"00000000", + 4249 => x"00000000", + 4250 => x"00000000", + 4251 => x"00000000", + 4252 => x"00000000", + 4253 => x"00000000", + 4254 => x"00000000", + 4255 => x"00000000", + 4256 => x"00000000", + 4257 => x"00000000", + 4258 => x"00000000", + 4259 => x"00000000", + 4260 => x"00000000", + 4261 => x"00000000", + 4262 => x"00000000", + 4263 => x"00000000", + 4264 => x"00000000", + 4265 => x"00000000", + 4266 => x"00000000", + 4267 => x"00000000", + 4268 => x"00000000", + 4269 => x"00000000", + 4270 => x"00000000", + 4271 => x"00000000", + 4272 => x"00000000", + 4273 => x"00000000", + 4274 => x"00000000", + 4275 => x"00000000", + 4276 => x"00000000", + 4277 => x"00000000", + 4278 => x"00000000", + 4279 => x"00000000", + 4280 => x"00000000", + 4281 => x"00000000", + 4282 => x"00000000", + 4283 => x"00000000", + 4284 => x"00000000", + 4285 => x"00000000", + 4286 => x"00000000", + 4287 => x"00000000", + 4288 => x"00000000", + 4289 => x"00000000", + 4290 => x"00000000", + 4291 => x"00000000", + 4292 => x"00000000", + 4293 => x"00000000", + 4294 => x"00000000", + 4295 => x"00000000", + 4296 => x"00000000", + 4297 => x"00000000", + 4298 => x"00000000", + 4299 => x"00000000", + 4300 => x"00000000", + 4301 => x"00000000", + 4302 => x"00000000", + 4303 => x"00000000", + 4304 => x"00000000", + 4305 => x"00000000", + 4306 => x"00000000", + 4307 => x"00000000", + 4308 => x"00000000", + 4309 => x"00000000", + 4310 => x"00000000", + 4311 => x"00000000", + 4312 => x"00000000", + 4313 => x"00000000", + 4314 => x"00000000", + 4315 => x"00000000", + 4316 => x"00000000", + 4317 => x"00000000", + 4318 => x"00000000", + 4319 => x"00000000", + 4320 => x"00000000", + 4321 => x"00000000", + 4322 => x"00000000", + 4323 => x"00000000", + 4324 => x"00000000", + 4325 => x"00000000", + 4326 => x"00000000", + 4327 => x"00000000", + 4328 => x"00000000", + 4329 => x"00000000", + 4330 => x"00000000", + 4331 => x"00000000", + 4332 => x"00000000", + 4333 => x"00000000", + 4334 => x"00000000", + 4335 => x"00000000", + 4336 => x"00000000", + 4337 => x"00000000", + 4338 => x"00000000", + 4339 => x"00000000", + 4340 => x"00000000", + 4341 => x"00000000", + 4342 => x"00000000", + 4343 => x"00000000", + 4344 => x"00000000", + 4345 => x"00000000", + 4346 => x"00000000", + 4347 => x"00000000", + 4348 => x"00000000", + 4349 => x"00000000", + 4350 => x"00000000", + 4351 => x"00000000", + 4352 => x"00000000", + 4353 => x"00000000", + 4354 => x"00000000", + 4355 => x"00000000", + 4356 => x"00000000", + 4357 => x"00000000", + 4358 => x"00000000", + 4359 => x"00000000", + 4360 => x"00000000", + 4361 => x"00000000", + 4362 => x"00000000", + 4363 => x"00000000", + 4364 => x"00000000", + 4365 => x"00000000", + 4366 => x"00000000", + 4367 => x"00000000", + 4368 => x"00000000", + 4369 => x"00000000", + 4370 => x"00003c4c", + 4371 => x"ffffffff", + 4372 => x"00000000", + 4373 => x"ffffffff", + 4374 => x"00000000", + 4375 => x"00000000", + +others => x"00000000" +); +begin + do_port_a: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then + report "DualPortRAM write collision" severity failure; + end if; + iaddr:=to_integer(a_addr_i); + if a_we_i='1' then + ram(iaddr):=a_write_i; + -- Write First mode + a_read_o <= a_write_i; + else + a_read_o <= ram(iaddr); + end if; + end if; + end process do_port_a; + + do_port_b: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + iaddr:=to_integer(b_addr_i); + if b_we_i='1' then + ram(iaddr):=b_write_i; + b_read_o <= b_write_i; + else + b_read_o <= ram(iaddr); + end if; + end if; + end process do_port_b; +end architecture Xilinx; -- Entity: DualPortRAM diff --git a/zpu/hdl/zealot/roms/hello_bram.vhdl b/zpu/hdl/zealot/roms/hello_bram.vhdl new file mode 100644 index 0000000..7724423 --- /dev/null +++ b/zpu/hdl/zealot/roms/hello_bram.vhdl @@ -0,0 +1,3056 @@ +------------------------------------------------------------------------------ +---- ---- +---- Single Port RAM that maps to a Xilinx BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ---- +---- File name: rom_s.in.vhdl (template used) ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity SinglePortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + we_i : in std_logic; + re_i : in std_logic; + addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + write_i : in unsigned(WORD_SIZE-1 downto 0); + read_o : out unsigned(WORD_SIZE-1 downto 0); + busy_o : out std_logic); +end entity SinglePortRAM; + +architecture Xilinx of SinglePortRAM is + type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0); + signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS); + + signal ram : ram_type := +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80cd800c", + 3 => x"3a0b0b80", + 4 => x"c58f0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80c5d62d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80cc", + 162 => x"ec738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88aa0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b0b8b", + 171 => x"8a2d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"80088408", + 177 => x"88087575", + 178 => x"0b0b0b8c", + 179 => x"bc2d5050", + 180 => x"80085688", + 181 => x"0c840c80", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"810b0b0b", + 209 => x"80ccfc0c", + 210 => x"51040000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"00000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"82c73f80", + 257 => x"c4913f04", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10101053", + 266 => x"51047381", + 267 => x"ff067383", + 268 => x"06098105", + 269 => x"83051010", + 270 => x"102b0772", + 271 => x"fc060c51", + 272 => x"51043c04", + 273 => x"72728072", + 274 => x"8106ff05", + 275 => x"09720605", + 276 => x"71105272", + 277 => x"0a100a53", + 278 => x"72ed3851", + 279 => x"51535104", + 280 => x"fe3d0d0b", + 281 => x"0b80dce8", + 282 => x"08538413", + 283 => x"0870882a", + 284 => x"70810651", + 285 => x"52527080", + 286 => x"2ef03871", + 287 => x"81ff0680", + 288 => x"0c843d0d", + 289 => x"04ff3d0d", + 290 => x"0b0b80dc", + 291 => x"e8085271", + 292 => x"0870882a", + 293 => x"81327081", + 294 => x"06515151", + 295 => x"70f13873", + 296 => x"720c833d", + 297 => x"0d0480cc", + 298 => x"fc08802e", + 299 => x"a43880cd", + 300 => x"8008822e", + 301 => x"bd388380", + 302 => x"800b0b0b", + 303 => x"80dce80c", + 304 => x"82a0800b", + 305 => x"80dcec0c", + 306 => x"8290800b", + 307 => x"80dcf00c", + 308 => x"04f88080", + 309 => x"80a40b0b", + 310 => x"0b80dce8", + 311 => x"0cf88080", + 312 => x"82800b80", + 313 => x"dcec0cf8", + 314 => x"80808480", + 315 => x"0b80dcf0", + 316 => x"0c0480c0", + 317 => x"a8808c0b", + 318 => x"0b0b80dc", + 319 => x"e80c80c0", + 320 => x"a880940b", + 321 => x"80dcec0c", + 322 => x"0b0b80cc", + 323 => x"c40b80dc", + 324 => x"f00c04ff", + 325 => x"3d0d80dc", + 326 => x"f4335170", + 327 => x"a73880cd", + 328 => x"88087008", + 329 => x"52527080", + 330 => x"2e943884", + 331 => x"1280cd88", + 332 => x"0c702d80", + 333 => x"cd880870", + 334 => x"08525270", + 335 => x"ee38810b", + 336 => x"80dcf434", + 337 => x"833d0d04", + 338 => x"04803d0d", + 339 => x"0b0b80dc", + 340 => x"e408802e", + 341 => x"8e380b0b", + 342 => x"0b0b800b", + 343 => x"802e0981", + 344 => x"06853882", + 345 => x"3d0d040b", + 346 => x"0b80dce4", + 347 => x"510b0b0b", + 348 => x"f58e3f82", + 349 => x"3d0d0404", + 350 => x"803d0d80", + 351 => x"ccc85185", + 352 => x"de3f800b", + 353 => x"800c823d", + 354 => x"0d048c08", + 355 => x"028c0cf9", + 356 => x"3d0d800b", + 357 => x"8c08fc05", + 358 => x"0c8c0888", + 359 => x"05088025", + 360 => x"ab388c08", + 361 => x"88050830", + 362 => x"8c088805", + 363 => x"0c800b8c", + 364 => x"08f4050c", + 365 => x"8c08fc05", + 366 => x"08883881", + 367 => x"0b8c08f4", + 368 => x"050c8c08", + 369 => x"f405088c", + 370 => x"08fc050c", + 371 => x"8c088c05", + 372 => x"088025ab", + 373 => x"388c088c", + 374 => x"0508308c", + 375 => x"088c050c", + 376 => x"800b8c08", + 377 => x"f0050c8c", + 378 => x"08fc0508", + 379 => x"8838810b", + 380 => x"8c08f005", + 381 => x"0c8c08f0", + 382 => x"05088c08", + 383 => x"fc050c80", + 384 => x"538c088c", + 385 => x"0508528c", + 386 => x"08880508", + 387 => x"5181a73f", + 388 => x"8008708c", + 389 => x"08f8050c", + 390 => x"548c08fc", + 391 => x"0508802e", + 392 => x"8c388c08", + 393 => x"f8050830", + 394 => x"8c08f805", + 395 => x"0c8c08f8", + 396 => x"05087080", + 397 => x"0c54893d", + 398 => x"0d8c0c04", + 399 => x"8c08028c", + 400 => x"0cfb3d0d", + 401 => x"800b8c08", + 402 => x"fc050c8c", + 403 => x"08880508", + 404 => x"80259338", + 405 => x"8c088805", + 406 => x"08308c08", + 407 => x"88050c81", + 408 => x"0b8c08fc", + 409 => x"050c8c08", + 410 => x"8c050880", + 411 => x"258c388c", + 412 => x"088c0508", + 413 => x"308c088c", + 414 => x"050c8153", + 415 => x"8c088c05", + 416 => x"08528c08", + 417 => x"88050851", + 418 => x"ad3f8008", + 419 => x"708c08f8", + 420 => x"050c548c", + 421 => x"08fc0508", + 422 => x"802e8c38", + 423 => x"8c08f805", + 424 => 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x"51ffa93f", + 2343 => x"80088215", + 2344 => x"23845288", + 2345 => x"1551ff9c", + 2346 => x"3f800884", + 2347 => x"150c8452", + 2348 => x"8c1551ff", + 2349 => x"8f3f8008", + 2350 => x"88152384", + 2351 => x"52901551", + 2352 => x"ff823f80", + 2353 => x"088a1523", + 2354 => x"84529415", + 2355 => x"51fef53f", + 2356 => x"80088c15", + 2357 => x"23845298", + 2358 => x"1551fee8", + 2359 => x"3f80088e", + 2360 => x"15238852", + 2361 => x"9c1551fe", + 2362 => x"db3f8008", + 2363 => x"90150c86", + 2364 => x"3d0d04e9", + 2365 => x"3d0d6a80", + 2366 => x"dcfc0857", + 2367 => x"57759338", + 2368 => x"80c0800b", + 2369 => x"84180c75", + 2370 => x"ac180c75", + 2371 => x"800c993d", + 2372 => x"0d04893d", + 2373 => x"70556a54", + 2374 => x"558a5299", + 2375 => x"3dffbc05", + 2376 => x"51ffbe9e", + 2377 => x"3f800877", + 2378 => x"53755256", + 2379 => x"fecb3fbc", + 2380 => x"3f778008", + 2381 => x"0c75800c", + 2382 => x"993d0d04", + 2383 => x"fc3d0d81", + 2384 => x"5480dcfc", + 2385 => x"08883873", + 2386 => x"800c863d", + 2387 => x"0d047653", + 2388 => x"97b95286", + 2389 => x"3dfc0551", + 2390 => x"ffbde73f", + 2391 => x"8008548c", + 2392 => x"3f748008", + 2393 => x"0c73800c", + 2394 => x"863d0d04", + 2395 => x"80cd8c08", + 2396 => x"800c04f7", + 2397 => x"3d0d7b80", + 2398 => x"cd8c0882", + 2399 => x"c811085a", + 2400 => x"545a7780", + 2401 => x"2e80da38", + 2402 => x"81881884", + 2403 => x"1908ff05", + 2404 => x"81712b59", + 2405 => x"55598074", + 2406 => x"2480ea38", + 2407 => x"807424b5", + 2408 => x"3873822b", + 2409 => x"78118805", + 2410 => x"56568180", + 2411 => x"19087706", + 2412 => x"5372802e", + 2413 => x"b6387816", + 2414 => x"70085353", + 2415 => x"79517408", + 2416 => x"53722dff", + 2417 => x"14fc17fc", + 2418 => x"1779812c", + 2419 => x"5a575754", + 2420 => x"738025d6", + 2421 => x"38770858", + 2422 => x"77ffad38", + 2423 => x"80cd8c08", + 2424 => x"53bc1308", + 2425 => x"a5387951", + 2426 => x"f9e93f74", + 2427 => x"0853722d", + 2428 => x"ff14fc17", + 2429 => x"fc177981", + 2430 => x"2c5a5757", + 2431 => x"54738025", + 2432 => x"ffa838d1", + 2433 => x"398057ff", + 2434 => x"93397251", + 2435 => x"bc130853", + 2436 => x"722d7951", + 2437 => x"f9bd3fff", + 2438 => x"3d0d80dc", + 2439 => x"d80bfc05", + 2440 => x"70085252", + 2441 => x"70ff2e91", + 2442 => x"38702dfc", + 2443 => x"12700852", + 2444 => x"5270ff2e", + 2445 => x"098106f1", + 2446 => x"38833d0d", + 2447 => x"0404ffbd", + 2448 => x"d23f0400", + 2449 => x"00000040", + 2450 => x"48656c6c", + 2451 => x"6f20776f", + 2452 => x"726c6421", + 2453 => x"00000000", + 2454 => x"0a000000", + 2455 => x"43000000", + 2456 => x"64756d6d", + 2457 => x"792e6578", + 2458 => x"65000000", + 2459 => x"00ffffff", + 2460 => x"ff00ffff", + 2461 => x"ffff00ff", + 2462 => x"ffffff00", + 2463 => x"00000000", + 2464 => x"00000000", + 2465 => x"00000000", + 2466 => x"00002e60", + 2467 => x"00002690", + 2468 => x"00000000", + 2469 => x"000028f8", + 2470 => x"00002954", + 2471 => x"000029b0", + 2472 => x"00000000", + 2473 => x"00000000", + 2474 => x"00000000", + 2475 => x"00000000", + 2476 => x"00000000", + 2477 => x"00000000", + 2478 => x"00000000", + 2479 => x"00000000", + 2480 => x"00000000", + 2481 => x"0000265c", + 2482 => x"00000000", + 2483 => x"00000000", + 2484 => x"00000000", + 2485 => x"00000000", + 2486 => x"00000000", + 2487 => x"00000000", + 2488 => x"00000000", + 2489 => x"00000000", + 2490 => x"00000000", + 2491 => x"00000000", + 2492 => x"00000000", + 2493 => x"00000000", + 2494 => x"00000000", + 2495 => x"00000000", + 2496 => x"00000000", + 2497 => x"00000000", + 2498 => x"00000000", + 2499 => x"00000000", + 2500 => x"00000000", + 2501 => x"00000000", + 2502 => x"00000000", + 2503 => x"00000000", + 2504 => x"00000000", + 2505 => x"00000000", + 2506 => x"00000000", + 2507 => x"00000000", + 2508 => x"00000000", + 2509 => x"00000000", + 2510 => x"00000001", + 2511 => x"330eabcd", + 2512 => x"1234e66d", + 2513 => x"deec0005", + 2514 => x"000b0000", + 2515 => x"00000000", + 2516 => x"00000000", + 2517 => x"00000000", + 2518 => x"00000000", + 2519 => x"00000000", + 2520 => x"00000000", + 2521 => x"00000000", + 2522 => x"00000000", + 2523 => x"00000000", + 2524 => x"00000000", + 2525 => x"00000000", + 2526 => x"00000000", + 2527 => x"00000000", + 2528 => x"00000000", + 2529 => x"00000000", + 2530 => x"00000000", + 2531 => x"00000000", + 2532 => x"00000000", + 2533 => x"00000000", + 2534 => x"00000000", + 2535 => x"00000000", + 2536 => x"00000000", + 2537 => x"00000000", + 2538 => x"00000000", + 2539 => x"00000000", + 2540 => x"00000000", + 2541 => x"00000000", + 2542 => x"00000000", + 2543 => x"00000000", + 2544 => x"00000000", + 2545 => x"00000000", + 2546 => x"00000000", + 2547 => x"00000000", + 2548 => x"00000000", + 2549 => x"00000000", + 2550 => x"00000000", + 2551 => x"00000000", + 2552 => x"00000000", + 2553 => x"00000000", + 2554 => x"00000000", + 2555 => x"00000000", + 2556 => x"00000000", + 2557 => x"00000000", + 2558 => x"00000000", + 2559 => x"00000000", + 2560 => x"00000000", + 2561 => x"00000000", + 2562 => x"00000000", + 2563 => x"00000000", + 2564 => x"00000000", + 2565 => x"00000000", + 2566 => x"00000000", + 2567 => x"00000000", + 2568 => x"00000000", + 2569 => x"00000000", + 2570 => x"00000000", + 2571 => x"00000000", + 2572 => x"00000000", + 2573 => x"00000000", + 2574 => x"00000000", + 2575 => x"00000000", + 2576 => x"00000000", + 2577 => x"00000000", + 2578 => x"00000000", + 2579 => x"00000000", + 2580 => x"00000000", + 2581 => x"00000000", + 2582 => x"00000000", + 2583 => x"00000000", + 2584 => x"00000000", + 2585 => x"00000000", + 2586 => x"00000000", + 2587 => x"00000000", + 2588 => x"00000000", + 2589 => x"00000000", + 2590 => x"00000000", + 2591 => x"00000000", + 2592 => x"00000000", + 2593 => x"00000000", + 2594 => x"00000000", + 2595 => x"00000000", + 2596 => x"00000000", + 2597 => x"00000000", + 2598 => x"00000000", + 2599 => x"00000000", + 2600 => x"00000000", + 2601 => x"00000000", + 2602 => x"00000000", + 2603 => x"00000000", + 2604 => x"00000000", + 2605 => x"00000000", + 2606 => x"00000000", + 2607 => x"00000000", + 2608 => x"00000000", + 2609 => x"00000000", + 2610 => x"00000000", + 2611 => x"00000000", + 2612 => x"00000000", + 2613 => x"00000000", + 2614 => x"00000000", + 2615 => x"00000000", + 2616 => x"00000000", + 2617 => x"00000000", + 2618 => x"00000000", + 2619 => x"00000000", + 2620 => x"00000000", + 2621 => x"00000000", + 2622 => x"00000000", + 2623 => x"00000000", + 2624 => x"00000000", + 2625 => x"00000000", + 2626 => x"00000000", + 2627 => x"00000000", + 2628 => x"00000000", + 2629 => x"00000000", + 2630 => x"00000000", + 2631 => x"00000000", + 2632 => x"00000000", + 2633 => x"00000000", + 2634 => x"00000000", + 2635 => x"00000000", + 2636 => x"00000000", + 2637 => x"00000000", + 2638 => x"00000000", + 2639 => x"00000000", + 2640 => x"00000000", + 2641 => x"00000000", + 2642 => x"00000000", + 2643 => x"00000000", + 2644 => x"00000000", + 2645 => x"00000000", + 2646 => x"00000000", + 2647 => x"00000000", + 2648 => x"00000000", + 2649 => x"00000000", + 2650 => x"00000000", + 2651 => x"00000000", + 2652 => x"00000000", + 2653 => x"00000000", + 2654 => x"00000000", + 2655 => x"00000000", + 2656 => x"00000000", + 2657 => x"00000000", + 2658 => x"00000000", + 2659 => x"00000000", + 2660 => x"00000000", + 2661 => x"00000000", + 2662 => x"00000000", + 2663 => x"00000000", + 2664 => x"00000000", + 2665 => x"00000000", + 2666 => x"00000000", + 2667 => x"00000000", + 2668 => x"00000000", + 2669 => x"00000000", + 2670 => x"00000000", + 2671 => x"00000000", + 2672 => x"00000000", + 2673 => x"00000000", + 2674 => x"00000000", + 2675 => x"00000000", + 2676 => x"00000000", + 2677 => x"00000000", + 2678 => x"00000000", + 2679 => x"00000000", + 2680 => x"00000000", + 2681 => x"00000000", + 2682 => x"00000000", + 2683 => x"00000000", + 2684 => x"00000000", + 2685 => x"00000000", + 2686 => x"00000000", + 2687 => x"00000000", + 2688 => x"00000000", + 2689 => x"00000000", + 2690 => x"00000000", + 2691 => x"00000000", + 2692 => x"00000000", + 2693 => x"00000000", + 2694 => x"00000000", + 2695 => x"00000000", + 2696 => x"00000000", + 2697 => x"00000000", + 2698 => x"00000000", + 2699 => x"00000000", + 2700 => x"00000000", + 2701 => x"00000000", + 2702 => x"00000000", + 2703 => x"ffffffff", + 2704 => x"00000000", + 2705 => x"00020000", + 2706 => x"00000000", + 2707 => x"00000000", + 2708 => x"00002a48", + 2709 => x"00002a48", + 2710 => x"00002a50", + 2711 => x"00002a50", + 2712 => x"00002a58", + 2713 => x"00002a58", + 2714 => x"00002a60", + 2715 => x"00002a60", + 2716 => x"00002a68", + 2717 => x"00002a68", + 2718 => x"00002a70", + 2719 => x"00002a70", + 2720 => x"00002a78", + 2721 => x"00002a78", + 2722 => x"00002a80", + 2723 => x"00002a80", + 2724 => x"00002a88", + 2725 => x"00002a88", + 2726 => x"00002a90", + 2727 => x"00002a90", + 2728 => x"00002a98", + 2729 => x"00002a98", + 2730 => x"00002aa0", + 2731 => x"00002aa0", + 2732 => x"00002aa8", + 2733 => x"00002aa8", + 2734 => x"00002ab0", + 2735 => x"00002ab0", + 2736 => x"00002ab8", + 2737 => x"00002ab8", + 2738 => x"00002ac0", + 2739 => x"00002ac0", + 2740 => x"00002ac8", + 2741 => x"00002ac8", + 2742 => x"00002ad0", + 2743 => x"00002ad0", + 2744 => x"00002ad8", + 2745 => x"00002ad8", + 2746 => x"00002ae0", + 2747 => x"00002ae0", + 2748 => x"00002ae8", + 2749 => x"00002ae8", + 2750 => x"00002af0", + 2751 => x"00002af0", + 2752 => x"00002af8", + 2753 => x"00002af8", + 2754 => x"00002b00", + 2755 => x"00002b00", + 2756 => x"00002b08", + 2757 => x"00002b08", + 2758 => x"00002b10", + 2759 => x"00002b10", + 2760 => x"00002b18", + 2761 => x"00002b18", + 2762 => x"00002b20", + 2763 => x"00002b20", + 2764 => x"00002b28", + 2765 => x"00002b28", + 2766 => x"00002b30", + 2767 => x"00002b30", + 2768 => x"00002b38", + 2769 => x"00002b38", + 2770 => x"00002b40", + 2771 => x"00002b40", + 2772 => x"00002b48", + 2773 => x"00002b48", + 2774 => x"00002b50", + 2775 => x"00002b50", + 2776 => x"00002b58", + 2777 => x"00002b58", + 2778 => x"00002b60", + 2779 => x"00002b60", + 2780 => x"00002b68", + 2781 => x"00002b68", + 2782 => x"00002b70", + 2783 => x"00002b70", + 2784 => x"00002b78", + 2785 => x"00002b78", + 2786 => x"00002b80", + 2787 => x"00002b80", + 2788 => x"00002b88", + 2789 => x"00002b88", + 2790 => x"00002b90", + 2791 => x"00002b90", + 2792 => x"00002b98", + 2793 => x"00002b98", + 2794 => x"00002ba0", + 2795 => x"00002ba0", + 2796 => x"00002ba8", + 2797 => x"00002ba8", + 2798 => x"00002bb0", + 2799 => x"00002bb0", + 2800 => x"00002bb8", + 2801 => x"00002bb8", + 2802 => x"00002bc0", + 2803 => x"00002bc0", + 2804 => x"00002bc8", + 2805 => x"00002bc8", + 2806 => x"00002bd0", + 2807 => x"00002bd0", + 2808 => x"00002bd8", + 2809 => x"00002bd8", + 2810 => x"00002be0", + 2811 => x"00002be0", + 2812 => x"00002be8", + 2813 => x"00002be8", + 2814 => x"00002bf0", + 2815 => x"00002bf0", + 2816 => x"00002bf8", + 2817 => x"00002bf8", + 2818 => x"00002c00", + 2819 => x"00002c00", + 2820 => x"00002c08", + 2821 => x"00002c08", + 2822 => x"00002c10", + 2823 => x"00002c10", + 2824 => x"00002c18", + 2825 => x"00002c18", + 2826 => x"00002c20", + 2827 => x"00002c20", + 2828 => x"00002c28", + 2829 => x"00002c28", + 2830 => x"00002c30", + 2831 => x"00002c30", + 2832 => x"00002c38", + 2833 => x"00002c38", + 2834 => x"00002c40", + 2835 => x"00002c40", + 2836 => x"00002c48", + 2837 => x"00002c48", + 2838 => x"00002c50", + 2839 => x"00002c50", + 2840 => x"00002c58", + 2841 => x"00002c58", + 2842 => x"00002c60", + 2843 => x"00002c60", + 2844 => x"00002c68", + 2845 => x"00002c68", + 2846 => x"00002c70", + 2847 => x"00002c70", + 2848 => x"00002c78", + 2849 => x"00002c78", + 2850 => x"00002c80", + 2851 => x"00002c80", + 2852 => x"00002c88", + 2853 => x"00002c88", + 2854 => x"00002c90", + 2855 => x"00002c90", + 2856 => x"00002c98", + 2857 => x"00002c98", + 2858 => x"00002ca0", + 2859 => x"00002ca0", + 2860 => x"00002ca8", + 2861 => x"00002ca8", + 2862 => x"00002cb0", + 2863 => x"00002cb0", + 2864 => x"00002cb8", + 2865 => x"00002cb8", + 2866 => x"00002cc0", + 2867 => x"00002cc0", + 2868 => x"00002cc8", + 2869 => x"00002cc8", + 2870 => x"00002cd0", + 2871 => x"00002cd0", + 2872 => x"00002cd8", + 2873 => x"00002cd8", + 2874 => x"00002ce0", + 2875 => x"00002ce0", + 2876 => x"00002ce8", + 2877 => x"00002ce8", + 2878 => x"00002cf0", + 2879 => x"00002cf0", + 2880 => x"00002cf8", + 2881 => x"00002cf8", + 2882 => x"00002d00", + 2883 => x"00002d00", + 2884 => x"00002d08", + 2885 => x"00002d08", + 2886 => x"00002d10", + 2887 => x"00002d10", + 2888 => x"00002d18", + 2889 => x"00002d18", + 2890 => x"00002d20", + 2891 => x"00002d20", + 2892 => x"00002d28", + 2893 => x"00002d28", + 2894 => x"00002d30", + 2895 => x"00002d30", + 2896 => x"00002d38", + 2897 => x"00002d38", + 2898 => x"00002d40", + 2899 => x"00002d40", + 2900 => x"00002d48", + 2901 => x"00002d48", + 2902 => x"00002d50", + 2903 => x"00002d50", + 2904 => x"00002d58", + 2905 => x"00002d58", + 2906 => x"00002d60", + 2907 => x"00002d60", + 2908 => x"00002d68", + 2909 => x"00002d68", + 2910 => x"00002d70", + 2911 => x"00002d70", + 2912 => x"00002d78", + 2913 => x"00002d78", + 2914 => x"00002d80", + 2915 => x"00002d80", + 2916 => x"00002d88", + 2917 => x"00002d88", + 2918 => x"00002d90", + 2919 => x"00002d90", + 2920 => x"00002d98", + 2921 => x"00002d98", + 2922 => x"00002da0", + 2923 => x"00002da0", + 2924 => x"00002da8", + 2925 => x"00002da8", + 2926 => x"00002db0", + 2927 => x"00002db0", + 2928 => x"00002db8", + 2929 => x"00002db8", + 2930 => x"00002dc0", + 2931 => x"00002dc0", + 2932 => x"00002dc8", + 2933 => x"00002dc8", + 2934 => x"00002dd0", + 2935 => x"00002dd0", + 2936 => x"00002dd8", + 2937 => x"00002dd8", + 2938 => x"00002de0", + 2939 => x"00002de0", + 2940 => x"00002de8", + 2941 => x"00002de8", + 2942 => x"00002df0", + 2943 => x"00002df0", + 2944 => x"00002df8", + 2945 => x"00002df8", + 2946 => x"00002e00", + 2947 => x"00002e00", + 2948 => x"00002e08", + 2949 => x"00002e08", + 2950 => x"00002e10", + 2951 => x"00002e10", + 2952 => x"00002e18", + 2953 => x"00002e18", + 2954 => x"00002e20", + 2955 => x"00002e20", + 2956 => x"00002e28", + 2957 => x"00002e28", + 2958 => x"00002e30", + 2959 => x"00002e30", + 2960 => x"00002e38", + 2961 => x"00002e38", + 2962 => x"00002e40", + 2963 => x"00002e40", + 2964 => x"00002660", + 2965 => x"ffffffff", + 2966 => x"00000000", + 2967 => x"ffffffff", + 2968 => x"00000000", + 2969 => x"00000000", + +others => x"00000000" +); +begin + busy_o <= re_i; -- we're done on the cycle after we serve the read request + + do_ram: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + if we_i='1' then + ram(to_integer(addr_i)) <= write_i; + end if; + addr_r <= addr_i; + end if; + end process do_ram; + read_o <= ram(to_integer(addr_r)); +end architecture Xilinx; -- Entity: SinglePortRAM + diff --git a/zpu/hdl/zealot/roms/hello_dbram.vhdl b/zpu/hdl/zealot/roms/hello_dbram.vhdl new file mode 100644 index 0000000..28cac6f --- /dev/null +++ b/zpu/hdl/zealot/roms/hello_dbram.vhdl @@ -0,0 +1,3035 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity DualPortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + -- Port A + a_we_i : in std_logic; + a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + a_write_i : in unsigned(WORD_SIZE-1 downto 0); + a_read_o : out unsigned(WORD_SIZE-1 downto 0); + -- Port B + b_we_i : in std_logic; + b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + b_write_i : in unsigned(WORD_SIZE-1 downto 0); + b_read_o : out unsigned(WORD_SIZE-1 downto 0)); +end entity DualPortRAM; + +architecture DualPort_Arch of DualPortRAM is + type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0); + + shared variable ram : ram_type:= +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80cd800c", + 3 => x"3a0b0b80", + 4 => x"c58f0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80c5d62d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80cc", + 162 => x"ec738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88aa0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b0b8b", + 171 => x"8a2d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"80088408", + 177 => x"88087575", + 178 => x"0b0b0b8c", + 179 => x"bc2d5050", + 180 => x"80085688", + 181 => x"0c840c80", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"810b0b0b", + 209 => x"80ccfc0c", + 210 => x"51040000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"00000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"82c73f80", + 257 => x"c4913f04", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10101053", + 266 => x"51047381", + 267 => x"ff067383", + 268 => x"06098105", + 269 => x"83051010", + 270 => x"102b0772", + 271 => x"fc060c51", + 272 => x"51043c04", + 273 => x"72728072", + 274 => x"8106ff05", + 275 => x"09720605", + 276 => x"71105272", + 277 => x"0a100a53", + 278 => x"72ed3851", + 279 => x"51535104", + 280 => x"fe3d0d0b", + 281 => x"0b80dce8", + 282 => x"08538413", + 283 => x"0870882a", + 284 => x"70810651", + 285 => x"52527080", + 286 => x"2ef03871", + 287 => x"81ff0680", + 288 => x"0c843d0d", + 289 => x"04ff3d0d", + 290 => x"0b0b80dc", + 291 => x"e8085271", + 292 => x"0870882a", + 293 => x"81327081", + 294 => x"06515151", + 295 => x"70f13873", + 296 => x"720c833d", + 297 => x"0d0480cc", + 298 => x"fc08802e", + 299 => x"a43880cd", + 300 => x"8008822e", + 301 => x"bd388380", + 302 => x"800b0b0b", + 303 => x"80dce80c", + 304 => x"82a0800b", + 305 => x"80dcec0c", + 306 => x"8290800b", + 307 => x"80dcf00c", + 308 => x"04f88080", + 309 => x"80a40b0b", + 310 => x"0b80dce8", + 311 => x"0cf88080", + 312 => x"82800b80", + 313 => x"dcec0cf8", + 314 => x"80808480", + 315 => x"0b80dcf0", + 316 => x"0c0480c0", + 317 => x"a8808c0b", + 318 => x"0b0b80dc", + 319 => x"e80c80c0", + 320 => x"a880940b", + 321 => x"80dcec0c", + 322 => x"0b0b80cc", + 323 => x"c40b80dc", + 324 => x"f00c04ff", + 325 => x"3d0d80dc", + 326 => x"f4335170", + 327 => x"a73880cd", + 328 => x"88087008", + 329 => x"52527080", + 330 => x"2e943884", + 331 => x"1280cd88", + 332 => x"0c702d80", + 333 => x"cd880870", + 334 => x"08525270", + 335 => x"ee38810b", + 336 => x"80dcf434", + 337 => x"833d0d04", + 338 => x"04803d0d", + 339 => x"0b0b80dc", + 340 => x"e408802e", + 341 => x"8e380b0b", + 342 => x"0b0b800b", + 343 => x"802e0981", + 344 => x"06853882", + 345 => x"3d0d040b", + 346 => x"0b80dce4", + 347 => x"510b0b0b", + 348 => x"f58e3f82", + 349 => x"3d0d0404", + 350 => x"803d0d80", + 351 => x"ccc85185", + 352 => x"de3f800b", + 353 => x"800c823d", + 354 => x"0d048c08", + 355 => x"028c0cf9", + 356 => x"3d0d800b", + 357 => x"8c08fc05", + 358 => x"0c8c0888", + 359 => x"05088025", + 360 => x"ab388c08", + 361 => x"88050830", + 362 => x"8c088805", + 363 => x"0c800b8c", + 364 => x"08f4050c", + 365 => x"8c08fc05", + 366 => x"08883881", + 367 => x"0b8c08f4", + 368 => x"050c8c08", + 369 => x"f405088c", + 370 => x"08fc050c", + 371 => x"8c088c05", + 372 => x"088025ab", + 373 => x"388c088c", + 374 => x"0508308c", + 375 => x"088c050c", + 376 => x"800b8c08", + 377 => x"f0050c8c", + 378 => x"08fc0508", + 379 => x"8838810b", + 380 => x"8c08f005", + 381 => x"0c8c08f0", + 382 => x"05088c08", + 383 => x"fc050c80", + 384 => x"538c088c", + 385 => x"0508528c", + 386 => x"08880508", + 387 => x"5181a73f", + 388 => x"8008708c", + 389 => x"08f8050c", + 390 => x"548c08fc", + 391 => x"0508802e", + 392 => x"8c388c08", + 393 => x"f8050830", + 394 => x"8c08f805", + 395 => x"0c8c08f8", + 396 => x"05087080", + 397 => x"0c54893d", + 398 => x"0d8c0c04", + 399 => x"8c08028c", + 400 => x"0cfb3d0d", + 401 => x"800b8c08", + 402 => x"fc050c8c", + 403 => x"08880508", + 404 => x"80259338", + 405 => x"8c088805", + 406 => x"08308c08", + 407 => x"88050c81", + 408 => x"0b8c08fc", + 409 => x"050c8c08", + 410 => x"8c050880", + 411 => x"258c388c", + 412 => x"088c0508", + 413 => x"308c088c", + 414 => x"050c8153", + 415 => x"8c088c05", + 416 => x"08528c08", + 417 => x"88050851", + 418 => x"ad3f8008", + 419 => x"708c08f8", + 420 => x"050c548c", + 421 => x"08fc0508", + 422 => x"802e8c38", + 423 => x"8c08f805", + 424 => x"08308c08", + 425 => x"f8050c8c", + 426 => x"08f80508", + 427 => x"70800c54", + 428 => x"873d0d8c", + 429 => x"0c048c08", + 430 => x"028c0cfd", + 431 => x"3d0d810b", + 432 => x"8c08fc05", + 433 => x"0c800b8c", + 434 => x"08f8050c", + 435 => x"8c088c05", + 436 => x"088c0888", + 437 => x"050827ac", + 438 => x"388c08fc", + 439 => x"0508802e", + 440 => x"a338800b", + 441 => x"8c088c05", + 442 => x"08249938", + 443 => x"8c088c05", + 444 => x"08108c08", + 445 => x"8c050c8c", + 446 => x"08fc0508", + 447 => x"108c08fc", + 448 => x"050cc939", + 449 => x"8c08fc05", + 450 => x"08802e80", + 451 => x"c9388c08", + 452 => x"8c05088c", + 453 => x"08880508", + 454 => x"26a1388c", + 455 => x"08880508", + 456 => x"8c088c05", + 457 => x"08318c08", + 458 => x"88050c8c", + 459 => x"08f80508", + 460 => x"8c08fc05", + 461 => x"08078c08", + 462 => x"f8050c8c", + 463 => x"08fc0508", + 464 => x"812a8c08", + 465 => x"fc050c8c", + 466 => x"088c0508", + 467 => x"812a8c08", + 468 => x"8c050cff", + 469 => x"af398c08", + 470 => x"90050880", + 471 => x"2e8f388c", + 472 => x"08880508", + 473 => x"708c08f4", + 474 => x"050c518d", + 475 => x"398c08f8", + 476 => x"0508708c", + 477 => x"08f4050c", + 478 => x"518c08f4", + 479 => x"0508800c", + 480 => x"853d0d8c", + 481 => x"0c04fc3d", + 482 => x"0d767079", + 483 => x"7b555555", + 484 => x"558f7227", + 485 => x"8c387275", + 486 => x"07830651", + 487 => x"70802ea7", + 488 => x"38ff1252", + 489 => x"71ff2e98", + 490 => x"38727081", + 491 => x"05543374", + 492 => x"70810556", + 493 => x"34ff1252", + 494 => x"71ff2e09", + 495 => x"8106ea38", + 496 => x"74800c86", + 497 => x"3d0d0474", + 498 => x"51727084", + 499 => x"05540871", + 500 => x"70840553", + 501 => x"0c727084", + 502 => x"05540871", + 503 => x"70840553", + 504 => x"0c727084", + 505 => x"05540871", + 506 => x"70840553", + 507 => x"0c727084", + 508 => x"05540871", + 509 => x"70840553", + 510 => x"0cf01252", + 511 => x"718f26c9", + 512 => x"38837227", + 513 => x"95387270", + 514 => x"84055408", + 515 => x"71708405", + 516 => x"530cfc12", + 517 => x"52718326", + 518 => x"ed387054", + 519 => x"ff8339f7", + 520 => x"3d0d7c70", + 521 => x"525380c8", + 522 => x"3f725480", + 523 => x"085580cc", + 524 => x"d8568157", + 525 => x"80088105", + 526 => x"5a8b3de4", + 527 => x"11595382", + 528 => x"59f41352", + 529 => x"7b881108", + 530 => x"52538183", + 531 => x"3f800830", + 532 => x"70800807", + 533 => x"9f2c8a07", + 534 => x"800c538b", + 535 => x"3d0d04ff", + 536 => x"3d0d7352", + 537 => x"80cd8c08", + 538 => x"51ffb43f", + 539 => x"833d0d04", + 540 => x"fd3d0d75", + 541 => x"70718306", + 542 => x"53555270", + 543 => x"b8387170", + 544 => x"087009f7", + 545 => x"fbfdff12", + 546 => x"0670f884", + 547 => x"82818006", + 548 => x"51515253", + 549 => x"709d3884", + 550 => x"13700870", + 551 => x"09f7fbfd", + 552 => x"ff120670", + 553 => x"f8848281", + 554 => x"80065151", + 555 => x"52537080", + 556 => x"2ee53872", + 557 => x"52713351", + 558 => x"70802e8a", + 559 => x"38811270", + 560 => x"33525270", + 561 => x"f8387174", + 562 => x"31800c85", + 563 => x"3d0d04f2", + 564 => x"3d0d6062", + 565 => x"88110870", + 566 => x"57575f5a", + 567 => x"74802e81", + 568 => x"90388c1a", + 569 => x"2270832a", + 570 => x"81327081", + 571 => x"06515558", + 572 => x"73863890", + 573 => x"1a089138", + 574 => x"795190a2", + 575 => x"3fff5480", + 576 => x"0880ee38", + 577 => x"8c1a2258", + 578 => x"7d085780", + 579 => x"7883ffff", + 580 => x"06700a10", + 581 => x"0a708106", + 582 => x"51565755", + 583 => x"73752e80", + 584 => x"d7387490", + 585 => x"38760884", + 586 => x"18088819", + 587 => x"59565974", + 588 => x"802ef238", + 589 => x"74548880", + 590 => x"75278438", + 591 => x"88805473", + 592 => x"5378529c", + 593 => x"1a0851a4", + 594 => x"1a085473", + 595 => x"2d800b80", + 596 => x"082582e6", + 597 => x"38800819", + 598 => x"75800831", + 599 => x"7f880508", + 600 => x"80083170", + 601 => x"6188050c", + 602 => x"56565973", + 603 => x"ffb43880", + 604 => x"5473800c", + 605 => x"903d0d04", + 606 => x"75813270", + 607 => x"81067641", + 608 => x"51547380", + 609 => x"2e81c138", + 610 => x"74903876", + 611 => x"08841808", + 612 => x"88195956", + 613 => x"5974802e", + 614 => x"f238881a", + 615 => x"087883ff", + 616 => x"ff067089", + 617 => x"2a708106", + 618 => x"51565956", + 619 => x"73802e82", + 620 => x"fa387575", + 621 => x"278d3877", + 622 => x"872a7081", + 623 => x"06515473", + 624 => x"82b53874", + 625 => x"76278338", + 626 => x"74567553", + 627 => x"78527908", + 628 => x"5185823f", + 629 => x"881a0876", + 630 => x"31881b0c", + 631 => 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x"00000000", + 2584 => x"00000000", + 2585 => x"00000000", + 2586 => x"00000000", + 2587 => x"00000000", + 2588 => x"00000000", + 2589 => x"00000000", + 2590 => x"00000000", + 2591 => x"00000000", + 2592 => x"00000000", + 2593 => x"00000000", + 2594 => x"00000000", + 2595 => x"00000000", + 2596 => x"00000000", + 2597 => x"00000000", + 2598 => x"00000000", + 2599 => x"00000000", + 2600 => x"00000000", + 2601 => x"00000000", + 2602 => x"00000000", + 2603 => x"00000000", + 2604 => x"00000000", + 2605 => x"00000000", + 2606 => x"00000000", + 2607 => x"00000000", + 2608 => x"00000000", + 2609 => x"00000000", + 2610 => x"00000000", + 2611 => x"00000000", + 2612 => x"00000000", + 2613 => x"00000000", + 2614 => x"00000000", + 2615 => x"00000000", + 2616 => x"00000000", + 2617 => x"00000000", + 2618 => x"00000000", + 2619 => x"00000000", + 2620 => x"00000000", + 2621 => x"00000000", + 2622 => x"00000000", + 2623 => x"00000000", + 2624 => x"00000000", + 2625 => x"00000000", + 2626 => x"00000000", + 2627 => x"00000000", + 2628 => x"00000000", + 2629 => x"00000000", + 2630 => x"00000000", + 2631 => x"00000000", + 2632 => x"00000000", + 2633 => x"00000000", + 2634 => x"00000000", + 2635 => x"00000000", + 2636 => x"00000000", + 2637 => x"00000000", + 2638 => x"00000000", + 2639 => x"00000000", + 2640 => x"00000000", + 2641 => x"00000000", + 2642 => x"00000000", + 2643 => x"00000000", + 2644 => x"00000000", + 2645 => x"00000000", + 2646 => x"00000000", + 2647 => x"00000000", + 2648 => x"00000000", + 2649 => x"00000000", + 2650 => x"00000000", + 2651 => x"00000000", + 2652 => x"00000000", + 2653 => x"00000000", + 2654 => x"00000000", + 2655 => x"00000000", + 2656 => x"00000000", + 2657 => x"00000000", + 2658 => x"00000000", + 2659 => x"00000000", + 2660 => x"00000000", + 2661 => x"00000000", + 2662 => x"00000000", + 2663 => x"00000000", + 2664 => x"00000000", + 2665 => x"00000000", + 2666 => x"00000000", + 2667 => x"00000000", + 2668 => x"00000000", + 2669 => x"00000000", + 2670 => x"00000000", + 2671 => x"00000000", + 2672 => x"00000000", + 2673 => x"00000000", + 2674 => x"00000000", + 2675 => x"00000000", + 2676 => x"00000000", + 2677 => x"00000000", + 2678 => x"00000000", + 2679 => x"00000000", + 2680 => x"00000000", + 2681 => x"00000000", + 2682 => x"00000000", + 2683 => x"00000000", + 2684 => x"00000000", + 2685 => x"00000000", + 2686 => x"00000000", + 2687 => x"00000000", + 2688 => x"00000000", + 2689 => x"00000000", + 2690 => x"00000000", + 2691 => x"00000000", + 2692 => x"00000000", + 2693 => x"00000000", + 2694 => x"00000000", + 2695 => x"00000000", + 2696 => x"00000000", + 2697 => x"00000000", + 2698 => x"00000000", + 2699 => x"00000000", + 2700 => x"00000000", + 2701 => x"00000000", + 2702 => x"00000000", + 2703 => x"ffffffff", + 2704 => x"00000000", + 2705 => x"00020000", + 2706 => x"00000000", + 2707 => x"00000000", + 2708 => x"00002a48", + 2709 => x"00002a48", + 2710 => x"00002a50", + 2711 => x"00002a50", + 2712 => x"00002a58", + 2713 => x"00002a58", + 2714 => x"00002a60", + 2715 => x"00002a60", + 2716 => x"00002a68", + 2717 => x"00002a68", + 2718 => x"00002a70", + 2719 => x"00002a70", + 2720 => x"00002a78", + 2721 => x"00002a78", + 2722 => x"00002a80", + 2723 => x"00002a80", + 2724 => x"00002a88", + 2725 => x"00002a88", + 2726 => x"00002a90", + 2727 => x"00002a90", + 2728 => x"00002a98", + 2729 => x"00002a98", + 2730 => x"00002aa0", + 2731 => x"00002aa0", + 2732 => x"00002aa8", + 2733 => x"00002aa8", + 2734 => x"00002ab0", + 2735 => x"00002ab0", + 2736 => x"00002ab8", + 2737 => x"00002ab8", + 2738 => x"00002ac0", + 2739 => x"00002ac0", + 2740 => x"00002ac8", + 2741 => x"00002ac8", + 2742 => x"00002ad0", + 2743 => x"00002ad0", + 2744 => x"00002ad8", + 2745 => x"00002ad8", + 2746 => x"00002ae0", + 2747 => x"00002ae0", + 2748 => x"00002ae8", + 2749 => x"00002ae8", + 2750 => x"00002af0", + 2751 => x"00002af0", + 2752 => x"00002af8", + 2753 => x"00002af8", + 2754 => x"00002b00", + 2755 => x"00002b00", + 2756 => x"00002b08", + 2757 => x"00002b08", + 2758 => x"00002b10", + 2759 => x"00002b10", + 2760 => x"00002b18", + 2761 => x"00002b18", + 2762 => x"00002b20", + 2763 => x"00002b20", + 2764 => x"00002b28", + 2765 => x"00002b28", + 2766 => x"00002b30", + 2767 => x"00002b30", + 2768 => x"00002b38", + 2769 => x"00002b38", + 2770 => x"00002b40", + 2771 => x"00002b40", + 2772 => x"00002b48", + 2773 => x"00002b48", + 2774 => x"00002b50", + 2775 => x"00002b50", + 2776 => x"00002b58", + 2777 => x"00002b58", + 2778 => x"00002b60", + 2779 => x"00002b60", + 2780 => x"00002b68", + 2781 => x"00002b68", + 2782 => x"00002b70", + 2783 => x"00002b70", + 2784 => x"00002b78", + 2785 => x"00002b78", + 2786 => x"00002b80", + 2787 => x"00002b80", + 2788 => x"00002b88", + 2789 => x"00002b88", + 2790 => x"00002b90", + 2791 => x"00002b90", + 2792 => x"00002b98", + 2793 => x"00002b98", + 2794 => x"00002ba0", + 2795 => x"00002ba0", + 2796 => x"00002ba8", + 2797 => x"00002ba8", + 2798 => x"00002bb0", + 2799 => x"00002bb0", + 2800 => x"00002bb8", + 2801 => x"00002bb8", + 2802 => x"00002bc0", + 2803 => x"00002bc0", + 2804 => x"00002bc8", + 2805 => x"00002bc8", + 2806 => x"00002bd0", + 2807 => x"00002bd0", + 2808 => x"00002bd8", + 2809 => x"00002bd8", + 2810 => x"00002be0", + 2811 => x"00002be0", + 2812 => x"00002be8", + 2813 => x"00002be8", + 2814 => x"00002bf0", + 2815 => x"00002bf0", + 2816 => x"00002bf8", + 2817 => x"00002bf8", + 2818 => x"00002c00", + 2819 => x"00002c00", + 2820 => x"00002c08", + 2821 => x"00002c08", + 2822 => x"00002c10", + 2823 => x"00002c10", + 2824 => x"00002c18", + 2825 => x"00002c18", + 2826 => x"00002c20", + 2827 => x"00002c20", + 2828 => x"00002c28", + 2829 => x"00002c28", + 2830 => x"00002c30", + 2831 => x"00002c30", + 2832 => x"00002c38", + 2833 => x"00002c38", + 2834 => x"00002c40", + 2835 => x"00002c40", + 2836 => x"00002c48", + 2837 => x"00002c48", + 2838 => x"00002c50", + 2839 => x"00002c50", + 2840 => x"00002c58", + 2841 => x"00002c58", + 2842 => x"00002c60", + 2843 => x"00002c60", + 2844 => x"00002c68", + 2845 => x"00002c68", + 2846 => x"00002c70", + 2847 => x"00002c70", + 2848 => x"00002c78", + 2849 => x"00002c78", + 2850 => x"00002c80", + 2851 => x"00002c80", + 2852 => x"00002c88", + 2853 => x"00002c88", + 2854 => x"00002c90", + 2855 => x"00002c90", + 2856 => x"00002c98", + 2857 => x"00002c98", + 2858 => x"00002ca0", + 2859 => x"00002ca0", + 2860 => x"00002ca8", + 2861 => x"00002ca8", + 2862 => x"00002cb0", + 2863 => x"00002cb0", + 2864 => x"00002cb8", + 2865 => x"00002cb8", + 2866 => x"00002cc0", + 2867 => x"00002cc0", + 2868 => x"00002cc8", + 2869 => x"00002cc8", + 2870 => x"00002cd0", + 2871 => x"00002cd0", + 2872 => x"00002cd8", + 2873 => x"00002cd8", + 2874 => x"00002ce0", + 2875 => x"00002ce0", + 2876 => x"00002ce8", + 2877 => x"00002ce8", + 2878 => x"00002cf0", + 2879 => x"00002cf0", + 2880 => x"00002cf8", + 2881 => x"00002cf8", + 2882 => x"00002d00", + 2883 => x"00002d00", + 2884 => x"00002d08", + 2885 => x"00002d08", + 2886 => x"00002d10", + 2887 => x"00002d10", + 2888 => x"00002d18", + 2889 => x"00002d18", + 2890 => x"00002d20", + 2891 => x"00002d20", + 2892 => x"00002d28", + 2893 => x"00002d28", + 2894 => x"00002d30", + 2895 => x"00002d30", + 2896 => x"00002d38", + 2897 => x"00002d38", + 2898 => x"00002d40", + 2899 => x"00002d40", + 2900 => x"00002d48", + 2901 => x"00002d48", + 2902 => x"00002d50", + 2903 => x"00002d50", + 2904 => x"00002d58", + 2905 => x"00002d58", + 2906 => x"00002d60", + 2907 => x"00002d60", + 2908 => x"00002d68", + 2909 => x"00002d68", + 2910 => x"00002d70", + 2911 => x"00002d70", + 2912 => x"00002d78", + 2913 => x"00002d78", + 2914 => x"00002d80", + 2915 => x"00002d80", + 2916 => x"00002d88", + 2917 => x"00002d88", + 2918 => x"00002d90", + 2919 => x"00002d90", + 2920 => x"00002d98", + 2921 => x"00002d98", + 2922 => x"00002da0", + 2923 => x"00002da0", + 2924 => x"00002da8", + 2925 => x"00002da8", + 2926 => x"00002db0", + 2927 => x"00002db0", + 2928 => x"00002db8", + 2929 => x"00002db8", + 2930 => x"00002dc0", + 2931 => x"00002dc0", + 2932 => x"00002dc8", + 2933 => x"00002dc8", + 2934 => x"00002dd0", + 2935 => x"00002dd0", + 2936 => x"00002dd8", + 2937 => x"00002dd8", + 2938 => x"00002de0", + 2939 => x"00002de0", + 2940 => x"00002de8", + 2941 => x"00002de8", + 2942 => x"00002df0", + 2943 => x"00002df0", + 2944 => x"00002df8", + 2945 => x"00002df8", + 2946 => x"00002e00", + 2947 => x"00002e00", + 2948 => x"00002e08", + 2949 => x"00002e08", + 2950 => x"00002e10", + 2951 => x"00002e10", + 2952 => x"00002e18", + 2953 => x"00002e18", + 2954 => x"00002e20", + 2955 => x"00002e20", + 2956 => x"00002e28", + 2957 => x"00002e28", + 2958 => x"00002e30", + 2959 => x"00002e30", + 2960 => x"00002e38", + 2961 => x"00002e38", + 2962 => x"00002e40", + 2963 => x"00002e40", + 2964 => x"00002660", + 2965 => x"ffffffff", + 2966 => x"00000000", + 2967 => x"ffffffff", + 2968 => x"00000000", + 2969 => x"00000000", + +others => x"00000000" +); +begin + do_port_a: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then + report "DualPortRAM write collision" severity failure; + end if; + iaddr:=to_integer(a_addr_i); + if a_we_i='1' then + ram(iaddr):=a_write_i; + a_read_o <= a_write_i; + else + a_read_o <= ram(iaddr); + end if; + end if; + end process do_port_a; + + do_port_b: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + iaddr:=to_integer(b_addr_i); + if b_we_i='1' then + ram(iaddr):=b_write_i; + b_read_o <= b_write_i; + else + b_read_o <= ram(iaddr); + end if; + end if; + end process do_port_b; +end architecture DualPort_Arch; -- Entity: DualPortRAM diff --git a/zpu/hdl/zealot/roms/rom_pkg.vhdl b/zpu/hdl/zealot/roms/rom_pkg.vhdl new file mode 100644 index 0000000..c5a4161 --- /dev/null +++ b/zpu/hdl/zealot/roms/rom_pkg.vhdl @@ -0,0 +1,80 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU memories package ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a package with the memories used for the ZPU core. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: zpu_memory (Package) ---- +---- File name: rom_pkg.vhdl (template used) ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package zpu_memory is + component DualPortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + -- Port A + a_we_i : in std_logic; + a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + a_write_i : in unsigned(WORD_SIZE-1 downto 0); + a_read_o : out unsigned(WORD_SIZE-1 downto 0); + -- Port B + b_we_i : in std_logic; + b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + b_write_i : in unsigned(WORD_SIZE-1 downto 0); + b_read_o : out unsigned(WORD_SIZE-1 downto 0)); + end component DualPortRAM; + + component SinglePortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + we_i : in std_logic; + re_i : in std_logic; + addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + write_i : in unsigned(WORD_SIZE-1 downto 0); + read_o : out unsigned(WORD_SIZE-1 downto 0); + busy_o : out std_logic); + end component SinglePortRAM; +end package zpu_memory; diff --git a/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl new file mode 100644 index 0000000..8bdcdd3 --- /dev/null +++ b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------ +---- ---- +---- Testbench for the ZPU Medium connection to the FPGA ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a testbench to simulate the ZPU_Med1 core as used in the ---- +---- dmips_med1.vhdl ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DMIPS_Med1_TB(Behave) (Entity and architecture) ---- +---- File name: dmips_med1_tb.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- zpu.txt_util ---- +---- work.zpu_memory ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: N/A ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; +use zpu.txt_util.all; + +library work; +use work.zpu_memory.all; + +entity DMIPS_Med1_TB is +end entity DMIPS_Med1_TB; + +architecture Behave of DMIPS_Med1_TB is + constant WORD_SIZE : natural:=32; -- 32 bits data path + constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB + constant D_CARE_VAL : std_logic:='0'; -- Fill value + constant CLK_FREQ : positive:=50; -- 50 MHz clock + constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period + constant BRATE : positive:=115200; + + component ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Med1; + + signal clk : std_logic; + signal reset : std_logic:='1'; + + signal break : std_logic; + signal dbg : zpu_dbgo_t; -- Debug info + signal rs232_tx : std_logic; + signal rs232_rx : std_logic; +begin + zpu : ZPU_Med1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx, + rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg, + gpio_in => (others => '0')); + + trace_mod : Trace + generic map( + ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE, + LOG_FILE => "dmips_med1.log") + port map( + clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0'); + + do_clock: + process + begin + clk <= '0'; + wait for CLK_S_PER; + clk <= '1'; + wait for CLK_S_PER; + if break='1' then + print("* Break asserted, end of test"); + wait; + end if; + end process do_clock; + + do_reset: + process + begin + wait until rising_edge(clk); + reset <= '0'; + end process do_reset; +end architecture Behave; -- Entity: DMIPS_Med1_TB diff --git a/zpu/hdl/zealot/testbenches/small1_tb.vhdl b/zpu/hdl/zealot/testbenches/small1_tb.vhdl new file mode 100644 index 0000000..a77e5bc --- /dev/null +++ b/zpu/hdl/zealot/testbenches/small1_tb.vhdl @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------ +---- ---- +---- Testbench for the ZPU Small connection to the FPGA ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a testbench to simulate the ZPU_Small1 core as used in the ---- +---- *_small1.vhdl ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Small1_TB(Behave) (Entity and architecture) ---- +---- File name: small1_tb.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- zpu.txt_util ---- +---- work.zpu_memory ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: N/A ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; +use zpu.txt_util.all; + +library work; +use work.zpu_memory.all; + +entity Small1_TB is +end entity Small1_TB; + +architecture Behave of Small1_TB is + constant WORD_SIZE : natural:=32; -- 32 bits data path + constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB + constant D_CARE_VAL : std_logic:='0'; -- Fill value + constant CLK_FREQ : positive:=50; -- 50 MHz clock + constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period + constant BRATE : positive:=115200; + + component ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Small1; + + signal clk : std_logic; + signal reset : std_logic:='1'; + + signal break : std_logic; + signal dbg : zpu_dbgo_t; -- Debug info + signal rs232_tx : std_logic; + signal rs232_rx : std_logic; +begin + zpu : ZPU_Small1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx, + rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg, + gpio_in => (others => '0')); + + trace_mod : Trace + generic map( + ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE, + LOG_FILE => "small1_trace.log") + port map( + clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0'); + + do_clock: + process + begin + clk <= '0'; + wait for CLK_S_PER; + clk <= '1'; + wait for CLK_S_PER; + if break='1' then + print("* Break asserted, end of test"); + wait; + end if; + end process do_clock; + + do_reset: + process + begin + wait until rising_edge(clk); + reset <= '0'; + end process do_reset; +end architecture Behave; -- Entity: Small1_TB diff --git a/zpu/hdl/zealot/zpu_medium.vhdl b/zpu/hdl/zealot/zpu_medium.vhdl new file mode 100644 index 0000000..47950fe --- /dev/null +++ b/zpu/hdl/zealot/zpu_medium.vhdl @@ -0,0 +1,948 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is the medium size version. ---- +---- Supports external memories. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPUMediumCore(Behave) (Entity and architecture) ---- +---- File name: zpu_medium.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ +-- +-- write_en_o - set to '1' for a single cycle to send off a write request. +-- data_o is valid only while write_en_o='1'. +-- read_en_o - set to '1' for a single cycle to send off a read request. +-- mem_busy_i - It is illegal to send off a read/write request when +-- mem_busy_i='1'. +-- Set to '0' when data_i is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after read/ +-- write_en_o is '1'. +-- addr_o - address for read/write request +-- data_i - read data. Valid only on the cycle after mem_busy_i='0' +-- after read_en_o='1' for a single cycle. +-- data_o - data to write +-- break_o - set to '1' when CPU hits break instruction + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity ZPUMediumCore is + generic( + WORD_SIZE : integer:=32; -- 16/32 (2**wordPower) + ADDR_W : integer:=16; -- Total address space width (incl. I/O) + MEM_W : integer:=15; -- Memory (prog+data+stack) width + D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits + MULT_PIPE : boolean:=false; -- Pipeline multiplication + BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=) + ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd + ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub + ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel + ENA_LSHR : boolean:=true; -- lshiftright + ENA_IDLE : boolean:=false; -- Enable the enable_i input + FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states + port( + clk_i : in std_logic; -- CPU Clock + reset_i : in std_logic; -- Sync Reset + enable_i : in std_logic; -- Hold the CPU (after reset) + break_o : out std_logic; -- Break instruction executed + dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) + -- Memory interface + mem_busy_i : in std_logic; -- Memory is busy + data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem + data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem + addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address + write_en_o : out std_logic; -- Memory write enable + read_en_o : out std_logic); -- Memory read enable +end entity ZPUMediumCore; + +architecture Behave of ZPUMediumCore is + constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes + constant WORD_BYTES : integer:=WORD_SIZE/OPCODE_W; + constant MAX_ADDR_BIT : integer:=ADDR_W-2; + -- Stack Pointer initial value: BRAM size-8 + constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W); + constant SP_START : unsigned(ADDR_W-1 downto BYTE_BITS):= + SP_START_1(ADDR_W-1 downto BYTE_BITS); + + -- Update [SP+1]. We hold it in b_r, this writes the value to memory. + procedure FlushB(signal we : out std_logic; + signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS); + signal inc_sp : in unsigned(ADDR_W-1 downto BYTE_BITS); + signal data : out unsigned(WORD_SIZE-1 downto 0); + signal b : in unsigned(WORD_SIZE-1 downto 0)) is + begin + we <= '1'; + addr <= inc_sp; + data <= b; + end procedure FlushB; + + -- Do a simple stack push, it is performed in the internal cache registers, + -- not in the real memory. + procedure Push(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS); + signal a : in unsigned(WORD_SIZE-1 downto 0); + signal b : out unsigned(WORD_SIZE-1 downto 0)) is + begin + b <= a; -- Update cache [SP+1]=[SP] + sp <= sp-1; + end procedure Push; + + -- Do a simple stack pop, it is performed in the internal cache registers, + -- not in the real memory. + procedure Pop(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS); + signal a : out unsigned(WORD_SIZE-1 downto 0); + signal b : in unsigned(WORD_SIZE-1 downto 0)) is + begin + a <= b; -- Update cache [SP]=[SP+1] + sp <= sp+1; + end procedure Pop; + + -- Expand a PC value to WORD_SIZE + function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is + variable nv : unsigned(WORD_SIZE-1 downto 0); + begin + nv:=(others => '0'); + nv(ADDR_W-1 downto 0):=v; + return nv; + end function ExpandPC; + + -- Program counter + signal pc_r : unsigned(ADDR_W-1 downto 0):=(others => '0'); + -- Stack pointer + signal sp_r : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START; + -- SP+1, SP+2 and SP-1 are very used, these are shortcuts + signal inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS); + signal inc_inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS); + -- a_r is a cache for the top of the stack [SP] + -- Note: as this is a stack CPU this is a very important register. + signal a_r : unsigned(WORD_SIZE-1 downto 0); + -- b_r is a cache for the next value in the stack [SP+1] + signal b_r : unsigned(WORD_SIZE-1 downto 0); + signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + signal mult_res1_r : unsigned(WORD_SIZE-1 downto 0); + signal mult_res2_r : unsigned(WORD_SIZE-1 downto 0); + signal mult_res3_r : unsigned(WORD_SIZE-1 downto 0); + signal mult_a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + signal mult_b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + signal idim_r : std_logic; + signal write_en_r : std_logic; + signal read_en_r : std_logic; + signal addr_r : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0'); + signal fetched_w_r : unsigned(WORD_SIZE-1 downto 0); + + type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2, + st_fetch, st_execute, st_decode, st_decode2, st_resync, + st_store_sp2, st_resync2, st_resync3, st_loadb2, st_storeb2, + st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2, + st_binary_op_res, st_idle); + signal state : state_t:=st_resync; + + -- Go to st_fetch state or just do its work + procedure DoFetch(constant FAST : boolean; + signal state : out state_t; + signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS); + signal pc : in unsigned(ADDR_W-1 downto 0); + signal re : out std_logic; + signal busy : in std_logic) is + begin + if FAST then + -- Equivalent to st_fetch + if busy='0' then + addr <= pc(ADDR_W-1 downto BYTE_BITS); + re <= '1'; + state <= st_decode; + end if; + else + state <= st_fetch; + end if; + end procedure DoFetch; + + -- Perform a "binary operation" (2 operands) + procedure DoBinOp(result : in unsigned(WORD_SIZE-1 downto 0); + signal state : out state_t; + signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS); + signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS); + signal re : out std_logic; + signal dest : out unsigned(WORD_SIZE-1 downto 0); + signal dest_p : out unsigned(WORD_SIZE-1 downto 0); + constant DEPTH : natural) is + begin + if DEPTH=2 then + -- 2 clocks: st_binary_op_res+st_binary_op_res2 + state <= st_binary_op_res; + dest_p <= result; + elsif DEPTH=1 then + -- 1 clock: st_binary_op_res2 + state <= st_binary_op_res2; + dest_p <= result; + else -- 0 clocks + re <= '1'; + addr <= sp+2; + sp <= sp+1; + dest <= result; + state <= st_popped; + end if; + end procedure DoBinOp; + + -- Perform a boolean "binary operation" (2 operands) + procedure DoBinOpBool(result : in boolean; + signal state : out state_t; + signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS); + signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS); + signal re : out std_logic; + signal dest : out unsigned(WORD_SIZE-1 downto 0); + signal dest_p : out unsigned(WORD_SIZE-1 downto 0); + constant DEPTH : natural) is + variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + begin + if result then + res(0):='1'; + end if; + DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH); + end procedure DoBinOpBool; + + type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add, + dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop, + dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load, + dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip, + dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult, + dec_less_than, dec_less_than_or_equal, dec_lshr, + dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add, + dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb, + dec_insn_fetch, dec_pop_down); + signal insn : insn_t; + type insn_array_t is array(0 to WORD_BYTES-1) of insn_t; + signal insns : insn_array_t; + type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0); + signal opcode_r : opcode_array_t; +begin + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + write_en_o <= write_en_r; + read_en_o <= read_en_r; + addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r; + addr_o(BYTE_BITS-1 downto 0) <= (others => '0'); + + -- SP+1 and +2 + inc_sp <= sp_r+1; + inc_inc_sp <= sp_r+2; + + opcode_control: + process (clk_i) + variable topcode : unsigned(OPCODE_W-1 downto 0); + variable ex_opcode : unsigned(OPCODE_W-1 downto 0); + variable sp_offset : unsigned(4 downto 0); + variable tsp_offset : unsigned(4 downto 0); + variable next_pc : unsigned(ADDR_W-1 downto 0); + variable tdecoded : insn_t; + variable tinsns : insn_array_t; + variable mult_res : unsigned(WORD_SIZE*2-1 downto 0); + variable ipc_low : integer range 0 to 3; -- Address inside a word (pc_r) + variable inpc_low : integer range 0 to 3; -- Address inside a word (next_pc) + variable h_bit : integer; + variable l_bit : integer; + variable not_lshr : std_logic:='1'; + begin + if rising_edge(clk_i) then + break_o <= '0'; + if reset_i='1' then + if ENA_IDLE then + state <= st_idle; + else + state <= st_resync; + end if; + sp_r <= SP_START; + pc_r <= (others => '0'); + idim_r <= '0'; + write_en_r <= '0'; + read_en_r <= '0'; + mult_a_r <= (others => '0'); + mult_b_r <= (others => '0'); + dbg_o.b_inst <= '0'; + -- Reseting add_r here makes XST fail to use BRAMs ?! + else -- reset_i='1' + if MULT_PIPE then + -- We must multiply unconditionally to get pipelined multiplication + mult_res:=mult_a_r*mult_b_r; + mult_res1_r <= mult_res(WORD_SIZE-1 downto 0); + mult_res2_r <= mult_res1_r; + mult_res3_r <= mult_res2_r; + mult_a_r <= (others => D_CARE_VAL); + mult_b_r <= (others => D_CARE_VAL); + end if; + + if BINOP_PIPE=2 then + bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit. + end if; + + read_en_r <='0'; + write_en_r <='0'; + -- Allow synthesis tools to load bogus values when we don't + -- care about the address and output data. + addr_r <= (others => D_CARE_VAL); + data_o <= (others => D_CARE_VAL); + + if (write_en_r='1') and (read_en_r='1') then + report "read/write collision" severity failure; + end if; + + ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0)); + sp_offset(4):=not opcode_r(ipc_low)(4); + sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0); + next_pc:=pc_r+1; + + -- Prepare trace snapshot + dbg_o.opcode <= opcode_r(ipc_low); + dbg_o.pc <= resize(pc_r,32); + dbg_o.stk_a <= resize(a_r,32); + dbg_o.stk_b <= resize(b_r,32); + dbg_o.b_inst <= '0'; + dbg_o.sp <= (others => '0'); + dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r; + + case state is + when st_idle => + if enable_i='1' then + state <= st_resync; + end if; + -- Initial state of ZPU, fetch top of stack (A/B) + first instruction + when st_resync => + if mem_busy_i='0' then + addr_r <= sp_r; + read_en_r <= '1'; + state <= st_resync2; + end if; + when st_resync2 => + if mem_busy_i='0' then + a_r <= data_i; + addr_r <= inc_sp; + read_en_r <= '1'; + state <= st_resync3; + end if; + when st_resync3 => + if mem_busy_i='0' then + b_r <= data_i; + addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + state <= st_decode; + end if; + when st_decode => + if mem_busy_i='0' then + -- Here we latch the fetched word to give one full clock + -- cycle to the instruction decoder. This could be removed + -- if using BRAMs and the decoder delay isn't important. + fetched_w_r <= data_i; + state <= st_decode2; + end if; + when st_decode2 => + -- decode 4 instructions in parallel + for i in 0 to WORD_BYTES-1 loop + topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8); + + tsp_offset(4):=not topcode(4); + tsp_offset(3 downto 0):=topcode(3 downto 0); + + opcode_r(i) <= topcode; + if topcode(7 downto 7)=OPCODE_IM then + tdecoded:=dec_im; + elsif topcode(7 downto 5)=OPCODE_STORESP then + if tsp_offset=0 then + -- Special case, we can avoid a write + tdecoded:=dec_pop; + elsif tsp_offset=1 then + -- Special case, collision + tdecoded:=dec_pop_down; + else + tdecoded:=dec_store_sp; + end if; + elsif topcode(7 downto 5)=OPCODE_LOADSP then + if tsp_offset=0 then + tdecoded:=dec_dup; + elsif tsp_offset=1 then + tdecoded:=dec_dup_stk_b; + else + tdecoded:=dec_load_sp; + end if; + elsif topcode(7 downto 5)=OPCODE_EMULATE then + tdecoded:=dec_emulate; + if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then + tdecoded:=dec_neq_branch; + elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then + tdecoded:=dec_eq; + elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then + tdecoded:=dec_loadb; + elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then + tdecoded:=dec_push_sp_add; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then + tdecoded:=dec_less_than; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then + tdecoded:=dec_u_less_than; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then + tdecoded:=dec_mult; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then + tdecoded:=dec_storeb; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then + tdecoded:=dec_call_pc_rel; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then + tdecoded:=dec_sub; + elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then + tdecoded:=dec_less_than_or_equal; + elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then + tdecoded:=dec_u_less_than_or_equal; + elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then + tdecoded:=dec_call; + elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then + tdecoded:=dec_pop_pc_rel; + elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then + tdecoded:=dec_lshr; + end if; + elsif topcode(7 downto 4)=OPCODE_ADDSP then + if tsp_offset=0 then + tdecoded:=dec_shift; + elsif tsp_offset=1 then + tdecoded:=dec_add_top; + else + tdecoded:=dec_add_sp; + end if; + else -- OPCODE_SHORT + case topcode(3 downto 0) is + when OPCODE_BREAK => + tdecoded:=dec_break; + when OPCODE_PUSHSP => + tdecoded:=dec_push_sp; + when OPCODE_POPPC => + tdecoded:=dec_pop_pc; + when OPCODE_ADD => + tdecoded:=dec_add; + when OPCODE_OR => + tdecoded:=dec_or; + when OPCODE_AND => + tdecoded:=dec_and; + when OPCODE_LOAD => + tdecoded:=dec_load; + when OPCODE_NOT => + tdecoded:=dec_not; + when OPCODE_FLIP => + tdecoded:=dec_flip; + when OPCODE_STORE => + tdecoded:=dec_store; + when OPCODE_POPSP => + tdecoded:=dec_pop_sp; + when others => -- OPCODE_NOP and others + tdecoded:=dec_nop; + end case; + end if; + tinsns(i):=tdecoded; + end loop; + + insn <= tinsns(ipc_low); + -- once we wrap, we need to fetch + tinsns(0):=dec_insn_fetch; + insns <= tinsns; + state <= st_execute; + + -- Each instruction must: + -- + -- 1. increase pc_r if applicable + -- 2. set next state if applicable + -- 3. do it's operation + when st_execute => + -- Some shortcut to make the code readable: + inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0)); + ex_opcode:=opcode_r(ipc_low); + insn <= insns(inpc_low); + -- Defaults used by most instructions + if insn/=dec_insn_fetch and insn/=dec_im then + dbg_o.b_inst <= '1'; + idim_r <= '0'; + end if; + case insn is + when dec_insn_fetch => + -- Not a real instruction, fetch new instructions + DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i); + when dec_im => + -- Push(immediate value), IDIM=1 + -- if IDIM=0 Push(signed(opcode & 0x7F)) else + -- Push((Pop()<<7)|(opcode&0x7F)) + if mem_busy_i='0' then + dbg_o.b_inst <= '1'; + idim_r <= '1'; + pc_r <= pc_r+1; + if idim_r='1' then + -- We already started an IM sequence + -- Shift left 7 bits + a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0); + -- Put the new value + a_r(6 downto 0) <= ex_opcode(6 downto 0); + else + -- First IM, push the value sign extended + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE)); + Push(sp_r,a_r,b_r); + end if; + end if; + when dec_store_sp => + -- [SP+Offset]=Pop() + if mem_busy_i='0' then + write_en_r <= '1'; + addr_r <= sp_r+sp_offset; + data_o <= a_r; + Pop(sp_r,a_r,b_r); + -- We need to fetch B + state <= st_store_sp2; + end if; + when dec_load_sp => + -- Push([SP+Offset]) + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + Push(sp_r,a_r,b_r); + -- We are flushing B cache, so we need more time to + -- read the value. + state <= st_load_sp2; + end if; + when dec_emulate => + -- Push(PC+1), PC=Opcode[4:0]*32 + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + state <= st_fetch; + a_r <= ExpandPC(pc_r+1); + Push(sp_r,a_r,b_r); + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc_r <= (others => '0'); + pc_r(9 downto 5) <= ex_opcode(4 downto 0); + end if; + when dec_call_pc_rel => + -- t=Pop(), Push(PC+1), PC=PC+t + if mem_busy_i='0' and ENA_LEVEL1 then + state <= st_fetch; + a_r <= ExpandPC(pc_r+1); + pc_r <= pc_r+a_r(ADDR_W-1 downto 0); + end if; + when dec_call => + -- t=Pop(), Push(PC+1), PC=t + if mem_busy_i='0' and ENA_LEVEL2 then + state <= st_fetch; + a_r <= ExpandPC(pc_r+1); + pc_r <= a_r(ADDR_W-1 downto 0); + end if; + when dec_add_sp => + -- Push(Pop()+[SP+Offset]) + if mem_busy_i='0' then + -- Read SP+Offset + state <= st_add_sp2; + read_en_r <= '1'; + addr_r <= sp_r+sp_offset; + pc_r <= pc_r+1; + end if; + when dec_push_sp => + -- Push(SP) + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + pc_r <= pc_r+1; + a_r <= (others => '0'); + a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r; + Push(sp_r,a_r,b_r); + end if; + when dec_pop_pc => + -- PC=Pop() (return) + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + state <= st_resync; + pc_r <= a_r(ADDR_W-1 downto 0); + sp_r <= inc_sp; + end if; + when dec_pop_pc_rel => + -- PC=PC+Pop() + if mem_busy_i='0' and ENA_LEVEL2 then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + state <= st_resync; + pc_r <= a_r(ADDR_W-1 downto 0)+pc_r; + sp_r <= inc_sp; + end if; + when dec_add => + -- Push(Pop()+Pop()) [A=A+B, SP++, update B] + if mem_busy_i='0' then + state <= st_popped; + a_r <= a_r+b_r; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + end if; + when dec_sub => + -- a=Pop(), b=Pop(), Push(b-a) + if mem_busy_i='0' and ENA_LEVEL1 then + DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r, + a_r,bin_op_res1_r,BINOP_PIPE); + end if; + when dec_pop => + -- Pop() + if mem_busy_i='0' then + state <= st_popped; + addr_r <= inc_inc_sp; + read_en_r <= '1'; + Pop(sp_r,a_r,b_r); + end if; + when dec_pop_down => + -- t=Pop(), Pop(), Push(t) + if mem_busy_i='0' then + -- PopDown leaves top of stack unchanged + state <= st_popped; + addr_r <= inc_inc_sp; + read_en_r <= '1'; + sp_r <= inc_sp; + end if; + when dec_or => + -- Push(Pop() or Pop()) + if mem_busy_i='0' then + state <= st_popped; + a_r <= a_r or b_r; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + end if; + when dec_and => + -- Push(Pop() and Pop()) + if mem_busy_i='0' then + state <= st_popped; + a_r <= a_r and b_r; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + end if; + when dec_eq => + -- a=Pop(), b=Pop(), Push(a=b ? 1 : 0) + if mem_busy_i='0' and ENA_LEVEL0 then + DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r, + a_r,bin_op_res1_r,BINOP_PIPE); + end if; + when dec_u_less_than => + -- a=Pop(), b=Pop(), Push(a<b ? 1 : 0) + if mem_busy_i='0' and ENA_LEVEL1 then + DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r, + a_r,bin_op_res1_r,BINOP_PIPE); + end if; + when dec_u_less_than_or_equal => + -- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0) + if mem_busy_i='0' and ENA_LEVEL2 then + DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r, + a_r,bin_op_res1_r,BINOP_PIPE); + end if; + when dec_less_than => + -- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0) + if mem_busy_i='0' and ENA_LEVEL1 then + DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r, + addr_r,read_en_r,a_r,bin_op_res1_r, + BINOP_PIPE); + end if; + when dec_less_than_or_equal => + -- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0) + if mem_busy_i='0' and ENA_LEVEL2 then + DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r, + addr_r,read_en_r,a_r,bin_op_res1_r, + BINOP_PIPE); + end if; + when dec_load => + -- Push([Pop()]) + if mem_busy_i='0' then + state <= st_load2; + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + pc_r <= pc_r+1; + end if; + when dec_dup => + -- t=Pop(), Push(t), Push(t) + if mem_busy_i='0' then + pc_r <= pc_r+1; + -- A is dupped, no change + Push(sp_r,a_r,b_r); + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + end if; + when dec_dup_stk_b => + -- Pop(), t=Pop(), Push(t), Push(t), Push(t) + if mem_busy_i='0' then + pc_r <= pc_r+1; + a_r <= b_r; + -- B goes to A + Push(sp_r,a_r,b_r); + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + end if; + when dec_store => + -- a=Pop(), b=Pop(), [a]=b + if mem_busy_i='0' then + state <= st_resync; + pc_r <= pc_r+1; + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + data_o <= b_r; + write_en_r <= '1'; + sp_r <= inc_inc_sp; + end if; + when dec_pop_sp => + -- SP=Pop() + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + state <= st_resync; + pc_r <= pc_r+1; + sp_r <= a_r(ADDR_W-1 downto BYTE_BITS); + end if; + when dec_nop => + pc_r <= pc_r+1; + when dec_not => + -- Push(not(Pop())) + pc_r <= pc_r+1; + a_r <= not a_r; + when dec_flip => + -- Push(flip(Pop())) + pc_r <= pc_r+1; + for i in 0 to WORD_SIZE-1 loop + a_r(i) <= a_r(WORD_SIZE-1-i); + end loop; + when dec_add_top => + -- a=Pop(), b=Pop(), Push(b), Push(a+b) + pc_r <= pc_r+1; + a_r <= a_r+b_r; + when dec_shift => + -- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)] + pc_r <= pc_r+1; + a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0); + a_r(0) <= '0'; + when dec_push_sp_add => + -- Push(Pop()+SP) + if ENA_LEVEL0 then + pc_r <= pc_r+1; + a_r <= (others => '0'); + a_r(ADDR_W-1 downto BYTE_BITS) <= + a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r; + end if; + when dec_neq_branch => + -- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a + -- Branches are almost always taken as they form loops + if ENA_LEVEL0 then + sp_r <= inc_inc_sp; + -- Need to fetch stack again. + state <= st_resync; + if b_r/=0 then + pc_r <= a_r(ADDR_W-1 downto 0)+pc_r; + else + pc_r <= pc_r+1; + end if; + end if; + when dec_mult => + -- Push(Pop()*Pop()) + if ENA_LEVEL1 then + if MULT_PIPE then + mult_a_r <= a_r; + mult_b_r <= b_r; + state <= st_mult2; + else + mult_res:=a_r*b_r; + mult_res1_r <= mult_res(WORD_SIZE-1 downto 0); + state <= st_mult5; + end if; + end if; + when dec_break => + -- Assert the break_o signal + --report "Break instruction encountered" severity failure; + break_o <= '1'; + pc_r <= pc_r+1; + when dec_loadb => + -- Push([Pop()] & 0xFF) (byte address) + if mem_busy_i='0' and ENA_LEVEL0 then + state <= st_loadb2; + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + pc_r <= pc_r+1; + end if; + when dec_storeb => + -- [Pop()]=Pop() & 0xFF (byte address) + if mem_busy_i='0' and ENA_LEVEL1 then + state <= st_storeb2; + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + pc_r <= pc_r+1; + end if; + when dec_lshr => + -- a=Pop(), b=Pop(), Push(b>>(a&0x3F)) + if ENA_LSHR then + -- This instruction takes more than one cycle. + -- We must avoid duplications in the trace log. + dbg_o.b_inst <= not_lshr; + not_lshr:='0'; + if a_r(5 downto 0)=0 then -- Only 6 bits used + -- No more shifts + if mem_busy_i='0' then + state <= st_popped; + a_r <= b_r; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + not_lshr:='1'; + end if; + else -- More shifts needed + b_r <= "0"&b_r(WORD_SIZE-1 downto 1); + a_r(5 downto 0) <= a_r(5 downto 0)-1; + insn <= insn; + end if; + end if; + when others => + -- Undefined behavior, we shouldn't get here. + -- It only helps synthesis tools. + sp_r <= (others => D_CARE_VAL); + report "Illegal decode instruction?!" severity failure; + --break_o <= '1'; + end case; + -- The followup of operations that takes more than one execution clock + when st_store_sp2 => + if mem_busy_i='0' then + addr_r <= inc_sp; + read_en_r <= '1'; + state <= st_popped; + end if; + when st_load_sp2 => + if mem_busy_i='0' then + state <= st_load_sp3; + -- Now we can read SP+Offset (SP already decremented) + read_en_r <= '1'; + addr_r <= sp_r+sp_offset+1; + end if; + when st_load_sp3 => + if mem_busy_i='0' then + -- Note: We can't increment PC in the decode stage + -- because it will modify sp_offset. + pc_r <= pc_r+1; + -- Finally we have the result in A + state <= st_execute; + a_r <= data_i; + end if; + when st_add_sp2 => + if mem_busy_i='0' then + state <= st_execute; + a_r <= a_r+data_i; + end if; + when st_load2 => + if mem_busy_i='0' then + a_r <= data_i; + state <= st_execute; + end if; + when st_loadb2 => + if mem_busy_i='0' then + a_r <= (others => '0'); + -- Select the source bits using the less significant bits (byte address) + h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1; + l_bit:=h_bit-7; + a_r(7 downto 0) <= data_i(h_bit downto l_bit); + state <= st_execute; + end if; + when st_storeb2 => + if mem_busy_i='0' then + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + data_o <= data_i; + -- Select the source bits using the less significant bits (byte address) + h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1; + l_bit:=h_bit-7; + data_o(h_bit downto l_bit) <= b_r(7 downto 0); + write_en_r <= '1'; + sp_r <= inc_inc_sp; + state <= st_resync; + end if; + when st_fetch => + if mem_busy_i='0' then + addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + state <= st_decode; + end if; + -- The following states can be used to leave cycles free for + -- tools that can automagically decompose the multiplication + -- in various stages. Xilinx tools can do it to increase the + -- multipliers performance. + when st_mult2 => + state <= st_mult3; + when st_mult3 => + state <= st_mult4; + when st_mult4 => + state <= st_mult5; + when st_mult5 => + if mem_busy_i='0' then + if MULT_PIPE then + a_r <= mult_res3_r; + else + a_r <= mult_res1_r; + end if; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + state <= st_popped; + end if; + when st_binary_op_res => + -- BINOP_PIPE=2 + state <= st_binary_op_res2; + when st_binary_op_res2 => + -- BINOP_PIPE>=1 + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + state <= st_popped; + if BINOP_PIPE=2 then + a_r <= bin_op_res2_r; + else -- 1 + a_r <= bin_op_res1_r; + end if; + when st_popped => + if mem_busy_i='0' then + -- Note: Moving this PC++ to the decoder seems to + -- consume more LUTs. + pc_r <= pc_r+1; + b_r <= data_i; + state <= st_execute; + end if; + when others => + -- Undefined behavior, we shouldn't get here. + -- It only helps synthesis tools. + sp_r <= (others => D_CARE_VAL); + report "Illegal state?!" severity failure; + --break_o <= '1'; + end case; -- state + end if; -- else reset_i='1' + end if; -- rising_edge(clk_i) + end process opcode_control; +end architecture Behave; -- Entity: ZPUMediumCore + diff --git a/zpu/hdl/zealot/zpu_pkg.vhdl b/zpu/hdl/zealot/zpu_pkg.vhdl new file mode 100644 index 0000000..915f352 --- /dev/null +++ b/zpu/hdl/zealot/zpu_pkg.vhdl @@ -0,0 +1,292 @@ +------------------------------------------------------------------------------
+---- ----
+---- ZPU Package ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- ZPU is a 32 bits small stack cpu. This is the package. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Øyvind Harboe, oyvind.harboe zylin.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: zpupkg, UART (Package) ----
+---- File name: zpu_medium.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package zpupkg is
+ constant OPCODE_W : integer:=8;
+
+ -- Debug structure, currently only for the trace module
+ type zpu_dbgo_t is record
+ b_inst : std_logic;
+ opcode : unsigned(OPCODE_W-1 downto 0);
+ pc : unsigned(31 downto 0);
+ sp : unsigned(31 downto 0);
+ stk_a : unsigned(31 downto 0);
+ stk_b : unsigned(31 downto 0);
+ end record;
+
+ component Trace is
+ generic(
+ LOG_FILE : string:="trace.txt"; -- Name of the trace file
+ ADDR_W : integer:=16; -- Address width
+ WORD_SIZE : integer:=32); -- 16/32
+ port(
+ clk_i : in std_logic;
+ dbg_i : in zpu_dbgo_t;
+ stop_i : in std_logic;
+ busy_i : in std_logic
+ );
+ end component Trace;
+
+ component ZPUSmallCore is
+ generic(
+ WORD_SIZE : integer:=32; -- Data width 16/32
+ ADDR_W : integer:=16; -- Total address space width (incl. I/O)
+ MEM_W : integer:=15; -- Memory (prog+data+stack) width
+ D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
+ port(
+ clk_i : in std_logic; -- System Clock
+ reset_i : in std_logic; -- Synchronous Reset
+ interrupt_i : in std_logic; -- Interrupt
+ break_o : out std_logic; -- Breakpoint opcode executed
+ dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+ -- BRAM (text, data, bss and stack)
+ a_we_o : out std_logic; -- BRAM A port Write Enable
+ a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
+ a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
+ a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
+ b_we_o : out std_logic; -- BRAM B port Write Enable
+ b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
+ b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
+ b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
+ -- Memory mapped I/O
+ mem_busy_i : in std_logic;
+ data_i : in unsigned(WORD_SIZE-1 downto 0);
+ data_o : out unsigned(WORD_SIZE-1 downto 0);
+ addr_o : out unsigned(ADDR_W-1 downto 0);
+ write_en_o : out std_logic;
+ read_en_o : out std_logic);
+ end component ZPUSmallCore;
+
+ component ZPUMediumCore is
+ generic(
+ WORD_SIZE : integer:=32; -- Data width 16/32
+ ADDR_W : integer:=16; -- Total address space width (incl. I/O)
+ MEM_W : integer:=15; -- Memory (prog+data+stack) width
+ D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
+ MULT_PIPE : boolean:=false; -- Pipeline multiplication
+ BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+ ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
+ ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+ ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+ ENA_LSHR : boolean:=true; -- lshiftright
+ ENA_IDLE : boolean:=false; -- Enable the enable_i input
+ FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
+ port(
+ clk_i : in std_logic; -- CPU Clock
+ reset_i : in std_logic; -- Sync Reset
+ enable_i : in std_logic; -- Hold the CPU (after reset)
+ break_o : out std_logic; -- Break instruction executed
+ dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+ -- Memory interface
+ mem_busy_i : in std_logic; -- Memory is busy
+ data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+ data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+ addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
+ write_en_o : out std_logic; -- Memory write enable
+ read_en_o : out std_logic); -- Memory read enable
+ end component ZPUMediumCore;
+
+ component Timer is
+ port(
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ we_i : in std_logic;
+ data_i : in unsigned(31 downto 0);
+ addr_i : in unsigned(0 downto 0);
+ data_o : out unsigned(31 downto 0));
+ end component Timer;
+
+ component gpio is
+ port(
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ --
+ we_i : in std_logic;
+ data_i : in unsigned(31 downto 0);
+ addr_i : in unsigned( 0 downto 0);
+ data_o : out unsigned(31 downto 0);
+ --
+ port_in : in std_logic_vector(31 downto 0);
+ port_out : out std_logic_vector(31 downto 0);
+ port_dir : out std_logic_vector(31 downto 0)
+ );
+ end component gpio;
+
+
+ component ZPUPhiIO is
+ generic(
+ BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4
+ ENA_LOG : boolean:=true; -- Enable log
+ LOG_FILE : string:="log.txt"); -- Name for the log file
+ port(
+ clk_i : in std_logic; -- System Clock
+ reset_i : in std_logic; -- Synchronous Reset
+ busy_o : out std_logic; -- I/O is busy
+ we_i : in std_logic; -- Write Enable
+ re_i : in std_logic; -- Read Enable
+ data_i : in unsigned(31 downto 0);
+ data_o : out unsigned(31 downto 0);
+ addr_i : in unsigned(2 downto 0); -- Address bits 4-2
+ --
+ rs232_rx_i : in std_logic; -- UART Rx input
+ rs232_tx_o : out std_logic; -- UART Tx output
+ br_clk_i : in std_logic; -- UART base clock (enable)
+ --
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0)
+ );
+ end component ZPUPhiIO;
+
+ -- Opcode decode constants
+ -- Note: these are the basic opcodes, always implemented using hardware.
+ constant OPCODE_IM : unsigned(7 downto 7):="1";
+ constant OPCODE_STORESP : unsigned(7 downto 5):="010";
+ constant OPCODE_LOADSP : unsigned(7 downto 5):="011";
+ constant OPCODE_EMULATE : unsigned(7 downto 5):="001";
+ constant OPCODE_ADDSP : unsigned(7 downto 4):="0001";
+ constant OPCODE_SHORT : unsigned(7 downto 4):="0000";
+
+ constant OPCODE_BREAK : unsigned(3 downto 0):="0000";
+ constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
+ constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010";
+ constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011";
+
+ constant OPCODE_POPPC : unsigned(3 downto 0):="0100";
+ constant OPCODE_ADD : unsigned(3 downto 0):="0101";
+ constant OPCODE_AND : unsigned(3 downto 0):="0110";
+ constant OPCODE_OR : unsigned(3 downto 0):="0111";
+
+ constant OPCODE_LOAD : unsigned(3 downto 0):="1000";
+ constant OPCODE_NOT : unsigned(3 downto 0):="1001";
+ constant OPCODE_FLIP : unsigned(3 downto 0):="1010";
+ constant OPCODE_NOP : unsigned(3 downto 0):="1011";
+
+ constant OPCODE_STORE : unsigned(3 downto 0):="1100";
+ constant OPCODE_POPSP : unsigned(3 downto 0):="1101";
+ constant OPCODE_COMPARE : unsigned(3 downto 0):="1110";
+ constant OPCODE_POPINT : unsigned(3 downto 0):="1111";
+
+ -- The following instructions are emulated in the small version and
+ -- implemented as hardware in the full version.
+ -- The constants correpond to the "emulated" instruction number.
+
+ -- Enabled by the ENA_LEVEL0 generic:
+ constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6);
+ constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6);
+ constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6);
+ constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6);
+ -- Enabled by the ENA_LEVEL1 generic:
+ constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6);
+ constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6);
+ constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6);
+ constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6);
+ constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6);
+ constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6);
+ -- Enabled by the ENA_LEVEL2 generic:
+ constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6);
+ constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
+ constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6);
+ constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6);
+ -- Enabled by the ENA_LSHR generic:
+ constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6);
+ -- The following opcodes are always emulated.
+ constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6);
+ constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6);
+ constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6);
+ constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6);
+ constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6);
+ constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6);
+ constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6);
+ constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6);
+ constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6);
+ constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6);
+ constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6);
+ constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6);
+end package zpupkg;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package UART is
+ ----------------------
+ -- Very simple UART --
+ ----------------------
+ component RxUnit is
+ port(
+ clk_i : in std_logic; -- System clock signal
+ reset_i : in std_logic; -- Reset input (sync)
+ enable_i : in std_logic; -- Enable input (rate*4)
+ read_i : in std_logic; -- Received Byte Read
+ rxd_i : in std_logic; -- RS-232 data input
+ rxav_o : out std_logic; -- Byte available
+ datao_o : out std_logic_vector(7 downto 0)); -- Byte received
+ end component RxUnit;
+
+ component TxUnit is
+ port (
+ clk_i : in std_logic; -- Clock signal
+ reset_i : in std_logic; -- Reset input
+ enable_i : in std_logic; -- Enable input
+ load_i : in std_logic; -- Load input
+ txd_o : out std_logic; -- RS-232 data output
+ busy_o : out std_logic; -- Tx Busy
+ datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
+ end component TxUnit;
+
+ component BRGen is
+ generic(
+ COUNT : integer range 0 to 65535);-- Count revolution
+ port (
+ clk_i : in std_logic; -- Clock
+ reset_i : in std_logic; -- Reset input
+ ce_i : in std_logic; -- Chip Enable
+ o_o : out std_logic); -- Output
+ end component BRGen;
+end package UART;
+
diff --git a/zpu/hdl/zealot/zpu_small.vhdl b/zpu/hdl/zealot/zpu_small.vhdl new file mode 100644 index 0000000..056b924 --- /dev/null +++ b/zpu/hdl/zealot/zpu_small.vhdl @@ -0,0 +1,472 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is the small size version. ---- +---- It doesn't support external memories, needs a dual ported memory. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ---- +---- File name: zpu_small.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity ZPUSmallCore is + generic( + WORD_SIZE : integer:=32; -- Data width 16/32 + ADDR_W : integer:=16; -- Total address space width (incl. I/O) + MEM_W : integer:=15; -- Memory (prog+data+stack) width + D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits + port( + clk_i : in std_logic; -- System Clock + reset_i : in std_logic; -- Synchronous Reset + interrupt_i : in std_logic; -- Interrupt + break_o : out std_logic; -- Breakpoint opcode executed + dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) + -- BRAM (text, data, bss and stack) + a_we_o : out std_logic; -- BRAM A port Write Enable + a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address + a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port + a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port + b_we_o : out std_logic; -- BRAM B port Write Enable + b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address + b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port + b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port + -- Memory mapped I/O + mem_busy_i : in std_logic; + data_i : in unsigned(WORD_SIZE-1 downto 0); + data_o : out unsigned(WORD_SIZE-1 downto 0); + addr_o : out unsigned(ADDR_W-1 downto 0); + write_en_o : out std_logic; + read_en_o : out std_logic); +end entity ZPUSmallCore; + +architecture Behave of ZPUSmallCore is + constant MAX_ADDR_BIT : integer:=ADDR_W-2; + constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes + -- Stack Pointer initial value: BRAM size-8 + constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W); + constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):= + SP_START_1(MAX_ADDR_BIT downto BYTE_BITS); + constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O + + -- Program counter + signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0'); + -- Stack pointer + signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START; + signal idim_r : std_logic:='0'; + + -- BRAM (text, data, bss and stack) + -- a_r is a register for the top of the stack [SP] + -- Note: as this is a stack CPU this is a very important register. + signal a_we_r : std_logic:='0'; + signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0'); + signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + -- b_r is a register for the next value in the stack [SP+1] + -- We also use the B port to fetch instructions. + signal b_we_r : std_logic:='0'; + signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0'); + signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + + -- State machine. + type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or, + st_and, st_store, st_read_io, st_write_io, st_fetch_next, + st_add_sp, st_decode, st_resync); + signal state : state_t:=st_resync; + + -- Decoded Opcode + type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp, + dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add, + dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store, + dec_pop_sp, dec_interrupt); + signal d_opcode_r : decode_t; + signal d_opcode : decode_t; + + signal opcode : unsigned(OPCODE_W-1 downto 0); -- Decoded + signal opcode_r : unsigned(OPCODE_W-1 downto 0); -- Registered + + -- IRQ flag + signal in_irq_r : std_logic:='0'; + -- I/O space address + signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0'); +begin + -- Dual ported memory interface + a_we_o <= a_we_r; + a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS); + a_o <= a_r; + b_we_o <= b_we_r; + b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS); + b_o <= b_r; + + ------------------------- + -- Instruction Decoder -- + ------------------------- + -- Note: We use Port B memory to fetch the opcodes. + decode_control: + process(b_i, pc_r) + variable topcode : unsigned(OPCODE_W-1 downto 0); + begin + -- Select the addressed byte inside the fetched word + case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is + when 0 => + topcode := to_01( b_i(31 downto 24)); + when 1 => + topcode := to_01( b_i(23 downto 16)); + when 2 => + topcode := to_01( b_i(15 downto 8)); + when others => -- 3 + topcode := to_01( b_i(7 downto 0)); + end case; + opcode <= topcode; + + if (topcode(7 downto 7)=OPCODE_IM) then + d_opcode <= dec_im; + elsif (topcode(7 downto 5)=OPCODE_STORESP) then + d_opcode <= dec_store_sp; + elsif (topcode(7 downto 5)=OPCODE_LOADSP) then + d_opcode <= dec_load_sp; + elsif (topcode(7 downto 5)=OPCODE_EMULATE) then + d_opcode <= dec_emulate; + elsif (topcode(7 downto 4)=OPCODE_ADDSP) then + d_opcode <= dec_add_sp; + else -- OPCODE_SHORT + case topcode(3 downto 0) is + when OPCODE_BREAK => + d_opcode <= dec_break; + when OPCODE_PUSHSP => + d_opcode <= dec_push_sp; + when OPCODE_POPPC => + d_opcode <= dec_pop_pc; + when OPCODE_ADD => + d_opcode <= dec_add; + when OPCODE_OR => + d_opcode <= dec_or; + when OPCODE_AND => + d_opcode <= dec_and; + when OPCODE_LOAD => + d_opcode <= dec_load; + when OPCODE_NOT => + d_opcode <= dec_not; + when OPCODE_FLIP => + d_opcode <= dec_flip; + when OPCODE_STORE => + d_opcode <= dec_store; + when OPCODE_POPSP => + d_opcode <= dec_pop_sp; + when others => -- OPCODE_NOP and others + d_opcode <= dec_nop; + end case; + end if; + end process decode_control; + + data_o <= b_i; + opcode_control: + process (clk_i) + variable sp_offset : unsigned(4 downto 0); + begin + if rising_edge(clk_i) then + break_o <= '0'; + write_en_o <= '0'; + read_en_o <= '0'; + dbg_o.b_inst <= '0'; + if reset_i='1' then + state <= st_resync; + sp_r <= SP_START; + pc_r <= (others => '0'); + idim_r <= '0'; + a_addr_r <= (others => '0'); + b_addr_r <= (others => '0'); + a_we_r <= '0'; + b_we_r <= '0'; + a_r <= (others => '0'); + b_r <= (others => '0'); + in_irq_r <= '0'; + addr_r <= (others => '0'); + else -- reset_i/='1' + a_we_r <= '0'; + b_we_r <= '0'; + -- This saves LUTs, by explicitly declaring that the + -- a_o can be left at whatever value if a_we_r is + -- not set. + a_r <= (others => D_CARE_VAL); + b_r <= (others => D_CARE_VAL); + sp_offset:=(others => D_CARE_VAL); + a_addr_r <= (others => D_CARE_VAL); + b_addr_r <= (others => D_CARE_VAL); + addr_r <= a_i(ADDR_W-1 downto 0); + d_opcode_r <= d_opcode; + opcode_r <= opcode; + if interrupt_i='0' then + in_irq_r <= '0'; -- no longer in an interrupt + end if; + + case state is + when st_execute => + state <= st_fetch; + -- At this point: + -- b_i contains opcode word + -- a_i contains top of stack + pc_r <= pc_r+1; + + -- Debug info (Trace) + dbg_o.b_inst <= '1'; + dbg_o.pc <= (others => '0'); + dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r; + dbg_o.opcode <= opcode_r; + dbg_o.sp <= (others => '0'); + dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r; + dbg_o.stk_a <= a_i; + dbg_o.stk_b <= b_i; + + -- During the next cycle we'll be reading the next opcode + sp_offset(4):=not opcode_r(4); + sp_offset(3 downto 0):=opcode_r(3 downto 0); + + idim_r <= '0'; + + -------------------- + -- Execution Unit -- + -------------------- + case d_opcode_r is + when dec_interrupt => + -- Not a real instruction, but an interrupt + -- Push(PC); PC=32 + sp_r <= sp_r-1; + a_addr_r <= sp_r-1; + a_we_r <= '1'; + a_r <= (others => D_CARE_VAL); + a_r(MAX_ADDR_BIT downto 0) <= pc_r; + -- Jump to ISR + pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address + --report "ZPU jumped to interrupt!" severity note; + when dec_im => + idim_r <= '1'; + a_we_r <= '1'; + if idim_r='0' then + -- First IM + -- Push the 7 bits (extending the sign) + sp_r <= sp_r-1; + a_addr_r <= sp_r-1; + a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE)); + else + -- Next IMs, shift the word and put the new value in the lower + -- bits + a_addr_r <= sp_r; + a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0); + a_r(6 downto 0) <= opcode_r(6 downto 0); + end if; + when dec_store_sp => + -- [SP+Offset]=Pop() + b_we_r <= '1'; + b_addr_r <= sp_r+sp_offset; + b_r <= a_i; + sp_r <= sp_r+1; + state <= st_resync; + when dec_load_sp => + -- Push([SP+Offset]) + sp_r <= sp_r-1; + a_addr_r <= sp_r+sp_offset; + when dec_emulate => + -- Push(PC+1), PC=Opcode[4:0]*32 + sp_r <= sp_r-1; + a_we_r <= '1'; + a_addr_r <= sp_r-1; + a_r <= (others => D_CARE_VAL); + a_r(MAX_ADDR_BIT downto 0) <= pc_r+1; + -- Jump to NUM*32 + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc_r <= (others => '0'); + pc_r(9 downto 5) <= opcode_r(4 downto 0); + when dec_add_sp => + -- Push(Pop()+[SP+Offset]) + a_addr_r <= sp_r; + b_addr_r <= sp_r+sp_offset; + state <= st_add_sp; + when dec_break => + --report "Break instruction encountered" severity failure; + break_o <= '1'; + when dec_push_sp => + -- Push(SP) + sp_r <= sp_r-1; + a_we_r <= '1'; + a_addr_r <= sp_r-1; + a_r <= (others => D_CARE_VAL); + a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r; + when dec_pop_pc => + -- Pop(PC) + pc_r <= a_i(MAX_ADDR_BIT downto 0); + sp_r <= sp_r+1; + state <= st_resync; + when dec_add => + -- Push(Pop()+Pop()) + sp_r <= sp_r+1; + state <= st_add; + when dec_or => + -- Push(Pop() or Pop()) + sp_r <= sp_r+1; + state <= st_or; + when dec_and => + -- Push(Pop() and Pop()) + sp_r <= sp_r+1; + state <= st_and; + when dec_load => + -- Push([Pop()]) + if a_i(IO_BIT)='1' then + addr_r <= a_i(ADDR_W-1 downto 0); + read_en_o <= '1'; + state <= st_read_io; + else + a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS); + end if; + when dec_not => + -- Push(not(Pop())) + a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS); + a_we_r <= '1'; + a_r <= not a_i; + when dec_flip => + -- Push(flip(Pop())) + a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS); + a_we_r <= '1'; + for i in 0 to WORD_SIZE-1 loop + a_r(i) <= a_i(WORD_SIZE-1-i); + end loop; + when dec_store => + -- a=Pop(), b=Pop(), [a]=b + b_addr_r <= sp_r+1; + sp_r <= sp_r+1; + if a_i(IO_BIT)='1' then + state <= st_write_io; + else + state <= st_store; + end if; + when dec_pop_sp => + -- SP=Pop() + sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS); + state <= st_resync; + when dec_nop => + -- Default, keep addressing to of the stack (A) + a_addr_r <= sp_r; + when others => + null; + end case; + when st_read_io => + a_addr_r <= sp_r; + -- Wait until memory I/O isn't busy + if mem_busy_i='0' then + state <= st_fetch; + a_we_r <= '1'; + a_r <= data_i; + end if; + when st_write_io => + -- [A]=B + sp_r <= sp_r+1; + write_en_o <= '1'; + addr_r <= a_i(ADDR_W-1 downto 0); + state <= st_write_io_done; + when st_write_io_done => + -- Wait until memory I/O isn't busy + if mem_busy_i='0' then + state <= st_resync; + end if; + when st_fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for st_execute the cycle after + -- next + b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS); + state <= st_fetch_next; + when st_fetch_next => + -- At this point a_i contains the value that is either + -- from the top of stack or should be copied to the top of the stack + a_we_r <= '1'; + a_r <= a_i; + a_addr_r <= sp_r; + b_addr_r <= sp_r+1; + state <= st_decode; + when st_decode => + if interrupt_i='1' and in_irq_r='0' and idim_r='0' then + -- We got an interrupt, execute interrupt instead of next instruction + in_irq_r <= '1'; + d_opcode_r <= dec_interrupt; + end if; + -- during the st_execute cycle we'll be fetching SP+1 + a_addr_r <= sp_r; + b_addr_r <= sp_r+1; + state <= st_execute; + when st_store => + sp_r <= sp_r+1; + a_we_r <= '1'; + a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS); + a_r <= b_i; + state <= st_resync; + when st_add_sp => + state <= st_add; + when st_add => + a_addr_r <= sp_r; + a_we_r <= '1'; + a_r <= a_i+b_i; + state <= st_fetch; + when st_or => + a_addr_r <= sp_r; + a_we_r <= '1'; + a_r <= a_i or b_i; + state <= st_fetch; + when st_and => + a_addr_r <= sp_r; + a_we_r <= '1'; + a_r <= a_i and b_i; + state <= st_fetch; + when st_resync => + a_addr_r <= sp_r; + state <= st_fetch; + when others => + null; + end case; + end if; -- else reset_i/='1' + end if; -- rising_edge(clk_i) + end process opcode_control; + addr_o <= addr_r; + +end architecture Behave; -- Entity: ZPUSmallCore + diff --git a/zpu/hdl/zpu4/core/histogram.perl b/zpu/hdl/zpu4/core/histogram.perl new file mode 100644 index 0000000..479ee0f --- /dev/null +++ b/zpu/hdl/zpu4/core/histogram.perl @@ -0,0 +1,218 @@ +#!/usr/bin/perl +############################################################################## +# +# Copyright (c) 2008 Salvador E. Tropea <salvador en inti gov ar> +# Copyright (c) 2008 Instituto Nacional de Tecnología Industrial +# +############################################################################## +# +# Target: Any +# Language: Perl +# Interpreter used: v5.6.1/v5.8.4 +# Text editor: SETEdit 0.5.5 +# +############################################################################## +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA +# +############################################################################## +# +# Description: Takes a ZPU trace and does some raw stats about opcodes +# frequency and speed. +# +############################################################################## +# +# TODO +# +# A lot ... +# + + +# 0x40-0x460 +# div y mod son especiales +@used=(); +@clks=(); + +$line=1; +$startLine=1; +#$endLine=10000; +$endLine=-1; +$lastClk=0; +$lastOpcode=-1; +while (<>) + { + if ($_=~/^(\S+) (\S+) (\S+) (\S+) (\S+) (\S+) (\S+)/) + { + $clk=hex($7); + #print "$line\n"; + if ($line>=$startLine) + { + #print $_; + $addr=hex($1); + $opcode=hex($2); + $sp=hex($3); + $a=hex($4); + $b=hex($5); + if ($addr>=0x40 and $addr<0x460) + { + @used[$opcode+0x100]++; + @clks[$lastOpcodeEmu]+=$clk-$lastClkEmu unless lastOpcodeEmu==-1; + $lastOpcodeEmu=$opcode+0x100; + $lastClkEmu=$clk; + } + else + { + @used[$opcode]++; + @clks[$lastOpcode]+=$clk-$lastClk unless $lastOpcode==-1; + #printf "%d+=%d\n",$lastOpcode,$clk-$lastClk; + $lastOpcode=$opcode; + $lastClk=$clk; + $lastOpcodeEmu=-1; + $lastClkEmu=$clk; + } + } + else + { + $lastClk=$clk; + } + last if $line==$endLine; + $line++; + } + } +@used[$lastOpcode]--; + +$id=0; +# Cluster them +AddSimple('breakpoint',0); +# 1=shiftleft, invalid +AddSimple('pushsp',2); +# 3=pushint, invalid +AddSimple('poppc',4); +AddSimple('add',5); +AddSimple('and',6); +AddSimple('or',7); +AddSimple('load',8); +AddSimple('not',9); +AddSimple('flip',10); +AddSimple('nop',11); +AddSimple('store',12); +AddSimple('popsp',13); +# 14=compare, invalid +# 15=popint, invalid +AddSimpleRange('addsp',16,31); +# 32-63 emulate +AddSimpleRange('storesp',64,95); +AddSimpleRange('loadsp',96,127); +AddSimpleRange('im',128,255); + +# 32 is the reset entry point +# 33 is the interrupt entry point +AddEmulate('loadh',34); +AddEmulate('storeh',35); +AddEmulate('lessthan',36); +AddEmulate('lessthanorequal',37); +AddEmulate('ulessthan',38); +AddEmulate('ulessthanorequal',39); +AddEmulate('swap',40); # unimplemented +AddEmulate('mult',41); +AddEmulate('lshiftright',42); +AddEmulate('ashiftleft',43); +AddEmulate('ashiftright',44); +AddEmulate('call',45); +AddEmulate('eq',46); +AddEmulate('neq',47); +AddEmulate('neg',48); +AddEmulate('sub',49); +AddEmulate('xor',50); +AddEmulate('loadb',51); +AddEmulate('storeb',52); +AddEmulate('div',53); +AddEmulate('mod',54); +AddEmulate('eqbranch',55); +AddEmulate('neqbranch',56); +AddEmulate('poppcrel',57); +AddEmulate('config',58); +AddEmulate('pushpc',59); +AddEmulate('syscall_emulate',60); # unimplemented +AddEmulate('pushspadd',61); +AddEmulate('halfmult',62); # unimplemented +AddEmulate('callpcrel',63); + +$maxID=$id; +print "Total clocks: $lastClk\n"; +print "Unsorted:\n\n"; +for ($i=0; $i<$maxID; $i++) + { + $used=@used_noemu[$i]; + $clkm=0; + $clkm=@clks_noemu[$i]/$used if $used; + printf "%-20s %8d %6.2f\n",$names[$i],$used,$clkm; + $by_times{$i}=$used; + $by_clks{$i}=@clks_noemu[$i]; + } +print "Sorted by consumed clocks:\n\n"; +foreach $key (sort { $by_clks{$b} <=> $by_clks{$a} } keys %by_clks) + { + printf "%5.2f %-20s %8d\n",$by_clks{$key}/$lastClk*100,$names[$key],$by_clks{$key}; + } + + +sub AddSimple +{ + my ($name, $opcode)=@_; + + $names[$id]=$name; + @used_noemu[$id]=@used[$opcode]; + @used_emu[$id]=@used[$opcode+0x100]; + @used_both[$id]=@used[$opcode]+@used[$opcode+0x100]; + @clks_noemu[$id]=@clks[$opcode]; + @clks_emu[$id]=@clks[$opcode+0x100]; + @clks_both[$id]=@clks[$opcode]+@clks[$opcode+0x100]; + $id++; +} + +sub AddEmulate +{ + my ($name, $opcode)=@_; + + $names[$id]=$name; + @used_noemu[$id]=@used[$opcode]; + @used_emu[$id]=@used[$opcode+0x100]; + @used_both[$id]=@used[$opcode]; + @clks_noemu[$id]=@clks[$opcode]; + @clks_emu[$id]=@clks[$opcode+0x100]; + @clks_both[$id]=@clks[$opcode]; + $id++; +} + +sub AddSimpleRange +{ + my ($name, $opStart, $opLast)=@_; + my $i; + + $names[$id]=$name; + for ($i=$opStart; $i<=$opLast; $i++) + { + @used_noemu[$id]+=@used[$i]; + @used_emu[$id]+=@used[$i+0x100]; + @used_both[$id]+=@used[$i]+@used[$i+0x100]; + @clks_noemu[$id]+=@clks[$i]; + @clks_emu[$id]+=@clks[$i+0x100]; + @clks_both[$id]+=@clks[$i]+@clks[$i+0x100]; + } + $id++; +} + + diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd new file mode 100644 index 0000000..c678044 --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -0,0 +1,58 @@ +-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package zpu_config is
+
+ -- generate trace output or not.
+ constant Generate_Trace : boolean := false;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := 'X';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
+ -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+ constant maxAddrBitIncIO : integer := 15;
+ constant maxAddrBitBRAM : integer := 14;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
+ std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1));
+
+end zpu_config;
diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd new file mode 100644 index 0000000..f423f80 --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -0,0 +1,1014 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + + + + +entity zpu_core is + port ( + clk : in std_logic; + reset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask : out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic + ); +end zpu_core; + + +architecture behave of zpu_core is + + type InsnType is ( + Insn_AddTop, + Insn_Dup, + Insn_DupStackB, + Insn_Pop, + Insn_PopDown, + Insn_Add, + Insn_Or, + Insn_And, + Insn_Store, + Insn_AddSP, + Insn_Shift, + Insn_Nop, + Insn_Im, + Insn_LoadSP, + Insn_StoreSP, + Insn_Emulate, + Insn_Load, + Insn_PushSP, + Insn_PopPC, + Insn_PopPCrel, + Insn_Not, + Insn_Flip, + Insn_PopSP, + Insn_Neqbranch, + Insn_Eq, + Insn_Loadb, + Insn_Mult, + Insn_Lessthan, + Insn_Lessthanorequal, + Insn_Ulessthanorequal, + Insn_Ulessthan, + Insn_PushSPadd, + Insn_Call, + Insn_CallPCrel, + Insn_Sub, + Insn_Break, + Insn_Storeb, + Insn_InsnFetch + ); + + type StateType is ( + State_Load2, + State_Popped, + State_LoadSP2, + State_LoadSP3, + State_AddSP2, + State_Fetch, + State_Execute, + State_Decode, + State_Decode2, + State_Resync, + + State_StoreSP2, + State_Resync2, + State_Resync3, + State_Loadb2, + State_Storeb2, + State_Mult2, + State_Mult3, + State_Mult5, + State_Mult4, + State_BinaryOpResult2, + State_BinaryOpResult, + State_Idle, + State_Interrupt + ); + + + signal pc : unsigned(maxAddrBitIncIO downto 0); + signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); + signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); + signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); + signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); + signal stackA : unsigned(wordSize-1 downto 0); + signal binaryOpResult : unsigned(wordSize-1 downto 0); + signal binaryOpResult2 : unsigned(wordSize-1 downto 0); + signal multResult2 : unsigned(wordSize-1 downto 0); + signal multResult3 : unsigned(wordSize-1 downto 0); + signal multResult : unsigned(wordSize-1 downto 0); + signal multA : unsigned(wordSize-1 downto 0); + signal multB : unsigned(wordSize-1 downto 0); + signal stackB : unsigned(wordSize-1 downto 0); + signal idim_flag : std_logic; + signal busy : std_logic; + signal mem_writeEnable : std_logic; + signal mem_readEnable : std_logic; + signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); + signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); + signal mem_delayReadEnable : std_logic; + -- + signal inInterrupt : std_logic; + -- + signal decodeWord : std_logic_vector(wordSize-1 downto 0); + -- + -- + signal state : StateType; + signal insn : InsnType; + type InsnArray is array(0 to wordBytes-1) of InsnType; + signal decodedOpcode : InsnArray; + -- + type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + -- + signal opcode : OpcodeArray; + + + + signal begin_inst : std_logic; + signal trace_opcode : std_logic_vector(7 downto 0); + signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); + signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); + signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); + signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +begin + + + traceFileGenerate : + if Generate_Trace generate + trace_file : trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + + opcodeControl : process(clk, reset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : unsigned(4 downto 0); + variable tSpOffset : unsigned(4 downto 0); + variable nextPC : unsigned(maxAddrBitIncIO downto 0); + variable tNextInsn : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + if reset = '1' then + state <= State_Idle; + break <= '0'; + sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + inInterrupt <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif rising_edge(clk) then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + + mem_addr <= (others => DontCareValue); + mem_readEnable <= '0'; + mem_writeEnable <= '0'; + mem_write <= (others => DontCareValue); + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + + + spOffset(4) := not opcode(to_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0) := unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); + trace_pc <= std_logic_vector(pc); + trace_sp <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(stackA); + trace_topOfStackB <= std_logic_vector(stackB); + begin_inst <= '0'; + + if (interrupt = '0') then + -- Interrupt ended, we can serve ISR again + inInterrupt <= '0'; + end if; + + case state is + + when State_Idle => + if enable = '1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + + when State_Resync => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(sp); + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + + when State_Resync2 => + if in_mem_busy = '0' then + stackA <= unsigned(mem_read); + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Resync3; + end if; + + when State_Resync3 => + if in_mem_busy = '0' then + stackB <= unsigned(mem_read); + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + + when State_Decode => + if in_mem_busy = '0' then + decodeWord <= mem_read; + state <= State_Decode2; + -- Do not recurse into ISR while interrupt line is active + if interrupt = '1' and inInterrupt = '0' and idim_flag = '0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + pc <= to_unsigned(32, maxAddrBitIncIO+1); + state <= State_Interrupt; + end if; -- interrupt + end if; -- in_mem_busy + + when State_Interrupt => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + report "ZPU jumped to interrupt!" severity note; + end if; + + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4) := not tOpcode(4); + tSpOffset(3 downto 0) := unsigned(tOpcode(3 downto 0)); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7) = OpCode_Im) then + tNextInsn := Insn_Im; + elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then + if tSpOffset = 0 then + tNextInsn := Insn_Pop; + elsif tSpOffset = 1 then + tNextInsn := Insn_PopDown; + else + tNextInsn := Insn_StoreSP; + end if; + elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then + if tSpOffset = 0 then + tNextInsn := Insn_Dup; + elsif tSpOffset = 1 then + tNextInsn := Insn_DupStackB; + else + tNextInsn := Insn_LoadSP; + end if; + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then + tNextInsn := Insn_Emulate; + if tOpcode(5 downto 0) = OpCode_Neqbranch then + tNextInsn := Insn_Neqbranch; + elsif tOpcode(5 downto 0) = OpCode_Eq then + tNextInsn := Insn_Eq; + elsif tOpcode(5 downto 0) = OpCode_Lessthan then + tNextInsn := Insn_Lessthan; + elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then + --tNextInsn :=Insn_Lessthanorequal; + elsif tOpcode(5 downto 0) = OpCode_Ulessthan then + tNextInsn := Insn_Ulessthan; + elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then + --tNextInsn :=Insn_Ulessthanorequal; + elsif tOpcode(5 downto 0) = OpCode_Loadb then + tNextInsn := Insn_Loadb; + elsif tOpcode(5 downto 0) = OpCode_Mult then + tNextInsn := Insn_Mult; + elsif tOpcode(5 downto 0) = OpCode_Storeb then + tNextInsn := Insn_Storeb; + elsif tOpcode(5 downto 0) = OpCode_Pushspadd then + tNextInsn := Insn_PushSPadd; + elsif tOpcode(5 downto 0) = OpCode_Callpcrel then + tNextInsn := Insn_CallPCrel; + elsif tOpcode(5 downto 0) = OpCode_Call then + --tNextInsn :=Insn_Call; + elsif tOpcode(5 downto 0) = OpCode_Sub then + tNextInsn := Insn_Sub; + elsif tOpcode(5 downto 0) = OpCode_PopPCRel then + --tNextInsn :=Insn_PopPCrel; + end if; + elsif (tOpcode(7 downto 4) = OpCode_AddSP) then + if tSpOffset = 0 then + tNextInsn := Insn_Shift; + elsif tSpOffset = 1 then + tNextInsn := Insn_AddTop; + else + tNextInsn := Insn_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextInsn := Insn_Nop; + when OpCode_PushSP => + tNextInsn := Insn_PushSP; + when OpCode_PopPC => + tNextInsn := Insn_PopPC; + when OpCode_Add => + tNextInsn := Insn_Add; + when OpCode_Or => + tNextInsn := Insn_Or; + when OpCode_And => + tNextInsn := Insn_And; + when OpCode_Load => + tNextInsn := Insn_Load; + when OpCode_Not => + tNextInsn := Insn_Not; + when OpCode_Flip => + tNextInsn := Insn_Flip; + when OpCode_Store => + tNextInsn := Insn_Store; + when OpCode_PopSP => + tNextInsn := Insn_PopSP; + when others => + tNextInsn := Insn_Break; + + end case; -- tOpcode(3 downto 0) + end if; -- tOpcode + tDecodedOpcode(i) := tNextInsn; + + end loop; -- 0 to wordBytes-1 + + insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := Insn_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase PC if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); + + case insn is + + when Insn_InsnFetch => + state <= State_Fetch; + + when Insn_Im => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag = '1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + else + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + end if; -- idim_flag + end if; -- in_mem_busy + + when Insn_StoreSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + mem_write <= std_logic_vector(stackA); + stackA <= stackB; + sp <= incSp; + end if; + + + when Insn_LoadSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + + when Insn_Emulate => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); + state <= State_Fetch; + end if; -- in_mem_busy + + when Insn_CallPCrel => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + + when Insn_Call => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + + when Insn_AddSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + end if; + + when Insn_PushSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + + when Insn_PopPC => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + + when Insn_PopPCrel => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + + when Insn_Add => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + + when Insn_Sub => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + + when Insn_Pop => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + + when Insn_PopDown => + if in_mem_busy = '0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + + when Insn_Or => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + + when Insn_And => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + + when Insn_Eq => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA = stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when Insn_Ulessthan => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA < stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when Insn_Ulessthanorequal => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA <= stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when Insn_Lessthan => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) < signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when Insn_Lessthanorequal => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) <= signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when Insn_Load => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when Insn_Dup => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + + when Insn_DupStackB => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + + when Insn_Store => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= std_logic_vector(stackB); + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + + when Insn_PopSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + end if; + + when Insn_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + when Insn_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + + when Insn_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + + when Insn_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + + when Insn_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + + when Insn_PushSPadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + + when Insn_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB /= 0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + + when Insn_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + + when Insn_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when Insn_Loadb => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when Insn_Storeb => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + + end case; -- insn/State_Execute + + + when State_StoreSP2 => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Popped; + end if; + + when State_LoadSP2 => + if in_mem_busy = '0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset+1); + end if; + + when State_LoadSP3 => + if in_mem_busy = '0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= unsigned(mem_read); + end if; + + when State_AddSP2 => + if in_mem_busy = '0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + unsigned(mem_read); + end if; + + when State_Load2 => + if in_mem_busy = '0' then + stackA <= unsigned(mem_read); + pc <= pc + 1; + state <= State_Execute; + end if; + + when State_Loadb2 => + if in_mem_busy = '0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); + pc <= pc + 1; + state <= State_Execute; + end if; + + when State_Storeb2 => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= mem_read; + mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + + when State_Fetch => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + + when State_Mult2 => + state <= State_Mult3; + + when State_Mult3 => + state <= State_Mult4; + + when State_Mult4 => + state <= State_Mult5; + + when State_Mult5 => + if in_mem_busy = '0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + + when State_Popped => + if in_mem_busy = '0' then + pc <= pc + 1; + stackB <= unsigned(mem_read); + state <= State_Execute; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + + end case; -- state + end if; -- clk'event + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd new file mode 100644 index 0000000..9ac35a8 --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -0,0 +1,602 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + port ( + clk : in std_logic; + -- asynchronous reset signal + reset : in std_logic; + -- this particular implementation of the ZPU does not + -- have a clocked enable signal + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + -- this implementation of the ZPU *always* reads and writes entire + -- 32 bit words, so mem_writeMask is tied to (others => '1'). + mem_writeMask : out std_logic_vector(wordBytes-1 downto 0); + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + interrupt : in std_logic; + -- Signal that the break instruction is executed, normally only used + -- in simulation to stop simulation + break : out std_logic + ); +end zpu_core; + + + +architecture behave of zpu_core is + + signal memAWriteEnable : std_logic; + signal memAAddr : unsigned(maxAddrBit downto minAddrBit); + signal memAWrite : unsigned(wordSize-1 downto 0); + signal memARead : unsigned(wordSize-1 downto 0); + signal memBWriteEnable : std_logic; + signal memBAddr : unsigned(maxAddrBit downto minAddrBit); + signal memBWrite : unsigned(wordSize-1 downto 0); + signal memBRead : unsigned(wordSize-1 downto 0); + + + + signal pc : unsigned(maxAddrBit downto 0); + signal sp : unsigned(maxAddrBit downto minAddrBit); + + -- this signal is set upon executing an IM instruction + -- the subsequence IM instruction will then behave differently. + -- all other instructions will clear the idim_flag. + -- this yields highly compact immediate instructions. + signal idim_flag : std_logic; + -- + signal busy : std_logic; + -- + signal begin_inst : std_logic; + + + signal trace_opcode : std_logic_vector(7 downto 0); + signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); + signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); + signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); + signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + + -- state machine. + type State_Type is ( + State_Fetch, + State_WriteIODone, + State_Execute, + State_StoreToStack, + State_Add, + State_Or, + State_And, + State_Store, + State_ReadIO, + State_WriteIO, + State_Load, + State_FetchNext, + State_AddSP, + State_ReadIODone, + State_Decode, + State_Resync, + State_Interrupt + ); + + type DecodedOpcodeType is ( + Decoded_Nop, + Decoded_Im, + Decoded_ImShift, + Decoded_LoadSP, + Decoded_StoreSP , + Decoded_AddSP, + Decoded_Emulate, + Decoded_Break, + Decoded_PushSP, + Decoded_PopPC, + Decoded_Add, + Decoded_Or, + Decoded_And, + Decoded_Load, + Decoded_Not, + Decoded_Flip, + Decoded_Store, + Decoded_PopSP, + Decoded_Interrupt + ); + + + + signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); + signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + -- + signal decodedOpcode : DecodedOpcodeType; + signal sampledDecodedOpcode : DecodedOpcodeType; + + + signal state : State_Type; + -- + subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; + signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); + signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); + signal memARead_stdlogic : std_logic_vector(memARead'range); + signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); + signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); + signal memBRead_stdlogic : std_logic_vector(memBRead'range); + -- + subtype index is integer range 0 to 3; + -- + signal tOpcode_sel : index; + -- + signal inInterrupt : std_logic; + + + +begin + + -- generate a trace file. + -- + -- This is only used in simulation to see what instructions are + -- executed. + -- + -- a quick & dirty regression test is then to commit trace files + -- to CVS and compare the latest trace file against the last known + -- good trace file + traceFileGenerate : if Generate_Trace generate + trace_file : trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- mem_writeMask is not used in this design, tie it to 1 + mem_writeMask <= (others => '1'); + + + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + + + -- dualport_ram must be defined by the application. + -- + -- How this can be implemented is highly dependent on the FPGA + -- and synthesis technology used. + -- + -- sometimes it can be instantiated as in the + -- zpu/example/helloworld.vhd, using inference, + -- but oftentimes it must be instantiated directly + -- portmapping to part specific FPGA resources + -- + -- + -- DANGER!!!!!! If inference fails, then synthesis will try + -- to implement the memory using basic logic resources. This + -- will almost certainly cause the compiler to get "stuck" + -- since synthesising such a huge number of basic logic resources + -- will take more or less forever. + -- + -- So: if your compiler gets "stuck" then inference is not + -- the way to go. + memory : dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic + ); + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); + + + + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + + -- move out calculation of the opcode to a seperate process + -- to make things a bit easier to read + decodeControl : process(memBRead, pc, tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + + -- simplify opcode selection a bit so it passes more synthesizers + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7) = OpCode_Im) then + sampledDecodedOpcode <= Decoded_Im; + elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then + sampledDecodedOpcode <= Decoded_StoreSP; + elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then + sampledDecodedOpcode <= Decoded_LoadSP; + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then + sampledDecodedOpcode <= Decoded_Emulate; + elsif (tOpcode(7 downto 4) = OpCode_AddSP) then + sampledDecodedOpcode <= Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode <= Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode <= Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode <= Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode <= Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode <= Decoded_Or; + when OpCode_And => + sampledDecodedOpcode <= Decoded_And; + when OpCode_Load => + sampledDecodedOpcode <= Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode <= Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode <= Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode <= Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode <= Decoded_PopSP; + when others => + sampledDecodedOpcode <= Decoded_Nop; + end case; -- tOpcode(3 downto 0) + end if; -- tOpcode + end process; + + + opcodeControl: process(clk, reset) + variable spOffset : unsigned(4 downto 0); + begin + + if reset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + inInterrupt <= '0'; + + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + if interrupt = '0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4) := not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + + case decodedOpcode is + + when Decoded_Interrupt => + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc; + pc <= to_unsigned(32, maxAddrBit+1); -- interrupt address + report "ZPU jumped to interrupt!" severity note; + + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag = '0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; -- idim_flag + + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + + when Decoded_And => + sp <= sp + 1; + state <= State_And; + + when Decoded_Load => + if (memARead(ioBit) = '1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit) = '1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + + when Decoded_Nop => + memAAddr <= sp; + + when others => + null; + + end case; -- decodedOpcode + + when State_ReadIO => + memAAddr <= sp; + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + + when State_Decode => + if interrupt = '1' and inInterrupt = '0' and idim_flag = '0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + decodedOpcode <= Decoded_Interrupt; + end if; + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + + when State_AddSP => + state <= State_Add; + + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + + when others => + null; + + end case; -- state + + end if; -- reset, enable + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd new file mode 100644 index 0000000..0363aca --- /dev/null +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -0,0 +1,218 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; + + +package zpupkg is + + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + + ------------------------------------------------------------ + -- components + + component dualport_ram is + port ( + clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0) + ); + end component dualport_ram; + + + component dram is + port ( + clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0) + ); + end component dram; + + + component trace is + port ( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component trace; + + + component zpu_core is + port ( + clk : in std_logic; + reset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask : out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic + ); + end component zpu_core; + + + component timer is + port ( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0) + ); + end component timer; + + + component zpuio is + port ( + areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0) + ); + end component zpuio; + + + ------------------------------------------------------------ + -- constants + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + -- + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011"; + -- + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + -- + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + -- + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_NA : std_logic_vector(3 downto 0) := "1111"; + -- + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); + -- + constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); + constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); + -- + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); + constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); + -- + constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); + constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); + -- + constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); + -- + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); + -- + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); + -- + -- + constant OpCode_Size : integer := 8; + + + +end zpupkg; diff --git a/zpu/hdl/zpu4/src/.cvsignore b/zpu/hdl/zpu4/src/.cvsignore new file mode 100644 index 0000000..41c40a0 --- /dev/null +++ b/zpu/hdl/zpu4/src/.cvsignore @@ -0,0 +1,5 @@ +work +vsim.wlf +xilinx_device_details.xml +tcl_stacktrace.txt +vish_stacktrace.vstf diff --git a/zpu/hdl/zpu4/src/clocks.vhd b/zpu/hdl/zpu4/src/clocks.vhd new file mode 100644 index 0000000..67433be --- /dev/null +++ b/zpu/hdl/zpu4/src/clocks.vhd @@ -0,0 +1,198 @@ +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ibufg; +use unisim.vcomponents.srl16; +use unisim.vcomponents.dcm; +use unisim.vcomponents.bufg; + + +entity clocks is + port ( + areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0) + ); +end entity clocks; + +architecture behave of clocks is + + signal low : std_logic; + -- + signal cpu_clk_in : std_logic; + signal sdr_clk_fb_in : std_logic; + -- + signal dcm_cpu1 : std_logic; + signal dcm_cpu2 : std_logic; + signal dcm_cpu2_dum : std_logic; + signal dcm_cpu4 : std_logic; + signal dcm_ddr2 : std_logic; + signal dcm_ddr2_2x : std_logic; + -- + signal cpu_clk_int : std_logic; + signal cpu_clk_2x_int : std_logic; + signal cpu_clk_2x_dum_int : std_logic; + signal cpu_clk_4x_int : std_logic; + signal ddr_in_clk_int : std_logic; + signal ddr_in_clk_2x_int : std_logic; + -- + signal dcm1_locked_del : std_logic; + signal dcm2_locked_del : std_logic; + signal dcm2_reset : std_logic; + signal dcm3_reset : std_logic; + -- + signal locked_int : std_logic_vector(2 downto 0); + signal del_addr : std_logic_vector(3 downto 0); + +begin + + low <= '0'; + del_addr <= "1111"; + -- + cpu_clk <= cpu_clk_int; + cpu_clk_2x <= cpu_clk_2x_int; + cpu_clk_4x <= cpu_clk_4x_int; + ddr_in_clk <= ddr_in_clk_int; + ddr_in_clk_2x <= ddr_in_clk_2x_int; + locked <= locked_int; + + + cpu_ibufg : ibufg + port map ( + O => cpu_clk_in, + I => cpu_clk_p + ); + + sdr_fb_ibufg : ibufg + port map ( + O => sdr_clk_fb_in, + I => sdr_clk_fb_p + ); + + dcm2_rst : srl16 + generic map ( + init => x"0000" + ) + port map ( + Q => dcm1_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(0) + ); + + dcm2_reset <= not(dcm1_locked_del); + + dcm3_rst : srl16 + generic map ( + init => x"0000" + ) + port map ( + Q => dcm2_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(1) + ); + + dcm3_reset <= not(dcm2_locked_del); + + cpu1_dcm : + dcm generic map ( + clkin_period => 15.625, -- Specify period of input clock + factory_jf => X"8080" -- FACTORY JF Values + ) + port map ( + clk0 => dcm_cpu1, -- 0 degree DCM CLK ouptput + clk2x => dcm_cpu2, -- 2X DCM CLK output + locked => locked_int(0), -- DCM LOCK status output + clkfb => cpu_clk_int, -- DCM clock feedback + clkin => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) + psclk => low, -- Dynamic phase adjust clock input + psen => low, -- Dynamic phase adjust enable input + psincdec => low, -- Dynamic phase adjust increment/decrement + rst => areset -- DCM asynchronous reset input + ); + + cpu2_dcm : dcm + generic map ( + clkin_period => 7.8125, -- Specify period of input clock + factory_jf => X"8080" -- FACTORY JF Values + ) + port map ( + clk0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput + clk2x => dcm_cpu4, -- 2X DCM CLK output + locked => locked_int(1), -- DCM LOCK status output + clkfb => cpu_clk_2x_dum_int, -- DCM clock feedback + clkin => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) + psclk => low, -- Dynamic phase adjust clock input + psen => low, -- Dynamic phase adjust enable input + psincdec => low, -- Dynamic phase adjust increment/decrement + rst => dcm2_reset -- DCM asynchronous reset input + ); + + ddr_read_dcm : dcm + generic map ( + clkin_period => 7.8125, -- Specify period of input clock + clkout_phase_shift => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE + factory_jf => X"8080", -- FACTORY JF Values + phase_shift => 103 -- Amount of fixed phase shift from -255 to 255 + ) + port map ( + clk0 => dcm_ddr2, -- 0 degree DCM CLK ouptput + clk2x => dcm_ddr2_2x, -- 2X DCM CLK output + locked => locked_int(2), -- DCM LOCK status output + clkfb => ddr_in_clk_int, -- DCM clock feedback + clkin => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) + psclk => low, -- Dynamic phase adjust clock input + psen => low, -- Dynamic phase adjust enable input + psincdec => low, -- Dynamic phase adjust increment/decrement + rst => dcm3_reset -- DCM asynchronous reset input + ); + + cpu1 : bufg + port map ( + I => dcm_cpu1, + O => cpu_clk_int + ); + + cpu2 : bufg + port map ( + I => dcm_cpu2, + O => cpu_clk_2x_int + ); + + cpu2_dum : bufg + port map ( + i => dcm_cpu2_dum, + o => cpu_clk_2x_dum_int + ); + + cpu4 : bufg + port map ( + i => dcm_cpu4, + o => cpu_clk_4x_int + ); + + ddr_clk : bufg port map ( + i => dcm_ddr2, + o => ddr_in_clk_int + ); + + ddr_clk_2x : bufg port map ( + i => dcm_ddr2_2x, + o => ddr_in_clk_2x_int + ); + +end architecture behave; diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd new file mode 100644 index 0000000..56c7fb5 --- /dev/null +++ b/zpu/hdl/zpu4/src/io.vhd @@ -0,0 +1,119 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + + +entity zpu_io is + generic ( + log_file : string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end entity zpu_io; + + +architecture behave of zpu_io is + + signal timer_read : std_logic_vector(7 downto 0); + signal timer_we : std_logic; + -- + signal serving : std_logic; + -- + file l_file : text open write_mode is log_file; + constant lowAddrBits : std_logic_vector(minAddrBit-1 downto 0) := (others => '0'); + constant tx_full : std_logic := '0'; + constant rx_empty : std_logic := '1'; + +begin + + + timerinst : timer + port map ( + clk => clk, + areset => areset, + we => timer_we, + din => write(7 downto 0), + adr => addr(4 downto 2), + dout => timer_read + ); + + busy <= writeEnable or readEnable; + timer_we <= writeEnable and addr(12); + + process(areset, clk) + variable taddr : std_logic_vector(maxAddrBit downto 0); + -- pragma translate_off + variable line_out : line := new string'(""); + variable char : character; + -- pragma translate_on + begin + taddr := (others => '0'); + taddr(maxAddrBit downto minAddrBit) := addr; + + if (areset = '1') then + elsif (clk'event and clk = '1') then + if writeEnable = '1' then + -- external interface (fixed address) + --<JK> extend compare to avoid waring messages + if ("1" & addr & lowAddrBits) = x"80a000c" then + -- Write to UART + report "Write to UART[0]" & " :0x" & hstr(write); + -- pragma translate_off + char := character'val(to_integer(unsigned(write))); + if char = lf then + std.textio.writeline(l_file, line_out); + else + std.textio.write(line_out, char); + end if; + -- pragma translate_on + + elsif addr(12) = '1' then + report "Write to TIMER" & " :0x" & hstr(write); + + else + + report "Illegal IO write @" & "0x" & hstr(taddr) severity warning; + end if; + + end if; + read <= (others => '0'); + if (readEnable = '1') then + --<JK> extend compare to avoid waring messages + if ("1" & addr & lowAddrBits) = x"80a000c" then + report "Read UART[0]"; + read(8) <= not tx_full; -- output fifo not full + read(9) <= not rx_empty; -- receiver not empty + elsif ("1" & addr & lowAddrBits) = x"80a0010" then + report "Read UART[1]"; + read(8) <= not rx_empty; -- receiver not empty + read(7 downto 0) <= (others => '0'); + elsif addr(12) = '1' then + report "Read TIMER"; + read(7 downto 0) <= timer_read; + elsif addr(11) = '1' then + report "Read ZPU Freq"; + read(7 downto 0) <= ZPU_Frequency; + else + report "Illegal IO read @" & "0x" & hstr(taddr) severity warning; + end if; + end if; + end if; + end process; + +end architecture behave; + diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd new file mode 100644 index 0000000..d6d9358 --- /dev/null +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -0,0 +1,61 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0) + ); +end entity timer; + + +architecture behave of timer is + + signal sample : std_logic; + signal reset : std_logic; + -- + signal cnt : unsigned(63 downto 0); + signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + elsif rising_edge(clk) then + cnt <= cnt + 1; + if sample = '1' then +-- report "sampling" severity failure; + cnt_smp <= std_logic_vector(cnt); + end if; + end if; + end process; + + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end architecture behave; + diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd new file mode 100644 index 0000000..01678c8 --- /dev/null +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -0,0 +1,107 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + + +entity trace is + generic ( + log_file : string := "trace.txt" + ); + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); +end entity trace; + + +architecture behave of trace is + + file l_file : text open write_mode is log_file; + +begin + + -- write data and control information to a file + receive_data : process + variable l : line; + variable t : std_logic_vector(wordSize-1 downto 0); + variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); + variable counter : unsigned(63 downto 0); + begin + + t := (others => '0'); + t2 := (others => '0'); + + counter := (others => '0'); + + -- print header for the logfile + print(l_file, "#pc,opcode,sp,top_of_stack "); + print(l_file, "#----------"); + print(l_file, " "); + + wait until clk = '1'; + wait until clk = '0'; + + while true loop + + counter := counter + 1; + if begin_inst = '1' then + t(maxAddrBitIncIO downto 2) := sp; + t2 := pc; + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter))); + end if; + + wait until clk = '0'; + + end loop; + end process receive_data; + +end architecture behave; + diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd new file mode 100644 index 0000000..4dca901 --- /dev/null +++ b/zpu/hdl/zpu4/src/txt_util.vhd @@ -0,0 +1,539 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text : string); + + -- prints the message when active + -- useful for debug switches + procedure print(active : boolean; text : string); + + -- converts std_logic into a character + function chr(sl : std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl : std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv : std_logic_vector) return string; + + -- converts boolean into a string + function str(b : boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int : integer) return character; + + -- converts integer into string using specified base + function str(int : integer; base : integer) return string; + + -- converts integer to string, using base 10 + function str(int : integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv : std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c : character) return character; + + -- convert a character to lower case + function to_lower(c : character) return character; + + -- convert a string to upper case + function to_upper(s : string) return string; + + -- convert a string to lower case + function to_lower(s : string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c : character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s : string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file : text; res_string : out string); + + -- print string to a file and start new line + procedure print(file out_file : text; new_string : in string); + + -- print character to a file and start new line + procedure print(file out_file : text; char : in character); + +end package txt_util; + + + + +package body txt_util is + + + -- prints text to the screen + procedure print(text : string) is + variable msg_line : line; + begin + write(msg_line, text); + writeline(output, msg_line); + end procedure print; + + + -- prints text to the screen when active + procedure print(active : boolean; text : string) is + begin + if active then + print(text); + end if; + end procedure print; + + + -- converts std_logic into a character + function chr(sl : std_logic) return character is + variable c : character; + begin + case sl is + when 'U' => c := 'U'; + when 'X' => c := 'X'; + when '0' => c := '0'; + when '1' => c := '1'; + when 'Z' => c := 'Z'; + when 'W' => c := 'W'; + when 'L' => c := 'L'; + when 'H' => c := 'H'; + when '-' => c := '-'; + end case; + return c; + end function chr; + + + -- converts std_logic into a string (1 to 1) + function str(sl : std_logic) return string is + variable s : string(1 to 1); + begin + s(1) := chr(sl); + return s; + end function str; + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + function str(slv : std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end function str; + + + function str(b : boolean) return string is + begin + if b then + return "true"; + else + return "false"; + end if; + end function str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + function chr(int : integer) return character is + variable c : character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end function chr; + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + function str(int : integer; base : integer) return string is + variable temp : string(1 to 10); + variable num : integer; + variable abs_int : integer; + variable len : integer := 1; + variable power : integer := 1; + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end function str; + + + -- convert integer to string, using base 10 + function str(int : integer) return string is + begin + return str(int, 10); + end function str; + + + -- converts a std_logic_vector into a hex string. + function hstr(slv : std_logic_vector) return string is + variable hexlen : integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end function hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c : character) return character is + variable u : character; + begin + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + return u; + end function to_upper; + + + -- convert a character to lower case + function to_lower(c : character) return character is + variable l : character; + begin + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + return l; + end function to_lower; + + + -- convert a string to upper case + function to_upper(s : string) return string is + variable uppercase : string (s'range); + begin + + for i in s'range loop + uppercase(i) := to_upper(s(i)); + end loop; + return uppercase; + + end function to_upper; + + + -- convert a string to lower case + function to_lower(s : string) return string is + variable lowercase : string (s'range); + begin + for i in s'range loop + lowercase(i) := to_lower(s(i)); + end loop; + return lowercase; + end function to_lower; + + + + -- functions to convert strings into other types + ------------------------------------------------ + + -- converts a character into a std_logic + function to_std_logic(c : character) return std_logic is + variable sl : std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end function to_std_logic; + + + -- converts a string into std_logic_vector + function to_std_logic_vector(s : string) return std_logic_vector is + variable slv : std_logic_vector(s'high-s'low downto 0); + variable k : integer; + begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; + end function to_std_logic_vector; + + + + -- file I/O + ------------- + + -- read variable length string from input file + procedure str_read(file in_file : text; res_string : out string) is + variable l : line; + variable c : character; + variable is_string : boolean; + begin + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + end procedure str_read; + + + -- print string to a file + procedure print(file out_file : text; new_string : in string) is + variable l : line; + begin + write(l, new_string); + writeline(out_file, l); + end procedure print; + + + -- print character to a file and start new line + procedure print(file out_file : text; char : in character) is + variable l : line; + begin + write(l, char); + writeline(out_file, l); + end procedure print; + + + -- appends contents of a string to a file until line feed occurs + -- (LF is considered to be the end of the string) + procedure str_write(file out_file : text; new_string : in string) is + begin + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + end procedure str_write; + + +end package body txt_util; + diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd new file mode 100644 index 0000000..9ca9050 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpuio.vhd @@ -0,0 +1,218 @@ +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity zpuio is + port ( + areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0) + ); +end zpuio; + +architecture behave of zpuio is + + signal timer_read : std_logic_vector(7 downto 0); + signal timer_we : std_logic; + -- + signal io_busy : std_logic; + signal io_read : std_logic_vector(7 downto 0); + signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); + signal io_writeEnable : std_logic; + signal Enable : std_logic; + -- + signal din : std_logic_vector(7 downto 0); + signal dout : std_logic_vector(7 downto 0); + signal adr : std_logic_vector(15 downto 0); + signal break : std_logic; + signal we : std_logic; + signal re : std_logic; + -- + -- uart forwarding... + signal uartTXPending : std_logic; + signal uartTXCleared : std_logic; + signal uartData : std_logic_vector(7 downto 0); + -- + signal readingTimer : std_logic; + -- + -- + signal mem_busy : std_logic; + signal mem_read : std_logic_vector(wordSize-1 downto 0); + signal mem_write : std_logic_vector(wordSize-1 downto 0); + signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); + signal mem_writeEnable : std_logic; + signal mem_readEnable : std_logic; + signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + -- + signal dram_mem_busy : std_logic; + signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_writeEnable : std_logic; + signal dram_mem_readEnable : std_logic; + signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + -- + signal io_readEnable : std_logic; + -- + signal dram_read : std_logic; + +begin + + io_addr <= mem_addr(maxAddrBit downto minAddrBit); + + timerinst : timer + port map ( + clk => cpu_clk, + areset => areset, + we => timer_we, + din => mem_write(7 downto 0), + adr => io_addr(4 downto 2), + dout => timer_read + ); + + zpu : zpu_core + port map ( + clk => cpu_clk , + areset => areset, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break + ); + + + ram_imp : dram + port map ( + clk => cpu_clk, + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask + ); + + + fauxUart : process(cpu_clk, areset) + begin + if areset = '1' then + io_busy <= '0'; + uartTXPending <= '0'; + timer_we <= '0'; + io_busy <= '0'; + uartData <= x"58"; -- 'X' + readingTimer <= '0'; + elsif rising_edge(cpu_clk) then + timer_we <= '0'; + io_busy <= '0'; + if uartTXCleared = '1' then + uartTXPending <= '0'; + end if; + + if io_writeEnable = '1' then + if io_addr = x"2028003" then + -- Write to UART + uartData <= mem_write(7 downto 0); + uartTXPending <= '1'; + io_busy <= '1'; + elsif io_addr(12) = '1' then + timer_we <= '1'; + io_busy <= '1'; + else + -- report "Illegal IO write" severity failure; + end if; + end if; + if (io_readEnable = '1') then + if io_addr = x"2028003" then + io_read <= (0 => '1', -- recieve empty + 1 => uartTXPending, -- tx full + others => '0'); + io_busy <= '1'; + elsif io_addr(12) = '1' then + readingTimer <= '1'; + io_busy <= '1'; + elsif io_addr(11) = '1' then + io_read <= ZPU_Frequency; + io_busy <= '1'; + else + -- report "Illegal IO read" severity failure; + end if; + + else + if (readingTimer = '1') then + readingTimer <= '0'; + io_read <= timer_read; + io_busy <= '0'; + else + io_read <= (others => '1'); + end if; + end if; + end if; + end process; + + + forwardUARTOutputToARM : process(cpu_clk, areset) + begin + if areset = '1' then + uartTXCleared <= '0'; + elsif rising_edge(cpu_clkt) then + if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then + uartTXCleared <= cpu_din(0); + else + uartTXCleared <= uartTXCleared; + end if; + end if; + end process; + + cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); + cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_writeEnable <= mem_writeEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol : process(cpu_clk, areset) + begin + if areset = '1' then + dram_read <= '0'; + io_readEnable <= '0'; + + elsif rising_edge(cpu_clk) then + mem_read <= (others => '0'); + if mem_addr(ioBit) = '0' and mem_readEnable = '1' then + dram_read <= '1'; + end if; + if dram_read = '1' and dram_mem_busy = '0' then + dram_read <= '0'; + mem_read <= dram_mem_read; + end if; + + if mem_addr(ioBit) = '1' and mem_readEnable = '1' then + io_readEnable <= '1'; + end if; + if io_readEnable = '1' and io_busy = '0' then + io_readEnable <= '0'; + mem_read(7 downto 0) <= io_read; + end if; + + end if; + end process; + + +end architecture behave; diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh new file mode 100755 index 0000000..44ead41 --- /dev/null +++ b/zpu/hdl/zpu4/test/dmips/build.sh @@ -0,0 +1,4 @@ +zpu-elf-gcc -DTIME ../../../../../../roadshow/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -phi -o dmips.elf +zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf +zpu-elf-objcopy -O binary dmips.elf dmips.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam dmips.bin >dmips.ram diff --git a/zpu/hdl/zpu4/test/dmips/dmips.bin b/zpu/hdl/zpu4/test/dmips/dmips.bin Binary files differnew file mode 100644 index 0000000..ee1a6fe --- /dev/null +++ b/zpu/hdl/zpu4/test/dmips/dmips.bin diff --git a/zpu/hdl/zpu4/test/dmips/dmips.elf b/zpu/hdl/zpu4/test/dmips/dmips.elf Binary files differnew file mode 100644 index 0000000..3a04a5b --- /dev/null +++ b/zpu/hdl/zpu4/test/dmips/dmips.elf diff --git a/zpu/hdl/zpu4/test/dmips/dmips.ram b/zpu/hdl/zpu4/test/dmips/dmips.ram new file mode 100644 index 0000000..0919ce1 --- /dev/null +++ b/zpu/hdl/zpu4/test/dmips/dmips.ram @@ -0,0 +1,3256 @@ +0 => x"0b0b0b0b",
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+2838 => x"00002c4c",
+2839 => x"00002c54",
+2840 => x"00002c54",
+2841 => x"00002c5c",
+2842 => x"00002c5c",
+2843 => x"00002c64",
+2844 => x"00002c64",
+2845 => x"00002c6c",
+2846 => x"00002c6c",
+2847 => x"00002c74",
+2848 => x"00002c74",
+2849 => x"00002c7c",
+2850 => x"00002c7c",
+2851 => x"00002c84",
+2852 => x"00002c84",
+2853 => x"00002c8c",
+2854 => x"00002c8c",
+2855 => x"00002c94",
+2856 => x"00002c94",
+2857 => x"00002c9c",
+2858 => x"00002c9c",
+2859 => x"00002ca4",
+2860 => x"00002ca4",
+2861 => x"00002cac",
+2862 => x"00002cac",
+2863 => x"00002cb4",
+2864 => x"00002cb4",
+2865 => x"00002cbc",
+2866 => x"00002cbc",
+2867 => x"00002cc4",
+2868 => x"00002cc4",
+2869 => x"00002ccc",
+2870 => x"00002ccc",
+2871 => x"00002cd4",
+2872 => x"00002cd4",
+2873 => x"00002cdc",
+2874 => x"00002cdc",
+2875 => x"00002ce4",
+2876 => x"00002ce4",
+2877 => x"00002cec",
+2878 => x"00002cec",
+2879 => x"00002cf4",
+2880 => x"00002cf4",
+2881 => x"00002cfc",
+2882 => x"00002cfc",
+2883 => x"00002d04",
+2884 => x"00002d04",
+2885 => x"00002d0c",
+2886 => x"00002d0c",
+2887 => x"00002d14",
+2888 => x"00002d14",
+2889 => x"00002d1c",
+2890 => x"00002d1c",
+2891 => x"00002d24",
+2892 => x"00002d24",
+2893 => x"00002d2c",
+2894 => x"00002d2c",
+2895 => x"00002d34",
+2896 => x"00002d34",
+2897 => x"00002d3c",
+2898 => x"00002d3c",
+2899 => x"00002d44",
+2900 => x"00002d44",
+2901 => x"00002d4c",
+2902 => x"00002d4c",
+2903 => x"00002d54",
+2904 => x"00002d54",
+2905 => x"00002d5c",
+2906 => x"00002d5c",
+2907 => x"00002d64",
+2908 => x"00002d64",
+2909 => x"00002d6c",
+2910 => x"00002d6c",
+2911 => x"00002d74",
+2912 => x"00002d74",
+2913 => x"00002d7c",
+2914 => x"00002d7c",
+2915 => x"00002d84",
+2916 => x"00002d84",
+2917 => x"00002d8c",
+2918 => x"00002d8c",
+2919 => x"00002d94",
+2920 => x"00002d94",
+2921 => x"00002d9c",
+2922 => x"00002d9c",
+2923 => x"00002da4",
+2924 => x"00002da4",
+2925 => x"00002dac",
+2926 => x"00002dac",
+2927 => x"00002db4",
+2928 => x"00002db4",
+2929 => x"00002dbc",
+2930 => x"00002dbc",
+2931 => x"00002dc4",
+2932 => x"00002dc4",
+2933 => x"00002dcc",
+2934 => x"00002dcc",
+2935 => x"00002dd4",
+2936 => x"00002dd4",
+2937 => x"00002ddc",
+2938 => x"00002ddc",
+2939 => x"00002de4",
+2940 => x"00002de4",
+2941 => x"00002dec",
+2942 => x"00002dec",
+2943 => x"00002df4",
+2944 => x"00002df4",
+2945 => x"00002dfc",
+2946 => x"00002dfc",
+2947 => x"00002e04",
+2948 => x"00002e04",
+2949 => x"00002e0c",
+2950 => x"00002e0c",
+2951 => x"00002e14",
+2952 => x"00002e14",
+2953 => x"00002e1c",
+2954 => x"00002e1c",
+2955 => x"00002e24",
+2956 => x"00002e24",
+2957 => x"00002e2c",
+2958 => x"00002e2c",
+2959 => x"00002e34",
+2960 => x"00002e34",
+2961 => x"00002e3c",
+2962 => x"00002e3c",
+2963 => x"00002e44",
+2964 => x"00002e44",
+2965 => x"00002e4c",
+2966 => x"00002e4c",
+2967 => x"00002e54",
+2968 => x"00002e54",
+2969 => x"00002e5c",
+2970 => x"00002e5c",
+2971 => x"00002e64",
+2972 => x"00002e64",
+2973 => x"00002e6c",
+2974 => x"00002e6c",
+2975 => x"00002e74",
+2976 => x"00002e74",
+2977 => x"00002e7c",
+2978 => x"00002e7c",
+2979 => x"00002e84",
+2980 => x"00002e84",
+2981 => x"00002e8c",
+2982 => x"00002e8c",
+2983 => x"00002e94",
+2984 => x"00002e94",
+2985 => x"00002e9c",
+2986 => x"00002e9c",
+2987 => x"00002ea4",
+2988 => x"00002ea4",
+2989 => x"00002eac",
+2990 => x"00002eac",
+2991 => x"00002eb4",
+2992 => x"00002eb4",
+2993 => x"00002ebc",
+2994 => x"00002ebc",
+2995 => x"00002ec4",
+2996 => x"00002ec4",
+2997 => x"00002ecc",
+2998 => x"00002ecc",
+2999 => x"00002ed4",
+3000 => x"00002ed4",
+3001 => x"00002edc",
+3002 => x"00002edc",
+3003 => x"00002ee4",
+3004 => x"00002ee4",
+3005 => x"00002eec",
+3006 => x"00002eec",
+3007 => x"00002ef4",
+3008 => x"00002ef4",
+3009 => x"00002efc",
+3010 => x"00002efc",
+3011 => x"00002f04",
+3012 => x"00002f04",
+3013 => x"00002f0c",
+3014 => x"00002f0c",
+3015 => x"00002f14",
+3016 => x"00002f14",
+3017 => x"00002f1c",
+3018 => x"00002f1c",
+3019 => x"00002f24",
+3020 => x"00002f24",
+3021 => x"00002f2c",
+3022 => x"00002f2c",
+3023 => x"00002f34",
+3024 => x"00002f34",
+3025 => x"00002f3c",
+3026 => x"00002f3c",
+3027 => x"00002f50",
+3028 => x"00000000",
+3029 => x"000031b8",
+3030 => x"00003214",
+3031 => x"00003270",
+3032 => x"00000000",
+3033 => x"00000000",
+3034 => x"00000000",
+3035 => x"00000000",
+3036 => x"00000000",
+3037 => x"00000000",
+3038 => x"00000000",
+3039 => x"00000000",
+3040 => x"00000000",
+3041 => x"00002ad0",
+3042 => x"00000000",
+3043 => x"00000000",
+3044 => x"00000000",
+3045 => x"00000000",
+3046 => x"00000000",
+3047 => x"00000000",
+3048 => x"00000000",
+3049 => x"00000000",
+3050 => x"00000000",
+3051 => x"00000000",
+3052 => x"00000000",
+3053 => x"00000000",
+3054 => x"00000000",
+3055 => x"00000000",
+3056 => x"00000000",
+3057 => x"00000000",
+3058 => x"00000000",
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+3060 => x"00000000",
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+3062 => x"00000000",
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+3064 => x"00000000",
+3065 => x"00000000",
+3066 => x"00000000",
+3067 => x"00000000",
+3068 => x"00000000",
+3069 => x"00000000",
+3070 => x"00000001",
+3071 => x"330eabcd",
+3072 => x"1234e66d",
+3073 => x"deec0005",
+3074 => x"000b0000",
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+3076 => x"00000000",
+3077 => x"00000000",
+3078 => x"00000000",
+3079 => x"00000000",
+3080 => x"00000000",
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+3083 => x"00000000",
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+3088 => x"00000000",
+3089 => x"00000000",
+3090 => x"00000000",
+3091 => x"00000000",
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+3095 => x"00000000",
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+3097 => x"00000000",
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+3100 => x"00000000",
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+3103 => x"00000000",
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+3140 => x"00000000",
+3141 => x"00000000",
+3142 => x"00000000",
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+3144 => x"00000000",
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+3147 => x"00000000",
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+3150 => x"00000000",
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+3152 => x"00000000",
+3153 => x"00000000",
+3154 => x"00000000",
+3155 => x"00000000",
+3156 => x"00000000",
+3157 => x"00000000",
+3158 => x"00000000",
+3159 => x"00000000",
+3160 => x"00000000",
+3161 => x"00000000",
+3162 => x"00000000",
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+3164 => x"00000000",
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+3166 => x"00000000",
+3167 => x"00000000",
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+3193 => x"00000000",
+3194 => x"00000000",
+3195 => x"00000000",
+3196 => x"00000000",
+3197 => x"00000000",
+3198 => x"00000000",
+3199 => x"00000000",
+3200 => x"00000000",
+3201 => x"00000000",
+3202 => x"00000000",
+3203 => x"00000000",
+3204 => x"00000000",
+3205 => x"00000000",
+3206 => x"00000000",
+3207 => x"00000000",
+3208 => x"00000000",
+3209 => x"00000000",
+3210 => x"00000000",
+3211 => x"00000000",
+3212 => x"00000000",
+3213 => x"00000000",
+3214 => x"00000000",
+3215 => x"00000000",
+3216 => x"00000000",
+3217 => x"00000000",
+3218 => x"00000000",
+3219 => x"00000000",
+3220 => x"00000000",
+3221 => x"00000000",
+3222 => x"00000000",
+3223 => x"00000000",
+3224 => x"00000000",
+3225 => x"00000000",
+3226 => x"00000000",
+3227 => x"00000000",
+3228 => x"00000000",
+3229 => x"00000000",
+3230 => x"00000000",
+3231 => x"00000000",
+3232 => x"00000000",
+3233 => x"00000000",
+3234 => x"00000000",
+3235 => x"00000000",
+3236 => x"00000000",
+3237 => x"00000000",
+3238 => x"00000000",
+3239 => x"00000000",
+3240 => x"00000000",
+3241 => x"00000000",
+3242 => x"00000000",
+3243 => x"00000000",
+3244 => x"00000000",
+3245 => x"00000000",
+3246 => x"00000000",
+3247 => x"00000000",
+3248 => x"00000000",
+3249 => x"00000000",
+3250 => x"00000000",
+3251 => x"00002ad4",
+3252 => x"ffffffff",
+3253 => x"00000000",
+3254 => x"ffffffff",
+3255 => x"00000000",
diff --git a/zpu/hdl/zpu4/test/gpiotest/build.sh b/zpu/hdl/zpu4/test/gpiotest/build.sh new file mode 100755 index 0000000..c0385ad --- /dev/null +++ b/zpu/hdl/zpu4/test/gpiotest/build.sh @@ -0,0 +1,4 @@ +zpu-elf-gcc -O3 -phi `pwd`/gpiotest.c -o gpiotest.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >gpiotest.dis gpiotest.elf +zpu-elf-objcopy -O binary gpiotest.elf gpiotest.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam gpiotest.bin >gpiotest.ram diff --git a/zpu/hdl/zpu4/test/gpiotest/gpiotest.c b/zpu/hdl/zpu4/test/gpiotest/gpiotest.c new file mode 100644 index 0000000..393ab9f --- /dev/null +++ b/zpu/hdl/zpu4/test/gpiotest/gpiotest.c @@ -0,0 +1,72 @@ +/*
+ * Small test program to check GPIOs
+ *
+ * LED chaser until keypress
+ *
+ */
+
+// addresses refer to Phi memory layout
+#define GPIO_DATA *((volatile unsigned int *) 0x080a0004)
+#define GPIO_DIR *((volatile unsigned int *) 0x080a0008)
+
+
+#define BUTTON_EAST (3)
+#define BUTTON_NORTH (2)
+#define BUTTON_SOUTH (1)
+#define BUTTON_WEST (0)
+
+
+#define bit_is_set(var, bit) ((var) & (1 << (bit)))
+#define bit_is_clear(var, bit) ((!(var)) & (1 << (bit)))
+#define loop_until_bit_is_set(var, bit) do { } while (bit_is_clear(var, bit))
+#define loop_until_bit_is_clear(var, bit) do { } while (bit_is_set(var, bit))
+
+
+void led_test( void)
+{
+ unsigned char runs;
+ unsigned char leds;
+
+ runs = 1;
+ leds = 0x01;
+
+ while( runs)
+ {
+ // output
+ GPIO_DATA = leds;
+
+ // read button status
+ if bit_is_set(GPIO_DATA, BUTTON_NORTH)
+ {
+ runs = 0;
+ }
+
+ // LED chaser
+ leds = leds << 1;
+ if (leds == 0)
+ {
+ leds = 0x01;
+ }
+ }
+}
+
+
+void header_test( void)
+{
+ // this test is special for the SP601 header connector
+ // check the output in simulation
+ GPIO_DATA = 0x00550000;
+ GPIO_DIR = 0xff00ffff;
+ GPIO_DATA = 0x00aa0000;
+ GPIO_DIR = 0xffffffff;
+}
+
+
+int main(int argc, char **argv)
+{
+
+ led_test();
+ header_test();
+
+ abort();
+}
diff --git a/zpu/hdl/zpu4/test/hello/build.sh b/zpu/hdl/zpu4/test/hello/build.sh new file mode 100755 index 0000000..dd87410 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/build.sh @@ -0,0 +1,4 @@ +zpu-elf-gcc -O3 -phi `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >hello.dis hello.elf +zpu-elf-objcopy -O binary hello.elf hello.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.ram diff --git a/zpu/hdl/zpu4/test/hello/hello.bin b/zpu/hdl/zpu4/test/hello/hello.bin Binary files differnew file mode 100644 index 0000000..7c37759 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/hello.bin diff --git a/zpu/hdl/zpu4/test/hello/hello.c b/zpu/hdl/zpu4/test/hello/hello.c new file mode 100644 index 0000000..609c163 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/hello.c @@ -0,0 +1,47 @@ +/*
+ * Small hello world example, does not use printf()
+ */
+#include <stdio.h>
+
+int j;
+int k;
+
+int main(int argc, char **argv)
+{
+ int i;
+ for (i=0; i< 10; i++)
+ {
+ puts("Hello world 1\n");
+ puts("Hello world 2\n");
+ j=-4;
+ if ((j>>1)!=-2)
+ {
+ abort();
+ }
+
+ k=10;
+ if (k*j!=-40)
+ {
+ abort();
+ }
+
+ j=10;
+ k=10000000;
+ if (k*j!=100000000)
+ {
+ abort();
+ }
+
+ j=0x80000000;
+ k=0xffffffff;
+ if (j>k)
+ {
+ abort();
+ }
+ }
+ if (i!=10)
+ {
+ abort();
+ }
+
+}
diff --git a/zpu/hdl/zpu4/test/hello/hello.elf b/zpu/hdl/zpu4/test/hello/hello.elf Binary files differnew file mode 100644 index 0000000..73d28e7 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/hello.elf diff --git a/zpu/hdl/zpu4/test/hello/hello.ram b/zpu/hdl/zpu4/test/hello/hello.ram new file mode 100644 index 0000000..175d3a8 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/hello.ram @@ -0,0 +1,3055 @@ +0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
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diff --git a/zpu/hdl/zpu4/test/interrupt/build.sh b/zpu/hdl/zpu4/test/interrupt/build.sh new file mode 100755 index 0000000..3d617e9 --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/build.sh @@ -0,0 +1,4 @@ +zpu-elf-gcc -O3 -phi `pwd`/int.c -o int.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >int.dis int.elf +zpu-elf-objcopy -O binary int.elf int.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam int.bin >int.ram diff --git a/zpu/hdl/zpu4/test/interrupt/int.bin b/zpu/hdl/zpu4/test/interrupt/int.bin Binary files differnew file mode 100644 index 0000000..282f53b --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/int.bin diff --git a/zpu/hdl/zpu4/test/interrupt/int.c b/zpu/hdl/zpu4/test/interrupt/int.c new file mode 100644 index 0000000..6ab28f7 --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/int.c @@ -0,0 +1,40 @@ +/*
+ * Shows usage of interrupts. Goes along with zpu_core_small_wip.vhd.
+ */
+#include <stdio.h>
+
+
+volatile int counter;
+
+/* Example of single, fixed interval non-maskable, nested interrupt. The interrupt signal is
+ * held high for enough cycles to guarantee that it will be noticed, i.e. longer than
+ * any io access + 4 cycles roughly.
+ *
+ * Any non-trivial interrupt controller would have support for
+ * acknowledging interrupts(i.e. keep interrupts asserted until
+ * software acknowledges them via memory mapped IO).
+ */
+void _zpu_interrupt(void)
+{
+ /* interrupts are enabled so we need to finish up quickly,
+ * lest we will get infinite recursion!*/
+ counter++;
+}
+
+int main(int argc, char **argv)
+{
+ int t;
+ t=counter;
+ for (;;)
+ {
+ if (t==counter)
+ {
+ puts("No interrupt\n");
+ } else
+ {
+ puts("Got interrupt\n");
+ t=counter;
+ }
+ }
+
+}
diff --git a/zpu/hdl/zpu4/test/interrupt/int.elf b/zpu/hdl/zpu4/test/interrupt/int.elf Binary files differnew file mode 100644 index 0000000..346d148 --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/int.elf diff --git a/zpu/hdl/zpu4/test/interrupt/int.ram b/zpu/hdl/zpu4/test/interrupt/int.ram new file mode 100644 index 0000000..6751ec2 --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/int.ram @@ -0,0 +1,3057 @@ +0 => x"0b0b0b0b",
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diff --git a/zpu/hdl/zy2000/timer.vhd b/zpu/hdl/zy2000/timer.vhd new file mode 100644 index 0000000..735d55c --- /dev/null +++ b/zpu/hdl/zy2000/timer.vhd @@ -0,0 +1,137 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + sample : in std_logic; + reset : in std_logic; + counter : out std_logic_vector(63 downto 0)); +end timer; + + +architecture behave of timer is + +signal c : std_logic_vector(1 to 7); + +signal cnt : std_logic_vector(63 downto 0); +signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + counter <= cnt_smp; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + c <= "0000000"; + elsif (clk'event and clk = '1') then + if reset = '1' then + c <= "0000000"; + else + if cnt(7 downto 0) = "11111110" then + c(1) <= '1'; + else + c(1) <= '0'; + end if; + if cnt(15 downto 8) = "11111111" then + c(2) <= '1'; + else + c(2) <= '0'; + end if; + if cnt(23 downto 16) = "11111111" and c(2) = '1' then + c(3) <= '1'; + else + c(3) <= '0'; + end if; + if cnt(31 downto 24) = "11111111" and c(3) = '1' then + c(4) <= '1'; + else + c(4) <= '0'; + end if; + if cnt(39 downto 32) = "11111111" and c(4) = '1' then + c(5) <= '1'; + else + c(5) <= '0'; + end if; + if cnt(47 downto 40) = "11111111" and c(5) = '1' then + c(6) <= '1'; + else + c(6) <= '0'; + end if; + if cnt(55 downto 48) = "11111111" and c(6) = '1' then + c(7) <= '1'; + else + c(7) <= '0'; + end if; + end if; + end if; + end process; + + process(clk, areset) + begin + if areset = '1' then + cnt <= (others=>'0'); + elsif (clk'event and clk = '1') then + if reset = '1' then + cnt <= (others=>'0'); + else + cnt(7 downto 0) <= cnt(7 downto 0) + '1'; + if c(1) = '1' then + cnt(15 downto 8) <= cnt(15 downto 8) + '1'; + else + cnt(15 downto 8) <= cnt(15 downto 8); + end if; + if c(2) = '1' and c(1) = '1' then + cnt(23 downto 16) <= cnt(23 downto 16) + '1'; + else + cnt(23 downto 16) <= cnt(23 downto 16); + end if; + if c(3) = '1' and c(1) = '1' then + cnt(31 downto 24) <= cnt(31 downto 24) + '1'; + else + cnt(31 downto 24) <= cnt(31 downto 24); + end if; + if c(4) = '1' and c(1) = '1' then + cnt(39 downto 32) <= cnt(39 downto 32) + '1'; + else + cnt(39 downto 32) <= cnt(39 downto 32); + end if; + if c(5) = '1' and c(1) = '1' then + cnt(47 downto 40) <= cnt(47 downto 40) + '1'; + else + cnt(47 downto 40) <= cnt(47 downto 40); + end if; + if c(6) = '1' and c(1) = '1' then + cnt(55 downto 48) <= cnt(55 downto 48) + '1'; + else + cnt(55 downto 48) <= cnt(55 downto 48); + end if; + if c(7) = '1' and c(1) = '1' then + cnt(63 downto 56) <= cnt(63 downto 56) + '1'; + else + cnt(63 downto 56) <= cnt(63 downto 56); + end if; + end if; + end if; + end process; + + process(clk, areset) + begin + if areset = '1' then + cnt_smp <= (others=>'0'); + elsif (clk'event and clk = '1') then + if reset = '1' then + cnt_smp <= (others=>'0'); + elsif sample = '1' then + cnt_smp <= cnt; + else + cnt_smp <= cnt_smp; + end if; + end if; + end process; + +end behave; + diff --git a/zpu/hdl/zy2000/trace.vhd b/zpu/hdl/zy2000/trace.vhd new file mode 100644 index 0000000..ec6be57 --- /dev/null +++ b/zpu/hdl/zy2000/trace.vhd @@ -0,0 +1,84 @@ +library ieee; +use ieee.std_logic_1164.all; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + + +entity trace is + generic ( + log_file: string := "trace.txt" + ); + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); +end trace; + + +architecture behave of trace is + + +file l_file : TEXT open write_mode is log_file; + + +begin + + +-- write data and control information to a file + +receive_data: process + +variable l: line; +variable t : std_logic_vector(wordSize-1 downto 0); +variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); +variable counter : std_logic_vector(63 downto 0); + + + +begin + + t:= (others => '0'); + t2:= (others => '0'); + +counter := (others => '0'); + -- print header for the logfile + print(l_file, "#pc,opcode,sp,top_of_stack "); + print(l_file, "#----------"); + print(l_file, " "); + + wait until clk = '1'; + wait until clk = '0'; + + while true loop + + counter := counter + 1; + if begin_inst = '1' then + t(maxAddrBitIncIO downto 2):=sp; + t2:=pc; + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter)); + end if; + + wait until clk = '0'; + + end loop; + + end process receive_data; + + + +end behave; + diff --git a/zpu/hdl/zy2000/txt_util.vhd b/zpu/hdl/zy2000/txt_util.vhd new file mode 100644 index 0000000..40d39b9 --- /dev/null +++ b/zpu/hdl/zy2000/txt_util.vhd @@ -0,0 +1,587 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + +library work; + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + diff --git a/zpu/hdl/zy2000/zpu_config.vhd b/zpu/hdl/zy2000/zpu_config.vhd new file mode 100644 index 0000000..c0df294 --- /dev/null +++ b/zpu/hdl/zy2000/zpu_config.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 27; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; + +end zpu_config; diff --git a/zpu/hdl/zy2000/zpu_config_fast.vhd b/zpu/hdl/zy2000/zpu_config_fast.vhd new file mode 100644 index 0000000..c0df294 --- /dev/null +++ b/zpu/hdl/zy2000/zpu_config_fast.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 27; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; + +end zpu_config; diff --git a/zpu/hdl/zy2000/zpu_core.vhd b/zpu/hdl/zy2000/zpu_core.vhd new file mode 100644 index 0000000..2450f14 --- /dev/null +++ b/zpu/hdl/zy2000/zpu_core.vhd @@ -0,0 +1,948 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + mem_req : out std_logic; + mem_we : out std_logic; + mem_ack : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic; + zpu_status : out std_logic_vector(63 downto 0)); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_Interrupt, +State_InsnFetch +); + +type StateType is +( +State_Idle, -- using first state first on the list out of paranoia +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult6, +State_Mult4, +State_BinaryOpResult +); + + +signal pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal stackA : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); +signal multResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult3 : std_logic_vector(wordSize-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); +signal multA : std_logic_vector(wordSize-1 downto 0); +signal multB : std_logic_vector(wordSize-1 downto 0); +signal stackB : std_logic_vector(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; +signal mem_busy : std_logic; +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +signal out_mem_req : std_logic; + +signal inInterrupt : std_logic; + +-- state machine. + +begin + + zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; + zpu_status(31) <= '1'; + zpu_status(39 downto 32) <= trace_opcode; + zpu_status(40) <= '1' when (state = State_Idle) else '0'; + zpu_status(62) <= '1'; + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + mem_req <= out_mem_req; + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable tSpOffset : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= spStart(maxAddrBitIncIO downto minAddrBit); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_we <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + out_mem_req <= '0'; + mem_addr <= (others => DontCareValue); + mem_write <= (others => DontCareValue); + inInterrupt <= '0'; + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); + trace_pc <= pc; + trace_sp <= sp; + trace_topOfStack <= stackA; + trace_topOfStackB <= stackB; + begin_inst <= '0'; + + -- we terminate the requeset as soon as we get acknowledge + if mem_ack = '1' then + out_mem_req <= '0'; + mem_we <= '0'; + end if; + + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if mem_busy='0' then + mem_addr <= sp; + out_mem_req <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if mem_busy='0' then + stackA <= mem_read; + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if mem_busy='0' then + stackB <= mem_read; + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=tOpcode(3 downto 0); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + else + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + end if; + else + insn <= insn; + end if; + when State_StoreSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= sp+spOffset; + mem_write <= stackA; + stackA <= stackB; + sp <= incSp; + else + insn <= insn; + end if; + + + when State_LoadSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_Emulate => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Callpcrel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Call => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_AddSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + out_mem_req <= '1'; + mem_addr <= sp+spOffset; + else + insn <= insn; + end if; + when State_PushSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_PopPC => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopPCRel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_Add => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Sub => + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + when State_Pop => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + else + insn <= insn; + end if; + when State_PopDown => + if mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Or => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_And => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Eq => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Ulessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Ulessthanorequal => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Lessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Lessthanorequal => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Load => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when State_Dup => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_DupStackB => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_Store => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= stackB; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= incIncSp; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + else + insn <= insn; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + when State_Storeb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when others => +-- sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if mem_busy='0' then + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if mem_busy='0' then + state <= State_LoadSP3; + out_mem_req <= '1'; + mem_addr <= sp+spOffset+1; + end if; + when State_LoadSP3 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= mem_read; + end if; + when State_AddSP2 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + mem_read; + end if; + when State_Load2 => + if mem_busy='0' then + stackA <= mem_read; + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if mem_busy='0' then + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= mem_read; + mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; + out_mem_req <= '1'; + mem_we <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if mem_busy='0' then + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt + inInterrupt <= '1'; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + + report "ZPU jumped to interrupt!" severity note; + else + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + stackA <= multResult3; + state <= State_Mult6; + when State_Mult6 => + if mem_busy='0' then + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + if mem_busy='0' then + -- NB!!!! we know that the memory isn't busy at this point!!!! + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + stackA <= binaryOpResult; + state <= State_Popped; + end if; + when State_Popped => + if mem_busy='0' then + pc <= pc + 1; + stackB <= mem_read; + state <= State_Execute; + end if; + when others => +-- sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zy2000/zpupkg.vhd b/zpu/hdl/zy2000/zpupkg.vhd new file mode 100644 index 0000000..a7e6cf1 --- /dev/null +++ b/zpu/hdl/zy2000/zpupkg.vhd @@ -0,0 +1,168 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; + +library work; +use work.zpu_config.all; + +package zpupkg is + + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + component dram is + port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); + end component; + + + component trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component; + + component zpu_core is + port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + mem_req : out std_logic; + mem_we : out std_logic; + mem_ack : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic; + zpu_status : out std_logic_vector(63 downto 0)); + end component; + + + + component timer is + port( + clk : in std_logic; + areset : in std_logic; + sample : in std_logic; + reset : in std_logic; + counter : out std_logic_vector(63 downto 0)); + end component; + + component zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + + + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); + + constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); + constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6); + + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); + constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6); + + constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); + constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); + + constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); + + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6); + + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); + + + + constant OpCode_Size : integer := 8; + + + +end zpupkg; |
