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-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut39
1 files changed, 39 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut
new file mode 100644
index 0000000..e0159fb
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut
@@ -0,0 +1,39 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:2
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g InitPin:Pullup
+-g CsPin:Pullup
+-g DinPin:Pullup
+-g BusyPin:Pullup
+-g RdWrPin:Pullup
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ConfigFallback:Enable
+-g SelectMAPAbort:Enable
+-g BPI_page_size:1
+-g OverTempPowerDown:Disable
+-g JTAG_SysMon:Enable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g Encrypt:No
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