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| author | Bert Lange <b.lange@hzdr.de> | 2011-10-25 23:26:36 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@hzdr.de> | 2011-10-25 23:26:36 +0200 |
| commit | c883cd4a4e4fa1974e5d7d72a79240de88bd26da (patch) | |
| tree | ff3c0f3f7aa62f809001ea9ac9130683ab98a49e /zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj | |
| parent | 105f8b40509ea2657e36e13af76b7580029fd2e5 (diff) | |
| download | zpu-c883cd4a4e4fa1974e5d7d72a79240de88bd26da.zip zpu-c883cd4a4e4fa1974e5d7d72a79240de88bd26da.tar.gz | |
add: GPIO module to zealot SoC
Diffstat (limited to 'zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj')
| -rw-r--r-- | zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj index 81d56ef..24120d5 100644 --- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj @@ -12,6 +12,7 @@ vhdl zpu ../../../helpers/zpu_med1.vhdl vhdl zpu ../../../devices/txt_util.vhdl vhdl zpu ../../../devices/phi_io.vhdl vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/gpio.vhdl vhdl zpu ../../../devices/rx_unit.vhdl vhdl zpu ../../../devices/tx_unit.vhdl vhdl zpu ../../../devices/br_gen.vhdl |
