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authorBert Lange <b.lange@hzdr.de>2011-10-25 23:26:36 +0200
committerBert Lange <b.lange@hzdr.de>2011-10-25 23:26:36 +0200
commitc883cd4a4e4fa1974e5d7d72a79240de88bd26da (patch)
treeff3c0f3f7aa62f809001ea9ac9130683ab98a49e
parent105f8b40509ea2657e36e13af76b7580029fd2e5 (diff)
downloadzpu-c883cd4a4e4fa1974e5d7d72a79240de88bd26da.zip
zpu-c883cd4a4e4fa1974e5d7d72a79240de88bd26da.tar.gz
add: GPIO module to zealot SoC
-rw-r--r--zpu/hdl/zealot/devices/gpio.vhdl107
-rw-r--r--zpu/hdl/zealot/devices/phi_io.vhdl71
-rwxr-xr-xzpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh1
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do56
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf13
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj1
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd58
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd3
-rwxr-xr-xzpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh1
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do6
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do30
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj37
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut44
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst112
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd866
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd559
-rw-r--r--zpu/hdl/zealot/fpga/dmips_med1.vhdl8
-rw-r--r--zpu/hdl/zealot/fpga/dmips_small1.vhdl8
-rw-r--r--zpu/hdl/zealot/fpga/hello_med1.vhdl8
-rw-r--r--zpu/hdl/zealot/fpga/hello_small1.vhdl8
-rwxr-xr-xzpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh1
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do4
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj37
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut60
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst106
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf606
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd1096
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd800
-rw-r--r--zpu/hdl/zealot/helpers/zpu_med1.vhdl29
-rw-r--r--zpu/hdl/zealot/helpers/zpu_small1.vhdl29
-rw-r--r--zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl9
-rw-r--r--zpu/hdl/zealot/testbenches/small1_tb.vhdl9
-rw-r--r--zpu/hdl/zealot/zpu_pkg.vhdl27
33 files changed, 2590 insertions, 2220 deletions
diff --git a/zpu/hdl/zealot/devices/gpio.vhdl b/zpu/hdl/zealot/devices/gpio.vhdl
new file mode 100644
index 0000000..fc66bde
--- /dev/null
+++ b/zpu/hdl/zealot/devices/gpio.vhdl
@@ -0,0 +1,107 @@
+--
+-- this module desribes a simple GPIO interface
+--
+-- data on port_in is synhronized to clk_i and can be read at
+-- address 0
+--
+-- any write to address 0 is mapped to port_out
+--
+-- at address 1 is a direction register (port_dir)
+-- initialized with '1's, what mean direction = in
+-- this register is useful for bidirectional pins, e.g. headers
+--
+--
+-- some examples:
+--
+-- to connect 4 buttons:
+-- port_in( 3 downto 0) <= gpio_button;
+--
+--
+-- to connect 8 LEDs:
+-- gpio_led <= port_out(7 downto 0);
+--
+--
+-- to connect 2 bidirectional header pins:
+-- port_in(8) <= gpio_pin(0);
+-- gpio_pin(0) <= port_out(8) when port_dir(8) = '0' else 'Z';
+--
+-- port_in(9) <= gpio_pin(1);
+-- gpio_pin(1) <= port_out(9) when port_dir(9) = '0' else 'Z';
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity gpio is
+ port(
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ --
+ we_i : in std_logic;
+ data_i : in unsigned(31 downto 0);
+ addr_i : in unsigned( 0 downto 0);
+ data_o : out unsigned(31 downto 0);
+ --
+ port_in : in std_logic_vector(31 downto 0);
+ port_out : out std_logic_vector(31 downto 0);
+ port_dir : out std_logic_vector(31 downto 0)
+ );
+end entity gpio;
+
+
+architecture rtl of gpio is
+
+ signal port_in_reg : std_logic_vector(31 downto 0);
+ signal port_in_sync : std_logic_vector(31 downto 0);
+ --
+ signal direction : std_logic_vector(31 downto 0) := (others => '1');
+
+begin
+
+ process
+ begin
+ wait until rising_edge( clk_i);
+
+ -- synchronize all inputs with two registers
+ -- to avoid metastability
+ port_in_reg <= port_in;
+ port_in_sync <= port_in_reg;
+
+ -- write access to gpio
+ if we_i = '1' then
+ -- data
+ if addr_i = "0" then
+ port_out <= std_logic_vector( data_i);
+ end if;
+ -- direction
+ if addr_i = "1" then
+ direction <= std_logic_vector( data_i);
+ end if;
+ end if;
+
+ -- read access to gpio
+ -- data
+ if addr_i = "0" then
+ data_o <= unsigned( port_in_sync);
+ end if;
+ -- direction
+ if addr_i = "1" then
+ data_o <= unsigned( direction);
+ end if;
+
+ -- outputs
+ port_dir <= direction;
+
+ -- sync reset
+ if reset_i = '1' then
+ direction <= (others => '1');
+ port_in_reg <= (others => '0');
+ port_in_sync <= (others => '0');
+ end if;
+
+ end process;
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/devices/phi_io.vhdl b/zpu/hdl/zealot/devices/phi_io.vhdl
index 99e0f8f..71e881c 100644
--- a/zpu/hdl/zealot/devices/phi_io.vhdl
+++ b/zpu/hdl/zealot/devices/phi_io.vhdl
@@ -56,7 +56,8 @@ use IEEE.numeric_std.all;
use std.textio.all;
library zpu;
-use zpu.zpupkg.all;
+use zpu.zpupkg.timer;
+use zpu.zpupkg.gpio;
use zpu.UART.all;
use zpu.txt_util.all;
@@ -73,25 +74,31 @@ entity ZPUPhiIO is
re_i : in std_logic; -- Read Enable
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
- addr_i : in unsigned(2 downto 0); -- Address bits 4-2
+ addr_i : in unsigned(2 downto 0); -- Address bits 4-2
+ --
rs232_rx_i : in std_logic; -- UART Rx input
rs232_tx_o : out std_logic; -- UART Tx output
- br_clk_i : in std_logic); -- UART base clock (enable)
+ br_clk_i : in std_logic; -- UART base clock (enable)
+ --
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
end entity ZPUPhiIO;
architecture Behave of ZPUPhiIO is
- constant LOW_BITS : unsigned(1 downto 0):=(others=>'0');
- constant TX_FULL : std_logic:='0';
- constant RX_EMPTY : std_logic:='1';
+ constant LOW_BITS : unsigned(1 downto 0):=(others=>'0');
+ constant TX_FULL : std_logic:='0';
+ constant RX_EMPTY : std_logic:='1';
-- "000" 0x00 is CPU enable ... useful?
- -- "001" 0x04 Unused
- -- "010" 0x08 Unused
- constant UART_TX : unsigned(2 downto 0):="011"; -- 0x0C
- constant UART_RX : unsigned(2 downto 0):="100"; -- 0x10
- constant CNT_1 : unsigned(2 downto 0):="101"; -- 0x14
- constant CNT_2 : unsigned(2 downto 0):="110"; -- 0x18
+ constant IO_DATA : unsigned(2 downto 0):="001"; -- 0x04
+ constant IO_DIR : unsigned(2 downto 0):="010"; -- 0x08
+ constant UART_TX : unsigned(2 downto 0):="011"; -- 0x0C
+ constant UART_RX : unsigned(2 downto 0):="100"; -- 0x10
+ constant CNT_1 : unsigned(2 downto 0):="101"; -- 0x14
+ constant CNT_2 : unsigned(2 downto 0):="110"; -- 0x18
-- "111" 0x1C Unused
-- Unimplemented: Interrupt control and timer (not counter ...?)
@@ -110,7 +117,13 @@ architecture Behave of ZPUPhiIO is
signal uart_write : std_logic; -- ZPU is writing
signal tx_busy : std_logic; -- Tx can't get a new value
+ -- GPIO
+ signal gpio_we : std_logic;
+ signal is_gpio : std_logic;
+ signal gpio_read : unsigned(31 downto 0);
+
file l_file : text open write_mode is LOG_FILE;
+
begin
-----------
-- Timer --
@@ -155,6 +168,27 @@ begin
generic map(COUNT => 4)
port map(
clk_i => clk_i, reset_i => reset_i, ce_i => rx_br, o_o => tx_br);
+
+ ----------
+ -- GPIO --
+ ----------
+ gpio_i0: gpio
+ port map(
+ clk_i => clk_i, -- : in std_logic;
+ reset_i => reset_i, -- : in std_logic;
+ --
+ we_i => gpio_we, -- : in std_logic;
+ data_i => data_i, -- : in unsigned(31 downto 0);
+ addr_i => addr_i(1 downto 1), -- : in unsigned( 0 downto 0);
+ data_o => gpio_read, -- : out unsigned(31 downto 0);
+ --
+ port_in => gpio_in, -- : std_logic_vector(31 downto 0);
+ port_out => gpio_out, -- : std_logic_vector(31 downto 0);
+ port_dir => gpio_dir -- : std_logic_vector(31 downto 0);
+ );
+ is_gpio <= '1' when addr_i = IO_DATA or addr_i = IO_DIR else '0'; -- 0x80A0004/8
+ gpio_we <= we_i and is_gpio;
+
do_io:
process(clk_i)
@@ -177,8 +211,10 @@ begin
else
std.textio.write(line_out, char);
end if;
+ elsif is_gpio = '1' and ENA_LOG then
+ print("- Write GPIO: 0x" & hstr(data_i));
elsif is_timer='1' and ENA_LOG then
- print("- Write to TIMER: 0x"&hstr(data_i));
+ print("- Write to TIMER: 0x" & hstr(data_i));
else
--print(l_file,character'val(to_integer(data_i)));
report "Illegal IO data_i=0x"&hstr(data_i)&" @0x"&
@@ -188,7 +224,12 @@ begin
--synopsys translate on
data_o <= (others => '0');
if re_i='1' then
- if addr_i=UART_TX then
+ if is_gpio = '1' then
+ if ENA_LOG then
+ print("- Read GPIO: 0x" & hstr(gpio_read));
+ end if;
+ data_o <= gpio_read;
+ elsif addr_i=UART_TX then
if ENA_LOG then
print("- Read UART Tx");
end if;
@@ -201,7 +242,7 @@ begin
data_o(7 downto 0) <= unsigned(rx_data);
elsif is_timer='1' then
if ENA_LOG then
- print("- Read TIMER: 0x"&hstr(timer_read));
+ print("- Read TIMER: 0x" & hstr(timer_read));
end if;
data_o <= timer_read;
else
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
index febf588..d525737 100755
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
@@ -28,6 +28,7 @@ vcom -work zpu ../../helpers/zpu_med1.vhdl
vcom -work zpu ../../devices/txt_util.vhdl
vcom -work zpu ../../devices/phi_io.vhdl
vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
vcom -work zpu ../../devices/rx_unit.vhdl
vcom -work zpu ../../devices/tx_unit.vhdl
vcom -work zpu ../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
index 20e68e0..d572a06 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
@@ -1,26 +1,30 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /top_tb/tb_gpio_button(0)
-add wave -noupdate /top_tb/tb_clk_100mhz
-add wave -noupdate -divider <NULL>
-add wave -noupdate /top_tb/tb_rs232_rx
-add wave -noupdate /top_tb/tb_rs232_tx
-add wave -noupdate /top_tb/tb_rs232_rts
-add wave -noupdate /top_tb/tb_rs232_cts
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {0 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 2
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {1188293312 ps}
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_gpio_button(0)
+add wave -noupdate /top_tb/tb_clk_100MHz
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_rs232_rx
+add wave -noupdate /top_tb/tb_rs232_tx
+add wave -noupdate /top_tb/tb_rs232_rts
+add wave -noupdate /top_tb/tb_rs232_cts
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_gpio_button
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/tb_gpio_led_n
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {126912555 ps}
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
index 30b3982..8494af3 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
@@ -29,6 +29,19 @@ TIMESPEC "TS_clk_100" = PERIOD "clk_100" 100 MHz;
############################################################
+## design placement constraints
+############################################################
+#
+# the following constraint are need if you want to synthesize
+# zpu_medium with 125 MHz
+#
+INST "zpu_i0_medium.zpu_i0/zpu/*" AREA_GROUP = "zpu_block";
+AREA_GROUP "zpu_block" RANGE=SLICE_X18Y0:SLICE_X55Y41;
+AREA_GROUP "zpu_block" RANGE=DSP48_X0Y0:DSP48_X0Y15;
+AREA_GROUP "zpu_block" RANGE=RAMB36_X1Y0:RAMB36_X3Y7;
+
+
+############################################################
## pin placement constraints
############################################################
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
index 81d56ef..24120d5 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
@@ -12,6 +12,7 @@ vhdl zpu ../../../helpers/zpu_med1.vhdl
vhdl zpu ../../../devices/txt_util.vhdl
vhdl zpu ../../../devices/phi_io.vhdl
vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
vhdl zpu ../../../devices/rx_unit.vhdl
vhdl zpu ../../../devices/tx_unit.vhdl
vhdl zpu ../../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
index 1e2fa97..53383cc 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
@@ -22,7 +22,7 @@ use unisim.vcomponents.dcm_base;
entity top is
port (
-- pragma translate_off
- stop_simulation : out std_logic;
+ stop_simulation : out std_logic;
-- pragma translate_on
clk_100MHz : in std_logic; -- 100 MHz clock
clk_socket : in std_logic; -- user clock
@@ -169,7 +169,10 @@ architecture rtl of top is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end component zpu_small1;
@@ -188,7 +191,10 @@ architecture rtl of top is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end component zpu_med1;
@@ -210,7 +216,11 @@ architecture rtl of top is
--
signal ibufds_i0_o : std_ulogic;
signal ibufds_i1_o : std_ulogic;
-
+ --
+ signal gpio_in : std_logic_vector(31 downto 0) := (others => '0');
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
begin
-- default output drivers
@@ -348,12 +358,15 @@ begin
clk_freq => clk_frequency * clk_multiply / clk_divide
)
port map (
- clk_i => clk, -- : in std_logic; - CPU clock
- rst_i => reset_sync, -- : in std_logic; - Reset
- break_o => zpu_i0_break, -- : out std_logic; - Break executed
- dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info
- rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx
- rs232_rx_i => rs232_rx -- : in std_logic - UART Rx
+ clk_i => clk, -- : in std_logic; - CPU clock
+ rst_i => reset_sync, -- : in std_logic; - Reset
+ break_o => zpu_i0_break, -- : out std_logic; - Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info
+ rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx
+ rs232_rx_i => rs232_rx, -- : in std_logic - UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end generate zpu_i0_small;
@@ -365,12 +378,15 @@ begin
clk_freq => clk_frequency * clk_multiply / clk_divide
)
port map (
- clk_i => clk, -- : in std_logic; - CPU clock
- rst_i => reset_sync, -- : in std_logic; - Reset
- break_o => zpu_i0_break, -- : out std_logic; - Break executed
- dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info
- rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx
- rs232_rx_i => rs232_rx -- : in std_logic - UART Rx
+ clk_i => clk, -- : in std_logic; - CPU clock
+ rst_i => reset_sync, -- : in std_logic; - Reset
+ break_o => zpu_i0_break, -- : out std_logic; - Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info
+ rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx
+ rs232_rx_i => rs232_rx, -- : in std_logic - UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end generate zpu_i0_medium;
@@ -392,17 +408,21 @@ begin
);
-- pragma translate_on
+ -- assign GPIOs
+ -- no bidirectional pins (e.g. headers), so
+ -- gpio_dir is unused
+ gpio_in(15 downto 8) <= gpio_dipswitch;
+ gpio_in( 3 downto 0) <= gpio_button;
+
-- switch on all LEDs in case of break
process
begin
wait until rising_edge(clk);
+ gpio_led_n <= not zpu_i0_gpio_out(7 downto 0);
if zpu_i0_break = '1' then
gpio_led_n <= (others => '0');
end if;
- if reset_sync = '1' then
- gpio_led_n <= (others => '1');
- end if;
end process;
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
index 0d173e2..751ce22 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
@@ -144,6 +144,9 @@ begin
tb_gpio_button(0) <= '1', '0' after 6.66 * clk_100MHz_period;
+ -- simulate keypress
+ tb_gpio_button(2) <= '0', '1' after 55 us, '0' after 56 us;
+
-- dut
top_i0 : entity work.top
port map (
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
index febf588..d525737 100755
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
@@ -28,6 +28,7 @@ vcom -work zpu ../../helpers/zpu_med1.vhdl
vcom -work zpu ../../devices/txt_util.vhdl
vcom -work zpu ../../devices/phi_io.vhdl
vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
vcom -work zpu ../../devices/rx_unit.vhdl
vcom -work zpu ../../devices/tx_unit.vhdl
vcom -work zpu ../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
index 7c5e18f..0d29e0a 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
@@ -1,4 +1,2 @@
-add wave tb_rot_center
-add wave tb_clk_50mhz
-add wave tb_rs232_dce*
-run -all
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do
new file mode 100644
index 0000000..12582ce
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_rot_center
+add wave -noupdate /top_tb/tb_clk_50mhz
+add wave -noupdate /top_tb/tb_rs232_dce_rxd
+add wave -noupdate /top_tb/tb_rs232_dce_txd
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_btn_east
+add wave -noupdate /top_tb/tb_btn_north
+add wave -noupdate /top_tb/tb_btn_south
+add wave -noupdate /top_tb/tb_btn_west
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/top_i0/led
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {56714893 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {151772250 ps}
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
index 81d56ef..965ae4c 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
@@ -1,18 +1,19 @@
-vhdl work ../top.vhd
-vhdl zpu ../../../zpu_pkg.vhdl
-vhdl zpu ../../../zpu_small.vhdl
-vhdl zpu ../../../zpu_medium.vhdl
-vhdl zpu ../../../roms/rom_pkg.vhdl
-#vhdl zpu ../../../roms/hello_dbram.vhdl
-#vhdl zpu ../../../roms/hello_bram.vhdl
-vhdl zpu ../../../roms/dmips_dbram.vhdl
-vhdl zpu ../../../roms/dmips_bram.vhdl
-vhdl zpu ../../../helpers/zpu_small1.vhdl
-vhdl zpu ../../../helpers/zpu_med1.vhdl
-vhdl zpu ../../../devices/txt_util.vhdl
-vhdl zpu ../../../devices/phi_io.vhdl
-vhdl zpu ../../../devices/timer.vhdl
-vhdl zpu ../../../devices/rx_unit.vhdl
-vhdl zpu ../../../devices/tx_unit.vhdl
-vhdl zpu ../../../devices/br_gen.vhdl
-vhdl zpu ../../../devices/trace.vhdl
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
index 06de8d5..4bf13c6 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
@@ -1,22 +1,22 @@
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g ConfigRate:1
--g ProgPin:PullUp
--g DonePin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g DCMShutdown:Disable
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
index fc7cc1d..d357860 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
@@ -1,56 +1,56 @@
-set -tmpdir "tmp"
-set -xsthdpdir "xst"
-run
--ifn ../synthesis_config/top.prj
--ifmt mixed
--ofn top
--ofmt NGC
--p xc3s500e-4-fg320
--top top
--opt_mode Speed
--opt_level 1
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract Yes
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--rom_style Auto
--auto_bram_packing NO
--mux_extract Yes
--resource_sharing YES
--async_to_sync NO
--mult_style Auto
--iobuf YES
--max_fanout 500
--bufg 24
--register_duplication YES
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set Yes
--use_sync_reset Yes
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s500e-4-fg320
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
index 127f6a8..79668e5 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
@@ -1,419 +1,447 @@
--- top module of
--- Spartan-3E Starter Kit Board
---
--- using following external connections:
--- rotary pushbutton as reset
--- LEDs for output
--- RS232 (DCE, the left one)
---
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-library zpu;
-use zpu.zpupkg.all; -- zpu_dbgo_t
-
-library unisim;
-use unisim.vcomponents.dcm_sp;
-
-
-entity top is
- port (
- -- pragma translate_off
- stop_simulation : out std_logic;
- -- pragma translate_on
- --
- -- Analog-to-Digital Converter (ADC)
- ad_conv : out std_logic;
- -- Programmable Gain Amplifier (AMP)
- amp_cs : out std_logic; -- active low chip select
- amp_dout : in std_logic;
- amp_shdn : out std_logic; -- active high shutdown, reset
- -- Pushbuttons (BTN)
- btn_east : in std_logic;
- btn_north : in std_logic;
- btn_south : in std_logic;
- btn_west : in std_logic;
- -- Clock inputs (CLK)
- clk_50mhz : in std_logic;
- clk_aux : in std_logic;
- clk_sma : in std_logic;
- -- Digital-to-Analog Converter (DAC)
- dac_clr : out std_logic; -- async, active low reset input
- dac_cs : out std_logic; -- active low chip select, conv start with rising edge
- -- 1-Wire Secure EEPROM (DS)
- ds_wire : inout std_logic;
- -- Ethernet PHY (E)
- e_col : in std_logic; -- MII collision detect
- e_crs : in std_logic; -- carrier sense
- e_mdc : out std_logic; -- management clock
- e_mdio : inout std_logic; -- management data io
- e_rx_clk : in std_logic; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
- e_rx_dv : in std_logic; -- receive data valid
- e_rxd : in std_logic_vector(3 downto 0);
- e_rx_er : in std_logic;
- e_tx_clk : in std_logic; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
- e_tx_en : out std_logic; -- transmit enable
- e_txd : out std_logic_vector(3 downto 0);
- e_tx_er : out std_logic;
- -- FPGA Configuration Mode, INIT_B Pins (FPGA)
- fpga_m0 : inout std_logic;
- fpga_m1 : inout std_logic;
- fpga_m2 : inout std_logic;
- fpga_init_b : inout std_logic;
- fpga_rdwr_b : in std_logic;
- fpga_hswap : in std_logic;
- -- FX2 Connector (FX2)
- fx2_clkin : inout std_logic;
- fx2_clkio : inout std_logic;
- fx2_clkout : inout std_logic;
- fx2_io : inout std_logic_vector(40 downto 1);
- -- These are shared connections with the FX2 connector
- --j1 : inout std_logic_vector(3 downto 0);
- --j2 : inout std_logic_vector(3 downto 0);
- --j4 : inout std_logic_vector(3 downto 0);
- --led : out std_logic_vector(7 downto 0);
- -- Character LCD (LCD)
- lcd_e : out std_logic;
- lcd_rs : out std_logic;
- lcd_rw : out std_logic;
- -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
- --sf_d : inout std_ulogic_vector(11 downto 8);
- -- PS/2 Mouse/Keyboard Port (PS2)
- ps2_clk : inout std_logic;
- ps2_data : inout std_logic;
- -- Rotary Pushbutton Switch (ROT)
- rot_a : in std_logic;
- rot_b : in std_logic;
- rot_center : in std_logic;
- -- RS-232 Serial Ports (RS232)
- rs232_dce_rxd : in std_logic;
- rs232_dce_txd : out std_logic;
- rs232_dte_rxd : in std_logic;
- rs232_dte_txd : out std_logic;
- -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
- sd_a : out std_logic_vector(12 downto 0); -- address inputs
- sd_dq : inout std_logic_vector(15 downto 0); -- data io
- sd_ba : out std_logic_vector(1 downto 0); -- bank address inputs
- sd_ras : out std_logic; -- command output
- sd_cas : out std_logic; -- command output
- sd_we : out std_logic; -- command output
- sd_udm : out std_logic; -- data mask
- sd_ldm : out std_logic; -- data mask
- sd_udqs : inout std_logic; -- data strobe
- sd_ldqs : inout std_logic; -- data strobe
- sd_cs : out std_logic; -- active low chip select
- sd_cke : out std_logic; -- active high clock enable
- sd_ck_n : out std_logic; -- differential clock
- sd_ck_p : out std_logic; -- differential clock
- -- Path to allow connection to top DCM connection
- sd_ck_fb : in std_logic;
- -- Intel StrataFlash Parallel NOR Flash (SF)
- sf_a : out std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32
- sf_byte : out std_logic;
- sf_ce0 : out std_logic;
- sf_d : inout std_logic_vector(15 downto 1);
- sf_oe : out std_logic;
- sf_sts : in std_logic;
- sf_we : out std_logic;
- -- STMicro SPI serial Flash (SPI)
- spi_mosi : out std_logic; -- master out slave in
- spi_miso : in std_logic; -- master in slave out
- spi_sck : out std_logic; -- clock
- spi_ss_b : out std_logic; -- active low slave select
- spi_alt_cs_jp11 : out std_logic;
- -- Slide Switches (SW)
- sw : in std_logic_vector(3 downto 0);
- -- VGA Port (VGA)
- vga_blue : out std_logic;
- vga_green : out std_logic;
- vga_hsync : out std_logic;
- vga_red : out std_logic;
- vga_vsync : out std_logic;
- -- Xilinx CPLD (XC)
- xc_cmd : out std_logic_vector(1 downto 0);
- xc_cpld_en : out std_logic;
- xc_d : inout std_logic_vector(2 downto 0);
- xc_trig : in std_logic;
- xc_gck0 : inout std_logic;
- gclk10 : inout std_logic
- );
-end entity top;
-
-
-architecture rtl of top is
-
- ---------------------------
- -- type declarations
- type zpu_type is (zpu_small, zpu_medium);
-
- ---------------------------
- -- constant declarations
- constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
- -- modify frequency here
- constant clk_multiply : positive := 3; -- 2 for small, 3 for medium
- constant clk_divide : positive := 2; -- 1 for small, 2 for medium
- --
- constant word_size_c : natural := 32; -- 32 bits data path
- constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
-
-
- constant spi_ss_b_disable : std_ulogic := '1'; -- 1 = disable SPI serial flash
- constant dac_cs_disable : std_ulogic := '1'; -- 1 = disable DAC
- constant amp_cs_disable : std_ulogic := '1'; -- 1 = disable programmable pre-amplifier
- constant ad_conv_disable : std_ulogic := '0'; -- 0 = disable ADC
- constant sf_ce0_disable : std_ulogic := '1';
- constant fpga_init_b_disable : std_ulogic := '1'; -- 1 = disable pflatform flash PROM
- --
- -- connect ldc to fpga
- constant sf_ce0_lcd_to_fpga : std_ulogic := '1';
- --
- constant clk_frequency : positive := 50; -- input frequency for correct calculation
-
-
- ---------------------------
- -- component declarations
- component zpu_small1 is
- generic (
- word_size : natural := 32; -- 32 bits data path
- d_care_val : std_logic := '0'; -- Fill value
- clk_freq : positive := 50; -- 50 MHz clock
- brate : positive := 115200; -- RS232 baudrate
- addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
- bram_w : natural := 15 -- 15 bits RAM space=32 kB
- );
- port (
- clk_i : in std_logic; -- CPU clock
- rst_i : in std_logic; -- Reset
- break_o : out std_logic; -- Break executed
- dbg_o : out zpu_dbgo_t; -- Debug info
- rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic -- UART Rx
- );
- end component zpu_small1;
-
- component zpu_med1 is
- generic(
- word_size : natural := 32; -- 32 bits data path
- d_care_val : std_logic := '0'; -- Fill value
- clk_freq : positive := 50; -- 50 MHz clock
- brate : positive := 115200; -- RS232 baudrate
- addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
- bram_w : natural := 15 -- 15 bits RAM space=32 kB
- );
- port(
- clk_i : in std_logic; -- CPU clock
- rst_i : in std_logic; -- Reset
- break_o : out std_logic; -- Break executed
- dbg_o : out zpu_dbgo_t; -- Debug info
- rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic -- UART Rx
- );
- end component zpu_med1;
-
-
- ---------------------------
- -- signal declarations
- signal dcm_sp_i0_clk0 : std_ulogic;
- signal dcm_sp_i0_clkfx : std_ulogic;
- signal clk_fb : std_ulogic;
- signal clk : std_ulogic;
- --
- signal reset_shift_reg : std_ulogic_vector(3 downto 0);
- signal reset_sync : std_ulogic;
- --
- signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
- signal zpu_i0_break : std_logic;
-
- ---------------------------
- -- alias declarations
- alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13);
-
-
-begin
-
- -- default output drivers
- -- to pass bitgen DRC
- -- outputs used by design are commented
- --
- ad_conv <= ad_conv_disable;
- amp_cs <= amp_cs_disable;
- amp_shdn <= '1';
- --
- dac_clr <= '0';
- dac_cs <= dac_cs_disable;
- --
- ds_wire <= 'Z';
- --
- e_txd(3 downto 0) <= (others => '1');
- e_tx_en <= '0';
- e_tx_er <= '0';
- e_mdc <= '1';
- e_mdio <= 'Z';
- --
- fpga_m0 <= 'Z';
- fpga_m1 <= 'Z';
- fpga_m2 <= 'Z';
- fpga_init_b <= fpga_init_b_disable;
- --
- fx2_clkin <= 'Z';
- fx2_clkio <= 'Z';
- fx2_clkout <= 'Z';
- fx2_io <= (others => 'Z');
- --
- lcd_e <= '0';
- lcd_rs <= '0';
- lcd_rw <= '0';
- --
- ps2_clk <= 'Z';
- ps2_data <= 'Z';
- --
- --rs232_dce_txd <= '1';
- rs232_dte_txd <= '1';
- --
- sd_a <= (others => '1');
- sd_dq <= (others => 'Z');
- sd_ba <= (others => '1');
- sd_ras <= '0';
- sd_cas <= '0';
- sd_we <= '0';
- sd_udm <= '1';
- sd_ldm <= '1';
- sd_udqs <= '1';
- sd_ldqs <= '1';
- sd_cs <= '1';
- sd_cke <= '1';
- sd_ck_n <= '0';
- sd_ck_p <= '1';
- --
- sf_a <= (others => '0');
- sf_byte <= '0';
- sf_ce0 <= sf_ce0_lcd_to_fpga;
- sf_d <= (others => 'Z');
- sf_oe <= '1';
- sf_we <= '0';
- --
- spi_mosi <= '0';
- spi_sck <= '0';
- spi_ss_b <= spi_ss_b_disable;
- spi_alt_cs_jp11 <= spi_ss_b_disable;
- --
- vga_red <= '0';
- vga_green <= '0';
- vga_blue <= '0';
- vga_hsync <= '0';
- vga_vsync <= '0';
- --
- xc_cmd <= "00";
- xc_d <= (others => 'Z');
- xc_cpld_en <= '0';
- xc_gck0 <= 'Z';
- gclk10 <= 'Z';
- -- led out
- --fx2_io(20 downto 13) <= (others => '0');
-
-
- -- digital clock manager (DCM)
- -- to generate higher/other system clock frequencys
- dcm_sp_i0 : dcm_sp
- generic map (
- startup_wait => true, -- wait with DONE till locked
- clkfx_multiply => clk_multiply,
- clkfx_divide => clk_divide,
- clk_feedback => "1X"
- )
- port map (
- clkin => clk_50mhz,
- clk0 => dcm_sp_i0_clk0,
- clkfx => dcm_sp_i0_clkfx,
- clkfb => clk_fb
- );
-
- clk_fb <= dcm_sp_i0_clk0;
- clk <= dcm_sp_i0_clkfx;
-
-
- -- reset synchronizer
- -- generate synchronous reset
- reset_synchronizer : process(clk, rot_center)
- begin
- if rot_center = '1' then
- reset_shift_reg <= (others => '1');
- elsif rising_edge(clk) then
- reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
- end if;
- end process;
- reset_sync <= reset_shift_reg(reset_shift_reg'high);
-
-
- -- select instance of zpu
- zpu_i0_small : if zpu_flavour = zpu_small generate
- zpu_i0 : zpu_small1
- generic map (
- addr_w => addr_w_c,
- word_size => word_size_c,
- clk_freq => clk_frequency * clk_multiply / clk_divide
- )
- port map (
- clk_i => clk, -- : in std_logic; -- CPU clock
- rst_i => reset_sync, -- : in std_logic; -- Reset
- break_o => zpu_i0_break, -- : out std_logic; -- Break executed
- dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
- rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
- rs232_rx_i => rs232_dce_rxd -- : in std_logic -- UART Rx
- );
- end generate zpu_i0_small;
-
- zpu_i0_medium : if zpu_flavour = zpu_medium generate
- zpu_i0 : zpu_med1
- generic map (
- addr_w => addr_w_c,
- word_size => word_size_c,
- clk_freq => clk_frequency * clk_multiply / clk_divide
- )
- port map (
- clk_i => clk, -- : in std_logic; -- CPU clock
- rst_i => reset_sync, -- : in std_logic; -- Reset
- break_o => zpu_i0_break, -- : out std_logic; -- Break executed
- dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
- rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
- rs232_rx_i => rs232_dce_rxd -- : in std_logic -- UART Rx
- );
- end generate zpu_i0_medium;
-
-
- -- pragma translate_off
- stop_simulation <= zpu_i0_break;
-
-
- trace_mod : trace
- generic map (
- addr_w => addr_w_c,
- word_size => word_size_c,
- log_file => "zpu_trace.log"
- )
- port map (
- clk_i => clk,
- dbg_i => zpu_i0_dbg,
- stop_i => zpu_i0_break,
- busy_i => '0'
- );
- -- pragma translate_on
-
-
- -- switch on all LEDs in case of break
- process
- begin
- wait until rising_edge(clk);
- if zpu_i0_break = '1' then
- led <= (others => '1');
- end if;
- if reset_sync = '1' then
- led <= (others => '0');
- end if;
- end process;
-
-
-
-end architecture rtl;
+-- top module of
+-- Spartan-3E Starter Kit Board
+--
+-- using following external connections:
+-- rotary pushbutton as reset
+-- LEDs for output
+-- RS232 (DCE, the left one)
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ --
+ -- Analog-to-Digital Converter (ADC)
+ ad_conv : out std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ amp_cs : out std_logic; -- active low chip select
+ amp_dout : in std_logic;
+ amp_shdn : out std_logic; -- active high shutdown, reset
+ -- Pushbuttons (BTN)
+ btn_east : in std_logic;
+ btn_north : in std_logic;
+ btn_south : in std_logic;
+ btn_west : in std_logic;
+ -- Clock inputs (CLK)
+ clk_50mhz : in std_logic;
+ clk_aux : in std_logic;
+ clk_sma : in std_logic;
+ -- Digital-to-Analog Converter (DAC)
+ dac_clr : out std_logic; -- async, active low reset input
+ dac_cs : out std_logic; -- active low chip select, conv start with rising edge
+ -- 1-Wire Secure EEPROM (DS)
+ ds_wire : inout std_logic;
+ -- Ethernet PHY (E)
+ e_col : in std_logic; -- MII collision detect
+ e_crs : in std_logic; -- carrier sense
+ e_mdc : out std_logic; -- management clock
+ e_mdio : inout std_logic; -- management data io
+ e_rx_clk : in std_logic; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ e_rx_dv : in std_logic; -- receive data valid
+ e_rxd : in std_logic_vector(3 downto 0);
+ e_rx_er : in std_logic;
+ e_tx_clk : in std_logic; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ e_tx_en : out std_logic; -- transmit enable
+ e_txd : out std_logic_vector(3 downto 0);
+ e_tx_er : out std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ fpga_m0 : inout std_logic;
+ fpga_m1 : inout std_logic;
+ fpga_m2 : inout std_logic;
+ fpga_init_b : inout std_logic;
+ fpga_rdwr_b : in std_logic;
+ fpga_hswap : in std_logic;
+ -- FX2 Connector (FX2)
+ fx2_clkin : inout std_logic;
+ fx2_clkio : inout std_logic;
+ fx2_clkout : inout std_logic;
+ fx2_io : inout std_logic_vector(40 downto 1);
+ -- These are shared connections with the FX2 connector
+ --j1 : inout std_logic_vector(3 downto 0);
+ --j2 : inout std_logic_vector(3 downto 0);
+ --j4 : inout std_logic_vector(3 downto 0);
+ --led : out std_logic_vector(7 downto 0);
+ -- Character LCD (LCD)
+ lcd_e : out std_logic;
+ lcd_rs : out std_logic;
+ lcd_rw : out std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ --sf_d : inout std_ulogic_vector(11 downto 8);
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ ps2_clk : inout std_logic;
+ ps2_data : inout std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ rot_a : in std_logic;
+ rot_b : in std_logic;
+ rot_center : in std_logic;
+ -- RS-232 Serial Ports (RS232)
+ rs232_dce_rxd : in std_logic;
+ rs232_dce_txd : out std_logic;
+ rs232_dte_rxd : in std_logic;
+ rs232_dte_txd : out std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ sd_a : out std_logic_vector(12 downto 0); -- address inputs
+ sd_dq : inout std_logic_vector(15 downto 0); -- data io
+ sd_ba : out std_logic_vector(1 downto 0); -- bank address inputs
+ sd_ras : out std_logic; -- command output
+ sd_cas : out std_logic; -- command output
+ sd_we : out std_logic; -- command output
+ sd_udm : out std_logic; -- data mask
+ sd_ldm : out std_logic; -- data mask
+ sd_udqs : inout std_logic; -- data strobe
+ sd_ldqs : inout std_logic; -- data strobe
+ sd_cs : out std_logic; -- active low chip select
+ sd_cke : out std_logic; -- active high clock enable
+ sd_ck_n : out std_logic; -- differential clock
+ sd_ck_p : out std_logic; -- differential clock
+ -- Path to allow connection to top DCM connection
+ sd_ck_fb : in std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ sf_a : out std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32
+ sf_byte : out std_logic;
+ sf_ce0 : out std_logic;
+ sf_d : inout std_logic_vector(15 downto 1);
+ sf_oe : out std_logic;
+ sf_sts : in std_logic;
+ sf_we : out std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ spi_mosi : out std_logic; -- master out slave in
+ spi_miso : in std_logic; -- master in slave out
+ spi_sck : out std_logic; -- clock
+ spi_ss_b : out std_logic; -- active low slave select
+ spi_alt_cs_jp11 : out std_logic;
+ -- Slide Switches (SW)
+ sw : in std_logic_vector(3 downto 0);
+ -- VGA Port (VGA)
+ vga_blue : out std_logic;
+ vga_green : out std_logic;
+ vga_hsync : out std_logic;
+ vga_red : out std_logic;
+ vga_vsync : out std_logic;
+ -- Xilinx CPLD (XC)
+ xc_cmd : out std_logic_vector(1 downto 0);
+ xc_cpld_en : out std_logic;
+ xc_d : inout std_logic_vector(2 downto 0);
+ xc_trig : in std_logic;
+ xc_gck0 : inout std_logic;
+ gclk10 : inout std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 3; -- 2 for small, 3 for medium
+ constant clk_divide : positive := 2; -- 1 for small, 2 for medium
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+
+
+ constant spi_ss_b_disable : std_ulogic := '1'; -- 1 = disable SPI serial flash
+ constant dac_cs_disable : std_ulogic := '1'; -- 1 = disable DAC
+ constant amp_cs_disable : std_ulogic := '1'; -- 1 = disable programmable pre-amplifier
+ constant ad_conv_disable : std_ulogic := '0'; -- 0 = disable ADC
+ constant sf_ce0_disable : std_ulogic := '1';
+ constant fpga_init_b_disable : std_ulogic := '1'; -- 1 = disable pflatform flash PROM
+ --
+ -- connect ldc to fpga
+ constant sf_ce0_lcd_to_fpga : std_ulogic := '1';
+ --
+ constant clk_frequency : positive := 50; -- input frequency for correct calculation
+
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+ ---------------------------
+ -- signal declarations
+ signal dcm_sp_i0_clk0 : std_ulogic;
+ signal dcm_sp_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+ ---------------------------
+ -- alias declarations
+ alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13);
+
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- outputs used by design are commented
+ --
+ ad_conv <= ad_conv_disable;
+ amp_cs <= amp_cs_disable;
+ amp_shdn <= '1';
+ --
+ dac_clr <= '0';
+ dac_cs <= dac_cs_disable;
+ --
+ ds_wire <= 'Z';
+ --
+ e_txd(3 downto 0) <= (others => '1');
+ e_tx_en <= '0';
+ e_tx_er <= '0';
+ e_mdc <= '1';
+ e_mdio <= 'Z';
+ --
+ fpga_m0 <= 'Z';
+ fpga_m1 <= 'Z';
+ fpga_m2 <= 'Z';
+ fpga_init_b <= fpga_init_b_disable;
+ --
+ fx2_clkin <= 'Z';
+ fx2_clkio <= 'Z';
+ fx2_clkout <= 'Z';
+ fx2_io <= (others => 'Z');
+ --
+ lcd_e <= '0';
+ lcd_rs <= '0';
+ lcd_rw <= '0';
+ --
+ ps2_clk <= 'Z';
+ ps2_data <= 'Z';
+ --
+ --rs232_dce_txd <= '1';
+ rs232_dte_txd <= '1';
+ --
+ sd_a <= (others => '1');
+ sd_dq <= (others => 'Z');
+ sd_ba <= (others => '1');
+ sd_ras <= '0';
+ sd_cas <= '0';
+ sd_we <= '0';
+ sd_udm <= '1';
+ sd_ldm <= '1';
+ sd_udqs <= '1';
+ sd_ldqs <= '1';
+ sd_cs <= '1';
+ sd_cke <= '1';
+ sd_ck_n <= '0';
+ sd_ck_p <= '1';
+ --
+ sf_a <= (others => '0');
+ sf_byte <= '0';
+ sf_ce0 <= sf_ce0_lcd_to_fpga;
+ sf_d <= (others => 'Z');
+ sf_oe <= '1';
+ sf_we <= '0';
+ --
+ spi_mosi <= '0';
+ spi_sck <= '0';
+ spi_ss_b <= spi_ss_b_disable;
+ spi_alt_cs_jp11 <= spi_ss_b_disable;
+ --
+ vga_red <= '0';
+ vga_green <= '0';
+ vga_blue <= '0';
+ vga_hsync <= '0';
+ vga_vsync <= '0';
+ --
+ xc_cmd <= "00";
+ xc_d <= (others => 'Z');
+ xc_cpld_en <= '0';
+ xc_gck0 <= 'Z';
+ gclk10 <= 'Z';
+ -- led out
+ --fx2_io(20 downto 13) <= (others => '0');
+
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_sp_i0 : dcm_sp
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ clkin => clk_50mhz,
+ clk0 => dcm_sp_i0_clk0,
+ clkfx => dcm_sp_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ clk_fb <= dcm_sp_i0_clk0;
+ clk <= dcm_sp_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, rot_center)
+ begin
+ if rot_center = '1' then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+ -- select instance of zpu
+ zpu_i0_small : if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_dce_rxd, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium : if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_dce_rxd, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break;
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+
+ -- assign GPIOs
+ -- no bidirectional pins (e.g. headers), so
+ -- gpio_dir is unused
+ gpio_in <= ((6) => rot_a,
+ (5) => rot_b,
+ (4) => rot_center,
+ --
+ (3) => btn_east,
+ (2) => btn_north,
+ (1) => btn_south,
+ (0) => btn_west,
+ others => '0');
+
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ led <= zpu_i0_gpio_out(7 downto 0);
+ if zpu_i0_break = '1' then
+ led <= (others => '1');
+ end if;
+ end process;
+
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
index c774e89..d62bed9 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
@@ -1,278 +1,281 @@
--- testbench for Digilent Spartan 3E Starter Board
---
--- includes "model" for clock generation
--- simulate press on Rotary Pushbutton Switch as reset
---
--- place models for external components (PHY, SDRAM) in this file
---
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-
-entity top_tb is
-end entity top_tb;
-
-architecture testbench of top_tb is
-
- ---------------------------
- -- constant declarations
- constant clk_50mhz_period : time := 1 sec / 50_000_000; -- 50 MHz
-
-
- ---------------------------
- -- signal declarations
- signal simulation_run : boolean := true;
- signal tb_stop_simulation : std_logic;
- --
- -- Analog-to-Digital Converter (ADC)
- signal tb_ad_conv : std_logic;
- -- Programmable Gain Amplifier (AMP)
- signal tb_amp_cs : std_logic; -- active low chip select
- signal tb_amp_dout : std_logic := '1';
- signal tb_amp_shdn : std_logic; -- active high shutdown, reset
- -- Pushbuttons (BTN)
- signal tb_btn_east : std_logic := '0';
- signal tb_btn_north : std_logic := '0';
- signal tb_btn_south : std_logic := '0';
- signal tb_btn_west : std_logic := '0';
- -- Clock inputs (CLK)
- signal tb_clk_50mhz : std_logic := '0';
- signal tb_clk_aux : std_logic := '0';
- signal tb_clk_sma : std_logic := '0';
- -- Digital-to-Analog Converter (DAC)
- signal tb_dac_clr : std_logic; -- async, active low reset input
- signal tb_dac_cs : std_logic; -- active low chip select, conv start with rising edge
- -- 1-Wire Secure EEPROM (DS)
- signal tb_ds_wire : std_logic;
- -- Ethernet PHY (E)
- signal tb_e_col : std_logic := '0'; -- MII collision detect
- signal tb_e_crs : std_logic := '0'; -- carrier sense
- signal tb_e_mdc : std_logic; -- management clock
- signal tb_e_mdio : std_logic; -- management data io
- signal tb_e_rx_clk : std_logic := '0'; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
- signal tb_e_rx_dv : std_logic := '0'; -- receive data valid
- signal tb_e_rxd : std_logic_vector(3 downto 0) := (others => '0');
- signal tb_e_rx_er : std_logic := '0';
- signal tb_e_tx_clk : std_logic := '0'; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
- signal tb_e_tx_en : std_logic; -- transmit enable
- signal tb_e_txd : std_logic_vector(3 downto 0);
- signal tb_e_tx_er : std_logic;
- -- FPGA Configuration Mode, INIT_B Pins (FPGA)
- signal tb_fpga_m0 : std_logic;
- signal tb_fpga_m1 : std_logic;
- signal tb_fpga_m2 : std_logic;
- signal tb_fpga_init_b : std_logic;
- signal tb_fpga_rdwr_b : std_logic := '0';
- signal tb_fpga_hswap : std_logic := '0';
- -- FX2 Connector (FX2)
- signal tb_fx2_clkin : std_logic;
- signal tb_fx2_clkio : std_logic;
- signal tb_fx2_clkout : std_logic;
- signal tb_fx2_io : std_logic_vector(40 downto 1);
- -- Character LCD (LCD)
- signal tb_lcd_e : std_logic;
- signal tb_lcd_rs : std_logic;
- signal tb_lcd_rw : std_logic;
- -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
- -- PS/2 Mouse/Keyboard Port (PS2)
- signal tb_ps2_clk : std_logic;
- signal tb_ps2_data : std_logic;
- -- Rotary Pushbutton Switch (ROT)
- signal tb_rot_a : std_logic := '0';
- signal tb_rot_b : std_logic := '0';
- signal tb_rot_center : std_logic; -- use as reset
- -- RS-232 Serial Ports (RS232)
- signal tb_rs232_dce_rxd : std_logic := '1';
- signal tb_rs232_dce_txd : std_logic;
- signal tb_rs232_dte_rxd : std_logic := '1';
- signal tb_rs232_dte_txd : std_logic;
- -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
- signal tb_sd_a : std_logic_vector(12 downto 0); -- address inputs
- signal tb_sd_dq : std_logic_vector(15 downto 0); -- data io
- signal tb_sd_ba : std_logic_vector(1 downto 0); -- bank address inputs
- signal tb_sd_ras : std_logic; -- command output
- signal tb_sd_cas : std_logic; -- command output
- signal tb_sd_we : std_logic; -- command output
- signal tb_sd_udm : std_logic; -- data mask
- signal tb_sd_ldm : std_logic; -- data mask
- signal tb_sd_udqs : std_logic; -- data strobe
- signal tb_sd_ldqs : std_logic; -- data strobe
- signal tb_sd_cs : std_logic; -- active low chip select
- signal tb_sd_cke : std_logic; -- active high clock enable
- signal tb_sd_ck_n : std_logic; -- differential clock
- signal tb_sd_ck_p : std_logic; -- differential clock
- -- Path to allow connection to top DCM connection
- signal tb_sd_ck_fb : std_logic;
- -- Intel StrataFlash Parallel NOR Flash (SF)
- signal tb_sf_a : std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32 :-(
- signal tb_sf_byte : std_logic;
- signal tb_sf_ce0 : std_logic;
- signal tb_sf_d : std_logic_vector(15 downto 1);
- signal tb_sf_oe : std_logic;
- signal tb_sf_sts : std_logic := '0';
- signal tb_sf_we : std_logic;
- -- STMicro SPI serial Flash (SPI)
- signal tb_spi_mosi : std_logic; -- master out slave in
- signal tb_spi_miso : std_logic := '0'; -- master in slave out
- signal tb_spi_sck : std_logic; -- clock
- signal tb_spi_ss_b : std_logic; -- active low slave select
- signal tb_spi_alt_cs_jp11 : std_logic;
- -- Slide Switches (SW)
- signal tb_sw : std_logic_vector(3 downto 0) := (others => '0');
- -- VGA Port (VGA)
- signal tb_vga_blue : std_logic;
- signal tb_vga_green : std_logic;
- signal tb_vga_hsync : std_logic;
- signal tb_vga_red : std_logic;
- signal tb_vga_vsync : std_logic;
- -- Xilinx CPLD (XC)
- signal tb_xc_cmd : std_logic_vector(1 downto 0);
- signal tb_xc_cpld_en : std_logic;
- signal tb_xc_d : std_logic_vector(2 downto 0);
- signal tb_xc_trig : std_logic := '0';
- signal tb_xc_gck0 : std_logic;
- signal tb_gclk10 : std_logic;
-
-
-begin
-
-
- -- generate clock
- tb_clk_50mhz <= not tb_clk_50mhz after clk_50mhz_period / 2 when simulation_run;
-
- -- generate reset
- tb_rot_center <= '1', '0' after 6.66 * clk_50mhz_period;
-
-
- -- clock feedback for SD-RAM (on board)
- tb_sd_ck_fb <= tb_sd_ck_p;
-
-
- -- dut
- top_i0 : entity work.top
- port map (
- stop_simulation => tb_stop_simulation, -- : out std_logic;
- -- Analog-to-Digital Converter (ADC)
- ad_conv => tb_ad_conv, -- : out std_logic;
- -- Programmable Gain Amplifier (AMP)
- amp_cs => tb_amp_cs, -- : out std_logic;
- amp_dout => tb_amp_dout, -- : in std_logic;
- amp_shdn => tb_amp_shdn, -- : out std_logic;
- -- Pushbuttons (BTN)
- btn_east => tb_btn_east, -- : in std_logic;
- btn_north => tb_btn_north, -- : in std_logic;
- btn_south => tb_btn_south, -- : in std_logic;
- btn_west => tb_btn_west, -- : in std_logic;
- -- Clock inputs (CLK)
- clk_50mhz => tb_clk_50mhz, -- : in std_logic;
- clk_aux => tb_clk_aux, -- : in std_logic;
- clk_sma => tb_clk_sma, -- : in std_logic;
- -- Digital-to-Analog Converter (DAC)
- dac_clr => tb_dac_clr, -- : out std_logic;
- dac_cs => tb_dac_cs, -- : out std_logic;
- -- 1-Wire Secure EEPROM (DS)
- ds_wire => tb_ds_wire, -- : inout std_logic;
- -- Ethernet PHY (E)
- e_col => tb_e_col, -- : in std_logic;
- e_crs => tb_e_crs, -- : in std_logic;
- e_mdc => tb_e_mdc, -- : out std_logic;
- e_mdio => tb_e_mdio, -- : inout std_logic;
- e_rx_clk => tb_e_rx_clk, -- : in std_logic;
- e_rx_dv => tb_e_rx_dv, -- : in std_logic;
- e_rxd => tb_e_rxd, -- : in std_logic_vector(3 downto 0);
- e_rx_er => tb_e_rx_er, -- : in std_logic;
- e_tx_clk => tb_e_tx_clk, -- : in std_logic;
- e_tx_en => tb_e_tx_en, -- : out std_logic;
- e_txd => tb_e_txd, -- : out std_logic_vector(3 downto 0);
- e_tx_er => tb_e_tx_er, -- : out std_logic;
- -- FPGA Configuration Mode, INIT_B Pins (FPGA)
- fpga_m0 => tb_fpga_m0, -- : inout std_logic;
- fpga_m1 => tb_fpga_m1, -- : inout std_logic;
- fpga_m2 => tb_fpga_m2, -- : inout std_logic;
- fpga_init_b => tb_fpga_init_b, -- : inout std_logic;
- fpga_rdwr_b => tb_fpga_rdwr_b, -- : in std_logic;
- fpga_hswap => tb_fpga_hswap, -- : in std_logic;
- -- FX2 Connector (FX2)
- fx2_clkin => tb_fx2_clkin, -- : inout std_logic;
- fx2_clkio => tb_fx2_clkio, -- : inout std_logic;
- fx2_clkout => tb_fx2_clkout, -- : inout std_logic;
- fx2_io => tb_fx2_io, -- : inout std_logic_vector(40 downto 1);
- -- Character LCD (LCD)
- lcd_e => tb_lcd_e, -- : out std_logic;
- lcd_rs => tb_lcd_rs, -- : out std_logic;
- lcd_rw => tb_lcd_rw, -- : out std_logic;
- -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
- -- PS/2 Mouse/Keyboard Port (PS2)
- ps2_clk => tb_ps2_clk, -- : inout std_logic;
- ps2_data => tb_ps2_data, -- : inout std_logic;
- -- Rotary Pushbutton Switch (ROT)
- rot_a => tb_rot_a, -- : in std_logic;
- rot_b => tb_rot_b, -- : in std_logic;
- rot_center => tb_rot_center, -- : in std_logic;
- -- RS-232 Serial Ports (RS232)
- rs232_dce_rxd => tb_rs232_dce_rxd, -- : in std_logic;
- rs232_dce_txd => tb_rs232_dce_txd, -- : out std_logic;
- rs232_dte_rxd => tb_rs232_dte_rxd, -- : in std_logic;
- rs232_dte_txd => tb_rs232_dte_txd, -- : out std_logic;
- -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
- sd_a => tb_sd_a, -- : out std_logic_vector(12 downto 0);
- sd_dq => tb_sd_dq, -- : inout std_logic_vector(15 downto 0);
- sd_ba => tb_sd_ba, -- : out std_logic_vector(1 downto 0);
- sd_ras => tb_sd_ras, -- : out std_logic;
- sd_cas => tb_sd_cas, -- : out std_logic;
- sd_we => tb_sd_we, -- : out std_logic;
- sd_udm => tb_sd_udm, -- : out std_logic;
- sd_ldm => tb_sd_ldm, -- : out std_logic;
- sd_udqs => tb_sd_udqs, -- : inout std_logic;
- sd_ldqs => tb_sd_ldqs, -- : inout std_logic;
- sd_cs => tb_sd_cs, -- : out std_logic;
- sd_cke => tb_sd_cke, -- : out std_logic;
- sd_ck_n => tb_sd_ck_n, -- : out std_logic;
- sd_ck_p => tb_sd_ck_p, -- : out std_logic;
- -- Path to allow connection to top DCM connection
- sd_ck_fb => tb_sd_ck_fb, -- : in std_logic;
- -- Intel StrataFlash Parallel NOR Flash (SF)
- sf_a => tb_sf_a, -- : out std_logic_vector(23 downto 0);
- sf_byte => tb_sf_byte, -- : out std_logic;
- sf_ce0 => tb_sf_ce0, -- : out std_logic;
- sf_d => tb_sf_d, -- : inout std_logic_vector(15 downto 1);
- sf_oe => tb_sf_oe, -- : out std_logic;
- sf_sts => tb_sf_sts, -- : in std_logic;
- sf_we => tb_sf_we, -- : out std_logic;
- -- STMicro SPI serial Flash (SPI)
- spi_mosi => tb_spi_mosi, -- : out std_logic;
- spi_miso => tb_spi_miso, -- : in std_logic;
- spi_sck => tb_spi_sck, -- : out std_logic;
- spi_ss_b => tb_spi_ss_b, -- : out std_logic;
- spi_alt_cs_jp11 => tb_spi_alt_cs_jp11, -- : out std_logic;
- -- Slide Switches (SW)
- sw => tb_sw, -- : in std_logic_vector(3 downto 0);
- -- VGA Port (VGA)
- vga_blue => tb_vga_blue, -- : out std_logic;
- vga_green => tb_vga_green, -- : out std_logic;
- vga_hsync => tb_vga_hsync, -- : out std_logic;
- vga_red => tb_vga_red, -- : out std_logic;
- vga_vsync => tb_vga_vsync, -- : out std_logic;
- -- Xilinx CPLD (XC)
- xc_cmd => tb_xc_cmd, -- : out std_logic_vector(1 downto 0);
- xc_cpld_en => tb_xc_cpld_en, -- : out std_logic;
- xc_d => tb_xc_d, -- : inout std_logic_vector(2 downto 0);
- xc_trig => tb_xc_trig, -- : in std_logic;
- xc_gck0 => tb_xc_gck0, -- : inout std_logic;
- gclk10 => tb_gclk10 -- : inout std_logic
- );
-
-
- -- check for simulation stopping
- process (tb_stop_simulation)
- begin
- if tb_stop_simulation = '1' then
- report "Simulation end." severity note;
- simulation_run <= false;
- end if;
- end process;
-
-
-end architecture testbench;
+-- testbench for
+-- Digilent Spartan 3E Starter Board
+--
+-- includes "model" for clock generation
+-- simulate press on Rotary Pushbutton Switch as reset
+--
+-- place models for external components (PHY, SDRAM) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant clk_50mhz_period : time := 1 sec / 50_000_000; -- 50 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ -- Analog-to-Digital Converter (ADC)
+ signal tb_ad_conv : std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ signal tb_amp_cs : std_logic; -- active low chip select
+ signal tb_amp_dout : std_logic := '1';
+ signal tb_amp_shdn : std_logic; -- active high shutdown, reset
+ -- Pushbuttons (BTN)
+ signal tb_btn_east : std_logic := '0';
+ signal tb_btn_north : std_logic := '0';
+ signal tb_btn_south : std_logic := '0';
+ signal tb_btn_west : std_logic := '0';
+ -- Clock inputs (CLK)
+ signal tb_clk_50mhz : std_logic := '0';
+ signal tb_clk_aux : std_logic := '0';
+ signal tb_clk_sma : std_logic := '0';
+ -- Digital-to-Analog Converter (DAC)
+ signal tb_dac_clr : std_logic; -- async, active low reset input
+ signal tb_dac_cs : std_logic; -- active low chip select, conv start with rising edge
+ -- 1-Wire Secure EEPROM (DS)
+ signal tb_ds_wire : std_logic;
+ -- Ethernet PHY (E)
+ signal tb_e_col : std_logic := '0'; -- MII collision detect
+ signal tb_e_crs : std_logic := '0'; -- carrier sense
+ signal tb_e_mdc : std_logic; -- management clock
+ signal tb_e_mdio : std_logic; -- management data io
+ signal tb_e_rx_clk : std_logic := '0'; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ signal tb_e_rx_dv : std_logic := '0'; -- receive data valid
+ signal tb_e_rxd : std_logic_vector(3 downto 0) := (others => '0');
+ signal tb_e_rx_er : std_logic := '0';
+ signal tb_e_tx_clk : std_logic := '0'; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ signal tb_e_tx_en : std_logic; -- transmit enable
+ signal tb_e_txd : std_logic_vector(3 downto 0);
+ signal tb_e_tx_er : std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ signal tb_fpga_m0 : std_logic;
+ signal tb_fpga_m1 : std_logic;
+ signal tb_fpga_m2 : std_logic;
+ signal tb_fpga_init_b : std_logic;
+ signal tb_fpga_rdwr_b : std_logic := '0';
+ signal tb_fpga_hswap : std_logic := '0';
+ -- FX2 Connector (FX2)
+ signal tb_fx2_clkin : std_logic;
+ signal tb_fx2_clkio : std_logic;
+ signal tb_fx2_clkout : std_logic;
+ signal tb_fx2_io : std_logic_vector(40 downto 1);
+ -- Character LCD (LCD)
+ signal tb_lcd_e : std_logic;
+ signal tb_lcd_rs : std_logic;
+ signal tb_lcd_rw : std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ signal tb_ps2_clk : std_logic;
+ signal tb_ps2_data : std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ signal tb_rot_a : std_logic := '0';
+ signal tb_rot_b : std_logic := '0';
+ signal tb_rot_center : std_logic; -- use as reset
+ -- RS-232 Serial Ports (RS232)
+ signal tb_rs232_dce_rxd : std_logic := '1';
+ signal tb_rs232_dce_txd : std_logic;
+ signal tb_rs232_dte_rxd : std_logic := '1';
+ signal tb_rs232_dte_txd : std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ signal tb_sd_a : std_logic_vector(12 downto 0); -- address inputs
+ signal tb_sd_dq : std_logic_vector(15 downto 0); -- data io
+ signal tb_sd_ba : std_logic_vector(1 downto 0); -- bank address inputs
+ signal tb_sd_ras : std_logic; -- command output
+ signal tb_sd_cas : std_logic; -- command output
+ signal tb_sd_we : std_logic; -- command output
+ signal tb_sd_udm : std_logic; -- data mask
+ signal tb_sd_ldm : std_logic; -- data mask
+ signal tb_sd_udqs : std_logic; -- data strobe
+ signal tb_sd_ldqs : std_logic; -- data strobe
+ signal tb_sd_cs : std_logic; -- active low chip select
+ signal tb_sd_cke : std_logic; -- active high clock enable
+ signal tb_sd_ck_n : std_logic; -- differential clock
+ signal tb_sd_ck_p : std_logic; -- differential clock
+ -- Path to allow connection to top DCM connection
+ signal tb_sd_ck_fb : std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ signal tb_sf_a : std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32 :-(
+ signal tb_sf_byte : std_logic;
+ signal tb_sf_ce0 : std_logic;
+ signal tb_sf_d : std_logic_vector(15 downto 1);
+ signal tb_sf_oe : std_logic;
+ signal tb_sf_sts : std_logic := '0';
+ signal tb_sf_we : std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ signal tb_spi_mosi : std_logic; -- master out slave in
+ signal tb_spi_miso : std_logic := '0'; -- master in slave out
+ signal tb_spi_sck : std_logic; -- clock
+ signal tb_spi_ss_b : std_logic; -- active low slave select
+ signal tb_spi_alt_cs_jp11 : std_logic;
+ -- Slide Switches (SW)
+ signal tb_sw : std_logic_vector(3 downto 0) := (others => '0');
+ -- VGA Port (VGA)
+ signal tb_vga_blue : std_logic;
+ signal tb_vga_green : std_logic;
+ signal tb_vga_hsync : std_logic;
+ signal tb_vga_red : std_logic;
+ signal tb_vga_vsync : std_logic;
+ -- Xilinx CPLD (XC)
+ signal tb_xc_cmd : std_logic_vector(1 downto 0);
+ signal tb_xc_cpld_en : std_logic;
+ signal tb_xc_d : std_logic_vector(2 downto 0);
+ signal tb_xc_trig : std_logic := '0';
+ signal tb_xc_gck0 : std_logic;
+ signal tb_gclk10 : std_logic;
+
+
+begin
+
+
+ -- generate clock
+ tb_clk_50mhz <= not tb_clk_50mhz after clk_50mhz_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_rot_center <= '1', '0' after 6.66 * clk_50mhz_period;
+
+
+ -- clock feedback for SD-RAM (on board)
+ tb_sd_ck_fb <= tb_sd_ck_p;
+
+ -- simulate keypress
+ tb_btn_north <= '0', '1' after 55 us, '0' after 56 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ -- Analog-to-Digital Converter (ADC)
+ ad_conv => tb_ad_conv, -- : out std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ amp_cs => tb_amp_cs, -- : out std_logic;
+ amp_dout => tb_amp_dout, -- : in std_logic;
+ amp_shdn => tb_amp_shdn, -- : out std_logic;
+ -- Pushbuttons (BTN)
+ btn_east => tb_btn_east, -- : in std_logic;
+ btn_north => tb_btn_north, -- : in std_logic;
+ btn_south => tb_btn_south, -- : in std_logic;
+ btn_west => tb_btn_west, -- : in std_logic;
+ -- Clock inputs (CLK)
+ clk_50mhz => tb_clk_50mhz, -- : in std_logic;
+ clk_aux => tb_clk_aux, -- : in std_logic;
+ clk_sma => tb_clk_sma, -- : in std_logic;
+ -- Digital-to-Analog Converter (DAC)
+ dac_clr => tb_dac_clr, -- : out std_logic;
+ dac_cs => tb_dac_cs, -- : out std_logic;
+ -- 1-Wire Secure EEPROM (DS)
+ ds_wire => tb_ds_wire, -- : inout std_logic;
+ -- Ethernet PHY (E)
+ e_col => tb_e_col, -- : in std_logic;
+ e_crs => tb_e_crs, -- : in std_logic;
+ e_mdc => tb_e_mdc, -- : out std_logic;
+ e_mdio => tb_e_mdio, -- : inout std_logic;
+ e_rx_clk => tb_e_rx_clk, -- : in std_logic;
+ e_rx_dv => tb_e_rx_dv, -- : in std_logic;
+ e_rxd => tb_e_rxd, -- : in std_logic_vector(3 downto 0);
+ e_rx_er => tb_e_rx_er, -- : in std_logic;
+ e_tx_clk => tb_e_tx_clk, -- : in std_logic;
+ e_tx_en => tb_e_tx_en, -- : out std_logic;
+ e_txd => tb_e_txd, -- : out std_logic_vector(3 downto 0);
+ e_tx_er => tb_e_tx_er, -- : out std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ fpga_m0 => tb_fpga_m0, -- : inout std_logic;
+ fpga_m1 => tb_fpga_m1, -- : inout std_logic;
+ fpga_m2 => tb_fpga_m2, -- : inout std_logic;
+ fpga_init_b => tb_fpga_init_b, -- : inout std_logic;
+ fpga_rdwr_b => tb_fpga_rdwr_b, -- : in std_logic;
+ fpga_hswap => tb_fpga_hswap, -- : in std_logic;
+ -- FX2 Connector (FX2)
+ fx2_clkin => tb_fx2_clkin, -- : inout std_logic;
+ fx2_clkio => tb_fx2_clkio, -- : inout std_logic;
+ fx2_clkout => tb_fx2_clkout, -- : inout std_logic;
+ fx2_io => tb_fx2_io, -- : inout std_logic_vector(40 downto 1);
+ -- Character LCD (LCD)
+ lcd_e => tb_lcd_e, -- : out std_logic;
+ lcd_rs => tb_lcd_rs, -- : out std_logic;
+ lcd_rw => tb_lcd_rw, -- : out std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ ps2_clk => tb_ps2_clk, -- : inout std_logic;
+ ps2_data => tb_ps2_data, -- : inout std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ rot_a => tb_rot_a, -- : in std_logic;
+ rot_b => tb_rot_b, -- : in std_logic;
+ rot_center => tb_rot_center, -- : in std_logic;
+ -- RS-232 Serial Ports (RS232)
+ rs232_dce_rxd => tb_rs232_dce_rxd, -- : in std_logic;
+ rs232_dce_txd => tb_rs232_dce_txd, -- : out std_logic;
+ rs232_dte_rxd => tb_rs232_dte_rxd, -- : in std_logic;
+ rs232_dte_txd => tb_rs232_dte_txd, -- : out std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ sd_a => tb_sd_a, -- : out std_logic_vector(12 downto 0);
+ sd_dq => tb_sd_dq, -- : inout std_logic_vector(15 downto 0);
+ sd_ba => tb_sd_ba, -- : out std_logic_vector(1 downto 0);
+ sd_ras => tb_sd_ras, -- : out std_logic;
+ sd_cas => tb_sd_cas, -- : out std_logic;
+ sd_we => tb_sd_we, -- : out std_logic;
+ sd_udm => tb_sd_udm, -- : out std_logic;
+ sd_ldm => tb_sd_ldm, -- : out std_logic;
+ sd_udqs => tb_sd_udqs, -- : inout std_logic;
+ sd_ldqs => tb_sd_ldqs, -- : inout std_logic;
+ sd_cs => tb_sd_cs, -- : out std_logic;
+ sd_cke => tb_sd_cke, -- : out std_logic;
+ sd_ck_n => tb_sd_ck_n, -- : out std_logic;
+ sd_ck_p => tb_sd_ck_p, -- : out std_logic;
+ -- Path to allow connection to top DCM connection
+ sd_ck_fb => tb_sd_ck_fb, -- : in std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ sf_a => tb_sf_a, -- : out std_logic_vector(23 downto 0);
+ sf_byte => tb_sf_byte, -- : out std_logic;
+ sf_ce0 => tb_sf_ce0, -- : out std_logic;
+ sf_d => tb_sf_d, -- : inout std_logic_vector(15 downto 1);
+ sf_oe => tb_sf_oe, -- : out std_logic;
+ sf_sts => tb_sf_sts, -- : in std_logic;
+ sf_we => tb_sf_we, -- : out std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ spi_mosi => tb_spi_mosi, -- : out std_logic;
+ spi_miso => tb_spi_miso, -- : in std_logic;
+ spi_sck => tb_spi_sck, -- : out std_logic;
+ spi_ss_b => tb_spi_ss_b, -- : out std_logic;
+ spi_alt_cs_jp11 => tb_spi_alt_cs_jp11, -- : out std_logic;
+ -- Slide Switches (SW)
+ sw => tb_sw, -- : in std_logic_vector(3 downto 0);
+ -- VGA Port (VGA)
+ vga_blue => tb_vga_blue, -- : out std_logic;
+ vga_green => tb_vga_green, -- : out std_logic;
+ vga_hsync => tb_vga_hsync, -- : out std_logic;
+ vga_red => tb_vga_red, -- : out std_logic;
+ vga_vsync => tb_vga_vsync, -- : out std_logic;
+ -- Xilinx CPLD (XC)
+ xc_cmd => tb_xc_cmd, -- : out std_logic_vector(1 downto 0);
+ xc_cpld_en => tb_xc_cpld_en, -- : out std_logic;
+ xc_d => tb_xc_d, -- : inout std_logic_vector(2 downto 0);
+ xc_trig => tb_xc_trig, -- : in std_logic;
+ xc_gck0 => tb_xc_gck0, -- : inout std_logic;
+ gclk10 => tb_gclk10 -- : inout std_logic
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+
+end architecture testbench;
diff --git a/zpu/hdl/zealot/fpga/dmips_med1.vhdl b/zpu/hdl/zealot/fpga/dmips_med1.vhdl
index 9920c2c..b95016c 100644
--- a/zpu/hdl/zealot/fpga/dmips_med1.vhdl
+++ b/zpu/hdl/zealot/fpga/dmips_med1.vhdl
@@ -100,7 +100,11 @@ architecture FPGA of DMIPS_Med1 is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic); -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
end component ZPU_Med1;
begin
zpu : ZPU_Med1
@@ -110,6 +114,6 @@ begin
BRAM_W => BRAM_W)
port map(
clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
- rs232_rx_i => rs232_rx_i, dbg_o => open);
+ rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
end architecture FPGA; -- Entity: DMIPS_Med1
diff --git a/zpu/hdl/zealot/fpga/dmips_small1.vhdl b/zpu/hdl/zealot/fpga/dmips_small1.vhdl
index 018ab2d..6edec00 100644
--- a/zpu/hdl/zealot/fpga/dmips_small1.vhdl
+++ b/zpu/hdl/zealot/fpga/dmips_small1.vhdl
@@ -101,7 +101,11 @@ architecture FPGA of DMIPS_Small1 is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic); -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
end component ZPU_Small1;
begin
zpu : ZPU_Small1
@@ -111,6 +115,6 @@ begin
BRAM_W => BRAM_W)
port map(
clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
- rs232_rx_i => rs232_rx_i, dbg_o => open);
+ rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
end architecture FPGA; -- Entity: DMIPS_Small1
diff --git a/zpu/hdl/zealot/fpga/hello_med1.vhdl b/zpu/hdl/zealot/fpga/hello_med1.vhdl
index 7356c72..5ffea1f 100644
--- a/zpu/hdl/zealot/fpga/hello_med1.vhdl
+++ b/zpu/hdl/zealot/fpga/hello_med1.vhdl
@@ -100,7 +100,11 @@ architecture FPGA of Hello_Med1 is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic); -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
end component ZPU_Med1;
begin
zpu : ZPU_Med1
@@ -110,6 +114,6 @@ begin
BRAM_W => BRAM_W)
port map(
clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
- rs232_rx_i => rs232_rx_i, dbg_o => open);
+ rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
end architecture FPGA; -- Entity: Hello_Med1
diff --git a/zpu/hdl/zealot/fpga/hello_small1.vhdl b/zpu/hdl/zealot/fpga/hello_small1.vhdl
index ccd87c5..a7e2c21 100644
--- a/zpu/hdl/zealot/fpga/hello_small1.vhdl
+++ b/zpu/hdl/zealot/fpga/hello_small1.vhdl
@@ -101,7 +101,11 @@ architecture FPGA of Hello_Small1 is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic); -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
end component ZPU_Small1;
begin
zpu : ZPU_Small1
@@ -111,6 +115,6 @@ begin
BRAM_W => BRAM_W)
port map(
clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
- rs232_rx_i => rs232_rx_i, dbg_o => open);
+ rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
end architecture FPGA; -- Entity: Hello_Small1
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
index febf588..d525737 100755
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
@@ -28,6 +28,7 @@ vcom -work zpu ../../helpers/zpu_med1.vhdl
vcom -work zpu ../../devices/txt_util.vhdl
vcom -work zpu ../../devices/phi_io.vhdl
vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
vcom -work zpu ../../devices/rx_unit.vhdl
vcom -work zpu ../../devices/tx_unit.vhdl
vcom -work zpu ../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
index acc1710..0d29e0a 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
@@ -1,2 +1,2 @@
-do wave.do
-run -all
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
index 81d56ef..965ae4c 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
@@ -1,18 +1,19 @@
-vhdl work ../top.vhd
-vhdl zpu ../../../zpu_pkg.vhdl
-vhdl zpu ../../../zpu_small.vhdl
-vhdl zpu ../../../zpu_medium.vhdl
-vhdl zpu ../../../roms/rom_pkg.vhdl
-#vhdl zpu ../../../roms/hello_dbram.vhdl
-#vhdl zpu ../../../roms/hello_bram.vhdl
-vhdl zpu ../../../roms/dmips_dbram.vhdl
-vhdl zpu ../../../roms/dmips_bram.vhdl
-vhdl zpu ../../../helpers/zpu_small1.vhdl
-vhdl zpu ../../../helpers/zpu_med1.vhdl
-vhdl zpu ../../../devices/txt_util.vhdl
-vhdl zpu ../../../devices/phi_io.vhdl
-vhdl zpu ../../../devices/timer.vhdl
-vhdl zpu ../../../devices/rx_unit.vhdl
-vhdl zpu ../../../devices/tx_unit.vhdl
-vhdl zpu ../../../devices/br_gen.vhdl
-vhdl zpu ../../../devices/trace.vhdl
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
index ea9319f..be56902 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
@@ -1,30 +1,30 @@
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g Reset_on_err:No
--g ConfigRate:2
--g ProgPin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g ExtMasterCclk_en:No
--g SPI_buswidth:1
--g TIMER_CFG:0xFFFF
--g multipin_wakeup:No
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
--g en_sw_gsr:No
--g drive_awake:No
--g sw_clk:Startupclk
--g sw_gwe_cycle:5
--g sw_gts_cycle:4
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
index 8952afe..ddddddd 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
@@ -1,53 +1,53 @@
-set -tmpdir "tmp"
-set -xsthdpdir "xst"
-run
--ifn ../synthesis_config/top.prj
--ifmt mixed
--ofn top
--ofmt NGC
--p xc6slx16-2-csg324
--top top
--opt_mode Speed
--opt_level 1
--power NO
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--dsp_utilization_ratio 100
--lc Auto
--reduce_control_sets Auto
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--shreg_extract YES
--rom_style Auto
--auto_bram_packing NO
--resource_sharing YES
--async_to_sync NO
--shreg_min_size 2
--use_dsp48 Auto
--iobuf YES
--max_fanout 100000
--bufg 16
--register_duplication YES
--register_balancing No
--optimize_primitives NO
--use_clock_enable Auto
--use_sync_set Auto
--use_sync_reset Auto
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc6slx16-2-csg324
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
index c54705a..a0c60e7 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
@@ -1,303 +1,303 @@
-############################################################
-# SPARTAN-6 SP601 Board Constraints File
-#
-# Family: Spartan6
-# Device: XC6SLX16
-# Package: CSG324
-# Speed: -2
-#
-#
-# Bank Voltage
-# Bank 0: 2.5 V
-# Bank 1: 2.5 V
-# Bank 2: 2.5 V
-# Bank 3: 1.8 V
-# VCCAUX: 2.5 V
-
-# following pins are connected to VCC1V8/2:
-# N3, M5, C1
-
-
-############################################################
-## clock/timing constraints
-############################################################
-
-TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 200 MHz HIGH 50 %;
-TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 50 MHz HIGH 50 %;
-NET "USER_CLOCK" PERIOD = 27 MHz HIGH 40%;
-
-
-############################################################
-## pin placement constraints
-############################################################
-
-NET "CPU_RESET" LOC = "N4";
-
-## 128 MB DDR2 Component Memory
-NET "DDR2_A<12>" LOC ="G6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<11>" LOC ="D3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<10>" LOC ="F4"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<9>" LOC ="D1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<8>" LOC ="D2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<7>" LOC ="H6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<6>" LOC ="H3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<5>" LOC ="H4"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<4>" LOC ="F3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<3>" LOC ="L7"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<2>" LOC ="H5"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<1>" LOC ="J6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<0>" LOC ="J7"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<15>" LOC ="U1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<14>" LOC ="U2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<13>" LOC ="T1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<12>" LOC ="T2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<11>" LOC ="N1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<10>" LOC ="N2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<9>" LOC ="M1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<8>" LOC ="M3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<7>" LOC ="J1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<6>" LOC ="J3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<5>" LOC ="H1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<4>" LOC ="H2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<3>" LOC ="K1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<2>" LOC ="K2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<1>" LOC ="L1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<0>" LOC ="L2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_WE_B" LOC ="E3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_UDQS_P" LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_UDQS_N" LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_UDM" LOC ="K4"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_RAS_B" LOC ="L5"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_ODT" LOC ="K6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_LDQS_P" LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_LDQS_N" LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_LDM" LOC ="K3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_CLK_P" LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_CLK_N" LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_CKE" LOC ="H7"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_CAS_B" LOC ="K5"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_BA<2>" LOC ="E1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_BA<1>" LOC ="F1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_BA<0>" LOC ="F2"; # | IOSTANDARD = SSTL18_II ;
-
-## Flash Memory
-NET "FLASH_A<0>" LOC = "K18";
-NET "FLASH_A<1>" LOC = "K17";
-NET "FLASH_A<2>" LOC = "J18";
-NET "FLASH_A<3>" LOC = "J16";
-NET "FLASH_A<4>" LOC = "G18";
-NET "FLASH_A<5>" LOC = "G16";
-NET "FLASH_A<6>" LOC = "H16";
-NET "FLASH_A<7>" LOC = "H15";
-NET "FLASH_A<8>" LOC = "H14";
-NET "FLASH_A<9>" LOC = "H13";
-NET "FLASH_A<10>" LOC = "F18";
-NET "FLASH_A<11>" LOC = "F17";
-NET "FLASH_A<12>" LOC = "K13";
-NET "FLASH_A<13>" LOC = "K12";
-NET "FLASH_A<14>" LOC = "E18";
-NET "FLASH_A<15>" LOC = "E16";
-NET "FLASH_A<16>" LOC = "G13";
-NET "FLASH_A<17>" LOC = "H12";
-NET "FLASH_A<18>" LOC = "D18";
-NET "FLASH_A<19>" LOC = "D17";
-NET "FLASH_A<20>" LOC = "G14";
-NET "FLASH_A<21>" LOC = "F14";
-NET "FLASH_A<22>" LOC = "C18";
-NET "FLASH_A<23>" LOC = "C17";
-NET "FLASH_A<24>" LOC = "F16";
-#NET "FLASH_D<0>" LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;
-#NET "FLASH_D<1>" LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;
-#NET "FLASH_D<2>" LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<3>" LOC = "U5" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<4>" LOC = "V5" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<5>" LOC = "R3" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<6>" LOC = "T3" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<7>" LOC = "R5" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_OE_B" LOC = "L18";
-NET "FLASH_WE_B" LOC = "M16";
-NET "FLASH_CE_B" LOC = "L17";
-
-# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)
-NET "FMC_CLK0_M2C_N" LOC = "A10";
-NET "FMC_CLK0_M2C_P" LOC = "C10";
-NET "FMC_CLK1_M2C_N" LOC = "V9" ;
-NET "FMC_CLK1_M2C_P" LOC = "T9" ;
-NET "FMC_LA00_CC_N" LOC = "C9" ;
-NET "FMC_LA00_CC_P" LOC = "D9" ;
-NET "FMC_LA01_CC_N" LOC = "C11";
-NET "FMC_LA01_CC_P" LOC = "D11";
-NET "FMC_LA02_N" LOC = "A15";
-NET "FMC_LA02_P" LOC = "C15";
-NET "FMC_LA03_N" LOC = "A13";
-NET "FMC_LA03_P" LOC = "C13";
-NET "FMC_LA04_N" LOC = "A16";
-NET "FMC_LA04_P" LOC = "B16";
-NET "FMC_LA05_N" LOC = "A14";
-NET "FMC_LA05_P" LOC = "B14";
-NET "FMC_LA06_N" LOC = "C12";
-NET "FMC_LA06_P" LOC = "D12";
-NET "FMC_LA07_N" LOC = "E8" ;
-NET "FMC_LA07_P" LOC = "E7" ;
-NET "FMC_LA08_N" LOC = "E11";
-NET "FMC_LA08_P" LOC = "F11";
-NET "FMC_LA09_N" LOC = "F10";
-NET "FMC_LA09_P" LOC = "G11";
-NET "FMC_LA10_N" LOC = "C8" ;
-NET "FMC_LA10_P" LOC = "D8" ;
-NET "FMC_LA11_N" LOC = "A12";
-NET "FMC_LA11_P" LOC = "B12";
-NET "FMC_LA12_N" LOC = "C6" ;
-NET "FMC_LA12_P" LOC = "D6" ;
-NET "FMC_LA13_N" LOC = "A11";
-NET "FMC_LA13_P" LOC = "B11";
-NET "FMC_LA14_N" LOC = "A2" ;
-NET "FMC_LA14_P" LOC = "B2" ;
-NET "FMC_LA15_N" LOC = "F9" ;
-NET "FMC_LA15_P" LOC = "G9" ;
-NET "FMC_LA16_N" LOC = "A7" ;
-NET "FMC_LA16_P" LOC = "C7" ;
-NET "FMC_LA17_CC_N" LOC = "T8" ;
-NET "FMC_LA17_CC_P" LOC = "R8" ;
-NET "FMC_LA18_CC_N" LOC = "T10";
-NET "FMC_LA18_CC_P" LOC = "R10";
-NET "FMC_LA19_N" LOC = "P7" ;
-NET "FMC_LA19_P" LOC = "N6" ;
-NET "FMC_LA20_N" LOC = "P8" ;
-NET "FMC_LA20_P" LOC = "N7" ;
-NET "FMC_LA21_N" LOC = "V4" ;
-NET "FMC_LA21_P" LOC = "T4" ;
-NET "FMC_LA22_N" LOC = "T7" ;
-NET "FMC_LA22_P" LOC = "R7" ;
-NET "FMC_LA23_N" LOC = "P6" ;
-NET "FMC_LA23_P" LOC = "N5" ;
-NET "FMC_LA24_N" LOC = "V8" ;
-NET "FMC_LA24_P" LOC = "U8" ;
-NET "FMC_LA25_N" LOC = "N11";
-NET "FMC_LA25_P" LOC = "M11";
-NET "FMC_LA26_N" LOC = "V7" ;
-NET "FMC_LA26_P" LOC = "U7" ;
-NET "FMC_LA27_N" LOC = "T11";
-NET "FMC_LA27_P" LOC = "R11";
-NET "FMC_LA28_N" LOC = "V11";
-NET "FMC_LA28_P" LOC = "U11";
-NET "FMC_LA29_N" LOC = "N8" ;
-NET "FMC_LA29_P" LOC = "M8" ;
-NET "FMC_LA30_N" LOC = "V12";
-NET "FMC_LA30_P" LOC = "T12";
-NET "FMC_LA31_N" LOC = "V6" ;
-NET "FMC_LA31_P" LOC = "T6" ;
-NET "FMC_LA32_N" LOC = "V15";
-NET "FMC_LA32_P" LOC = "U15";
-NET "FMC_LA33_N" LOC = "N9" ;
-NET "FMC_LA33_P" LOC = "M10";
-NET "FMC_PRSNT_M2C_L" LOC = "U13";
-NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
-
-# special FPGA pins
-NET "FPGA_AWAKE" LOC = "P15"| SLEW = SLOW | DRIVE = 2;
-NET "FPGA_CCLK" LOC = "R15";
-NET "FPGA_CMP_CLK" LOC = "U16";
-NET "FPGA_CMP_MOSI" LOC = "V16";
-NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
-NET "FPGA_D1_MISO2" LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
-NET "FPGA_D2_MISO3" LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12
-NET "FPGA_HSWAPEN" LOC = "D4";
-NET "FPGA_INIT_B" LOC = "U3" | SLEW = SLOW | DRIVE = 4;
-NET "FPGA_M0_CMP_MISO" LOC = "T15";
-NET "FPGA_M1" LOC = "N12";
-NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13" | DRIVE = 4;
-NET "FPGA_ONCHIP_TERM1" LOC = "L6";
-NET "FPGA_ONCHIP_TERM2" LOC = "C2";
-NET "FPGA_VTEMP" LOC = "P3";
-
-## Pushbuttons, Bank 3, external Pulldown
-NET "GPIO_BUTTON<0>" LOC = "P4" ;
-NET "GPIO_BUTTON<1>" LOC = "F6" ;
-NET "GPIO_BUTTON<2>" LOC = "E4" ;
-NET "GPIO_BUTTON<3>" LOC = "F5" ;
-NET "GPIO_BUTTON*" TIG;
-
-## 8 Pin GPIO Header J13, Bank 0,1,2
-NET "GPIO_HEADER_LS<0>" LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<1>" LOC = "M18"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<2>" LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<3>" LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<4>" LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<5>" LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<6>" LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<7>" LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;
-
-## 4 GPIO LEDs, Bank 0
-NET "GPIO_LED<0>" LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED<1>" LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED<2>" LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED<3>" LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED*" TIG;
-
-## GPIO Dip Switches, Bank 0,2, external Pulldown
-NET "GPIO_SWITCH<0>" LOC = "D14";
-NET "GPIO_SWITCH<1>" LOC = "E12";
-NET "GPIO_SWITCH<2>" LOC = "F12";
-NET "GPIO_SWITCH<3>" LOC = "V13";
-NET "GPIO_SWITCH*" TIG;
-
-## IIC Bus
-NET "IIC_SCL_MAIN" LOC = "P11";
-NET "IIC_SDA_MAIN" LOC = "N10";
-
-## 10/100/1000 Tri-Speed Ethernet PHY
-NET "PHY_COL" LOC = "L14";
-NET "PHY_CRS" LOC = "M13";
-NET "PHY_INT" LOC = "J13";
-NET "PHY_MDC" LOC = "N14" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_MDIO" LOC = "P16" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_RESET" LOC = "L13";
-NET "PHY_RXCLK" LOC = "L16";
-NET "PHY_RXCTL_RXDV" LOC = "N18";
-NET "PHY_RXD<0>" LOC = "M14";
-NET "PHY_RXD<1>" LOC = "U18";
-NET "PHY_RXD<2>" LOC = "U17";
-NET "PHY_RXD<3>" LOC = "T18";
-NET "PHY_RXD<4>" LOC = "T17";
-NET "PHY_RXD<5>" LOC = "N16";
-NET "PHY_RXD<6>" LOC = "N15";
-NET "PHY_RXD<7>" LOC = "P18";
-NET "PHY_RXER" LOC = "P17";
-NET "PHY_TXCLK" LOC = "B9" ;
-NET "PHY_TXCTL_TXEN" LOC = "B8" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXC_GTXCLK" LOC = "A9" ;
-NET "PHY_TXD<0>" LOC = "F8" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<1>" LOC = "G8" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<2>" LOC = "A6" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<3>" LOC = "B6" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<4>" LOC = "E6" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<5>" LOC = "F7" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<6>" LOC = "A5" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<7>" LOC = "C5" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXER" LOC = "A8" | SLEW = SLOW | DRIVE = 4;
-
-## SPI x4 Flash
-NET "SPI_CS_B" LOC = "V3";
-
-## 200 MHz oscillator (differential)
-NET "SYSCLK_N" LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
-NET "SYSCLK_P" LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
-
-## USB-UART
-## this names are real net names
-NET "USB_1_CTS" LOC = "U10"| DRIVE = 4 | SLEW = SLOW; # RTS output
-NET "USB_1_RTS" LOC = "T5" ; # CTS input
-NET "USB_1_RX" LOC = "L12"| DRIVE = 4 | SLEW = SLOW; # TX data out
-NET "USB_1_TX" LOC = "K14"; # RX data in
-
-## 27 MHz
-NET "USER_CLOCK" LOC = "V10"| IOSTANDARD = LVCMOS33 ;
-##
-NET "USER_SMA_CLOCK_N" LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";
-NET "USER_SMA_CLOCK_P" LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";
-
-# pins used for voltage termination
-CONFIG PROHIBIT = C1;
-CONFIG PROHIBIT = M5;
-CONFIG PROHIBIT = N3;
+############################################################
+# SPARTAN-6 SP601 Board Constraints File
+#
+# Family: Spartan6
+# Device: XC6SLX16
+# Package: CSG324
+# Speed: -2
+#
+#
+# Bank Voltage
+# Bank 0: 2.5 V
+# Bank 1: 2.5 V
+# Bank 2: 2.5 V
+# Bank 3: 1.8 V
+# VCCAUX: 2.5 V
+
+# following pins are connected to VCC1V8/2:
+# N3, M5, C1
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 200 MHz HIGH 50 %;
+TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 50 MHz HIGH 50 %;
+NET "USER_CLOCK" PERIOD = 27 MHz HIGH 40%;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "CPU_RESET" LOC = "N4";
+
+## 128 MB DDR2 Component Memory
+NET "DDR2_A<12>" LOC ="G6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<11>" LOC ="D3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<10>" LOC ="F4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<9>" LOC ="D1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<8>" LOC ="D2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<7>" LOC ="H6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<6>" LOC ="H3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<5>" LOC ="H4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<4>" LOC ="F3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<3>" LOC ="L7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<2>" LOC ="H5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<1>" LOC ="J6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<0>" LOC ="J7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<15>" LOC ="U1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<14>" LOC ="U2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<13>" LOC ="T1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<12>" LOC ="T2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<11>" LOC ="N1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<10>" LOC ="N2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<9>" LOC ="M1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<8>" LOC ="M3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<7>" LOC ="J1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<6>" LOC ="J3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<5>" LOC ="H1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<4>" LOC ="H2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<3>" LOC ="K1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<2>" LOC ="K2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<1>" LOC ="L1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<0>" LOC ="L2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_WE_B" LOC ="E3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_UDQS_P" LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDQS_N" LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDM" LOC ="K4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_RAS_B" LOC ="L5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_ODT" LOC ="K6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_LDQS_P" LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDQS_N" LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDM" LOC ="K3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CLK_P" LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CLK_N" LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CKE" LOC ="H7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CAS_B" LOC ="K5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<2>" LOC ="E1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<1>" LOC ="F1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<0>" LOC ="F2"; # | IOSTANDARD = SSTL18_II ;
+
+## Flash Memory
+NET "FLASH_A<0>" LOC = "K18";
+NET "FLASH_A<1>" LOC = "K17";
+NET "FLASH_A<2>" LOC = "J18";
+NET "FLASH_A<3>" LOC = "J16";
+NET "FLASH_A<4>" LOC = "G18";
+NET "FLASH_A<5>" LOC = "G16";
+NET "FLASH_A<6>" LOC = "H16";
+NET "FLASH_A<7>" LOC = "H15";
+NET "FLASH_A<8>" LOC = "H14";
+NET "FLASH_A<9>" LOC = "H13";
+NET "FLASH_A<10>" LOC = "F18";
+NET "FLASH_A<11>" LOC = "F17";
+NET "FLASH_A<12>" LOC = "K13";
+NET "FLASH_A<13>" LOC = "K12";
+NET "FLASH_A<14>" LOC = "E18";
+NET "FLASH_A<15>" LOC = "E16";
+NET "FLASH_A<16>" LOC = "G13";
+NET "FLASH_A<17>" LOC = "H12";
+NET "FLASH_A<18>" LOC = "D18";
+NET "FLASH_A<19>" LOC = "D17";
+NET "FLASH_A<20>" LOC = "G14";
+NET "FLASH_A<21>" LOC = "F14";
+NET "FLASH_A<22>" LOC = "C18";
+NET "FLASH_A<23>" LOC = "C17";
+NET "FLASH_A<24>" LOC = "F16";
+#NET "FLASH_D<0>" LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<1>" LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<2>" LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<3>" LOC = "U5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<4>" LOC = "V5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<5>" LOC = "R3" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<6>" LOC = "T3" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<7>" LOC = "R5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_OE_B" LOC = "L18";
+NET "FLASH_WE_B" LOC = "M16";
+NET "FLASH_CE_B" LOC = "L17";
+
+# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)
+NET "FMC_CLK0_M2C_N" LOC = "A10";
+NET "FMC_CLK0_M2C_P" LOC = "C10";
+NET "FMC_CLK1_M2C_N" LOC = "V9" ;
+NET "FMC_CLK1_M2C_P" LOC = "T9" ;
+NET "FMC_LA00_CC_N" LOC = "C9" ;
+NET "FMC_LA00_CC_P" LOC = "D9" ;
+NET "FMC_LA01_CC_N" LOC = "C11";
+NET "FMC_LA01_CC_P" LOC = "D11";
+NET "FMC_LA02_N" LOC = "A15";
+NET "FMC_LA02_P" LOC = "C15";
+NET "FMC_LA03_N" LOC = "A13";
+NET "FMC_LA03_P" LOC = "C13";
+NET "FMC_LA04_N" LOC = "A16";
+NET "FMC_LA04_P" LOC = "B16";
+NET "FMC_LA05_N" LOC = "A14";
+NET "FMC_LA05_P" LOC = "B14";
+NET "FMC_LA06_N" LOC = "C12";
+NET "FMC_LA06_P" LOC = "D12";
+NET "FMC_LA07_N" LOC = "E8" ;
+NET "FMC_LA07_P" LOC = "E7" ;
+NET "FMC_LA08_N" LOC = "E11";
+NET "FMC_LA08_P" LOC = "F11";
+NET "FMC_LA09_N" LOC = "F10";
+NET "FMC_LA09_P" LOC = "G11";
+NET "FMC_LA10_N" LOC = "C8" ;
+NET "FMC_LA10_P" LOC = "D8" ;
+NET "FMC_LA11_N" LOC = "A12";
+NET "FMC_LA11_P" LOC = "B12";
+NET "FMC_LA12_N" LOC = "C6" ;
+NET "FMC_LA12_P" LOC = "D6" ;
+NET "FMC_LA13_N" LOC = "A11";
+NET "FMC_LA13_P" LOC = "B11";
+NET "FMC_LA14_N" LOC = "A2" ;
+NET "FMC_LA14_P" LOC = "B2" ;
+NET "FMC_LA15_N" LOC = "F9" ;
+NET "FMC_LA15_P" LOC = "G9" ;
+NET "FMC_LA16_N" LOC = "A7" ;
+NET "FMC_LA16_P" LOC = "C7" ;
+NET "FMC_LA17_CC_N" LOC = "T8" ;
+NET "FMC_LA17_CC_P" LOC = "R8" ;
+NET "FMC_LA18_CC_N" LOC = "T10";
+NET "FMC_LA18_CC_P" LOC = "R10";
+NET "FMC_LA19_N" LOC = "P7" ;
+NET "FMC_LA19_P" LOC = "N6" ;
+NET "FMC_LA20_N" LOC = "P8" ;
+NET "FMC_LA20_P" LOC = "N7" ;
+NET "FMC_LA21_N" LOC = "V4" ;
+NET "FMC_LA21_P" LOC = "T4" ;
+NET "FMC_LA22_N" LOC = "T7" ;
+NET "FMC_LA22_P" LOC = "R7" ;
+NET "FMC_LA23_N" LOC = "P6" ;
+NET "FMC_LA23_P" LOC = "N5" ;
+NET "FMC_LA24_N" LOC = "V8" ;
+NET "FMC_LA24_P" LOC = "U8" ;
+NET "FMC_LA25_N" LOC = "N11";
+NET "FMC_LA25_P" LOC = "M11";
+NET "FMC_LA26_N" LOC = "V7" ;
+NET "FMC_LA26_P" LOC = "U7" ;
+NET "FMC_LA27_N" LOC = "T11";
+NET "FMC_LA27_P" LOC = "R11";
+NET "FMC_LA28_N" LOC = "V11";
+NET "FMC_LA28_P" LOC = "U11";
+NET "FMC_LA29_N" LOC = "N8" ;
+NET "FMC_LA29_P" LOC = "M8" ;
+NET "FMC_LA30_N" LOC = "V12";
+NET "FMC_LA30_P" LOC = "T12";
+NET "FMC_LA31_N" LOC = "V6" ;
+NET "FMC_LA31_P" LOC = "T6" ;
+NET "FMC_LA32_N" LOC = "V15";
+NET "FMC_LA32_P" LOC = "U15";
+NET "FMC_LA33_N" LOC = "N9" ;
+NET "FMC_LA33_P" LOC = "M10";
+NET "FMC_PRSNT_M2C_L" LOC = "U13";
+NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
+
+# special FPGA pins
+NET "FPGA_AWAKE" LOC = "P15"| SLEW = SLOW | DRIVE = 2;
+NET "FPGA_CCLK" LOC = "R15";
+NET "FPGA_CMP_CLK" LOC = "U16";
+NET "FPGA_CMP_MOSI" LOC = "V16";
+NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
+NET "FPGA_D1_MISO2" LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
+NET "FPGA_D2_MISO3" LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12
+NET "FPGA_HSWAPEN" LOC = "D4";
+NET "FPGA_INIT_B" LOC = "U3" | SLEW = SLOW | DRIVE = 4;
+NET "FPGA_M0_CMP_MISO" LOC = "T15";
+NET "FPGA_M1" LOC = "N12";
+NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13" | DRIVE = 4;
+NET "FPGA_ONCHIP_TERM1" LOC = "L6";
+NET "FPGA_ONCHIP_TERM2" LOC = "C2";
+NET "FPGA_VTEMP" LOC = "P3";
+
+## Pushbuttons, Bank 3, external Pulldown
+NET "GPIO_BUTTON<0>" LOC = "P4" ;
+NET "GPIO_BUTTON<1>" LOC = "F6" ;
+NET "GPIO_BUTTON<2>" LOC = "E4" ;
+NET "GPIO_BUTTON<3>" LOC = "F5" ;
+NET "GPIO_BUTTON*" TIG;
+
+## 8 Pin GPIO Header J13, Bank 0,1,2
+NET "GPIO_HEADER_LS<0>" LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<1>" LOC = "M18"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<2>" LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<3>" LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<4>" LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<5>" LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<6>" LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<7>" LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;
+
+## 4 GPIO LEDs, Bank 0
+NET "GPIO_LED<0>" LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<1>" LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<2>" LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<3>" LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED*" TIG;
+
+## GPIO Dip Switches, Bank 0,2, external Pulldown
+NET "GPIO_SWITCH<0>" LOC = "D14";
+NET "GPIO_SWITCH<1>" LOC = "E12";
+NET "GPIO_SWITCH<2>" LOC = "F12";
+NET "GPIO_SWITCH<3>" LOC = "V13";
+NET "GPIO_SWITCH*" TIG;
+
+## IIC Bus
+NET "IIC_SCL_MAIN" LOC = "P11";
+NET "IIC_SDA_MAIN" LOC = "N10";
+
+## 10/100/1000 Tri-Speed Ethernet PHY
+NET "PHY_COL" LOC = "L14";
+NET "PHY_CRS" LOC = "M13";
+NET "PHY_INT" LOC = "J13";
+NET "PHY_MDC" LOC = "N14" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_MDIO" LOC = "P16" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_RESET" LOC = "L13";
+NET "PHY_RXCLK" LOC = "L16";
+NET "PHY_RXCTL_RXDV" LOC = "N18";
+NET "PHY_RXD<0>" LOC = "M14";
+NET "PHY_RXD<1>" LOC = "U18";
+NET "PHY_RXD<2>" LOC = "U17";
+NET "PHY_RXD<3>" LOC = "T18";
+NET "PHY_RXD<4>" LOC = "T17";
+NET "PHY_RXD<5>" LOC = "N16";
+NET "PHY_RXD<6>" LOC = "N15";
+NET "PHY_RXD<7>" LOC = "P18";
+NET "PHY_RXER" LOC = "P17";
+NET "PHY_TXCLK" LOC = "B9" ;
+NET "PHY_TXCTL_TXEN" LOC = "B8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXC_GTXCLK" LOC = "A9" ;
+NET "PHY_TXD<0>" LOC = "F8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<1>" LOC = "G8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<2>" LOC = "A6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<3>" LOC = "B6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<4>" LOC = "E6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<5>" LOC = "F7" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<6>" LOC = "A5" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<7>" LOC = "C5" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXER" LOC = "A8" | SLEW = SLOW | DRIVE = 4;
+
+## SPI x4 Flash
+NET "SPI_CS_B" LOC = "V3";
+
+## 200 MHz oscillator (differential)
+NET "SYSCLK_N" LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+NET "SYSCLK_P" LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+
+## USB-UART
+## this names are real net names
+NET "USB_1_CTS" LOC = "U10"| DRIVE = 4 | SLEW = SLOW; # RTS output
+NET "USB_1_RTS" LOC = "T5" ; # CTS input
+NET "USB_1_RX" LOC = "L12"| DRIVE = 4 | SLEW = SLOW; # TX data out
+NET "USB_1_TX" LOC = "K14"; # RX data in
+
+## 27 MHz
+NET "USER_CLOCK" LOC = "V10"| IOSTANDARD = LVCMOS33 ;
+##
+NET "USER_SMA_CLOCK_N" LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";
+NET "USER_SMA_CLOCK_P" LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";
+
+# pins used for voltage termination
+CONFIG PROHIBIT = C1;
+CONFIG PROHIBIT = M5;
+CONFIG PROHIBIT = N3;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
index 120b1cf..bbeb0a2 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
@@ -1,533 +1,563 @@
--- top module of
--- SP601 evaluation board
---
--- using following external connections:
---
--- cpu_reset (SW9) reset
--- LEDs output
--- USB_UART communication
---
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-library zpu;
-use zpu.zpupkg.all; -- zpu_dbgo_t
-
-library unisim;
-use unisim.vcomponents.ibufgds;
-use unisim.vcomponents.dcm_sp;
-
-
-entity top is
- port (
- -- pragma translate_off
- stop_simulation : out std_logic;
- -- pragma translate_on
- --
- cpu_reset : in std_logic; -- SW9 pushbutton (active-high)
- --
- -- DDR2 memory 128 MB
- ddr2_a : out std_logic_vector(12 downto 0);
- ddr2_ba : out std_logic_vector(2 downto 0);
- ddr2_cas_b : out std_logic;
- ddr2_ras_b : out std_logic;
- ddr2_we_b : out std_logic;
- ddr2_cke : out std_logic;
- ddr2_clk_n : out std_logic;
- ddr2_clk_p : out std_logic;
- ddr2_dq : inout std_logic_vector(15 downto 0);
- ddr2_ldm : out std_logic;
- ddr2_udm : out std_logic;
- ddr2_ldqs_n : inout std_logic;
- ddr2_ldqs_p : inout std_logic;
- ddr2_udqs_n : inout std_logic;
- ddr2_udqs_p : inout std_logic;
- ddr2_odt : out std_logic;
- --
- -- flash memory
- flash_a : out std_logic_vector(24 downto 0);
- flash_d : inout std_logic_vector(7 downto 3);
- --
- fpga_d0_din_miso_miso1 : inout std_logic; -- dual use
- fpga_d1_miso2 : inout std_logic; -- dual use
- fpga_d2_miso3 : inout std_logic; -- dual use
- flash_we_b : out std_logic;
- flash_oe_b : out std_logic;
- flash_ce_b : out std_logic;
- --
- -- FMC connector
- -- M2C Mezzanine to Carrier
- -- C2M Carrier to Mezzanine
- fmc_clk0_m2c_n : in std_logic;
- fmc_clk0_m2c_p : in std_logic;
- fmc_clk1_m2c_n : in std_logic;
- fmc_clk1_m2c_p : in std_logic;
- -- IIC addresses:
- -- M24C08: 1010100..1010111
- -- 2kb EEPROM on FMC card: 1010010
- iic_scl_main : inout std_logic;
- iic_sda_main : inout std_logic;
- fmc_la00_cc_n : inout std_logic;
- fmc_la00_cc_p : inout std_logic;
- fmc_la01_cc_n : inout std_logic;
- fmc_la01_cc_p : inout std_logic;
- fmc_la02_n : inout std_logic;
- fmc_la02_p : inout std_logic;
- fmc_la03_n : inout std_logic;
- fmc_la03_p : inout std_logic;
- fmc_la04_n : inout std_logic;
- fmc_la04_p : inout std_logic;
- fmc_la05_n : inout std_logic;
- fmc_la05_p : inout std_logic;
- fmc_la06_n : inout std_logic;
- fmc_la06_p : inout std_logic;
- fmc_la07_n : inout std_logic;
- fmc_la07_p : inout std_logic;
- fmc_la08_n : inout std_logic;
- fmc_la08_p : inout std_logic;
- fmc_la09_n : inout std_logic;
- fmc_la09_p : inout std_logic;
- fmc_la10_n : inout std_logic;
- fmc_la10_p : inout std_logic;
- fmc_la11_n : inout std_logic;
- fmc_la11_p : inout std_logic;
- fmc_la12_n : inout std_logic;
- fmc_la12_p : inout std_logic;
- fmc_la13_n : inout std_logic;
- fmc_la13_p : inout std_logic;
- fmc_la14_n : inout std_logic;
- fmc_la14_p : inout std_logic;
- fmc_la15_n : inout std_logic;
- fmc_la15_p : inout std_logic;
- fmc_la16_n : inout std_logic;
- fmc_la16_p : inout std_logic;
- fmc_la17_cc_n : inout std_logic;
- fmc_la17_cc_p : inout std_logic;
- fmc_la18_cc_n : inout std_logic;
- fmc_la18_cc_p : inout std_logic;
- fmc_la19_n : inout std_logic;
- fmc_la19_p : inout std_logic;
- fmc_la20_n : inout std_logic;
- fmc_la20_p : inout std_logic;
- fmc_la21_n : inout std_logic;
- fmc_la21_p : inout std_logic;
- fmc_la22_n : inout std_logic;
- fmc_la22_p : inout std_logic;
- fmc_la23_n : inout std_logic;
- fmc_la23_p : inout std_logic;
- fmc_la24_n : inout std_logic;
- fmc_la24_p : inout std_logic;
- fmc_la25_n : inout std_logic;
- fmc_la25_p : inout std_logic;
- fmc_la26_n : inout std_logic;
- fmc_la26_p : inout std_logic;
- fmc_la27_n : inout std_logic;
- fmc_la27_p : inout std_logic;
- fmc_la28_n : inout std_logic;
- fmc_la28_p : inout std_logic;
- fmc_la29_n : inout std_logic;
- fmc_la29_p : inout std_logic;
- fmc_la30_n : inout std_logic;
- fmc_la30_p : inout std_logic;
- fmc_la31_n : inout std_logic;
- fmc_la31_p : inout std_logic;
- fmc_la32_n : inout std_logic;
- fmc_la32_p : inout std_logic;
- fmc_la33_n : inout std_logic;
- fmc_la33_p : inout std_logic;
- fmc_prsnt_m2c_l : in std_logic;
- fmc_pwr_good_flash_rst_b : out std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
- --
- fpga_awake : out std_logic;
- fpga_cclk : out std_logic;
- fpga_cmp_clk : in std_logic;
- fpga_cmp_mosi : in std_logic;
- --
- fpga_hswapen : in std_logic;
- fpga_init_b : out std_logic; -- low active
- fpga_m0_cmp_miso : in std_logic; -- mode DIP switch SW1 active high
- fpga_m1 : in std_logic; -- mode DIP switch SW1 active high
- fpga_mosi_csi_b_miso0 : inout std_logic;
- fpga_onchip_term1 : inout std_logic;
- fpga_onchip_term2 : inout std_logic;
- fpga_vtemp : in std_logic;
- --
- -- GPIOs
- gpio_button : in std_logic_vector(3 downto 0); -- active high
- gpio_header_ls : inout std_logic_vector(7 downto 0);
- gpio_led : out std_logic_vector(3 downto 0);
- gpio_switch : in std_logic_vector(3 downto 0); -- active high
- --
- -- Ethernet Gigabit PHY,
- -- default settings:
- -- phy address = 0b00111
- -- ANEG[3..0] = "1111"
- -- ENA_XC = 1
- -- DIS_125 = 1
- -- HWCFG_MD[3..0] = "1111"
- -- DIS_FC = 1
- -- DIS_SLEEP = 1
- -- SEL_BDT = 0
- -- INT_POL = 1
- -- 75/50Ohm = 0
- phy_col : in std_logic;
- phy_crs : in std_logic;
- phy_int : in std_logic;
- phy_mdc : out std_logic;
- phy_mdio : inout std_logic;
- phy_reset : out std_logic;
- phy_rxclk : in std_logic;
- phy_rxctl_rxdv : in std_logic;
- phy_rxd : in std_logic_vector(7 downto 0);
- phy_rxer : in std_logic;
- phy_txclk : in std_logic;
- phy_txctl_txen : out std_logic;
- phy_txc_gtxclk : out std_logic;
- phy_txd : out std_logic_vector(7 downto 0);
- phy_txer : out std_logic;
- --
- --
- spi_cs_b : out std_logic;
- --
- -- 200 MHz oscillator, jitter 50 ppm
- sysclk_n : in std_logic;
- sysclk_p : in std_logic;
- --
- -- RS232 via USB
- usb_1_cts : out std_logic; -- function: RTS output
- usb_1_rts : in std_logic; -- function: CTS input
- usb_1_rx : out std_logic; -- function: TX data out
- usb_1_tx : in std_logic; -- function: RX data in
- --
- -- 27 MHz, oscillator socket
- user_clock : in std_logic;
- --
- -- user clock provided per SMA
- user_sma_clock_p : in std_logic;
- user_sma_clock_n : in std_logic
- );
-end entity top;
-
-
-architecture rtl of top is
-
- ---------------------------
- -- type declarations
- type zpu_type is (zpu_small, zpu_medium);
-
- ---------------------------
- -- constant declarations
- constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
- -- modify frequency here
- constant clk_multiply : positive := 2; -- 2 for small, 2 for medium
- constant clk_divide : positive := 5; -- 4 for small, 5 for medium
- --
- --
- constant word_size_c : natural := 32; -- 32 bits data path
- constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
- --
- constant clk_frequency : positive := 200; -- input frequency for correct calculation
-
-
- ---------------------------
- -- component declarations
- component zpu_small1 is
- generic (
- word_size : natural := 32; -- 32 bits data path
- d_care_val : std_logic := '0'; -- Fill value
- clk_freq : positive := 50; -- 50 MHz clock
- brate : positive := 115200; -- RS232 baudrate
- addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
- bram_w : natural := 15 -- 15 bits RAM space=32 kB
- );
- port (
- clk_i : in std_logic; -- CPU clock
- rst_i : in std_logic; -- Reset
- break_o : out std_logic; -- Break executed
- dbg_o : out zpu_dbgo_t; -- Debug info
- rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic -- UART Rx
- );
- end component zpu_small1;
-
- component zpu_med1 is
- generic(
- word_size : natural := 32; -- 32 bits data path
- d_care_val : std_logic := '0'; -- Fill value
- clk_freq : positive := 50; -- 50 MHz clock
- brate : positive := 115200; -- RS232 baudrate
- addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
- bram_w : natural := 15 -- 15 bits RAM space=32 kB
- );
- port(
- clk_i : in std_logic; -- CPU clock
- rst_i : in std_logic; -- Reset
- break_o : out std_logic; -- Break executed
- dbg_o : out zpu_dbgo_t; -- Debug info
- rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic -- UART Rx
- );
- end component zpu_med1;
-
-
- ---------------------------
- -- signal declarations
- signal sys_clk : std_ulogic;
- signal dcm_sp_i0_clk0 : std_ulogic;
- signal dcm_sp_i0_clkfx : std_ulogic;
- signal clk_fb : std_ulogic;
- signal clk : std_ulogic;
- --
- signal reset_shift_reg : std_ulogic_vector(3 downto 0);
- signal reset_sync : std_ulogic;
- --
- signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
- signal zpu_i0_break : std_logic;
-
-
-begin
-
- -- default output drivers
- -- to pass bitgen DRC
- -- outputs used by design are commented
- --
- ddr2_a <= (others => '1');
- ddr2_ba <= (others => '1');
- ddr2_cas_b <= '1';
- ddr2_ras_b <= '1';
- ddr2_we_b <= '1';
- ddr2_cke <= '0';
- ddr2_clk_n <= '0';
- ddr2_clk_p <= '1';
- ddr2_dq <= (others => 'Z');
- ddr2_ldm <= '0';
- ddr2_udm <= '0';
- ddr2_ldqs_n <= 'Z';
- ddr2_ldqs_p <= 'Z';
- ddr2_udqs_n <= 'Z';
- ddr2_udqs_p <= 'Z';
- ddr2_odt <= '1';
- --
- flash_a <= (others => '1');
- flash_d <= (others => 'Z');
- flash_we_b <= '1';
- flash_oe_b <= '1';
- flash_ce_b <= '1';
- --
- fpga_d0_din_miso_miso1 <= 'Z';
- fpga_d1_miso2 <= 'Z';
- fpga_d2_miso3 <= 'Z';
- --
- iic_scl_main <= 'Z';
- iic_sda_main <= 'Z';
- fmc_la00_cc_n <= 'Z';
- fmc_la00_cc_p <= 'Z';
- fmc_la01_cc_n <= 'Z';
- fmc_la01_cc_p <= 'Z';
- fmc_la02_n <= 'Z';
- fmc_la02_p <= 'Z';
- fmc_la03_n <= 'Z';
- fmc_la03_p <= 'Z';
- fmc_la04_n <= 'Z';
- fmc_la04_p <= 'Z';
- fmc_la05_n <= 'Z';
- fmc_la05_p <= 'Z';
- fmc_la06_n <= 'Z';
- fmc_la06_p <= 'Z';
- fmc_la07_n <= 'Z';
- fmc_la07_p <= 'Z';
- fmc_la08_n <= 'Z';
- fmc_la08_p <= 'Z';
- fmc_la09_n <= 'Z';
- fmc_la09_p <= 'Z';
- fmc_la10_n <= 'Z';
- fmc_la10_p <= 'Z';
- fmc_la11_n <= 'Z';
- fmc_la11_p <= 'Z';
- fmc_la12_n <= 'Z';
- fmc_la12_p <= 'Z';
- fmc_la13_n <= 'Z';
- fmc_la13_p <= 'Z';
- fmc_la14_n <= 'Z';
- fmc_la14_p <= 'Z';
- fmc_la15_n <= 'Z';
- fmc_la15_p <= 'Z';
- fmc_la16_n <= 'Z';
- fmc_la16_p <= 'Z';
- fmc_la17_cc_n <= 'Z';
- fmc_la17_cc_p <= 'Z';
- fmc_la18_cc_n <= 'Z';
- fmc_la18_cc_p <= 'Z';
- fmc_la19_n <= 'Z';
- fmc_la19_p <= 'Z';
- fmc_la20_n <= 'Z';
- fmc_la20_p <= 'Z';
- fmc_la21_n <= 'Z';
- fmc_la21_p <= 'Z';
- fmc_la22_n <= 'Z';
- fmc_la22_p <= 'Z';
- fmc_la23_n <= 'Z';
- fmc_la23_p <= 'Z';
- fmc_la24_n <= 'Z';
- fmc_la24_p <= 'Z';
- fmc_la25_n <= 'Z';
- fmc_la25_p <= 'Z';
- fmc_la26_n <= 'Z';
- fmc_la26_p <= 'Z';
- fmc_la27_n <= 'Z';
- fmc_la27_p <= 'Z';
- fmc_la28_n <= 'Z';
- fmc_la28_p <= 'Z';
- fmc_la29_n <= 'Z';
- fmc_la29_p <= 'Z';
- fmc_la30_n <= 'Z';
- fmc_la30_p <= 'Z';
- fmc_la31_n <= 'Z';
- fmc_la31_p <= 'Z';
- fmc_la32_n <= 'Z';
- fmc_la32_p <= 'Z';
- fmc_la33_n <= 'Z';
- fmc_la33_p <= 'Z';
- fmc_pwr_good_flash_rst_b <= '1';
- --
- fpga_awake <= '1';
- fpga_cclk <= '1'; -- SPI clk
- fpga_init_b <= '1';
- fpga_mosi_csi_b_miso0 <= 'Z';
- fpga_onchip_term1 <= 'Z';
- fpga_onchip_term2 <= 'Z';
- --
- --gpio_led <= (others => '0');
- gpio_header_ls <= (others => 'Z');
- --
- phy_mdc <= '0';
- phy_mdio <= 'Z';
- phy_reset <= '0';
- phy_txc_gtxclk <= '0';
- phy_txctl_txen <= '0';
- phy_txd <= (others => '1');
- phy_txer <= '0';
- --
- spi_cs_b <= '1';
- --
- --usb_1_rx <= '1'; -- function: TX data out
- usb_1_cts <= '1'; -- function: RTS
-
-
- -- global differential input buffer
- ibufgds_i0 : ibufgds
- generic map (
- diff_term => true
- )
- port map (
- i => sysclk_p,
- ib => sysclk_n,
- o => sys_clk
- );
-
- -- digital clock manager (DCM)
- -- to generate higher/other system clock frequencys
- dcm_sp_i0 : dcm_sp
- generic map (
- startup_wait => true, -- wait with DONE till locked
- clkfx_multiply => clk_multiply,
- clkfx_divide => clk_divide,
- clk_feedback => "1X"
- )
- port map (
- clkin => sys_clk,
- clk0 => dcm_sp_i0_clk0,
- clkfx => dcm_sp_i0_clkfx,
- clkfb => clk_fb
- );
-
- clk_fb <= dcm_sp_i0_clk0;
- clk <= dcm_sp_i0_clkfx;
-
-
- -- reset synchronizer
- -- generate synchronous reset
- reset_synchronizer : process(clk, cpu_reset)
- begin
- if cpu_reset = '1' then
- reset_shift_reg <= (others => '1');
- elsif rising_edge(clk) then
- reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
- end if;
- end process;
- reset_sync <= reset_shift_reg(reset_shift_reg'high);
-
-
-
- -- select instance of zpu
- zpu_i0_small : if zpu_flavour = zpu_small generate
- zpu_i0 : zpu_small1
- generic map (
- addr_w => addr_w_c,
- word_size => word_size_c,
- clk_freq => clk_frequency * clk_multiply / clk_divide
- )
- port map (
- clk_i => clk, -- : in std_logic; -- CPU clock
- rst_i => reset_sync, -- : in std_logic; -- Reset
- break_o => zpu_i0_break, -- : out std_logic; -- Break executed
- dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
- rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
- rs232_rx_i => usb_1_tx -- : in std_logic -- UART Rx
- );
- end generate zpu_i0_small;
-
- zpu_i0_medium : if zpu_flavour = zpu_medium generate
- zpu_i0 : zpu_med1
- generic map (
- addr_w => addr_w_c,
- word_size => word_size_c,
- clk_freq => clk_frequency * clk_multiply / clk_divide
- )
- port map (
- clk_i => clk, -- : in std_logic; -- CPU clock
- rst_i => reset_sync, -- : in std_logic; -- Reset
- break_o => zpu_i0_break, -- : out std_logic; -- Break executed
- dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
- rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
- rs232_rx_i => usb_1_tx -- : in std_logic -- UART Rx
- );
- end generate zpu_i0_medium;
-
-
- -- pragma translate_off
- stop_simulation <= zpu_i0_break;
-
-
- trace_mod : trace
- generic map (
- addr_w => addr_w_c,
- word_size => word_size_c,
- log_file => "zpu_trace.log"
- )
- port map (
- clk_i => clk,
- dbg_i => zpu_i0_dbg,
- stop_i => zpu_i0_break,
- busy_i => '0'
- );
- -- pragma translate_on
-
-
- -- switch on all LEDs in case of break
- process
- begin
- wait until rising_edge(clk);
- if zpu_i0_break = '1' then
- gpio_led <= (others => '1');
- end if;
- if reset_sync = '1' then
- gpio_led <= (others => '0');
- end if;
- end process;
-
-
-
-end architecture rtl;
+-- top module of
+-- SP601 evaluation board
+--
+-- using following external connections:
+--
+-- cpu_reset (SW9) reset
+-- LEDs output
+-- USB_UART communication
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.ibufgds;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ --
+ cpu_reset : in std_logic; -- SW9 pushbutton (active-high)
+ --
+ -- DDR2 memory 128 MB
+ ddr2_a : out std_logic_vector(12 downto 0);
+ ddr2_ba : out std_logic_vector(2 downto 0);
+ ddr2_cas_b : out std_logic;
+ ddr2_ras_b : out std_logic;
+ ddr2_we_b : out std_logic;
+ ddr2_cke : out std_logic;
+ ddr2_clk_n : out std_logic;
+ ddr2_clk_p : out std_logic;
+ ddr2_dq : inout std_logic_vector(15 downto 0);
+ ddr2_ldm : out std_logic;
+ ddr2_udm : out std_logic;
+ ddr2_ldqs_n : inout std_logic;
+ ddr2_ldqs_p : inout std_logic;
+ ddr2_udqs_n : inout std_logic;
+ ddr2_udqs_p : inout std_logic;
+ ddr2_odt : out std_logic;
+ --
+ -- flash memory
+ flash_a : out std_logic_vector(24 downto 0);
+ flash_d : inout std_logic_vector(7 downto 3);
+ --
+ fpga_d0_din_miso_miso1 : inout std_logic; -- dual use
+ fpga_d1_miso2 : inout std_logic; -- dual use
+ fpga_d2_miso3 : inout std_logic; -- dual use
+ flash_we_b : out std_logic;
+ flash_oe_b : out std_logic;
+ flash_ce_b : out std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ fmc_clk0_m2c_n : in std_logic;
+ fmc_clk0_m2c_p : in std_logic;
+ fmc_clk1_m2c_n : in std_logic;
+ fmc_clk1_m2c_p : in std_logic;
+ -- IIC addresses:
+ -- M24C08: 1010100..1010111
+ -- 2kb EEPROM on FMC card: 1010010
+ iic_scl_main : inout std_logic;
+ iic_sda_main : inout std_logic;
+ fmc_la00_cc_n : inout std_logic;
+ fmc_la00_cc_p : inout std_logic;
+ fmc_la01_cc_n : inout std_logic;
+ fmc_la01_cc_p : inout std_logic;
+ fmc_la02_n : inout std_logic;
+ fmc_la02_p : inout std_logic;
+ fmc_la03_n : inout std_logic;
+ fmc_la03_p : inout std_logic;
+ fmc_la04_n : inout std_logic;
+ fmc_la04_p : inout std_logic;
+ fmc_la05_n : inout std_logic;
+ fmc_la05_p : inout std_logic;
+ fmc_la06_n : inout std_logic;
+ fmc_la06_p : inout std_logic;
+ fmc_la07_n : inout std_logic;
+ fmc_la07_p : inout std_logic;
+ fmc_la08_n : inout std_logic;
+ fmc_la08_p : inout std_logic;
+ fmc_la09_n : inout std_logic;
+ fmc_la09_p : inout std_logic;
+ fmc_la10_n : inout std_logic;
+ fmc_la10_p : inout std_logic;
+ fmc_la11_n : inout std_logic;
+ fmc_la11_p : inout std_logic;
+ fmc_la12_n : inout std_logic;
+ fmc_la12_p : inout std_logic;
+ fmc_la13_n : inout std_logic;
+ fmc_la13_p : inout std_logic;
+ fmc_la14_n : inout std_logic;
+ fmc_la14_p : inout std_logic;
+ fmc_la15_n : inout std_logic;
+ fmc_la15_p : inout std_logic;
+ fmc_la16_n : inout std_logic;
+ fmc_la16_p : inout std_logic;
+ fmc_la17_cc_n : inout std_logic;
+ fmc_la17_cc_p : inout std_logic;
+ fmc_la18_cc_n : inout std_logic;
+ fmc_la18_cc_p : inout std_logic;
+ fmc_la19_n : inout std_logic;
+ fmc_la19_p : inout std_logic;
+ fmc_la20_n : inout std_logic;
+ fmc_la20_p : inout std_logic;
+ fmc_la21_n : inout std_logic;
+ fmc_la21_p : inout std_logic;
+ fmc_la22_n : inout std_logic;
+ fmc_la22_p : inout std_logic;
+ fmc_la23_n : inout std_logic;
+ fmc_la23_p : inout std_logic;
+ fmc_la24_n : inout std_logic;
+ fmc_la24_p : inout std_logic;
+ fmc_la25_n : inout std_logic;
+ fmc_la25_p : inout std_logic;
+ fmc_la26_n : inout std_logic;
+ fmc_la26_p : inout std_logic;
+ fmc_la27_n : inout std_logic;
+ fmc_la27_p : inout std_logic;
+ fmc_la28_n : inout std_logic;
+ fmc_la28_p : inout std_logic;
+ fmc_la29_n : inout std_logic;
+ fmc_la29_p : inout std_logic;
+ fmc_la30_n : inout std_logic;
+ fmc_la30_p : inout std_logic;
+ fmc_la31_n : inout std_logic;
+ fmc_la31_p : inout std_logic;
+ fmc_la32_n : inout std_logic;
+ fmc_la32_p : inout std_logic;
+ fmc_la33_n : inout std_logic;
+ fmc_la33_p : inout std_logic;
+ fmc_prsnt_m2c_l : in std_logic;
+ fmc_pwr_good_flash_rst_b : out std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+ --
+ fpga_awake : out std_logic;
+ fpga_cclk : out std_logic;
+ fpga_cmp_clk : in std_logic;
+ fpga_cmp_mosi : in std_logic;
+ --
+ fpga_hswapen : in std_logic;
+ fpga_init_b : out std_logic; -- low active
+ fpga_m0_cmp_miso : in std_logic; -- mode DIP switch SW1 active high
+ fpga_m1 : in std_logic; -- mode DIP switch SW1 active high
+ fpga_mosi_csi_b_miso0 : inout std_logic;
+ fpga_onchip_term1 : inout std_logic;
+ fpga_onchip_term2 : inout std_logic;
+ fpga_vtemp : in std_logic;
+ --
+ -- GPIOs
+ gpio_button : in std_logic_vector(3 downto 0); -- active high
+ gpio_header_ls : inout std_logic_vector(7 downto 0);
+ gpio_led : out std_logic_vector(3 downto 0);
+ gpio_switch : in std_logic_vector(3 downto 0); -- active high
+ --
+ -- Ethernet Gigabit PHY,
+ -- default settings:
+ -- phy address = 0b00111
+ -- ANEG[3..0] = "1111"
+ -- ENA_XC = 1
+ -- DIS_125 = 1
+ -- HWCFG_MD[3..0] = "1111"
+ -- DIS_FC = 1
+ -- DIS_SLEEP = 1
+ -- SEL_BDT = 0
+ -- INT_POL = 1
+ -- 75/50Ohm = 0
+ phy_col : in std_logic;
+ phy_crs : in std_logic;
+ phy_int : in std_logic;
+ phy_mdc : out std_logic;
+ phy_mdio : inout std_logic;
+ phy_reset : out std_logic;
+ phy_rxclk : in std_logic;
+ phy_rxctl_rxdv : in std_logic;
+ phy_rxd : in std_logic_vector(7 downto 0);
+ phy_rxer : in std_logic;
+ phy_txclk : in std_logic;
+ phy_txctl_txen : out std_logic;
+ phy_txc_gtxclk : out std_logic;
+ phy_txd : out std_logic_vector(7 downto 0);
+ phy_txer : out std_logic;
+ --
+ --
+ spi_cs_b : out std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ sysclk_n : in std_logic;
+ sysclk_p : in std_logic;
+ --
+ -- RS232 via USB
+ usb_1_cts : out std_logic; -- function: RTS output
+ usb_1_rts : in std_logic; -- function: CTS input
+ usb_1_rx : out std_logic; -- function: TX data out
+ usb_1_tx : in std_logic; -- function: RX data in
+ --
+ -- 27 MHz, oscillator socket
+ user_clock : in std_logic;
+ --
+ -- user clock provided per SMA
+ user_sma_clock_p : in std_logic;
+ user_sma_clock_n : in std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 2; -- 2 for small, 2 for medium
+ constant clk_divide : positive := 5; -- 4 for small, 5 for medium
+ --
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ --
+ constant clk_frequency : positive := 200; -- input frequency for correct calculation
+
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+
+ ---------------------------
+ -- signal declarations
+ signal sys_clk : std_ulogic;
+ signal dcm_sp_i0_clk0 : std_ulogic;
+ signal dcm_sp_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0) := (others => '0');
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- outputs used by design are commented
+ --
+ ddr2_a <= (others => '1');
+ ddr2_ba <= (others => '1');
+ ddr2_cas_b <= '1';
+ ddr2_ras_b <= '1';
+ ddr2_we_b <= '1';
+ ddr2_cke <= '0';
+ ddr2_clk_n <= '0';
+ ddr2_clk_p <= '1';
+ ddr2_dq <= (others => 'Z');
+ ddr2_ldm <= '0';
+ ddr2_udm <= '0';
+ ddr2_ldqs_n <= 'Z';
+ ddr2_ldqs_p <= 'Z';
+ ddr2_udqs_n <= 'Z';
+ ddr2_udqs_p <= 'Z';
+ ddr2_odt <= '1';
+ --
+ flash_a <= (others => '1');
+ flash_d <= (others => 'Z');
+ flash_we_b <= '1';
+ flash_oe_b <= '1';
+ flash_ce_b <= '1';
+ --
+ fpga_d0_din_miso_miso1 <= 'Z';
+ fpga_d1_miso2 <= 'Z';
+ fpga_d2_miso3 <= 'Z';
+ --
+ iic_scl_main <= 'Z';
+ iic_sda_main <= 'Z';
+ fmc_la00_cc_n <= 'Z';
+ fmc_la00_cc_p <= 'Z';
+ fmc_la01_cc_n <= 'Z';
+ fmc_la01_cc_p <= 'Z';
+ fmc_la02_n <= 'Z';
+ fmc_la02_p <= 'Z';
+ fmc_la03_n <= 'Z';
+ fmc_la03_p <= 'Z';
+ fmc_la04_n <= 'Z';
+ fmc_la04_p <= 'Z';
+ fmc_la05_n <= 'Z';
+ fmc_la05_p <= 'Z';
+ fmc_la06_n <= 'Z';
+ fmc_la06_p <= 'Z';
+ fmc_la07_n <= 'Z';
+ fmc_la07_p <= 'Z';
+ fmc_la08_n <= 'Z';
+ fmc_la08_p <= 'Z';
+ fmc_la09_n <= 'Z';
+ fmc_la09_p <= 'Z';
+ fmc_la10_n <= 'Z';
+ fmc_la10_p <= 'Z';
+ fmc_la11_n <= 'Z';
+ fmc_la11_p <= 'Z';
+ fmc_la12_n <= 'Z';
+ fmc_la12_p <= 'Z';
+ fmc_la13_n <= 'Z';
+ fmc_la13_p <= 'Z';
+ fmc_la14_n <= 'Z';
+ fmc_la14_p <= 'Z';
+ fmc_la15_n <= 'Z';
+ fmc_la15_p <= 'Z';
+ fmc_la16_n <= 'Z';
+ fmc_la16_p <= 'Z';
+ fmc_la17_cc_n <= 'Z';
+ fmc_la17_cc_p <= 'Z';
+ fmc_la18_cc_n <= 'Z';
+ fmc_la18_cc_p <= 'Z';
+ fmc_la19_n <= 'Z';
+ fmc_la19_p <= 'Z';
+ fmc_la20_n <= 'Z';
+ fmc_la20_p <= 'Z';
+ fmc_la21_n <= 'Z';
+ fmc_la21_p <= 'Z';
+ fmc_la22_n <= 'Z';
+ fmc_la22_p <= 'Z';
+ fmc_la23_n <= 'Z';
+ fmc_la23_p <= 'Z';
+ fmc_la24_n <= 'Z';
+ fmc_la24_p <= 'Z';
+ fmc_la25_n <= 'Z';
+ fmc_la25_p <= 'Z';
+ fmc_la26_n <= 'Z';
+ fmc_la26_p <= 'Z';
+ fmc_la27_n <= 'Z';
+ fmc_la27_p <= 'Z';
+ fmc_la28_n <= 'Z';
+ fmc_la28_p <= 'Z';
+ fmc_la29_n <= 'Z';
+ fmc_la29_p <= 'Z';
+ fmc_la30_n <= 'Z';
+ fmc_la30_p <= 'Z';
+ fmc_la31_n <= 'Z';
+ fmc_la31_p <= 'Z';
+ fmc_la32_n <= 'Z';
+ fmc_la32_p <= 'Z';
+ fmc_la33_n <= 'Z';
+ fmc_la33_p <= 'Z';
+ fmc_pwr_good_flash_rst_b <= '1';
+ --
+ fpga_awake <= '1';
+ fpga_cclk <= '1'; -- SPI clk
+ fpga_init_b <= '1';
+ fpga_mosi_csi_b_miso0 <= 'Z';
+ fpga_onchip_term1 <= 'Z';
+ fpga_onchip_term2 <= 'Z';
+ --
+ --gpio_led <= (others => '0');
+ --gpio_header_ls <= (others => 'Z');
+ --
+ phy_mdc <= '0';
+ phy_mdio <= 'Z';
+ phy_reset <= '0';
+ phy_txc_gtxclk <= '0';
+ phy_txctl_txen <= '0';
+ phy_txd <= (others => '1');
+ phy_txer <= '0';
+ --
+ spi_cs_b <= '1';
+ --
+ --usb_1_rx <= '1'; -- function: TX data out
+ usb_1_cts <= '1'; -- function: RTS
+
+
+ -- global differential input buffer
+ ibufgds_i0 : ibufgds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ i => sysclk_p,
+ ib => sysclk_n,
+ o => sys_clk
+ );
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_sp_i0 : dcm_sp
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ clkin => sys_clk,
+ clk0 => dcm_sp_i0_clk0,
+ clkfx => dcm_sp_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ clk_fb <= dcm_sp_i0_clk0;
+ clk <= dcm_sp_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, cpu_reset)
+ begin
+ if cpu_reset = '1' then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+
+ -- select instance of zpu
+ zpu_i0_small: if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => usb_1_tx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium: if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => usb_1_tx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation
+
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+ -- assign GPIOs
+ gpio_in(23 downto 16) <= gpio_header_ls;
+ gpio_in(11 downto 8) <= gpio_switch;
+ gpio_in( 3 downto 0) <= gpio_button;
+
+ -- 3-state buffers for header_ls
+ gpio_header_ls(7) <= zpu_i0_gpio_out(23) when zpu_i0_gpio_dir(23) = '0' else 'Z';
+ gpio_header_ls(6) <= zpu_i0_gpio_out(22) when zpu_i0_gpio_dir(22) = '0' else 'Z';
+ gpio_header_ls(5) <= zpu_i0_gpio_out(21) when zpu_i0_gpio_dir(21) = '0' else 'Z';
+ gpio_header_ls(4) <= zpu_i0_gpio_out(20) when zpu_i0_gpio_dir(20) = '0' else 'Z';
+ gpio_header_ls(3) <= zpu_i0_gpio_out(19) when zpu_i0_gpio_dir(19) = '0' else 'Z';
+ gpio_header_ls(2) <= zpu_i0_gpio_out(18) when zpu_i0_gpio_dir(18) = '0' else 'Z';
+ gpio_header_ls(1) <= zpu_i0_gpio_out(17) when zpu_i0_gpio_dir(17) = '0' else 'Z';
+ gpio_header_ls(0) <= zpu_i0_gpio_out(16) when zpu_i0_gpio_dir(16) = '0' else 'Z';
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ gpio_led <= zpu_i0_gpio_out(3 downto 0);
+ if zpu_i0_break = '1' then
+ gpio_led <= (others => '1');
+ end if;
+ end process;
+
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
index b09b144..f089f29 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
@@ -1,398 +1,402 @@
--- testbench for
--- SP601 evaluation board
---
--- includes "model" for clock generation
--- simulate press on cpu_reset as reset
---
--- place models for external components (PHY, DDR2) in this file
---
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-
-entity top_tb is
-end entity top_tb;
-
-architecture testbench of top_tb is
-
- ---------------------------
- -- constant declarations
- constant sys_clk_period : time := 1 sec / 200_000_000; -- 200 MHz
- constant user_clk_period : time := 1 sec / 27_000_000; -- 27 MHz
-
-
- ---------------------------
- -- signal declarations
- signal simulation_run : boolean := true;
- signal tb_stop_simulation : std_logic;
- --
- signal tb_cpu_reset : std_logic; -- SW9 pushbutton (active-high)
- --
- -- DDR2 memory 128 MB
- signal tb_ddr2_a : std_logic_vector(12 downto 0);
- signal tb_ddr2_ba : std_logic_vector(2 downto 0);
- signal tb_ddr2_cas_b : std_logic;
- signal tb_ddr2_ras_b : std_logic;
- signal tb_ddr2_we_b : std_logic;
- signal tb_ddr2_cke : std_logic;
- signal tb_ddr2_clk_n : std_logic;
- signal tb_ddr2_clk_p : std_logic;
- signal tb_ddr2_dq : std_logic_vector(15 downto 0);
- signal tb_ddr2_ldm : std_logic;
- signal tb_ddr2_udm : std_logic;
- signal tb_ddr2_ldqs_n : std_logic;
- signal tb_ddr2_ldqs_p : std_logic;
- signal tb_ddr2_udqs_n : std_logic;
- signal tb_ddr2_udqs_p : std_logic;
- signal tb_ddr2_odt : std_logic;
- --
- -- flash memory
- signal tb_flash_a : std_logic_vector(24 downto 0);
- signal tb_flash_d : std_logic_vector(7 downto 3);
- signal tb_fpga_d0_din_miso_miso1 : std_logic; -- dual use
- signal tb_fpga_d1_miso2 : std_logic; -- dual use
- signal tb_fpga_d2_miso3 : std_logic; -- dual use
- signal tb_flash_we_b : std_logic;
- signal tb_flash_oe_b : std_logic;
- signal tb_flash_ce_b : std_logic;
- --
- -- FMC connector
- -- M2C Mezzanine to Carrier
- -- C2M Carrier to Mezzanine
- signal tb_fmc_clk0_m2c_n : std_logic := '1';
- signal tb_fmc_clk0_m2c_p : std_logic := '0';
- signal tb_fmc_clk1_m2c_n : std_logic := '1';
- signal tb_fmc_clk1_m2c_p : std_logic := '0';
- -- IIC addresses:
- -- M24C08: 1010100..1010111
- -- 2kb EEPROM on FMC card: 1010010
- signal tb_iic_scl_main : std_logic;
- signal tb_iic_sda_main : std_logic;
- signal tb_fmc_la00_cc_n : std_logic;
- signal tb_fmc_la00_cc_p : std_logic;
- signal tb_fmc_la01_cc_n : std_logic;
- signal tb_fmc_la01_cc_p : std_logic;
- signal tb_fmc_la02_n : std_logic;
- signal tb_fmc_la02_p : std_logic;
- signal tb_fmc_la03_n : std_logic;
- signal tb_fmc_la03_p : std_logic;
- signal tb_fmc_la04_n : std_logic;
- signal tb_fmc_la04_p : std_logic;
- signal tb_fmc_la05_n : std_logic;
- signal tb_fmc_la05_p : std_logic;
- signal tb_fmc_la06_n : std_logic;
- signal tb_fmc_la06_p : std_logic;
- signal tb_fmc_la07_n : std_logic;
- signal tb_fmc_la07_p : std_logic;
- signal tb_fmc_la08_n : std_logic;
- signal tb_fmc_la08_p : std_logic;
- signal tb_fmc_la09_n : std_logic;
- signal tb_fmc_la09_p : std_logic;
- signal tb_fmc_la10_n : std_logic;
- signal tb_fmc_la10_p : std_logic;
- signal tb_fmc_la11_n : std_logic;
- signal tb_fmc_la11_p : std_logic;
- signal tb_fmc_la12_n : std_logic;
- signal tb_fmc_la12_p : std_logic;
- signal tb_fmc_la13_n : std_logic;
- signal tb_fmc_la13_p : std_logic;
- signal tb_fmc_la14_n : std_logic;
- signal tb_fmc_la14_p : std_logic;
- signal tb_fmc_la15_n : std_logic;
- signal tb_fmc_la15_p : std_logic;
- signal tb_fmc_la16_n : std_logic;
- signal tb_fmc_la16_p : std_logic;
- signal tb_fmc_la17_cc_n : std_logic;
- signal tb_fmc_la17_cc_p : std_logic;
- signal tb_fmc_la18_cc_n : std_logic;
- signal tb_fmc_la18_cc_p : std_logic;
- signal tb_fmc_la19_n : std_logic;
- signal tb_fmc_la19_p : std_logic;
- signal tb_fmc_la20_n : std_logic;
- signal tb_fmc_la20_p : std_logic;
- signal tb_fmc_la21_n : std_logic;
- signal tb_fmc_la21_p : std_logic;
- signal tb_fmc_la22_n : std_logic;
- signal tb_fmc_la22_p : std_logic;
- signal tb_fmc_la23_n : std_logic;
- signal tb_fmc_la23_p : std_logic;
- signal tb_fmc_la24_n : std_logic;
- signal tb_fmc_la24_p : std_logic;
- signal tb_fmc_la25_n : std_logic;
- signal tb_fmc_la25_p : std_logic;
- signal tb_fmc_la26_n : std_logic;
- signal tb_fmc_la26_p : std_logic;
- signal tb_fmc_la27_n : std_logic;
- signal tb_fmc_la27_p : std_logic;
- signal tb_fmc_la28_n : std_logic;
- signal tb_fmc_la28_p : std_logic;
- signal tb_fmc_la29_n : std_logic;
- signal tb_fmc_la29_p : std_logic;
- signal tb_fmc_la30_n : std_logic;
- signal tb_fmc_la30_p : std_logic;
- signal tb_fmc_la31_n : std_logic;
- signal tb_fmc_la31_p : std_logic;
- signal tb_fmc_la32_n : std_logic;
- signal tb_fmc_la32_p : std_logic;
- signal tb_fmc_la33_n : std_logic;
- signal tb_fmc_la33_p : std_logic;
- signal tb_fmc_prsnt_m2c_l : std_logic := '0';
- signal tb_fmc_pwr_good_flash_rst_b : std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
- --
- signal tb_fpga_awake : std_logic;
- signal tb_fpga_cclk : std_logic;
- signal tb_fpga_cmp_clk : std_logic := '0';
- signal tb_fpga_cmp_mosi : std_logic := '0';
- signal tb_fpga_hswapen : std_logic := '0';
- signal tb_fpga_init_b : std_logic; -- low active
- signal tb_fpga_m0_cmp_miso : std_logic := '0'; -- mode DIP switch SW1 active high
- signal tb_fpga_m1 : std_logic := '0'; -- mode DIP switch SW1 active high
- signal tb_fpga_mosi_csi_b_miso0 : std_logic;
- signal tb_fpga_onchip_term1 : std_logic;
- signal tb_fpga_onchip_term2 : std_logic;
- signal tb_fpga_vtemp : std_logic := '0';
- --
- -- GPIOs
- signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0'); -- active high
- signal tb_gpio_header_ls : std_logic_vector(7 downto 0); --
- signal tb_gpio_led : std_logic_vector(3 downto 0);
- signal tb_gpio_switch : std_logic_vector(3 downto 0) := (others => '0'); -- active high
- --
- -- Ethernet Gigabit PHY
- signal tb_phy_col : std_logic := '0';
- signal tb_phy_crs : std_logic := '0';
- signal tb_phy_int : std_logic := '0';
- signal tb_phy_mdc : std_logic;
- signal tb_phy_mdio : std_logic;
- signal tb_phy_reset : std_logic;
- signal tb_phy_rxclk : std_logic := '0';
- signal tb_phy_rxctl_rxdv : std_logic := '0';
- signal tb_phy_rxd : std_logic_vector(7 downto 0);
- signal tb_phy_rxer : std_logic := '0';
- signal tb_phy_txclk : std_logic := '0';
- signal tb_phy_txctl_txen : std_logic;
- signal tb_phy_txc_gtxclk : std_logic;
- signal tb_phy_txd : std_logic_vector(7 downto 0);
- signal tb_phy_txer : std_logic;
- --
- --
- signal tb_spi_cs_b : std_logic;
- --
- -- 200 MHz oscillator, jitter 50 ppm
- signal tb_sysclk_n : std_logic := '1';
- signal tb_sysclk_p : std_logic := '0';
- --
- -- RS232 via USB
- signal tb_usb_1_cts : std_logic; -- function: RTS output
- signal tb_usb_1_rts : std_logic := '0'; -- function: CTS input
- signal tb_usb_1_rx : std_logic; -- function: TX data out
- signal tb_usb_1_tx : std_logic := '0'; -- function: RX data in
- --
- -- 27 MHz, oscillator socket
- signal tb_user_clock : std_logic := '0';
- --
- -- user clock provided per SMA
- signal tb_user_sma_clock_p : std_logic := '0';
- signal tb_user_sma_clock_n : std_logic := '0';
-
-
-
-begin
-
- -- generate clocks
- tb_sysclk_p <= not tb_sysclk_p after sys_clk_period / 2 when simulation_run;
- tb_sysclk_n <= not tb_sysclk_n after sys_clk_period / 2 when simulation_run;
- tb_user_clock <= not tb_user_clock after user_clk_period / 2 when simulation_run;
-
- -- generate reset
- tb_cpu_reset <= '1', '0' after 6.66 * sys_clk_period;
-
- -- dut
- top_i0 : entity work.top
- port map (
- stop_simulation => tb_stop_simulation, -- : out std_logic;
- --
- cpu_reset => tb_cpu_reset, -- : in std_logic;
- --
- -- DDR2 memory 128 MB
- ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0);
- ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(2 downto 0);
- ddr2_cas_b => tb_ddr2_cas_b, -- : out std_logic;
- ddr2_ras_b => tb_ddr2_ras_b, -- : out std_logic;
- ddr2_we_b => tb_ddr2_we_b, -- : out std_logic;
- ddr2_cke => tb_ddr2_cke, -- : out std_logic;
- ddr2_clk_n => tb_ddr2_clk_n, -- : out std_logic;
- ddr2_clk_p => tb_ddr2_clk_p, -- : out std_logic;
- ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(15 downto 0);
- ddr2_ldm => tb_ddr2_ldm, -- : out std_logic;
- ddr2_udm => tb_ddr2_udm, -- : out std_logic;
- ddr2_ldqs_n => tb_ddr2_ldqs_n, -- : inout std_logic;
- ddr2_ldqs_p => tb_ddr2_ldqs_p, -- : inout std_logic;
- ddr2_udqs_n => tb_ddr2_udqs_n, -- : inout std_logic;
- ddr2_udqs_p => tb_ddr2_udqs_p, -- : inout std_logic;
- ddr2_odt => tb_ddr2_odt, -- : out std_logic;
- --
- -- flash memory
- flash_a => tb_flash_a, -- : out std_logic_vector(24 downto 0);
- flash_d => tb_flash_d, -- : inout std_logic_vector(7 downto 3);
- -- --
- fpga_d0_din_miso_miso1 => tb_fpga_d0_din_miso_miso1, -- : inout std_logic;
- fpga_d1_miso2 => tb_fpga_d1_miso2, -- : inout std_logic;
- fpga_d2_miso3 => tb_fpga_d2_miso3, -- : inout std_logic;
- flash_we_b => tb_flash_we_b, -- : out std_logic;
- flash_oe_b => tb_flash_oe_b, -- : out std_logic;
- flash_ce_b => tb_flash_ce_b, -- : out std_logic;
- --
- -- FMC connector
- -- M2C Mezzanine to Carrier
- -- C2M Carrier to Mezzanine
- fmc_clk0_m2c_n => tb_fmc_clk0_m2c_n, -- : in std_logic;
- fmc_clk0_m2c_p => tb_fmc_clk0_m2c_p, -- : in std_logic;
- fmc_clk1_m2c_n => tb_fmc_clk1_m2c_n, -- : in std_logic;
- fmc_clk1_m2c_p => tb_fmc_clk1_m2c_p, -- : in std_logic;
- iic_scl_main => tb_iic_scl_main, -- : inout std_logic;
- iic_sda_main => tb_iic_sda_main, -- : inout std_logic;
- fmc_la00_cc_n => tb_fmc_la00_cc_n, -- : inout std_logic;
- fmc_la00_cc_p => tb_fmc_la00_cc_p, -- : inout std_logic;
- fmc_la01_cc_n => tb_fmc_la01_cc_n, -- : inout std_logic;
- fmc_la01_cc_p => tb_fmc_la01_cc_p, -- : inout std_logic;
- fmc_la02_n => tb_fmc_la02_n, -- : inout std_logic;
- fmc_la02_p => tb_fmc_la02_p, -- : inout std_logic;
- fmc_la03_n => tb_fmc_la03_n, -- : inout std_logic;
- fmc_la03_p => tb_fmc_la03_p, -- : inout std_logic;
- fmc_la04_n => tb_fmc_la04_n, -- : inout std_logic;
- fmc_la04_p => tb_fmc_la04_p, -- : inout std_logic;
- fmc_la05_n => tb_fmc_la05_n, -- : inout std_logic;
- fmc_la05_p => tb_fmc_la05_p, -- : inout std_logic;
- fmc_la06_n => tb_fmc_la06_n, -- : inout std_logic;
- fmc_la06_p => tb_fmc_la06_p, -- : inout std_logic;
- fmc_la07_n => tb_fmc_la07_n, -- : inout std_logic;
- fmc_la07_p => tb_fmc_la07_p, -- : inout std_logic;
- fmc_la08_n => tb_fmc_la08_n, -- : inout std_logic;
- fmc_la08_p => tb_fmc_la08_p, -- : inout std_logic;
- fmc_la09_n => tb_fmc_la09_n, -- : inout std_logic;
- fmc_la09_p => tb_fmc_la09_p, -- : inout std_logic;
- fmc_la10_n => tb_fmc_la10_n, -- : inout std_logic;
- fmc_la10_p => tb_fmc_la10_p, -- : inout std_logic;
- fmc_la11_n => tb_fmc_la11_n, -- : inout std_logic;
- fmc_la11_p => tb_fmc_la11_p, -- : inout std_logic;
- fmc_la12_n => tb_fmc_la12_n, -- : inout std_logic;
- fmc_la12_p => tb_fmc_la12_p, -- : inout std_logic;
- fmc_la13_n => tb_fmc_la13_n, -- : inout std_logic;
- fmc_la13_p => tb_fmc_la13_p, -- : inout std_logic;
- fmc_la14_n => tb_fmc_la14_n, -- : inout std_logic;
- fmc_la14_p => tb_fmc_la14_p, -- : inout std_logic;
- fmc_la15_n => tb_fmc_la15_n, -- : inout std_logic;
- fmc_la15_p => tb_fmc_la15_p, -- : inout std_logic;
- fmc_la16_n => tb_fmc_la16_n, -- : inout std_logic;
- fmc_la16_p => tb_fmc_la16_p, -- : inout std_logic;
- fmc_la17_cc_n => tb_fmc_la17_cc_n, -- : inout std_logic;
- fmc_la17_cc_p => tb_fmc_la17_cc_p, -- : inout std_logic;
- fmc_la18_cc_n => tb_fmc_la18_cc_n, -- : inout std_logic;
- fmc_la18_cc_p => tb_fmc_la18_cc_p, -- : inout std_logic;
- fmc_la19_n => tb_fmc_la19_n, -- : inout std_logic;
- fmc_la19_p => tb_fmc_la19_p, -- : inout std_logic;
- fmc_la20_n => tb_fmc_la20_n, -- : inout std_logic;
- fmc_la20_p => tb_fmc_la20_p, -- : inout std_logic;
- fmc_la21_n => tb_fmc_la21_n, -- : inout std_logic;
- fmc_la21_p => tb_fmc_la21_p, -- : inout std_logic;
- fmc_la22_n => tb_fmc_la22_n, -- : inout std_logic;
- fmc_la22_p => tb_fmc_la22_p, -- : inout std_logic;
- fmc_la23_n => tb_fmc_la23_n, -- : inout std_logic;
- fmc_la23_p => tb_fmc_la23_p, -- : inout std_logic;
- fmc_la24_n => tb_fmc_la24_n, -- : inout std_logic;
- fmc_la24_p => tb_fmc_la24_p, -- : inout std_logic;
- fmc_la25_n => tb_fmc_la25_n, -- : inout std_logic;
- fmc_la25_p => tb_fmc_la25_p, -- : inout std_logic;
- fmc_la26_n => tb_fmc_la26_n, -- : inout std_logic;
- fmc_la26_p => tb_fmc_la26_p, -- : inout std_logic;
- fmc_la27_n => tb_fmc_la27_n, -- : inout std_logic;
- fmc_la27_p => tb_fmc_la27_p, -- : inout std_logic;
- fmc_la28_n => tb_fmc_la28_n, -- : inout std_logic;
- fmc_la28_p => tb_fmc_la28_p, -- : inout std_logic;
- fmc_la29_n => tb_fmc_la29_n, -- : inout std_logic;
- fmc_la29_p => tb_fmc_la29_p, -- : inout std_logic;
- fmc_la30_n => tb_fmc_la30_n, -- : inout std_logic;
- fmc_la30_p => tb_fmc_la30_p, -- : inout std_logic;
- fmc_la31_n => tb_fmc_la31_n, -- : inout std_logic;
- fmc_la31_p => tb_fmc_la31_p, -- : inout std_logic;
- fmc_la32_n => tb_fmc_la32_n, -- : inout std_logic;
- fmc_la32_p => tb_fmc_la32_p, -- : inout std_logic;
- fmc_la33_n => tb_fmc_la33_n, -- : inout std_logic;
- fmc_la33_p => tb_fmc_la33_p, -- : inout std_logic;
- fmc_prsnt_m2c_l => tb_fmc_prsnt_m2c_l, -- : in std_logic;
- fmc_pwr_good_flash_rst_b => tb_fmc_pwr_good_flash_rst_b, -- : out std_logic;
- --
- fpga_awake => tb_fpga_awake, -- : out std_logic;
- fpga_cclk => tb_fpga_cclk, -- : out std_logic;
- fpga_cmp_clk => tb_fpga_cmp_clk, -- : in std_logic;
- fpga_cmp_mosi => tb_fpga_cmp_mosi, -- : in std_logic;
- -- --
- fpga_hswapen => tb_fpga_hswapen, -- : in std_logic;
- fpga_init_b => tb_fpga_init_b, -- : out std_logic;
- fpga_m0_cmp_miso => tb_fpga_m0_cmp_miso, -- : in std_logic;
- fpga_m1 => tb_fpga_m1, -- : in std_logic;
- fpga_mosi_csi_b_miso0 => tb_fpga_mosi_csi_b_miso0, -- : inout std_logic;
- fpga_onchip_term1 => tb_fpga_onchip_term1, -- : inout std_logic;
- fpga_onchip_term2 => tb_fpga_onchip_term2, -- : inout std_logic;
- fpga_vtemp => tb_fpga_vtemp, -- : in std_logic;
- --
- -- GPIOs
- gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0);
- gpio_header_ls => tb_gpio_header_ls, -- : inout std_logic_vector(7 downto 0);
- gpio_led => tb_gpio_led, -- : out std_logic_vector(3 downto 0);
- gpio_switch => tb_gpio_switch, -- : in std_logic_vector(3 downto 0);
- --
- -- Ethernet Gigabit PHY
- phy_col => tb_phy_col, -- : in std_logic;
- phy_crs => tb_phy_crs, -- : in std_logic;
- phy_int => tb_phy_int, -- : in std_logic;
- phy_mdc => tb_phy_mdc, -- : out std_logic;
- phy_mdio => tb_phy_mdio, -- : inout std_logic;
- phy_reset => tb_phy_reset, -- : out std_logic;
- phy_rxclk => tb_phy_rxclk, -- : in std_logic;
- phy_rxctl_rxdv => tb_phy_rxctl_rxdv, -- : in std_logic;
- phy_rxd => tb_phy_rxd, -- : in std_logic_vector(7 downto 0);
- phy_rxer => tb_phy_rxer, -- : in std_logic;
- phy_txclk => tb_phy_txclk, -- : in std_logic;
- phy_txctl_txen => tb_phy_txctl_txen, -- : out std_logic;
- phy_txc_gtxclk => tb_phy_txc_gtxclk, -- : out std_logic;
- phy_txd => tb_phy_txd, -- : out std_logic_vector(7 downto 0);
- phy_txer => tb_phy_txer, -- : out std_logic;
- --
- --
- spi_cs_b => tb_spi_cs_b, -- : out std_logic;
- --
- -- 200 MHz oscillator, jitter 50 ppm
- sysclk_n => tb_sysclk_n, -- : in std_logic;
- sysclk_p => tb_sysclk_p, -- : in std_logic;
- --
- -- RS232 via USB
- usb_1_cts => tb_usb_1_cts, -- : out std_logic;
- usb_1_rts => tb_usb_1_rts, -- : in std_logic;
- usb_1_rx => tb_usb_1_rx, -- : out std_logic;
- usb_1_tx => tb_usb_1_tx, -- : in std_logic;
- --
- -- 27 MHz, oscillator socket
- user_clock => tb_user_clock, -- : in std_logic;
- --
- -- user clock provided per SMA
- user_sma_clock_p => tb_user_sma_clock_p, -- : in std_logic;
- user_sma_clock_n => tb_user_sma_clock_n -- : in std_logic
- );
-
-
- -- check for simulation stopping
- process (tb_stop_simulation)
- begin
- if tb_stop_simulation = '1' then
- report "Simulation end." severity note;
- simulation_run <= false;
- end if;
- end process;
-
-
-end architecture testbench;
-
+-- testbench for
+-- SP601 evaluation board
+--
+-- includes "model" for clock generation
+-- simulate press on cpu_reset as reset
+--
+-- place models for external components (PHY, DDR2) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant sys_clk_period : time := 1 sec / 200_000_000; -- 200 MHz
+ constant user_clk_period : time := 1 sec / 27_000_000; -- 27 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ signal tb_cpu_reset : std_logic; -- SW9 pushbutton (active-high)
+ --
+ -- DDR2 memory 128 MB
+ signal tb_ddr2_a : std_logic_vector(12 downto 0);
+ signal tb_ddr2_ba : std_logic_vector(2 downto 0);
+ signal tb_ddr2_cas_b : std_logic;
+ signal tb_ddr2_ras_b : std_logic;
+ signal tb_ddr2_we_b : std_logic;
+ signal tb_ddr2_cke : std_logic;
+ signal tb_ddr2_clk_n : std_logic;
+ signal tb_ddr2_clk_p : std_logic;
+ signal tb_ddr2_dq : std_logic_vector(15 downto 0);
+ signal tb_ddr2_ldm : std_logic;
+ signal tb_ddr2_udm : std_logic;
+ signal tb_ddr2_ldqs_n : std_logic;
+ signal tb_ddr2_ldqs_p : std_logic;
+ signal tb_ddr2_udqs_n : std_logic;
+ signal tb_ddr2_udqs_p : std_logic;
+ signal tb_ddr2_odt : std_logic;
+ --
+ -- flash memory
+ signal tb_flash_a : std_logic_vector(24 downto 0);
+ signal tb_flash_d : std_logic_vector(7 downto 3);
+ signal tb_fpga_d0_din_miso_miso1 : std_logic; -- dual use
+ signal tb_fpga_d1_miso2 : std_logic; -- dual use
+ signal tb_fpga_d2_miso3 : std_logic; -- dual use
+ signal tb_flash_we_b : std_logic;
+ signal tb_flash_oe_b : std_logic;
+ signal tb_flash_ce_b : std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ signal tb_fmc_clk0_m2c_n : std_logic := '1';
+ signal tb_fmc_clk0_m2c_p : std_logic := '0';
+ signal tb_fmc_clk1_m2c_n : std_logic := '1';
+ signal tb_fmc_clk1_m2c_p : std_logic := '0';
+ -- IIC addresses:
+ -- M24C08: 1010100..1010111
+ -- 2kb EEPROM on FMC card: 1010010
+ signal tb_iic_scl_main : std_logic;
+ signal tb_iic_sda_main : std_logic;
+ signal tb_fmc_la00_cc_n : std_logic;
+ signal tb_fmc_la00_cc_p : std_logic;
+ signal tb_fmc_la01_cc_n : std_logic;
+ signal tb_fmc_la01_cc_p : std_logic;
+ signal tb_fmc_la02_n : std_logic;
+ signal tb_fmc_la02_p : std_logic;
+ signal tb_fmc_la03_n : std_logic;
+ signal tb_fmc_la03_p : std_logic;
+ signal tb_fmc_la04_n : std_logic;
+ signal tb_fmc_la04_p : std_logic;
+ signal tb_fmc_la05_n : std_logic;
+ signal tb_fmc_la05_p : std_logic;
+ signal tb_fmc_la06_n : std_logic;
+ signal tb_fmc_la06_p : std_logic;
+ signal tb_fmc_la07_n : std_logic;
+ signal tb_fmc_la07_p : std_logic;
+ signal tb_fmc_la08_n : std_logic;
+ signal tb_fmc_la08_p : std_logic;
+ signal tb_fmc_la09_n : std_logic;
+ signal tb_fmc_la09_p : std_logic;
+ signal tb_fmc_la10_n : std_logic;
+ signal tb_fmc_la10_p : std_logic;
+ signal tb_fmc_la11_n : std_logic;
+ signal tb_fmc_la11_p : std_logic;
+ signal tb_fmc_la12_n : std_logic;
+ signal tb_fmc_la12_p : std_logic;
+ signal tb_fmc_la13_n : std_logic;
+ signal tb_fmc_la13_p : std_logic;
+ signal tb_fmc_la14_n : std_logic;
+ signal tb_fmc_la14_p : std_logic;
+ signal tb_fmc_la15_n : std_logic;
+ signal tb_fmc_la15_p : std_logic;
+ signal tb_fmc_la16_n : std_logic;
+ signal tb_fmc_la16_p : std_logic;
+ signal tb_fmc_la17_cc_n : std_logic;
+ signal tb_fmc_la17_cc_p : std_logic;
+ signal tb_fmc_la18_cc_n : std_logic;
+ signal tb_fmc_la18_cc_p : std_logic;
+ signal tb_fmc_la19_n : std_logic;
+ signal tb_fmc_la19_p : std_logic;
+ signal tb_fmc_la20_n : std_logic;
+ signal tb_fmc_la20_p : std_logic;
+ signal tb_fmc_la21_n : std_logic;
+ signal tb_fmc_la21_p : std_logic;
+ signal tb_fmc_la22_n : std_logic;
+ signal tb_fmc_la22_p : std_logic;
+ signal tb_fmc_la23_n : std_logic;
+ signal tb_fmc_la23_p : std_logic;
+ signal tb_fmc_la24_n : std_logic;
+ signal tb_fmc_la24_p : std_logic;
+ signal tb_fmc_la25_n : std_logic;
+ signal tb_fmc_la25_p : std_logic;
+ signal tb_fmc_la26_n : std_logic;
+ signal tb_fmc_la26_p : std_logic;
+ signal tb_fmc_la27_n : std_logic;
+ signal tb_fmc_la27_p : std_logic;
+ signal tb_fmc_la28_n : std_logic;
+ signal tb_fmc_la28_p : std_logic;
+ signal tb_fmc_la29_n : std_logic;
+ signal tb_fmc_la29_p : std_logic;
+ signal tb_fmc_la30_n : std_logic;
+ signal tb_fmc_la30_p : std_logic;
+ signal tb_fmc_la31_n : std_logic;
+ signal tb_fmc_la31_p : std_logic;
+ signal tb_fmc_la32_n : std_logic;
+ signal tb_fmc_la32_p : std_logic;
+ signal tb_fmc_la33_n : std_logic;
+ signal tb_fmc_la33_p : std_logic;
+ signal tb_fmc_prsnt_m2c_l : std_logic := '0';
+ signal tb_fmc_pwr_good_flash_rst_b : std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+ --
+ signal tb_fpga_awake : std_logic;
+ signal tb_fpga_cclk : std_logic;
+ signal tb_fpga_cmp_clk : std_logic := '0';
+ signal tb_fpga_cmp_mosi : std_logic := '0';
+ signal tb_fpga_hswapen : std_logic := '0';
+ signal tb_fpga_init_b : std_logic; -- low active
+ signal tb_fpga_m0_cmp_miso : std_logic := '0'; -- mode DIP switch SW1 active high
+ signal tb_fpga_m1 : std_logic := '0'; -- mode DIP switch SW1 active high
+ signal tb_fpga_mosi_csi_b_miso0 : std_logic;
+ signal tb_fpga_onchip_term1 : std_logic;
+ signal tb_fpga_onchip_term2 : std_logic;
+ signal tb_fpga_vtemp : std_logic := '0';
+ --
+ -- GPIOs
+ signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0'); -- active high
+ signal tb_gpio_header_ls : std_logic_vector(7 downto 0); --
+ signal tb_gpio_led : std_logic_vector(3 downto 0);
+ signal tb_gpio_switch : std_logic_vector(3 downto 0) := (others => '0'); -- active high
+ --
+ -- Ethernet Gigabit PHY
+ signal tb_phy_col : std_logic := '0';
+ signal tb_phy_crs : std_logic := '0';
+ signal tb_phy_int : std_logic := '0';
+ signal tb_phy_mdc : std_logic;
+ signal tb_phy_mdio : std_logic;
+ signal tb_phy_reset : std_logic;
+ signal tb_phy_rxclk : std_logic := '0';
+ signal tb_phy_rxctl_rxdv : std_logic := '0';
+ signal tb_phy_rxd : std_logic_vector(7 downto 0);
+ signal tb_phy_rxer : std_logic := '0';
+ signal tb_phy_txclk : std_logic := '0';
+ signal tb_phy_txctl_txen : std_logic;
+ signal tb_phy_txc_gtxclk : std_logic;
+ signal tb_phy_txd : std_logic_vector(7 downto 0);
+ signal tb_phy_txer : std_logic;
+ --
+ --
+ signal tb_spi_cs_b : std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ signal tb_sysclk_n : std_logic := '1';
+ signal tb_sysclk_p : std_logic := '0';
+ --
+ -- RS232 via USB
+ signal tb_usb_1_cts : std_logic; -- function: RTS output
+ signal tb_usb_1_rts : std_logic := '0'; -- function: CTS input
+ signal tb_usb_1_rx : std_logic; -- function: TX data out
+ signal tb_usb_1_tx : std_logic := '0'; -- function: RX data in
+ --
+ -- 27 MHz, oscillator socket
+ signal tb_user_clock : std_logic := '0';
+ --
+ -- user clock provided per SMA
+ signal tb_user_sma_clock_p : std_logic := '0';
+ signal tb_user_sma_clock_n : std_logic := '0';
+
+
+
+begin
+
+ -- generate clocks
+ tb_sysclk_p <= not tb_sysclk_p after sys_clk_period / 2 when simulation_run;
+ tb_sysclk_n <= not tb_sysclk_n after sys_clk_period / 2 when simulation_run;
+ tb_user_clock <= not tb_user_clock after user_clk_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_cpu_reset <= '1', '0' after 6.66 * sys_clk_period;
+
+
+ -- simulate keypress
+ tb_gpio_button(2) <= '0', '1' after 50 us, '0' after 52 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ --
+ cpu_reset => tb_cpu_reset, -- : in std_logic;
+ --
+ -- DDR2 memory 128 MB
+ ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0);
+ ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(2 downto 0);
+ ddr2_cas_b => tb_ddr2_cas_b, -- : out std_logic;
+ ddr2_ras_b => tb_ddr2_ras_b, -- : out std_logic;
+ ddr2_we_b => tb_ddr2_we_b, -- : out std_logic;
+ ddr2_cke => tb_ddr2_cke, -- : out std_logic;
+ ddr2_clk_n => tb_ddr2_clk_n, -- : out std_logic;
+ ddr2_clk_p => tb_ddr2_clk_p, -- : out std_logic;
+ ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(15 downto 0);
+ ddr2_ldm => tb_ddr2_ldm, -- : out std_logic;
+ ddr2_udm => tb_ddr2_udm, -- : out std_logic;
+ ddr2_ldqs_n => tb_ddr2_ldqs_n, -- : inout std_logic;
+ ddr2_ldqs_p => tb_ddr2_ldqs_p, -- : inout std_logic;
+ ddr2_udqs_n => tb_ddr2_udqs_n, -- : inout std_logic;
+ ddr2_udqs_p => tb_ddr2_udqs_p, -- : inout std_logic;
+ ddr2_odt => tb_ddr2_odt, -- : out std_logic;
+ --
+ -- flash memory
+ flash_a => tb_flash_a, -- : out std_logic_vector(24 downto 0);
+ flash_d => tb_flash_d, -- : inout std_logic_vector(7 downto 3);
+ -- --
+ fpga_d0_din_miso_miso1 => tb_fpga_d0_din_miso_miso1, -- : inout std_logic;
+ fpga_d1_miso2 => tb_fpga_d1_miso2, -- : inout std_logic;
+ fpga_d2_miso3 => tb_fpga_d2_miso3, -- : inout std_logic;
+ flash_we_b => tb_flash_we_b, -- : out std_logic;
+ flash_oe_b => tb_flash_oe_b, -- : out std_logic;
+ flash_ce_b => tb_flash_ce_b, -- : out std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ fmc_clk0_m2c_n => tb_fmc_clk0_m2c_n, -- : in std_logic;
+ fmc_clk0_m2c_p => tb_fmc_clk0_m2c_p, -- : in std_logic;
+ fmc_clk1_m2c_n => tb_fmc_clk1_m2c_n, -- : in std_logic;
+ fmc_clk1_m2c_p => tb_fmc_clk1_m2c_p, -- : in std_logic;
+ iic_scl_main => tb_iic_scl_main, -- : inout std_logic;
+ iic_sda_main => tb_iic_sda_main, -- : inout std_logic;
+ fmc_la00_cc_n => tb_fmc_la00_cc_n, -- : inout std_logic;
+ fmc_la00_cc_p => tb_fmc_la00_cc_p, -- : inout std_logic;
+ fmc_la01_cc_n => tb_fmc_la01_cc_n, -- : inout std_logic;
+ fmc_la01_cc_p => tb_fmc_la01_cc_p, -- : inout std_logic;
+ fmc_la02_n => tb_fmc_la02_n, -- : inout std_logic;
+ fmc_la02_p => tb_fmc_la02_p, -- : inout std_logic;
+ fmc_la03_n => tb_fmc_la03_n, -- : inout std_logic;
+ fmc_la03_p => tb_fmc_la03_p, -- : inout std_logic;
+ fmc_la04_n => tb_fmc_la04_n, -- : inout std_logic;
+ fmc_la04_p => tb_fmc_la04_p, -- : inout std_logic;
+ fmc_la05_n => tb_fmc_la05_n, -- : inout std_logic;
+ fmc_la05_p => tb_fmc_la05_p, -- : inout std_logic;
+ fmc_la06_n => tb_fmc_la06_n, -- : inout std_logic;
+ fmc_la06_p => tb_fmc_la06_p, -- : inout std_logic;
+ fmc_la07_n => tb_fmc_la07_n, -- : inout std_logic;
+ fmc_la07_p => tb_fmc_la07_p, -- : inout std_logic;
+ fmc_la08_n => tb_fmc_la08_n, -- : inout std_logic;
+ fmc_la08_p => tb_fmc_la08_p, -- : inout std_logic;
+ fmc_la09_n => tb_fmc_la09_n, -- : inout std_logic;
+ fmc_la09_p => tb_fmc_la09_p, -- : inout std_logic;
+ fmc_la10_n => tb_fmc_la10_n, -- : inout std_logic;
+ fmc_la10_p => tb_fmc_la10_p, -- : inout std_logic;
+ fmc_la11_n => tb_fmc_la11_n, -- : inout std_logic;
+ fmc_la11_p => tb_fmc_la11_p, -- : inout std_logic;
+ fmc_la12_n => tb_fmc_la12_n, -- : inout std_logic;
+ fmc_la12_p => tb_fmc_la12_p, -- : inout std_logic;
+ fmc_la13_n => tb_fmc_la13_n, -- : inout std_logic;
+ fmc_la13_p => tb_fmc_la13_p, -- : inout std_logic;
+ fmc_la14_n => tb_fmc_la14_n, -- : inout std_logic;
+ fmc_la14_p => tb_fmc_la14_p, -- : inout std_logic;
+ fmc_la15_n => tb_fmc_la15_n, -- : inout std_logic;
+ fmc_la15_p => tb_fmc_la15_p, -- : inout std_logic;
+ fmc_la16_n => tb_fmc_la16_n, -- : inout std_logic;
+ fmc_la16_p => tb_fmc_la16_p, -- : inout std_logic;
+ fmc_la17_cc_n => tb_fmc_la17_cc_n, -- : inout std_logic;
+ fmc_la17_cc_p => tb_fmc_la17_cc_p, -- : inout std_logic;
+ fmc_la18_cc_n => tb_fmc_la18_cc_n, -- : inout std_logic;
+ fmc_la18_cc_p => tb_fmc_la18_cc_p, -- : inout std_logic;
+ fmc_la19_n => tb_fmc_la19_n, -- : inout std_logic;
+ fmc_la19_p => tb_fmc_la19_p, -- : inout std_logic;
+ fmc_la20_n => tb_fmc_la20_n, -- : inout std_logic;
+ fmc_la20_p => tb_fmc_la20_p, -- : inout std_logic;
+ fmc_la21_n => tb_fmc_la21_n, -- : inout std_logic;
+ fmc_la21_p => tb_fmc_la21_p, -- : inout std_logic;
+ fmc_la22_n => tb_fmc_la22_n, -- : inout std_logic;
+ fmc_la22_p => tb_fmc_la22_p, -- : inout std_logic;
+ fmc_la23_n => tb_fmc_la23_n, -- : inout std_logic;
+ fmc_la23_p => tb_fmc_la23_p, -- : inout std_logic;
+ fmc_la24_n => tb_fmc_la24_n, -- : inout std_logic;
+ fmc_la24_p => tb_fmc_la24_p, -- : inout std_logic;
+ fmc_la25_n => tb_fmc_la25_n, -- : inout std_logic;
+ fmc_la25_p => tb_fmc_la25_p, -- : inout std_logic;
+ fmc_la26_n => tb_fmc_la26_n, -- : inout std_logic;
+ fmc_la26_p => tb_fmc_la26_p, -- : inout std_logic;
+ fmc_la27_n => tb_fmc_la27_n, -- : inout std_logic;
+ fmc_la27_p => tb_fmc_la27_p, -- : inout std_logic;
+ fmc_la28_n => tb_fmc_la28_n, -- : inout std_logic;
+ fmc_la28_p => tb_fmc_la28_p, -- : inout std_logic;
+ fmc_la29_n => tb_fmc_la29_n, -- : inout std_logic;
+ fmc_la29_p => tb_fmc_la29_p, -- : inout std_logic;
+ fmc_la30_n => tb_fmc_la30_n, -- : inout std_logic;
+ fmc_la30_p => tb_fmc_la30_p, -- : inout std_logic;
+ fmc_la31_n => tb_fmc_la31_n, -- : inout std_logic;
+ fmc_la31_p => tb_fmc_la31_p, -- : inout std_logic;
+ fmc_la32_n => tb_fmc_la32_n, -- : inout std_logic;
+ fmc_la32_p => tb_fmc_la32_p, -- : inout std_logic;
+ fmc_la33_n => tb_fmc_la33_n, -- : inout std_logic;
+ fmc_la33_p => tb_fmc_la33_p, -- : inout std_logic;
+ fmc_prsnt_m2c_l => tb_fmc_prsnt_m2c_l, -- : in std_logic;
+ fmc_pwr_good_flash_rst_b => tb_fmc_pwr_good_flash_rst_b, -- : out std_logic;
+ --
+ fpga_awake => tb_fpga_awake, -- : out std_logic;
+ fpga_cclk => tb_fpga_cclk, -- : out std_logic;
+ fpga_cmp_clk => tb_fpga_cmp_clk, -- : in std_logic;
+ fpga_cmp_mosi => tb_fpga_cmp_mosi, -- : in std_logic;
+ -- --
+ fpga_hswapen => tb_fpga_hswapen, -- : in std_logic;
+ fpga_init_b => tb_fpga_init_b, -- : out std_logic;
+ fpga_m0_cmp_miso => tb_fpga_m0_cmp_miso, -- : in std_logic;
+ fpga_m1 => tb_fpga_m1, -- : in std_logic;
+ fpga_mosi_csi_b_miso0 => tb_fpga_mosi_csi_b_miso0, -- : inout std_logic;
+ fpga_onchip_term1 => tb_fpga_onchip_term1, -- : inout std_logic;
+ fpga_onchip_term2 => tb_fpga_onchip_term2, -- : inout std_logic;
+ fpga_vtemp => tb_fpga_vtemp, -- : in std_logic;
+ --
+ -- GPIOs
+ gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0);
+ gpio_header_ls => tb_gpio_header_ls, -- : inout std_logic_vector(7 downto 0);
+ gpio_led => tb_gpio_led, -- : out std_logic_vector(3 downto 0);
+ gpio_switch => tb_gpio_switch, -- : in std_logic_vector(3 downto 0);
+ --
+ -- Ethernet Gigabit PHY
+ phy_col => tb_phy_col, -- : in std_logic;
+ phy_crs => tb_phy_crs, -- : in std_logic;
+ phy_int => tb_phy_int, -- : in std_logic;
+ phy_mdc => tb_phy_mdc, -- : out std_logic;
+ phy_mdio => tb_phy_mdio, -- : inout std_logic;
+ phy_reset => tb_phy_reset, -- : out std_logic;
+ phy_rxclk => tb_phy_rxclk, -- : in std_logic;
+ phy_rxctl_rxdv => tb_phy_rxctl_rxdv, -- : in std_logic;
+ phy_rxd => tb_phy_rxd, -- : in std_logic_vector(7 downto 0);
+ phy_rxer => tb_phy_rxer, -- : in std_logic;
+ phy_txclk => tb_phy_txclk, -- : in std_logic;
+ phy_txctl_txen => tb_phy_txctl_txen, -- : out std_logic;
+ phy_txc_gtxclk => tb_phy_txc_gtxclk, -- : out std_logic;
+ phy_txd => tb_phy_txd, -- : out std_logic_vector(7 downto 0);
+ phy_txer => tb_phy_txer, -- : out std_logic;
+ --
+ --
+ spi_cs_b => tb_spi_cs_b, -- : out std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ sysclk_n => tb_sysclk_n, -- : in std_logic;
+ sysclk_p => tb_sysclk_p, -- : in std_logic;
+ --
+ -- RS232 via USB
+ usb_1_cts => tb_usb_1_cts, -- : out std_logic;
+ usb_1_rts => tb_usb_1_rts, -- : in std_logic;
+ usb_1_rx => tb_usb_1_rx, -- : out std_logic;
+ usb_1_tx => tb_usb_1_tx, -- : in std_logic;
+ --
+ -- 27 MHz, oscillator socket
+ user_clock => tb_user_clock, -- : in std_logic;
+ --
+ -- user clock provided per SMA
+ user_sma_clock_p => tb_user_sma_clock_p, -- : in std_logic;
+ user_sma_clock_n => tb_user_sma_clock_n -- : in std_logic
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+
+end architecture testbench;
+
diff --git a/zpu/hdl/zealot/helpers/zpu_med1.vhdl b/zpu/hdl/zealot/helpers/zpu_med1.vhdl
index fb19e0c..a0cbcb2 100644
--- a/zpu/hdl/zealot/helpers/zpu_med1.vhdl
+++ b/zpu/hdl/zealot/helpers/zpu_med1.vhdl
@@ -67,7 +67,11 @@ entity ZPU_Med1 is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic); -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
end entity ZPU_Med1;
architecture Structural of ZPU_Med1 is
@@ -114,12 +118,25 @@ begin
-- I/O: Phi layout
io_map: ZPUPhiIO
generic map(
- BRDIVISOR => BRDIVISOR, LOG_FILE => "zpu_med1_io.log")
+ BRDIVISOR => BRDIVISOR,
+ LOG_FILE => "zpu_med1_io.log"
+ )
port map(
- clk_i => clk_i, reset_i => rst_i, busy_o => io_busy, we_i => io_we,
- re_i => io_re, data_i => mem_write, data_o => io_read,
- addr_i => io_addr, rs232_rx_i => rs232_rx_i, rs232_tx_o => rs232_tx_o,
- br_clk_i => '1');
+ clk_i => clk_i,
+ reset_i => rst_i,
+ busy_o => io_busy,
+ we_i => io_we,
+ re_i => io_re,
+ data_i => mem_write,
+ data_o => io_read,
+ addr_i => io_addr,
+ rs232_rx_i => rs232_rx_i,
+ rs232_tx_o => rs232_tx_o,
+ br_clk_i => '1',
+ gpio_in => gpio_in,
+ gpio_out => gpio_out,
+ gpio_dir => gpio_dir
+ );
io_addr <= mem_addr(4 downto 2);
-- Here we decode 0x8xxxx as I/O and not just 0x80A00xx
-- Note: We define the address space as 256 kB, so writing to 0x80A00xx
diff --git a/zpu/hdl/zealot/helpers/zpu_small1.vhdl b/zpu/hdl/zealot/helpers/zpu_small1.vhdl
index 13dd485..52006e4 100644
--- a/zpu/hdl/zealot/helpers/zpu_small1.vhdl
+++ b/zpu/hdl/zealot/helpers/zpu_small1.vhdl
@@ -67,7 +67,11 @@ entity ZPU_Small1 is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic); -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
end entity ZPU_Small1;
architecture Structural of ZPU_Small1 is
@@ -111,12 +115,25 @@ begin
-- I/O: Phi layout
io_map: ZPUPhiIO
generic map(
- BRDIVISOR => BRDIVISOR, LOG_FILE => "zpu_small1_io.log")
+ BRDIVISOR => BRDIVISOR,
+ LOG_FILE => "zpu_small1_io.log"
+ )
port map(
- clk_i => clk_i, reset_i => rst_i, busy_o => io_busy, we_i => io_we,
- re_i => io_re, data_i => io_write, data_o => io_read,
- addr_i => phi_addr, rs232_rx_i => rs232_rx_i, rs232_tx_o => rs232_tx_o,
- br_clk_i => '1');
+ clk_i => clk_i,
+ reset_i => rst_i,
+ busy_o => io_busy,
+ we_i => io_we,
+ re_i => io_re,
+ data_i => io_write,
+ data_o => io_read,
+ addr_i => phi_addr,
+ rs232_rx_i => rs232_rx_i,
+ rs232_tx_o => rs232_tx_o,
+ br_clk_i => '1',
+ gpio_in => gpio_in,
+ gpio_out => gpio_out,
+ gpio_dir => gpio_dir
+ );
phi_addr <= io_addr(4 downto 2);
zpu : ZPUSmallCore
diff --git a/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl
index 4361b9c..8bdcdd3 100644
--- a/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl
+++ b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl
@@ -80,7 +80,11 @@ architecture Behave of DMIPS_Med1_TB is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic); -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
end component ZPU_Med1;
signal clk : std_logic;
@@ -98,7 +102,8 @@ begin
BRAM_W => BRAM_W)
port map(
clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
- rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg);
+ rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
+ gpio_in => (others => '0'));
trace_mod : Trace
generic map(
diff --git a/zpu/hdl/zealot/testbenches/small1_tb.vhdl b/zpu/hdl/zealot/testbenches/small1_tb.vhdl
index bada24b..a77e5bc 100644
--- a/zpu/hdl/zealot/testbenches/small1_tb.vhdl
+++ b/zpu/hdl/zealot/testbenches/small1_tb.vhdl
@@ -80,7 +80,11 @@ architecture Behave of Small1_TB is
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
- rs232_rx_i : in std_logic); -- UART Rx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
end component ZPU_Small1;
signal clk : std_logic;
@@ -98,7 +102,8 @@ begin
BRAM_W => BRAM_W)
port map(
clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
- rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg);
+ rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
+ gpio_in => (others => '0'));
trace_mod : Trace
generic map(
diff --git a/zpu/hdl/zealot/zpu_pkg.vhdl b/zpu/hdl/zealot/zpu_pkg.vhdl
index 2a15880..915f352 100644
--- a/zpu/hdl/zealot/zpu_pkg.vhdl
+++ b/zpu/hdl/zealot/zpu_pkg.vhdl
@@ -140,6 +140,23 @@ package zpupkg is
data_o : out unsigned(31 downto 0));
end component Timer;
+ component gpio is
+ port(
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ --
+ we_i : in std_logic;
+ data_i : in unsigned(31 downto 0);
+ addr_i : in unsigned( 0 downto 0);
+ data_o : out unsigned(31 downto 0);
+ --
+ port_in : in std_logic_vector(31 downto 0);
+ port_out : out std_logic_vector(31 downto 0);
+ port_dir : out std_logic_vector(31 downto 0)
+ );
+ end component gpio;
+
+
component ZPUPhiIO is
generic(
BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4
@@ -153,10 +170,16 @@ package zpupkg is
re_i : in std_logic; -- Read Enable
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
- addr_i : in unsigned(2 downto 0); -- Address bits 4-2
+ addr_i : in unsigned(2 downto 0); -- Address bits 4-2
+ --
rs232_rx_i : in std_logic; -- UART Rx input
rs232_tx_o : out std_logic; -- UART Tx output
- br_clk_i : in std_logic); -- UART base clock (enable)
+ br_clk_i : in std_logic; -- UART base clock (enable)
+ --
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0)
+ );
end component ZPUPhiIO;
-- Opcode decode constants
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