add: GPIO module to zealot SoC

6 files changed, 87 insertions, 45 deletions

diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
index febf588..d525737 100755
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
@@ -28,6 +28,7 @@ vcom -work zpu ../../helpers/zpu_med1.vhdl
 vcom -work zpu ../../devices/txt_util.vhdl
 vcom -work zpu ../../devices/phi_io.vhdl
 vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
 vcom -work zpu ../../devices/rx_unit.vhdl
 vcom -work zpu ../../devices/tx_unit.vhdl
 vcom -work zpu ../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
index 20e68e0..d572a06 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
@@ -1,26 +1,30 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /top_tb/tb_gpio_button(0)
-add wave -noupdate /top_tb/tb_clk_100mhz
-add wave -noupdate -divider <NULL>
-add wave -noupdate /top_tb/tb_rs232_rx
-add wave -noupdate /top_tb/tb_rs232_tx
-add wave -noupdate /top_tb/tb_rs232_rts
-add wave -noupdate /top_tb/tb_rs232_cts
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {0 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 2
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {1188293312 ps}
+onerror {resume}

+quietly WaveActivateNextPane {} 0

+add wave -noupdate /top_tb/tb_gpio_button(0)

+add wave -noupdate /top_tb/tb_clk_100MHz

+add wave -noupdate -divider <NULL>

+add wave -noupdate /top_tb/tb_rs232_rx

+add wave -noupdate /top_tb/tb_rs232_tx

+add wave -noupdate /top_tb/tb_rs232_rts

+add wave -noupdate /top_tb/tb_rs232_cts

+add wave -noupdate -divider Buttons

+add wave -noupdate /top_tb/tb_gpio_button

+add wave -noupdate -divider LEDs

+add wave -noupdate /top_tb/tb_gpio_led_n

+TreeUpdate [SetDefaultTree]

+WaveRestoreCursors {{Cursor 1} {0 ps} 0}

+configure wave -namecolwidth 150

+configure wave -valuecolwidth 100

+configure wave -justifyvalue left

+configure wave -signalnamewidth 2

+configure wave -snapdistance 10

+configure wave -datasetprefix 0

+configure wave -rowmargin 4

+configure wave -childrowmargin 2

+configure wave -gridoffset 0

+configure wave -gridperiod 1

+configure wave -griddelta 40

+configure wave -timeline 0

+configure wave -timelineunits ns

+update

+WaveRestoreZoom {0 ps} {126912555 ps}

diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
index 30b3982..8494af3 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
@@ -29,6 +29,19 @@ TIMESPEC "TS_clk_100" = PERIOD "clk_100" 100 MHz;
 
 
 ############################################################
+## design placement constraints
+############################################################
+#
+# the following constraint are need if you want to synthesize
+# zpu_medium with 125 MHz
+#
+INST "zpu_i0_medium.zpu_i0/zpu/*" AREA_GROUP = "zpu_block";
+AREA_GROUP "zpu_block" RANGE=SLICE_X18Y0:SLICE_X55Y41;
+AREA_GROUP "zpu_block" RANGE=DSP48_X0Y0:DSP48_X0Y15;
+AREA_GROUP "zpu_block" RANGE=RAMB36_X1Y0:RAMB36_X3Y7;
+
+
+############################################################
 ## pin placement constraints
 ############################################################
 
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
index 81d56ef..24120d5 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
@@ -12,6 +12,7 @@ vhdl zpu ../../../helpers/zpu_med1.vhdl
 vhdl zpu ../../../devices/txt_util.vhdl
 vhdl zpu ../../../devices/phi_io.vhdl
 vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
 vhdl zpu ../../../devices/rx_unit.vhdl
 vhdl zpu ../../../devices/tx_unit.vhdl
 vhdl zpu ../../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
index 1e2fa97..53383cc 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
@@ -22,7 +22,7 @@ use unisim.vcomponents.dcm_base;
 entity top is
     port (
         -- pragma translate_off 
-        stop_simulation : out   std_logic;
+        stop_simulation     : out   std_logic;
         -- pragma translate_on 
         clk_100MHz          : in    std_logic;  -- 100 MHz clock
         clk_socket          : in    std_logic;  -- user clock
@@ -169,7 +169,10 @@ architecture rtl of top is
             break_o    : out std_logic;        -- Break executed
             dbg_o      : out zpu_dbgo_t;       -- Debug info
             rs232_tx_o : out std_logic;        -- UART Tx
-            rs232_rx_i : in  std_logic         -- UART Rx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
             );
     end component zpu_small1;
 
@@ -188,7 +191,10 @@ architecture rtl of top is
             break_o    : out std_logic;        -- Break executed
             dbg_o      : out zpu_dbgo_t;       -- Debug info
             rs232_tx_o : out std_logic;        -- UART Tx
-            rs232_rx_i : in  std_logic         -- UART Rx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
             );
     end component zpu_med1;
 
@@ -210,7 +216,11 @@ architecture rtl of top is
     --
     signal ibufds_i0_o       : std_ulogic;
     signal ibufds_i1_o       : std_ulogic;
-
+    --
+    signal gpio_in           : std_logic_vector(31 downto 0) := (others => '0');
+    signal zpu_i0_gpio_out   : std_logic_vector(31 downto 0);
+    signal zpu_i0_gpio_dir   : std_logic_vector(31 downto 0);
+    
 begin
   
     -- default output drivers
@@ -348,12 +358,15 @@ begin
                 clk_freq  => clk_frequency * clk_multiply / clk_divide
                 )
             port map (
-                clk_i      => clk,           -- : in  std_logic;   - CPU clock
-                rst_i      => reset_sync,    -- : in  std_logic;   - Reset
-                break_o    => zpu_i0_break,  -- : out std_logic;   - Break executed
-                dbg_o      => zpu_i0_dbg,    -- : out zpu_dbgo_t;  - Debug info
-                rs232_tx_o => rs232_tx,      -- : out std_logic;   - UART Tx
-                rs232_rx_i => rs232_rx       -- : in  std_logic    - UART Rx
+                clk_i      => clk,             -- : in  std_logic;   - CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   - Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   - Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  - Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   - UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    - UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
                 );
     end generate zpu_i0_small;
 
@@ -365,12 +378,15 @@ begin
                 clk_freq  => clk_frequency * clk_multiply / clk_divide
                 )
             port map (
-                clk_i      => clk,           -- : in  std_logic;   - CPU clock
-                rst_i      => reset_sync,    -- : in  std_logic;   - Reset
-                break_o    => zpu_i0_break,  -- : out std_logic;   - Break executed
-                dbg_o      => zpu_i0_dbg,    -- : out zpu_dbgo_t;  - Debug info
-                rs232_tx_o => rs232_tx,      -- : out std_logic;   - UART Tx
-                rs232_rx_i => rs232_rx       -- : in  std_logic    - UART Rx
+                clk_i      => clk,             -- : in  std_logic;   - CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   - Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   - Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  - Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   - UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    - UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
                 );
     end generate zpu_i0_medium;
 
@@ -392,17 +408,21 @@ begin
             );
     -- pragma translate_on
 
+    -- assign GPIOs
+    -- no bidirectional pins (e.g. headers), so
+    -- gpio_dir is unused
+    gpio_in(15 downto 8) <= gpio_dipswitch;
+    gpio_in( 3 downto 0) <= gpio_button;
+
 
     -- switch on all LEDs in case of break
     process
     begin
         wait until rising_edge(clk);
+        gpio_led_n <= not zpu_i0_gpio_out(7 downto 0);
         if zpu_i0_break = '1' then
             gpio_led_n <= (others => '0');
         end if;
-        if reset_sync = '1' then
-            gpio_led_n <= (others => '1');
-        end if;
     end process;
 
 
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
index 0d173e2..751ce22 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
@@ -144,6 +144,9 @@ begin
     tb_gpio_button(0) <= '1', '0' after 6.66 * clk_100MHz_period;
 
 
+    -- simulate keypress
+    tb_gpio_button(2) <= '0', '1' after 55 us, '0' after 56 us;
+
     -- dut
     top_i0 : entity work.top
         port map (