whitespace fixes: use fromdos on all .vhd files

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>

37 files changed, 22553 insertions, 22553 deletions

diff --git a/misc/arm7/src/arm7pkg.vhd b/misc/arm7/src/arm7pkg.vhd
index 855fbdb..4dcbb9c 100644
--- a/misc/arm7/src/arm7pkg.vhd
+++ b/misc/arm7/src/arm7pkg.vhd
@@ -1,31 +1,31 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-library work;

-use work.wishbone_pkg.all;

-

-package arm7 is

-

-	component arm7wb

-	generic(

-			simulate_io_time	: boolean := false);

-	port (	areset			: in std_logic;

-			cpu_clk			: in std_logic;

-			cpu_clk_2x		: in std_logic;

-			cpu_a_p			: in std_logic_vector(23 downto 1);

-			cpu_wr_n_p		: in std_logic_vector(1 downto 0);

-			cpu_cs_n_p		: in std_logic_vector(3 downto 1);

-			cpu_oe_n_p		: in std_logic;

-			cpu_d_p			: inout std_logic_vector(15 downto 0);

-			cpu_wait_n_p	: out std_logic;

-			

-			arm7_debug		: out std_logic;

-			arm7_debug2		: out std_logic;

-			

-			wb_o			: out wishbone_bus_in;

-			wb_i            : in wishbone_bus_out);			

-	end component;

-	

-end arm7;

-

+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library work;
+use work.wishbone_pkg.all;
+
+package arm7 is
+
+	component arm7wb
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_a_p			: in std_logic_vector(23 downto 1);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_wait_n_p	: out std_logic;
+			
+			arm7_debug		: out std_logic;
+			arm7_debug2		: out std_logic;
+			
+			wb_o			: out wishbone_bus_in;
+			wb_i            : in wishbone_bus_out);			
+	end component;
+	
+end arm7;
+
 			
\ No newline at end of file
diff --git a/misc/arm7/src/arm7wb.vhd b/misc/arm7/src/arm7wb.vhd
index 3366352..85f0ef7 100644
--- a/misc/arm7/src/arm7wb.vhd
+++ b/misc/arm7/src/arm7wb.vhd
@@ -1,236 +1,236 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-library work;

-use work.phi_config.all;

-use work.wishbone_pkg.all;

-

-entity arm7wb is

-	generic(

-			simulate_io_time	: boolean := false);

-	port (	areset			: in std_logic;

-			cpu_clk			: in std_logic;

-			cpu_clk_2x		: in std_logic;

-			cpu_a_p			: in std_logic_vector(23 downto 1);

-			cpu_wr_n_p		: in std_logic_vector(1 downto 0);

-			cpu_cs_n_p		: in std_logic_vector(3 downto 1);

-			cpu_oe_n_p		: in std_logic;

-			cpu_d_p			: inout std_logic_vector(15 downto 0);

-			cpu_wait_n_p	: out std_logic;

-

-			arm7_debug		: out std_logic;

-			arm7_debug2		: out std_logic;

-

-			wb_o			: out wishbone_bus_in;

-			wb_i            : in wishbone_bus_out);			

-end arm7wb;

-			

-architecture behave of arm7wb is

-

-type	cpu_state_type		is (cpu_idle, cpu_cs, cpu_end);

-

--- Input simulated delay

-signal	cpu_wr_n_p_del		: std_logic_vector(1 downto 0);

-signal 	cpu_a_p_del			: std_logic_vector(23 downto 1);

-signal	cpu_d_p_del			: std_logic_vector(15 downto 0);

-signal	cpu_cs_n_p_del		: std_logic_vector(3 downto 1);

-signal	cpu_oe_n_p_del		: std_logic;

-

--- Clock phase detect signals

-signal	cpu_clk_toggle		: std_logic;

-signal	cpu_clk_smp1		: std_logic;

-signal	cpu_clk_smp2		: std_logic;

-signal	cpu_clk_phase		: std_logic;

-

--- Internal version of control signal (for feedback)

-signal	arm7_din_int		: std_logic_vector(15 downto 0);

-signal	arm7_dout_int		: std_logic_vector(15 downto 0);

-signal	arm7_a_int			: std_logic_vector(23 downto 1);

-signal	arm7_we_int			: std_logic_vector(1 downto 0);

-signal  cyc_int             : std_logic;

-signal	we_int				: std_logic;

-signal  adr_reg             : std_logic_vector(25 downto 24);

-

--- Input sampled

-signal	cpu_a_smp			: std_logic_vector(23 downto 1);

-signal	cpu_d_smp			: std_logic_vector(15 downto 0);

-signal	cpu_cs_n 			: std_logic_vector(3 downto 1);

-signal	cpu_oe_n			: std_logic;

-signal	cpu_wr_n 			: std_logic_vector(1 downto 0);

-

--- Main FSM

-signal	cpu_state			: cpu_state_type;

-

-constant	Clock_2_Out	: time := 5.5 ns;

-constant	Input_Setup	: time := 2.5 ns;

-

-begin

-

-	arm7_dout_int <= wb_i.dat(15 downto 0) when (arm7_a_int(1) = '0') else wb_i.dat(31 downto 16);

-	arm7_debug <= cpu_oe_n;

-	arm7_debug2 <= cpu_wr_n(0);

-

-	-- Generate 64 MBytes address based on 3 CS_N signals from CPU

-	-- Memory map FPGA internal

-	--  0x00000000 DDR 32 MBytes (CS_N2 and CS_N3)

-	--  0x00200000 FPGA/Ethernet (CS_N1)

-	wb_o.adr(31 downto 26) <= "000000";

-	wb_o.adr(25 downto 24) <= adr_reg;

-	wb_o.adr(23 downto 1) <= arm7_a_int(23 downto 1);

-	wb_o.adr(0) <= '0';

-	

-	wb_o.dat <= (x"0000" & arm7_din_int) when (arm7_a_int(1) = '0') else (arm7_din_int & x"0000");

-	wb_o.sel <= ("00" & arm7_we_int) when (arm7_a_int(1) = '0') else (arm7_we_int & "00");	

-	

-	wb_o.cyc <= cyc_int;

-	wb_o.stb <= cyc_int;

-	wb_o.we <= cpu_oe_n;

-

-	iotimingon:

-	if simulate_io_time generate

-	begin

-		cpu_wr_n_p_del <= transport "XX" after 0 ns, cpu_wr_n_p after Input_Setup;

-		cpu_a_p_del <= transport "XXXXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup;

-		cpu_d_p_del <= transport "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup;

-		cpu_cs_n_p_del <= transport "XXX" after 0 ns, cpu_cs_n_p after Input_Setup;

-		cpu_oe_n_p_del <= transport 'X' after 0 ns, cpu_oe_n_p after Input_Setup;

-	end generate;

-	

-	iotimingoff:

-	if not simulate_io_time generate

-	begin

-		cpu_wr_n_p_del <= cpu_wr_n_p;

-		cpu_a_p_del <=  cpu_a_p;

-		cpu_d_p_del <= cpu_d_p;

-		cpu_cs_n_p_del <= cpu_cs_n_p;

-		cpu_oe_n_p_del <= cpu_oe_n_p;

-	end generate;

-	

-	process(cpu_clk, areset)	-- Toggle FF with 1x clock to find phase

-	begin

-		if areset = '1' then

-			cpu_clk_toggle <= '0';

-		elsif (cpu_clk'event and cpu_clk = '1') then

-			cpu_clk_toggle <= not(cpu_clk_toggle);

-		end if;

-	end process;

-	

-	process(cpu_clk_2x, areset)	-- Find phase relationsship between 1x and 2x clock

-	begin

-		if areset = '1' then

-			cpu_clk_smp1 <= '0';

-			cpu_clk_smp2 <= '1';

-			cpu_clk_phase <= '0';

-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then

-			cpu_clk_smp1 <= cpu_clk_toggle;

-			cpu_clk_smp2 <= cpu_clk_smp1;

-			if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then

-				cpu_clk_phase <= '0';

-			else

-				cpu_clk_phase <= not(cpu_clk_phase);

-			end if;

-		end if;

-	end process;

-	

-	process(cpu_clk_2x, areset)	-- Sample input signals on 2x clock

-	begin

-		if areset = '1' then

-			cpu_d_smp <= "0000000000000000";

-			cpu_cs_n <= "111";

-		elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then

-			cpu_d_smp <= cpu_d_p_del;

-			cpu_cs_n <= cpu_cs_n_p_del;

-		end if;

-	end process;

-

-	process(cpu_clk, areset)	-- Sample input signals on 1x clock

-	begin

-		if areset = '1' then

-			cpu_a_smp <= "00000000000000000000000";

-			cpu_oe_n <= '1';

-			cpu_wr_n <= "11";

-		elsif (cpu_clk = '1' and cpu_clk'event) then

-			cpu_a_smp <= cpu_a_p_del;

-			cpu_oe_n <= cpu_oe_n_p_del;

-			cpu_wr_n <= cpu_wr_n_p_del;

-		end if;

-	end process;

-

-	arm7_din_int <= cpu_d_smp;

-	arm7_a_int <= cpu_a_smp;

-	arm7_we_int <= not(cpu_wr_n);

-	

-	process(cpu_clk, areset)

-	begin

-		if areset = '1' then

-			cpu_state <= cpu_idle;

-			cyc_int <= '0';

-			we_int <= '0';

-			adr_reg <= "00";

-			cpu_d_p	<= (others => 'Z');

-		elsif (cpu_clk'event and cpu_clk = '1') then

-			

-			cyc_int <= '0';

-			we_int <= '0';

-			cpu_d_p	<= (others => 'Z') after Clock_2_Out;

-			

-			

-			case cpu_state is

-			

-				when cpu_idle =>

-					if cpu_oe_n = '1' then

-						we_int <= '1';

-					end if;

-					if cpu_cs_n(1) = '0' then

-						cyc_int <= '1';

-						adr_reg <= "10";

-						cpu_state <= cpu_cs;

-					end if;

-					if cpu_cs_n(2) = '0' then

-						cyc_int <= '1';

-						adr_reg <= "00";

-						cpu_state <= cpu_cs;

-					end if;

-					if cpu_cs_n(3) = '0' then

-						cyc_int <= '1';

-						adr_reg <= "01";

-						cpu_state <= cpu_cs;

-					end if;

-					

-				when cpu_cs =>

-					if cpu_oe_n = '0' then

-						cpu_d_p <= arm7_dout_int after Clock_2_Out;

-						if wb_i.ack = '1' then

-							cpu_state <= cpu_end;

-						else

-							cyc_int <= '1';

-						end if;

-					else

-						if wb_i.ack = '0' then

-							cyc_int <= '1';

-							we_int <= '1';

-						else

-							cpu_state <= cpu_end;

-						end if;

-					end if;

-						

-				when others =>

-					cpu_state <= cpu_idle;

-

-			end case;

-		end if;

-	end process;

-	

-	process(cpu_clk_2x, areset)

-	begin

-		if areset = '1' then

-			cpu_wait_n_p <= '1';

-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then

-			cpu_wait_n_p <= '1' after Clock_2_Out;

-			if (cpu_state = cpu_cs and wb_i.ack = '0') then

-			   	cpu_wait_n_p <= '0' after Clock_2_Out;

-			end if;

-		end if;

-	end process;

-	

-end behave;			

+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library work;
+use work.phi_config.all;
+use work.wishbone_pkg.all;
+
+entity arm7wb is
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_a_p			: in std_logic_vector(23 downto 1);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_wait_n_p	: out std_logic;
+
+			arm7_debug		: out std_logic;
+			arm7_debug2		: out std_logic;
+
+			wb_o			: out wishbone_bus_in;
+			wb_i            : in wishbone_bus_out);			
+end arm7wb;
+			
+architecture behave of arm7wb is
+
+type	cpu_state_type		is (cpu_idle, cpu_cs, cpu_end);
+
+-- Input simulated delay
+signal	cpu_wr_n_p_del		: std_logic_vector(1 downto 0);
+signal 	cpu_a_p_del			: std_logic_vector(23 downto 1);
+signal	cpu_d_p_del			: std_logic_vector(15 downto 0);
+signal	cpu_cs_n_p_del		: std_logic_vector(3 downto 1);
+signal	cpu_oe_n_p_del		: std_logic;
+
+-- Clock phase detect signals
+signal	cpu_clk_toggle		: std_logic;
+signal	cpu_clk_smp1		: std_logic;
+signal	cpu_clk_smp2		: std_logic;
+signal	cpu_clk_phase		: std_logic;
+
+-- Internal version of control signal (for feedback)
+signal	arm7_din_int		: std_logic_vector(15 downto 0);
+signal	arm7_dout_int		: std_logic_vector(15 downto 0);
+signal	arm7_a_int			: std_logic_vector(23 downto 1);
+signal	arm7_we_int			: std_logic_vector(1 downto 0);
+signal  cyc_int             : std_logic;
+signal	we_int				: std_logic;
+signal  adr_reg             : std_logic_vector(25 downto 24);
+
+-- Input sampled
+signal	cpu_a_smp			: std_logic_vector(23 downto 1);
+signal	cpu_d_smp			: std_logic_vector(15 downto 0);
+signal	cpu_cs_n 			: std_logic_vector(3 downto 1);
+signal	cpu_oe_n			: std_logic;
+signal	cpu_wr_n 			: std_logic_vector(1 downto 0);
+
+-- Main FSM
+signal	cpu_state			: cpu_state_type;
+
+constant	Clock_2_Out	: time := 5.5 ns;
+constant	Input_Setup	: time := 2.5 ns;
+
+begin
+
+	arm7_dout_int <= wb_i.dat(15 downto 0) when (arm7_a_int(1) = '0') else wb_i.dat(31 downto 16);
+	arm7_debug <= cpu_oe_n;
+	arm7_debug2 <= cpu_wr_n(0);
+
+	-- Generate 64 MBytes address based on 3 CS_N signals from CPU
+	-- Memory map FPGA internal
+	--  0x00000000 DDR 32 MBytes (CS_N2 and CS_N3)
+	--  0x00200000 FPGA/Ethernet (CS_N1)
+	wb_o.adr(31 downto 26) <= "000000";
+	wb_o.adr(25 downto 24) <= adr_reg;
+	wb_o.adr(23 downto 1) <= arm7_a_int(23 downto 1);
+	wb_o.adr(0) <= '0';
+	
+	wb_o.dat <= (x"0000" & arm7_din_int) when (arm7_a_int(1) = '0') else (arm7_din_int & x"0000");
+	wb_o.sel <= ("00" & arm7_we_int) when (arm7_a_int(1) = '0') else (arm7_we_int & "00");	
+	
+	wb_o.cyc <= cyc_int;
+	wb_o.stb <= cyc_int;
+	wb_o.we <= cpu_oe_n;
+
+	iotimingon:
+	if simulate_io_time generate
+	begin
+		cpu_wr_n_p_del <= transport "XX" after 0 ns, cpu_wr_n_p after Input_Setup;
+		cpu_a_p_del <= transport "XXXXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup;
+		cpu_d_p_del <= transport "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup;
+		cpu_cs_n_p_del <= transport "XXX" after 0 ns, cpu_cs_n_p after Input_Setup;
+		cpu_oe_n_p_del <= transport 'X' after 0 ns, cpu_oe_n_p after Input_Setup;
+	end generate;
+	
+	iotimingoff:
+	if not simulate_io_time generate
+	begin
+		cpu_wr_n_p_del <= cpu_wr_n_p;
+		cpu_a_p_del <=  cpu_a_p;
+		cpu_d_p_del <= cpu_d_p;
+		cpu_cs_n_p_del <= cpu_cs_n_p;
+		cpu_oe_n_p_del <= cpu_oe_n_p;
+	end generate;
+	
+	process(cpu_clk, areset)	-- Toggle FF with 1x clock to find phase
+	begin
+		if areset = '1' then
+			cpu_clk_toggle <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			cpu_clk_toggle <= not(cpu_clk_toggle);
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	-- Find phase relationsship between 1x and 2x clock
+	begin
+		if areset = '1' then
+			cpu_clk_smp1 <= '0';
+			cpu_clk_smp2 <= '1';
+			cpu_clk_phase <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			cpu_clk_smp1 <= cpu_clk_toggle;
+			cpu_clk_smp2 <= cpu_clk_smp1;
+			if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then
+				cpu_clk_phase <= '0';
+			else
+				cpu_clk_phase <= not(cpu_clk_phase);
+			end if;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	-- Sample input signals on 2x clock
+	begin
+		if areset = '1' then
+			cpu_d_smp <= "0000000000000000";
+			cpu_cs_n <= "111";
+		elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then
+			cpu_d_smp <= cpu_d_p_del;
+			cpu_cs_n <= cpu_cs_n_p_del;
+		end if;
+	end process;
+
+	process(cpu_clk, areset)	-- Sample input signals on 1x clock
+	begin
+		if areset = '1' then
+			cpu_a_smp <= "00000000000000000000000";
+			cpu_oe_n <= '1';
+			cpu_wr_n <= "11";
+		elsif (cpu_clk = '1' and cpu_clk'event) then
+			cpu_a_smp <= cpu_a_p_del;
+			cpu_oe_n <= cpu_oe_n_p_del;
+			cpu_wr_n <= cpu_wr_n_p_del;
+		end if;
+	end process;
+
+	arm7_din_int <= cpu_d_smp;
+	arm7_a_int <= cpu_a_smp;
+	arm7_we_int <= not(cpu_wr_n);
+	
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			cpu_state <= cpu_idle;
+			cyc_int <= '0';
+			we_int <= '0';
+			adr_reg <= "00";
+			cpu_d_p	<= (others => 'Z');
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			
+			cyc_int <= '0';
+			we_int <= '0';
+			cpu_d_p	<= (others => 'Z') after Clock_2_Out;
+			
+			
+			case cpu_state is
+			
+				when cpu_idle =>
+					if cpu_oe_n = '1' then
+						we_int <= '1';
+					end if;
+					if cpu_cs_n(1) = '0' then
+						cyc_int <= '1';
+						adr_reg <= "10";
+						cpu_state <= cpu_cs;
+					end if;
+					if cpu_cs_n(2) = '0' then
+						cyc_int <= '1';
+						adr_reg <= "00";
+						cpu_state <= cpu_cs;
+					end if;
+					if cpu_cs_n(3) = '0' then
+						cyc_int <= '1';
+						adr_reg <= "01";
+						cpu_state <= cpu_cs;
+					end if;
+					
+				when cpu_cs =>
+					if cpu_oe_n = '0' then
+						cpu_d_p <= arm7_dout_int after Clock_2_Out;
+						if wb_i.ack = '1' then
+							cpu_state <= cpu_end;
+						else
+							cyc_int <= '1';
+						end if;
+					else
+						if wb_i.ack = '0' then
+							cyc_int <= '1';
+							we_int <= '1';
+						else
+							cpu_state <= cpu_end;
+						end if;
+					end if;
+						
+				when others =>
+					cpu_state <= cpu_idle;
+
+			end case;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)
+	begin
+		if areset = '1' then
+			cpu_wait_n_p <= '1';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			cpu_wait_n_p <= '1' after Clock_2_Out;
+			if (cpu_state = cpu_cs and wb_i.ack = '0') then
+			   	cpu_wait_n_p <= '0' after Clock_2_Out;
+			end if;
+		end if;
+	end process;
+	
+end behave;			
diff --git a/misc/ddrsdram/simsrc/ddr_tb.vhd b/misc/ddrsdram/simsrc/ddr_tb.vhd
index 249dffb..92d1e4b 100644
--- a/misc/ddrsdram/simsrc/ddr_tb.vhd
+++ b/misc/ddrsdram/simsrc/ddr_tb.vhd
@@ -1,301 +1,301 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-library work;

-use work.ddr.all;

-

-entity ddr_tb is

-	port (	areset			: in std_logic;

-			break_out		: out std_logic);

-end ddr_tb;

-

-architecture behave of ddr_tb is

-

-signal	cpu_clk			: std_logic;

-signal	cpu_clk_2x		: std_logic;

-signal	cpu_clk_4x		: std_logic;

-signal	ddr_in_clk		: std_logic;

-signal	ddr_in_clk_2x	: std_logic;

-

-signal	ddr_command		: std_logic_vector(15 downto 0);

-signal	ddr_command_we	: std_logic;

-			

-signal	ddr_data_read	: std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM

-signal	ddr_data_write	: std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM

-signal	ddr_req_adr		: std_logic_vector(23 downto 1);		-- Request address

-signal	ddr_req			: std_logic;							-- Request DDR SDRAM access

-signal	ddr_req_ack		: std_logic;							-- Request acknowledge

-signal	ddr_busy		: std_logic;							-- Request acknowledge

-signal	ddr_rd_wr_n		: std_logic;							-- Access type 1=READ, 0=WRITE

-signal	ddr_req_len		: std_logic;							-- Number of 16-bits words to transfer

-signal	ddr_read_en		: std_logic;						-- Enable signal for read data

-signal	ddr_write_en	: std_logic;						-- Enable (read) signal for data write

-signal	refresh_en		: std_logic;

-

-signal	sdr_clk_p       : std_logic;    -- ddr_sdram_clock

-signal	sdr_clk_n_p     : std_logic;    -- /ddr_sdram_clock

-signal	cke_q_p         : std_logic;    -- clock enable

-signal	cs_qn_p         : std_logic;    -- /chip select

-signal	ras_qn_p        : std_logic;    -- /ras

-signal	cas_qn_p        : std_logic;    -- /cas

-signal	we_qn_p         : std_logic;    -- /write enable

-signal	dm_q_p          : std_logic_vector(1 downto 0);     -- data mask bits, set to "00"

-signal	dqs_q_p         : std_logic_vector(1 downto 0);    -- data strobe, only for write

-signal	ba_q_p          : std_logic_vector(1 downto 0);   -- bank select

-signal	sdr_a_p		    : std_logic_vector(12 downto 0);   -- address bus 

-signal	sdr_d_p         : std_logic_vector(15 downto 0); 			-- bidir data bus

-

-constant min_time	: time := 1.875 ns;

-

-begin

-

-	clock1:

-	process

-	begin

-		loop

-			cpu_clk_4x <= '1';

-			wait for min_time;

-			cpu_clk_4x <= '0';

-			wait for min_time;

-		end loop;

-	end process;

-

-	clock2:

-	process

-	begin

-		loop

-			cpu_clk_2x <= '1' after 100 ps;

-			wait until rising_edge(cpu_clk_4x);

-			cpu_clk_2x <= '0' after 100 ps;

-			wait until rising_edge(cpu_clk_4x);

-		end loop;

-	end process;

-

-	clock3:

-	process

-	begin

-		loop

-			cpu_clk <= '1' after 100 ps;

-			wait until rising_edge(cpu_clk_2x);

-			cpu_clk <= '0' after 100 ps;

-			wait until rising_edge(cpu_clk_2x);

-		end loop;

-	end process;

-	

-	ddr_in_clk_2x <= cpu_clk_4x after 1 ns;

-

-	clock4:

-	process

-	begin

-		loop

-			ddr_in_clk <= '0' after 100 ps;

-			wait until rising_edge(ddr_in_clk_2x);

-			ddr_in_clk <= '1' after 100 ps;

-			wait until rising_edge(ddr_in_clk_2x);

-		end loop;

-	end process;

-	

-	inputdata:

-	process

-	begin

-		-- Wait until global reset released

-		loop

-			ddr_command <= x"0000";

-			ddr_command_we <= '0';

-			ddr_data_write <= x"000000000";

-			ddr_req <= '0';

-			ddr_req_adr <= "00000000000000000000000";

-			ddr_rd_wr_n <= '0';

-			ddr_req_len <= '0';

-			break_out <= '0';

-			refresh_en <= '0';

-			

-			wait until falling_edge(areset);

-			

-			-- DDR initialization sequence

-				-- Wait more than 200 us

-				wait for 201000 ns;	

-				

-				-- Send precharge command

-				wait until rising_edge(cpu_clk);	

-				ddr_command <= x"8000";

-				ddr_command_we <= '1';

-				wait until rising_edge(cpu_clk);

-				ddr_command <= x"0000";

-				ddr_command_we <= '0';

-				

-				-- Wait for 1 us

-				wait for 1000 ns;

-				

-				-- Load extended mode register

-				--  Enable DLL

-				--  Normal drive strength

-				wait until rising_edge(cpu_clk);	

-				ddr_command <= x"2000";

-				ddr_command_we <= '1';

-				wait until rising_edge(cpu_clk);

-				ddr_command <= x"0000";

-				ddr_command_we <= '0';

-							

-				-- Wait for 1 us

-				wait for 1000 ns;

-				

-				-- Load mode register

-				--  Burst length: 2

-				--  Burst type: Sequential

-				--  Cas latency: 2

-				--  Reset DLL

-				wait until rising_edge(cpu_clk);	

-				ddr_command <= x"0121";

-				ddr_command_we <= '1';

-				wait until rising_edge(cpu_clk);

-				ddr_command <= x"0000";

-				ddr_command_we <= '0';

-							

-				-- Wait for 1 us

-				wait for 1000 ns;

-				

-				-- Send precharge command

-				wait until rising_edge(cpu_clk);	

-				ddr_command <= x"8000";

-				ddr_command_we <= '1';

-				wait until rising_edge(cpu_clk);

-				ddr_command <= x"0000";

-				ddr_command_we <= '0';

-				

-				-- Enable refresh

-				refresh_en <= '1';

-			

-				-- Wait 30 us (minimum 2 autorefresh cycles)

-				wait for 30000 ns;

-						

-				-- Load mode register

-				--  Burst length: 2

-				--  Burst type: Sequential

-				--  Cas latency: 2

-				--  Deactivate Reset DLL

-				wait until rising_edge(cpu_clk);	

-				ddr_command <= x"0021";

-				ddr_command_we <= '1';

-				wait until rising_edge(cpu_clk);

-				ddr_command <= x"0000";

-				ddr_command_we <= '0';

-	

-				-- Wait for 2 us (DLL stable)

-				wait for 2000 ns;

-				

-			-- Write data to DDR

-			wait until rising_edge(cpu_clk_2x);

-			ddr_data_write <= x"312345678";

-			ddr_req <= '1';

-			ddr_req_adr <= "00000000000000000000000";

-			ddr_rd_wr_n <= '0';

-			ddr_req_len <= '0';

-			wait until rising_edge(ddr_write_en);

-			wait until rising_edge(cpu_clk_2x);

-			ddr_req <= '0';

-			ddr_req_adr <= "00000000000000000000000";

-			ddr_rd_wr_n <= '0';

-			ddr_req_len <= '0';

-			ddr_data_write <= x"000000000";

-			wait for 100 ns;

-			

-			-- Read data from DDR

-			wait until rising_edge(cpu_clk_2x);

-			ddr_req <= '1';

-			ddr_req_adr <= "00000000000000000000000";

-			ddr_rd_wr_n <= '1';

-			ddr_req_len <= '0';

-			wait until rising_edge(ddr_req_ack);

-			wait until rising_edge(cpu_clk_2x);

-			ddr_req <= '0';

-			ddr_req_adr <= "00000000000000000000000";

-			ddr_rd_wr_n <= '0';

-			ddr_req_len <= '0';

-			ddr_data_write <= x"000000000";

-

-

-

-			wait for 100 ns;

-			break_out <= '1';

-			wait for 100 ns;

-						

-		end loop;

-		

-	end process;

-	

-	ddr_ctrl:

-	ddr_top port map(

-		areset => areset,

-		cpu_clk => cpu_clk,

-		cpu_clk_2x => cpu_clk_2x,

-		cpu_clk_4x => cpu_clk_4x,

-		ddr_in_clk => ddr_in_clk,

-		ddr_in_clk_2x => ddr_in_clk_2x,

-		

-		-- Command interface

-		ddr_command => ddr_command,

-		ddr_command_we => ddr_command_we,

-		refresh_en => refresh_en,			

-		

-		-- Data interface signals

-		ddr_data_read => ddr_data_read,

-		ddr_data_write => ddr_data_write,

-		ddr_req_adr => ddr_req_adr,

-		ddr_req => ddr_req,

-		ddr_req_ack => ddr_req_ack,

-		ddr_busy => ddr_busy,

-		ddr_rd_wr_n => ddr_rd_wr_n,

-		ddr_req_len => ddr_req_len,

-		ddr_read_en => ddr_read_en,

-		ddr_write_en => ddr_write_en,

-		    -- DDR SDRAM Signals

-	    sdr_clk_p => sdr_clk_p,

-	    sdr_clk_n_p => sdr_clk_n_p,

-	    cke_q_p => cke_q_p,

-	    cs_qn_p => cs_qn_p,

-	    ras_qn_p => ras_qn_p,

-	    cas_qn_p => cas_qn_p,

-	    we_qn_p => we_qn_p,

-	    dm_q_p => dm_q_p,

-	    dqs_q_p => dqs_q_p,

-	    ba_q_p => ba_q_p,

-	    sdr_a_p => sdr_a_p,

-	    sdr_d_p => sdr_d_p);

-	   

-	myram:

-	MT46V16M16 generic map(

-        tCK => 7.500 ns,

-        tCH => 3.375 ns,       -- 0.45*tCK

-        tCL => 3.375 ns,       -- 0.45*tCK

-        tDH => 0.500 ns,

-        tDS => 0.500 ns,

-        tIH => 0.900 ns,

-        tIS => 0.900 ns,

-        tMRD => 15.000 ns,

-        tRAS => 40.000 ns,

-        tRAP => 20.000 ns,

-        tRC => 65.000 ns,

-        tRFC => 75.000 ns,

-        tRCD => 20.000 ns,

-        tRP => 20.000 ns,

-        tRRD => 15.000 ns,

-        tWR => 15.000 ns,

-        addr_bits => 13,

-        data_bits => 16,

-        cols_bits => 9)

-    port map(

-        Dq => sdr_d_p,

-        Dqs => dqs_q_p,

-        Addr => sdr_a_p,

-        Ba => ba_q_p,

-        Clk => sdr_clk_p,

-        Clk_n => sdr_clk_n_p,

-        Cke => cke_q_p,

-        Cs_n => cs_qn_p,

-        Ras_n => ras_qn_p,

-        Cas_n => cas_qn_p,

-        We_n => we_qn_p,

-        Dm => dm_q_p);

-

-end behave;

+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library work;
+use work.ddr.all;
+
+entity ddr_tb is
+	port (	areset			: in std_logic;
+			break_out		: out std_logic);
+end ddr_tb;
+
+architecture behave of ddr_tb is
+
+signal	cpu_clk			: std_logic;
+signal	cpu_clk_2x		: std_logic;
+signal	cpu_clk_4x		: std_logic;
+signal	ddr_in_clk		: std_logic;
+signal	ddr_in_clk_2x	: std_logic;
+
+signal	ddr_command		: std_logic_vector(15 downto 0);
+signal	ddr_command_we	: std_logic;
+			
+signal	ddr_data_read	: std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
+signal	ddr_data_write	: std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
+signal	ddr_req_adr		: std_logic_vector(23 downto 1);		-- Request address
+signal	ddr_req			: std_logic;							-- Request DDR SDRAM access
+signal	ddr_req_ack		: std_logic;							-- Request acknowledge
+signal	ddr_busy		: std_logic;							-- Request acknowledge
+signal	ddr_rd_wr_n		: std_logic;							-- Access type 1=READ, 0=WRITE
+signal	ddr_req_len		: std_logic;							-- Number of 16-bits words to transfer
+signal	ddr_read_en		: std_logic;						-- Enable signal for read data
+signal	ddr_write_en	: std_logic;						-- Enable (read) signal for data write
+signal	refresh_en		: std_logic;
+
+signal	sdr_clk_p       : std_logic;    -- ddr_sdram_clock
+signal	sdr_clk_n_p     : std_logic;    -- /ddr_sdram_clock
+signal	cke_q_p         : std_logic;    -- clock enable
+signal	cs_qn_p         : std_logic;    -- /chip select
+signal	ras_qn_p        : std_logic;    -- /ras
+signal	cas_qn_p        : std_logic;    -- /cas
+signal	we_qn_p         : std_logic;    -- /write enable
+signal	dm_q_p          : std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+signal	dqs_q_p         : std_logic_vector(1 downto 0);    -- data strobe, only for write
+signal	ba_q_p          : std_logic_vector(1 downto 0);   -- bank select
+signal	sdr_a_p		    : std_logic_vector(12 downto 0);   -- address bus 
+signal	sdr_d_p         : std_logic_vector(15 downto 0); 			-- bidir data bus
+
+constant min_time	: time := 1.875 ns;
+
+begin
+
+	clock1:
+	process
+	begin
+		loop
+			cpu_clk_4x <= '1';
+			wait for min_time;
+			cpu_clk_4x <= '0';
+			wait for min_time;
+		end loop;
+	end process;
+
+	clock2:
+	process
+	begin
+		loop
+			cpu_clk_2x <= '1' after 100 ps;
+			wait until rising_edge(cpu_clk_4x);
+			cpu_clk_2x <= '0' after 100 ps;
+			wait until rising_edge(cpu_clk_4x);
+		end loop;
+	end process;
+
+	clock3:
+	process
+	begin
+		loop
+			cpu_clk <= '1' after 100 ps;
+			wait until rising_edge(cpu_clk_2x);
+			cpu_clk <= '0' after 100 ps;
+			wait until rising_edge(cpu_clk_2x);
+		end loop;
+	end process;
+	
+	ddr_in_clk_2x <= cpu_clk_4x after 1 ns;
+
+	clock4:
+	process
+	begin
+		loop
+			ddr_in_clk <= '0' after 100 ps;
+			wait until rising_edge(ddr_in_clk_2x);
+			ddr_in_clk <= '1' after 100 ps;
+			wait until rising_edge(ddr_in_clk_2x);
+		end loop;
+	end process;
+	
+	inputdata:
+	process
+	begin
+		-- Wait until global reset released
+		loop
+			ddr_command <= x"0000";
+			ddr_command_we <= '0';
+			ddr_data_write <= x"000000000";
+			ddr_req <= '0';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			break_out <= '0';
+			refresh_en <= '0';
+			
+			wait until falling_edge(areset);
+			
+			-- DDR initialization sequence
+				-- Wait more than 200 us
+				wait for 201000 ns;	
+				
+				-- Send precharge command
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"8000";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+				
+				-- Wait for 1 us
+				wait for 1000 ns;
+				
+				-- Load extended mode register
+				--  Enable DLL
+				--  Normal drive strength
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"2000";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+							
+				-- Wait for 1 us
+				wait for 1000 ns;
+				
+				-- Load mode register
+				--  Burst length: 2
+				--  Burst type: Sequential
+				--  Cas latency: 2
+				--  Reset DLL
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"0121";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+							
+				-- Wait for 1 us
+				wait for 1000 ns;
+				
+				-- Send precharge command
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"8000";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+				
+				-- Enable refresh
+				refresh_en <= '1';
+			
+				-- Wait 30 us (minimum 2 autorefresh cycles)
+				wait for 30000 ns;
+						
+				-- Load mode register
+				--  Burst length: 2
+				--  Burst type: Sequential
+				--  Cas latency: 2
+				--  Deactivate Reset DLL
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"0021";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+	
+				-- Wait for 2 us (DLL stable)
+				wait for 2000 ns;
+				
+			-- Write data to DDR
+			wait until rising_edge(cpu_clk_2x);
+			ddr_data_write <= x"312345678";
+			ddr_req <= '1';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			wait until rising_edge(ddr_write_en);
+			wait until rising_edge(cpu_clk_2x);
+			ddr_req <= '0';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			ddr_data_write <= x"000000000";
+			wait for 100 ns;
+			
+			-- Read data from DDR
+			wait until rising_edge(cpu_clk_2x);
+			ddr_req <= '1';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '1';
+			ddr_req_len <= '0';
+			wait until rising_edge(ddr_req_ack);
+			wait until rising_edge(cpu_clk_2x);
+			ddr_req <= '0';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			ddr_data_write <= x"000000000";
+
+
+
+			wait for 100 ns;
+			break_out <= '1';
+			wait for 100 ns;
+						
+		end loop;
+		
+	end process;
+	
+	ddr_ctrl:
+	ddr_top port map(
+		areset => areset,
+		cpu_clk => cpu_clk,
+		cpu_clk_2x => cpu_clk_2x,
+		cpu_clk_4x => cpu_clk_4x,
+		ddr_in_clk => ddr_in_clk,
+		ddr_in_clk_2x => ddr_in_clk_2x,
+		
+		-- Command interface
+		ddr_command => ddr_command,
+		ddr_command_we => ddr_command_we,
+		refresh_en => refresh_en,			
+		
+		-- Data interface signals
+		ddr_data_read => ddr_data_read,
+		ddr_data_write => ddr_data_write,
+		ddr_req_adr => ddr_req_adr,
+		ddr_req => ddr_req,
+		ddr_req_ack => ddr_req_ack,
+		ddr_busy => ddr_busy,
+		ddr_rd_wr_n => ddr_rd_wr_n,
+		ddr_req_len => ddr_req_len,
+		ddr_read_en => ddr_read_en,
+		ddr_write_en => ddr_write_en,
+		    -- DDR SDRAM Signals
+	    sdr_clk_p => sdr_clk_p,
+	    sdr_clk_n_p => sdr_clk_n_p,
+	    cke_q_p => cke_q_p,
+	    cs_qn_p => cs_qn_p,
+	    ras_qn_p => ras_qn_p,
+	    cas_qn_p => cas_qn_p,
+	    we_qn_p => we_qn_p,
+	    dm_q_p => dm_q_p,
+	    dqs_q_p => dqs_q_p,
+	    ba_q_p => ba_q_p,
+	    sdr_a_p => sdr_a_p,
+	    sdr_d_p => sdr_d_p);
+	   
+	myram:
+	MT46V16M16 generic map(
+        tCK => 7.500 ns,
+        tCH => 3.375 ns,       -- 0.45*tCK
+        tCL => 3.375 ns,       -- 0.45*tCK
+        tDH => 0.500 ns,
+        tDS => 0.500 ns,
+        tIH => 0.900 ns,
+        tIS => 0.900 ns,
+        tMRD => 15.000 ns,
+        tRAS => 40.000 ns,
+        tRAP => 20.000 ns,
+        tRC => 65.000 ns,
+        tRFC => 75.000 ns,
+        tRCD => 20.000 ns,
+        tRP => 20.000 ns,
+        tRRD => 15.000 ns,
+        tWR => 15.000 ns,
+        addr_bits => 13,
+        data_bits => 16,
+        cols_bits => 9)
+    port map(
+        Dq => sdr_d_p,
+        Dqs => dqs_q_p,
+        Addr => sdr_a_p,
+        Ba => ba_q_p,
+        Clk => sdr_clk_p,
+        Clk_n => sdr_clk_n_p,
+        Cke => cke_q_p,
+        Cs_n => cs_qn_p,
+        Ras_n => ras_qn_p,
+        Cas_n => cas_qn_p,
+        We_n => we_qn_p,
+        Dm => dm_q_p);
+
+end behave;
diff --git a/misc/ddrsdram/src/ddr_pkg.vhd b/misc/ddrsdram/src/ddr_pkg.vhd
index 0e41a88..af4a705 100644
--- a/misc/ddrsdram/src/ddr_pkg.vhd
+++ b/misc/ddrsdram/src/ddr_pkg.vhd
@@ -1,107 +1,107 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-package ddr is

-

-	function mirror_bus32 ( org_sig  : std_logic_vector) return std_logic_vector;

-	function mirror_bus4 ( org_sig  : std_logic_vector) return std_logic_vector;

-

-	component ddr_top

-	generic(

-			simulate_io_time	: boolean := false);

-	port (	-- Asyncronous reset and clocks

-			areset			: in std_logic;

-			cpu_clk			: in std_logic;

-			cpu_clk_2x		: in std_logic;

-			cpu_clk_4x		: in std_logic;

-			ddr_in_clk		: in std_logic;

-			ddr_in_clk_2x	: in std_logic;

-			

-			-- Command interface

-			ddr_command		: in std_logic_vector(15 downto 0);

-			ddr_command_we	: in std_logic;

-			refresh_en		: in std_logic;

-			

-			

-			-- Data interface signals

-			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM

-			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM

-			ddr_req_adr		: in std_logic_vector(25 downto 1);		-- Request address

-			ddr_req			: in std_logic;							-- Request DDR SDRAM access

-			ddr_busy		: out std_logic;							-- Request acknowledge

-			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE

-			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)

-			ddr_read_en		: out std_logic;						-- Enable signal for read data

-			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write

-

-		    -- DDR SDRAM Signals

-		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock

-		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock

-		    cke_q_p         : out std_logic;    -- clock enable

-		    cs_qn_p         : out std_logic;    -- /chip select

-		    ras_qn_p        : inout std_logic;    -- /ras

-		    cas_qn_p        : inout std_logic;    -- /cas

-		    we_qn_p         : inout std_logic;    -- /write enable

-		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"

-		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write

-		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select

-		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 

-		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus

-	end component;

-	

-	component MT46V16M16

-    GENERIC (                                   -- Timing for -75Z CL2

-        tCK       : TIME    :=  7.500 ns;

-        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK

-        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK

-        tDH       : TIME    :=  0.500 ns;

-        tDS       : TIME    :=  0.500 ns;

-        tIH       : TIME    :=  0.900 ns;

-        tIS       : TIME    :=  0.900 ns;

-        tMRD      : TIME    := 15.000 ns;

-        tRAS      : TIME    := 40.000 ns;

-        tRAP      : TIME    := 20.000 ns;

-        tRC       : TIME    := 65.000 ns;

-        tRFC      : TIME    := 75.000 ns;

-        tRCD      : TIME    := 20.000 ns;

-        tRP       : TIME    := 20.000 ns;

-        tRRD      : TIME    := 15.000 ns;

-        tWR       : TIME    := 15.000 ns;

-        addr_bits : INTEGER := 13;

-        data_bits : INTEGER := 16;

-        cols_bits : INTEGER :=  9

-    );

-    PORT (

-        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');

-        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";

-        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);

-        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);

-        Clk   : IN    STD_LOGIC;

-        Clk_n : IN    STD_LOGIC;

-        Cke   : IN    STD_LOGIC;

-        Cs_n  : IN    STD_LOGIC;

-        Ras_n : IN    STD_LOGIC;

-        Cas_n : IN    STD_LOGIC;

-        We_n  : IN    STD_LOGIC;

-        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)

-    );

-	end component;

-	

-end;

-

-package body ddr is

-

-	function mirror_bus32 ( org_sig  : std_logic_vector) return std_logic_vector is

-	begin

-		return (org_sig(7 downto 0) & org_sig(15 downto 8) & org_sig(23 downto 16) & org_sig(31 downto 24));

-	end function mirror_bus32;

-

-	function mirror_bus4 ( org_sig  : std_logic_vector) return std_logic_vector is

-	begin

-		return (org_sig(0) & org_sig(1) & org_sig(2) & org_sig(3));

-	end function mirror_bus4;

-

-end package body;

-

+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package ddr is
+
+	function mirror_bus32 ( org_sig  : std_logic_vector) return std_logic_vector;
+	function mirror_bus4 ( org_sig  : std_logic_vector) return std_logic_vector;
+
+	component ddr_top
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	-- Asyncronous reset and clocks
+			areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_clk_4x		: in std_logic;
+			ddr_in_clk		: in std_logic;
+			ddr_in_clk_2x	: in std_logic;
+			
+			-- Command interface
+			ddr_command		: in std_logic_vector(15 downto 0);
+			ddr_command_we	: in std_logic;
+			refresh_en		: in std_logic;
+			
+			
+			-- Data interface signals
+			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
+			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
+			ddr_req_adr		: in std_logic_vector(25 downto 1);		-- Request address
+			ddr_req			: in std_logic;							-- Request DDR SDRAM access
+			ddr_busy		: out std_logic;							-- Request acknowledge
+			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE
+			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)
+			ddr_read_en		: out std_logic;						-- Enable signal for read data
+			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write
+
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
+	end component;
+	
+	component MT46V16M16
+    GENERIC (                                   -- Timing for -75Z CL2
+        tCK       : TIME    :=  7.500 ns;
+        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tDH       : TIME    :=  0.500 ns;
+        tDS       : TIME    :=  0.500 ns;
+        tIH       : TIME    :=  0.900 ns;
+        tIS       : TIME    :=  0.900 ns;
+        tMRD      : TIME    := 15.000 ns;
+        tRAS      : TIME    := 40.000 ns;
+        tRAP      : TIME    := 20.000 ns;
+        tRC       : TIME    := 65.000 ns;
+        tRFC      : TIME    := 75.000 ns;
+        tRCD      : TIME    := 20.000 ns;
+        tRP       : TIME    := 20.000 ns;
+        tRRD      : TIME    := 15.000 ns;
+        tWR       : TIME    := 15.000 ns;
+        addr_bits : INTEGER := 13;
+        data_bits : INTEGER := 16;
+        cols_bits : INTEGER :=  9
+    );
+    PORT (
+        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
+        Clk   : IN    STD_LOGIC;
+        Clk_n : IN    STD_LOGIC;
+        Cke   : IN    STD_LOGIC;
+        Cs_n  : IN    STD_LOGIC;
+        Ras_n : IN    STD_LOGIC;
+        Cas_n : IN    STD_LOGIC;
+        We_n  : IN    STD_LOGIC;
+        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
+    );
+	end component;
+	
+end;
+
+package body ddr is
+
+	function mirror_bus32 ( org_sig  : std_logic_vector) return std_logic_vector is
+	begin
+		return (org_sig(7 downto 0) & org_sig(15 downto 8) & org_sig(23 downto 16) & org_sig(31 downto 24));
+	end function mirror_bus32;
+
+	function mirror_bus4 ( org_sig  : std_logic_vector) return std_logic_vector is
+	begin
+		return (org_sig(0) & org_sig(1) & org_sig(2) & org_sig(3));
+	end function mirror_bus4;
+
+end package body;
+
 	
\ No newline at end of file
diff --git a/misc/ddrsdram/src/ddr_top.vhd b/misc/ddrsdram/src/ddr_top.vhd
index 033e9f8..2aceae9 100644
--- a/misc/ddrsdram/src/ddr_top.vhd
+++ b/misc/ddrsdram/src/ddr_top.vhd
@@ -1,743 +1,743 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-library UNISIM;

-use UNISIM.vcomponents.all;

-

-entity ddr_top is

-	generic(

-			simulate_io_time	: boolean := false);

-	port (	-- Asyncronous reset and clocks

-			areset			: in std_logic;

-			cpu_clk			: in std_logic;

-			cpu_clk_2x		: in std_logic;

-			cpu_clk_4x		: in std_logic;

-			ddr_in_clk		: in std_logic;

-			ddr_in_clk_2x	: in std_logic;

-			

-			-- Command interface

-			ddr_command		: in std_logic_vector(15 downto 0);

-			ddr_command_we	: in std_logic;

-			refresh_en		: in std_logic;

-			

-			-- Data interface signals

-			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM

-			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM

-			ddr_req_adr		: in std_logic_vector(25 downto 1);		-- Request address

-			ddr_req			: in std_logic;							-- Request DDR SDRAM access

-			ddr_busy		: out std_logic;							-- Request acknowledge

-			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE

-			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)

-			ddr_read_en		: out std_logic;						-- Enable signal for read data

-			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write

-

-		    -- DDR SDRAM Signals

-		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock

-		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock

-		    cke_q_p         : out std_logic;    -- clock enable

-		    cs_qn_p         : out std_logic;    -- /chip select

-		    ras_qn_p        : inout std_logic;    -- /ras

-		    cas_qn_p        : inout std_logic;    -- /cas

-		    we_qn_p         : inout std_logic;    -- /write enable

-		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"

-		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write

-		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select

-		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 

-		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus

-end ddr_top;

-

-architecture behave of ddr_top is

-

-attribute keep : string;

-

-type	clk4_type			is array(0 to 15) of std_logic_vector(1 downto 0);

-

-signal	cpu_clk_tog			: std_logic;

-signal	ddr_cmd				: std_logic_vector(15 downto 0);

-signal	ddr_cmd_we_smp		: std_logic;

-signal	new_command			: std_logic;

-

-signal	cpu_clk_2x_smp1		: std_logic;		

-signal	cpu_clk_2x_smp2		: std_logic;		

-signal	cpu_clk_4x_smp1		: std_logic;		

-signal	cpu_clk_4x_smp2		: std_logic;

-

-signal	clk2_phase			: std_logic;	

-signal	clk4_phase			: std_logic_vector(3 downto 0);

-signal	clk4_phase_short	: clk4_type;

-attribute keep of clk4_phase_short:signal is "true";

-

-signal	ddr_clk_tog			: std_logic;

-signal	ddr_clk_smp1		: std_logic;

-signal	ddr_clk_smp2		: std_logic;

-signal	ddr_clk_phase		: std_logic;

-

-signal	smp_req_adr			: std_logic_vector(25 downto 1);

-signal	smp_req_type		: std_logic;

-signal	smp_req_len			: std_logic;

-signal	ddr_write_en_int	: std_logic;

-signal	ddr_read_en_int		: std_logic;

-

-signal	dqs_q				: std_logic_vector(1 downto 0);

-signal	dqs_oe_n			: std_logic_vector(1 downto 0);

-attribute keep of dqs_oe_n:signal is "true";

-signal	cas_qn				: std_logic;

-signal	ras_qn				: std_logic;

-signal	we_qn				: std_logic;

-signal	ba_q				: std_logic_vector(1 downto 0);

-signal	sdr_clk				: std_logic;

-signal	sdr_clk_n			: std_logic;

-signal	sdr_a				: std_logic_vector(12 downto 0);

-signal	sdr_d				: std_logic_vector(15 downto 0);

-signal	sdr_smp				: std_logic_vector(35 downto 0);

-signal	sdr_oe_n			: std_logic_vector(15 downto 0);

-attribute keep of sdr_oe_n:signal is "true";

-signal	sdr_oe_ctrl			: std_logic_vector(15 downto 0);

-attribute keep of sdr_oe_ctrl:signal is "true";

-signal	sdr_wr_msw			: std_logic_vector(17 downto 0);

-attribute keep of sdr_wr_msw:signal is "true";

-signal	dm_q				: std_logic_vector(1 downto 0);

-

-signal  nowin_idle_dqs      : std_logic_vector(1 downto 0);

-signal  nowin_wr_nop1_d     : std_logic_vector(15 downto 0);

-signal  nowin_wr_nop1_dqs   : std_logic_vector(1 downto 0);

-signal  nowin_wr_nop1_dm    : std_logic_vector(1 downto 0);

-signal  nowin_wr_nop2_dqs   : std_logic_vector(1 downto 0);

-signal  nowin_wr_nop3_d     : std_logic_vector(15 downto 0);

-signal  nowin_wr_nop3_dqs   : std_logic_vector(1 downto 0);

-attribute keep of nowin_idle_dqs:signal is "true";

-attribute keep of nowin_wr_nop1_d:signal is "true";

-attribute keep of nowin_wr_nop1_dqs:signal is "true";

-attribute keep of nowin_wr_nop1_dm:signal is "true";

-attribute keep of nowin_wr_nop2_dqs:signal is "true";

-attribute keep of nowin_wr_nop3_d:signal is "true";

-attribute keep of nowin_wr_nop3_dqs:signal is "true";

-

-signal	cas_n_smp			: std_logic;

-signal	ras_n_smp			: std_logic;

-signal	we_n_smp			: std_logic;

-signal	read_start_sig		: std_logic;

-signal	sdr_d_in			: std_logic_vector(15 downto 0);

-signal	read_time_cnt		: std_logic_vector(1 downto 0);

-signal	read_input_en		: std_logic;

-signal	read_input_en_del	: std_logic;

-signal	ddr_data_read_int	: std_logic_vector(31 downto 0);

-

-signal	refresh_pend		: std_logic;

-signal	refresh_end			: std_logic;

-signal	refresh_cnt			: std_logic_vector(9 downto 0);

-signal	refresh_wait_cnt	: std_logic_vector(3 downto 0);

-signal	refresh_wait_end	: std_logic;

-

-signal	cas_qn_p_del		: std_logic;

-signal	ras_qn_p_del		: std_logic;

-signal	we_qn_p_del			: std_logic;

-signal	sdr_d_p_del			: std_logic_vector(15 downto 0);

-

-signal	saved_row			: std_logic_vector(26 downto 11);

-signal	operation			: std_logic_vector(1 downto 0);

-

-signal	ddr_req_adr_int		: std_logic_vector(25 downto 1);

-

-type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, 

-					rd_nop2,rd_nop3,rd_nop4, rd_nop5,pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, 

-					wr_nop3, cmd, cpu_pre, refresh, refresh_wait);

-signal	ddr_state			: state_type;

-

-constant	Clk_to_Output	: time := 2.2 ns;

-constant	Input_Setup	: time := 2.5 ns;

-

-constant	Refresh_Interval	: std_logic_vector(9 downto 0) := "1111100110";

-

-begin

-

-	iotimingon:

-	if simulate_io_time generate

-	begin

-		cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup;

-		ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup;

-		we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup;

-		sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup;

-	end generate;

-	

-	iotimingoff:

-	if not simulate_io_time generate

-	begin

-		cas_qn_p_del <= cas_qn_p;

-		ras_qn_p_del <= ras_qn_p;

-		we_qn_p_del <= we_qn_p;

-		sdr_d_p_del <= sdr_d_p;

-	end generate;

-	

-	ddr_write_en <= ddr_write_en_int;

-	ddr_read_en <= ddr_read_en_int;

-	ddr_data_read <= ddr_data_read_int;

-	

-	ddr_req_adr_int <= (ddr_req_adr(24 downto 10) & '0' & ddr_req_adr(9 downto 1)) when (simulate_io_time) else ddr_req_adr;

-

-	process(cpu_clk, areset)	-- Toggle a flip-flop with cpu_clk, in order 

-	begin						-- to find phase relation with 2x and 4x clocks

-		if areset = '1' then

-			cpu_clk_tog <= '0';

-		elsif (cpu_clk'event and cpu_clk = '1') then

-			cpu_clk_tog <= not(cpu_clk_tog);

-		end if;

-	end process;

-	

-	process(cpu_clk_2x, areset)	-- Find phase relation between cpu_clk and cpu_clk_2x

-	begin

-		if areset = '1' then

-			cpu_clk_2x_smp1 <= '0';

-			cpu_clk_2x_smp2 <= '0';

-			clk2_phase <= '0';

-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then

-			cpu_clk_2x_smp1 <= cpu_clk_tog;

-			cpu_clk_2x_smp2 <= cpu_clk_2x_smp1;

-			if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then

-				clk2_phase <= '0';

-			else

-				clk2_phase <= not(clk2_phase);

-			end if;

-		end if;

-	end process;

-	

-	process(cpu_clk_4x, areset)	-- Find phase relation between cpu_clk and cpu_clk_4x

-	begin

-		if areset = '1' then

-			cpu_clk_4x_smp1 <= '0';

-			cpu_clk_4x_smp2 <= '0';

-			clk4_phase <= "0000";

-			clk4_phase_short(0) <= "00";

-			clk4_phase_short(1) <= "00";

-			clk4_phase_short(2) <= "00";

-			clk4_phase_short(3) <= "00";

-			clk4_phase_short(4) <= "00";

-			clk4_phase_short(5) <= "00";

-			clk4_phase_short(6) <= "00";

-			clk4_phase_short(7) <= "00";

-			clk4_phase_short(8) <= "00";

-			clk4_phase_short(9) <= "00";

-			clk4_phase_short(10) <= "00";

-			clk4_phase_short(11) <= "00";

-			clk4_phase_short(12) <= "00";

-			clk4_phase_short(13) <= "00";

-			clk4_phase_short(14) <= "00";

-			clk4_phase_short(15) <= "00";

-		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then

-			cpu_clk_4x_smp1 <= cpu_clk_tog;

-			cpu_clk_4x_smp2 <= cpu_clk_4x_smp1;

-			for i in 0 to 15 loop

-				if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then

-					clk4_phase <= "0100";

-					clk4_phase_short(i) <= "01";

-				else

-					clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3));

-					clk4_phase_short(i) <= clk4_phase_short(i)(0) & clk4_phase_short(i)(1);

-				end if;

-			end loop;

-		end if;

-	end process;

-

-	process(cpu_clk_4x, areset)	--

-	begin

-		if areset = '1' then

-			sdr_clk <= '0';			

-			sdr_clk_n <= '0';			

-		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then

-			if clk4_phase_short(0)(0) = '1' then

-				sdr_clk <= '1';

-			else

-				sdr_clk <= '0';

-			end if;

-			if clk4_phase_short(0)(1) = '1' then

-				sdr_clk_n <= '1';

-			else

-				sdr_clk_n <= '0';

-			end if;

-		end if;

-	end process;

-	

-    cke_q_p <= '1' after Clk_to_Output;

-    cs_qn_p <= '0' after Clk_to_Output;

-	

-	process(cpu_clk_4x, areset)	--

-	begin

-		if areset = '1' then

-		    ras_qn_p <= '1';

-		    cas_qn_p <= '1';

-		    we_qn_p <= '1';

-		    dqs_q_p <= "ZZ";

-		    sdr_a_p <= "0000000000000";

-			ba_q_p <= "00";

-			sdr_clk_p <= '0';

-			sdr_clk_n_p <= '1';

-		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then

-		    ras_qn_p <= transport ras_qn after Clk_to_Output;

-		    cas_qn_p <= transport cas_qn after Clk_to_Output;

-		    we_qn_p <= transport we_qn after Clk_to_Output;

-		    if dqs_oe_n(0) = '0' then

-		    	dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output;

-		    else

-		    	dqs_q_p(0) <= transport 'Z' after Clk_to_Output;

-		    end if;

-		    if dqs_oe_n(1) = '0' then

-		    	dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output;

-		    else

-		    	dqs_q_p(1) <= transport 'Z' after Clk_to_Output;

-		    end if;

-		    sdr_a_p <= transport sdr_a after Clk_to_Output;

-		    ba_q_p <= transport ba_q after Clk_to_Output;

-		    sdr_clk_p <= transport sdr_clk after Clk_to_Output;

-		    sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output;

-		end if;

-	end process;

-	

-	process(cpu_clk_2x, areset)	--

-	begin

-		if areset = '1' then

-			ddr_state <= idle;

-			ras_qn <= '1';

-			cas_qn <= '1';

-			we_qn <= '1';

-			smp_req_adr <= (others => '0');

-			smp_req_type <= '0';

-			smp_req_len <= '0';

-			sdr_a <= "XXXXXXXXXXXXX";

-			ba_q <= "00";

-			ddr_busy <= '1';

-			saved_row <= "1000000000000000";

-			ddr_write_en_int <= '0';

-			ddr_read_en_int <= '0';

-			nowin_idle_dqs <= "11";

-			nowin_wr_nop1_d <= "0000000000000000";

-			nowin_wr_nop1_dqs <= "00";

-			nowin_wr_nop1_dm <= "00";

-			nowin_wr_nop2_dqs <= "00";

-			nowin_wr_nop3_d <= "0000000000000000";

-			nowin_wr_nop3_dqs <= "00";

-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then

-		

-			-- Default values

-			ras_qn <= '1';

-			cas_qn <= '1';

-			we_qn <= '1';

-			sdr_a <= "XXXXXXXXXXXXX";

-			ddr_busy <= '1';

-			ddr_write_en_int <= '0';

-			ddr_read_en_int <= '0';

-

-			nowin_idle_dqs <= "00";

-			nowin_wr_nop1_d <= "0000000000000000";

-			nowin_wr_nop1_dqs <= "00";

-			nowin_wr_nop1_dm <= "00";

-			nowin_wr_nop2_dqs <= "00";

-			nowin_wr_nop3_d <= "0000000000000000";

-			nowin_wr_nop3_dqs <= "00";

-		

-			case ddr_state is

-				when idle =>

-					smp_req_adr <= ddr_req_adr_int;

-					smp_req_type <= ddr_rd_wr_n;

-					smp_req_len <= ddr_req_len;

-					ddr_busy <= '0';

-					operation <= "00";

-					if refresh_pend = '1' then

-						operation <= "01";

-						ddr_state <= pre;

-					elsif new_command = '1' then

-						if ddr_cmd(15) = '1' then

-							operation <= "10";

-							ddr_state <= cpu_pre;

-						else

-							ddr_state <= cmd;

-						end if;

-					elsif (ddr_req = '1' and ddr_req_adr_int(25 downto 11) = saved_row(25 downto 11) and saved_row(26) = '0') then

-						operation <= "11";

-						ddr_write_en_int <= not(ddr_rd_wr_n);

-						ddr_state <= rd_wr;

-					elsif ddr_req = '1' then

-						operation <= "11";

-						ddr_state <= pre;

-					else

-						ddr_state <= idle;

-						nowin_idle_dqs <= "11";

-					end if;

-				when act =>

-					sdr_a <= smp_req_adr(23 downto 11);

-					ba_q <= smp_req_adr(25 downto 24);

-					ras_qn <= '0';

-					ddr_write_en_int <= not(smp_req_type);

-					ddr_state <= act_nop1;

-				when act_nop1 =>

-					ddr_state <= act_nop2;

-				when act_nop2 =>

-					ddr_state <= rd_wr;

-				when rd_wr =>

-					sdr_a(10) <= '0';		-- Disable auto precharge

-					sdr_a(9 downto 0) <= smp_req_adr(10 downto 1);

-					ba_q <= smp_req_adr(25 downto 24);

-					saved_row <= '0' & smp_req_adr(25 downto 11);

-					cas_qn <= '0';

-					we_qn <= smp_req_type;

-					if smp_req_type = '1' then

-						ddr_state <= rd_nop1;

-					else

-						ddr_state <= wr_nop1;

-						nowin_wr_nop1_d <= "1111111111111111";

-						nowin_wr_nop1_dqs <= "11";

-						nowin_wr_nop1_dm <= "11";

-					end if;

-				when wr_nop1 =>

-					ddr_state <= wr_nop2;	

-					nowin_wr_nop2_dqs <= "11";

-				when wr_nop2 =>

-					ddr_state <= wr_nop3;

-					nowin_wr_nop3_d <= "1111111111111111";

-					nowin_wr_nop3_dqs <= "11";

-				when wr_nop3 =>

-					nowin_idle_dqs <= "11";

-					ddr_state <= idle;

-				when rd_nop1 =>

-					ddr_state <= rd_nop2;

-				when rd_nop2 =>

-					if operation /= "11" then

-						nowin_idle_dqs <= "11";

-						ddr_state <= idle;

-					else

-						ddr_state <= rd_nop3;

-					end if;

-				when rd_nop3 =>

-					ddr_state <= rd_nop4;

-				when rd_nop4 =>

-					ddr_read_en_int <= '1';

-					ddr_state <= rd_nop5;

-				when rd_nop5 =>

-					nowin_idle_dqs <= "11";

-					ddr_state <= idle;

-				when pre =>					

-					ras_qn <= '0';

-					we_qn <= '0';

-					sdr_a(10) <= '1';	-- Precharge all banks

-					ba_q <= smp_req_adr(25 downto 24);

-					ddr_state <= pre_nop1;

-				when pre_nop1 =>

-					ddr_state <= pre_nop2;

-				when cmd =>

-					cas_qn <= '0';

-					ras_qn <= '0';

-					we_qn <= '0';

-					ba_q <= ddr_cmd(14 downto 13);

-					sdr_a <= ddr_cmd(12 downto 0);

-					nowin_idle_dqs <= "11";

-					ddr_state <= idle;

-				when cpu_pre =>

-					ddr_state <= pre;

-				when refresh =>

-					cas_qn <= '0';

-					ras_qn <= '0';

-					saved_row(26) <= '1';

-					ddr_state <= refresh_wait;

-				when refresh_wait =>

-					if refresh_wait_end = '1' then

-						ddr_state <= pre_nop2;

-					end if;

-				when pre_nop2 =>

-					if operation = "01" then

-						operation <= "10";

-						ddr_state <= refresh;

-					elsif operation = "10" then

-						nowin_idle_dqs <= "11";

-						ddr_state <= idle;

-					else

-						ddr_state <= act;

-					end if;

-				when others =>

-					ddr_state <= idle;

-					nowin_idle_dqs <= "11";

-			end case;

-		end if;

-	end process;

-	

-	process(cpu_clk, areset)	--

-	begin

-		if areset = '1' then

-			ddr_cmd <= "0000000000000000";

-		elsif (cpu_clk'event and cpu_clk = '1') then

-			if ddr_command_we = '1' then

-				ddr_cmd <= ddr_command;

-			else

-				ddr_cmd <= ddr_cmd;

-			end if;

-		end if;

-	end process;

-	

-	process(cpu_clk_2x, areset)	--

-	begin

-		if areset = '1' then

-			ddr_cmd_we_smp <= '0';

-			new_command <= '0';

-			sdr_smp <= "000000000000000000000000000000000000";

-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then

-			ddr_cmd_we_smp <= ddr_command_we;

-			if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then

-				new_command <= '1';

-			elsif ddr_state = cmd or ddr_state = cpu_pre then

-				new_command <= '0';

-			else

-				new_command <= new_command;

-			end if;

-			

-			if ddr_write_en_int = '1' then

-			   	sdr_smp <= ddr_data_write;

-			else

-				sdr_smp <= sdr_smp;

-			end if;

-			

-		end if;

-	end process;

-	

-	process(cpu_clk_4x, areset)	--

-	begin

-		if areset = '1' then

-			dqs_q <= "00";

-			dqs_oe_n <= "11";

-			sdr_oe_ctrl <= "1111111111111111";

-			sdr_wr_msw <= "000000000000000000";

-		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then

-		

-			for i in 0 to 15 loop

-				if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(0) = '1' then

-					sdr_oe_ctrl(i) <= '0';

-				elsif nowin_wr_nop3_d(i) = '1' and clk4_phase_short(i)(0) = '1' then

-					sdr_oe_ctrl(i) <= '1';

-				end if;

-			end loop;

-		

-			for i in 0 to 1 loop

-				if nowin_idle_dqs(i) = '1' or nowin_wr_nop3_dqs(i) = '1' then

-					dqs_oe_n(i) <= '1';

-				elsif nowin_wr_nop1_dqs(i) = '1' then

-					dqs_oe_n(i)  <= '0';

-				end if;

-			end loop;

-

-			for i in 0 to 1 loop

-				if (nowin_wr_nop2_dqs(i) = '1' and clk4_phase_short(i)(0) = '1') then

-					dqs_q(i) <= '1';

-				else

-					dqs_q(i) <= '0';

-				end if;

-			end loop;

-

-			for i in 0 to 15 loop

-				if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(1) = '1' then

-					sdr_wr_msw(i) <= '1';

-				else

-					sdr_wr_msw(i) <= '0';

-				end if;

-			end loop;

-			

-			for i in 0 to 1 loop

-				if nowin_wr_nop1_dm(i) = '1' and clk4_phase_short(i)(1) = '1' then

-					sdr_wr_msw(i+16) <= '1';

-				else

-					sdr_wr_msw(i+16) <= '0';

-				end if;

-			end loop;

-

-		end if;

-	end process;

-	

-	-- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK

-	process(cpu_clk_4x, areset)	--

-	begin

-		if areset = '1' then

-		    sdr_d_p <= "ZZZZZZZZZZZZZZZZ";

-		    dm_q_p <= "11";

-		    sdr_oe_n <= "1111111111111111";

-		    sdr_d <= "0000000000000000";

-		    dm_q <= "11";

-		elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then

-

-			for i in 0 to 15 loop

-				if sdr_oe_n(i) = '0' then

-					sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output;

-				else

-					sdr_d_p(i) <= transport 'Z' after Clk_to_Output;

-				end if;

-		   	end loop;			

-

-			dm_q_p <= transport dm_q after Clk_to_Output;

-

-			for i in 0 to 15 loop

-				if sdr_oe_ctrl(i) = '0' then

-					sdr_oe_n(i) <= '0';

-				else

-					sdr_oe_n(i) <= '1';

-				end if;

-			end loop;

-			

-			for i in 0 to 15 loop

-				if sdr_wr_msw(i) = '1' then

-		   			sdr_d(i) <= sdr_smp(i);

-		   		else

-	   				sdr_d(i) <= sdr_smp(i+16);

-	   			end if;

-		   	end loop;

-		   	

-			for i in 0 to 1 loop

-				if sdr_wr_msw(i+16) = '1' then

-		   			dm_q(i) <= sdr_smp(i+32);

-		   		else

-		   			dm_q(i) <= sdr_smp(i+34);

-		   		end if;

-		   	end loop;

-		   	

-		end if;

-	end process;

-	

-	process(cpu_clk_2x, areset)	--

-	begin

-		if areset = '1' then

-			refresh_cnt <= "0000000000";

-			refresh_pend <= '0';

-			refresh_end <= '0';

-			refresh_wait_cnt <= "0000";

-			refresh_wait_end <= '0';

-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then

-		

-			if refresh_cnt = Refresh_Interval then

-				refresh_end <= '1';

-			else

-				refresh_end <= '0';

-			end if;

-			

-			if refresh_end = '1' then

-				refresh_cnt <= "0000000000";

-			else

-				refresh_cnt <= refresh_cnt + '1';

-			end if;

-			

-			if refresh_end = '1' and refresh_en = '1' then

-				refresh_pend <= '1';

-			elsif ddr_state = refresh then

-				refresh_pend <= '0';

-			else

-				refresh_pend <= refresh_pend;

-			end if;

-			

-			if ddr_state = refresh_wait then

-				refresh_wait_cnt <= refresh_wait_cnt + '1';

-			else

-				refresh_wait_cnt <= "0000";

-			end if;

-			

-			if refresh_wait_cnt = "1011" then

-				refresh_wait_end <= '1';

-			else

-				refresh_wait_end <= '0';

-			end if;

-			

-		end if;

-	end process;

-	

-	-- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING

-

-	process(ddr_in_clk, areset)

-	begin

-		if areset = '1' then

-			ddr_clk_tog <= '0';

-		elsif (ddr_in_clk'event and ddr_in_clk = '1') then

-			ddr_clk_tog <= not(ddr_clk_tog);

-		end if;

-	end process;	

-	

-	process(ddr_in_clk_2x, areset)

-	begin

-		if areset = '1' then

-			ddr_clk_smp1 <= '0';

-			ddr_clk_smp2 <= '0';

-			ddr_clk_phase <= '0';

-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then

-			ddr_clk_smp1 <= ddr_clk_tog;

-			ddr_clk_smp2 <= ddr_clk_smp1;

-			if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then

-				ddr_clk_phase <= '0';

-			else

-				ddr_clk_phase <= not(ddr_clk_phase);

-			end if;

-		end if;

-	end process;

-

-	process(ddr_in_clk_2x, areset)

-	begin

-		if areset = '1' then

-			cas_n_smp <= '0';

-			ras_n_smp <= '0';

-			we_n_smp <= '0';

-			read_start_sig <= '0';

-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then

-			cas_n_smp <= cas_qn_p_del;

-			ras_n_smp <= ras_qn_p_del;

-			we_n_smp <= we_qn_p_del;

-			if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then

-				read_start_sig <= '1';

-			else

-				read_start_sig <= '0';

-			end if;

-		end if;

-	end process;

-

-	process(ddr_in_clk_2x, areset)

-	begin

-		if areset = '1' then

-			sdr_d_in <= "0000000000000000";

-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then

-			sdr_d_in <= sdr_d_p_del;

-		end if;

-	end process;

-	

-	process(ddr_in_clk_2x, areset)

-	begin

-		if areset = '1' then

-			read_time_cnt <= "00";

-			read_input_en <= '0';

-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then

-

-			if read_start_sig = '1' then	

-				read_time_cnt <= "01";

-			elsif read_time_cnt = "00" then

-				read_time_cnt <= read_time_cnt;

-			else

-				read_time_cnt <= read_time_cnt + '1';

-			end if;

-

-			if read_time_cnt = "11" then

-				read_input_en <= '1';

-			else

-				read_input_en <= '0';

-			end if;

-			

-			read_input_en_del <= read_input_en;

-

-		end if;

-	end process;

-	

-	process(ddr_in_clk_2x, areset)

-	begin

-		if areset = '1' then

-			ddr_data_read_int <= "00000000000000000000000000000000";

-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then

-			if read_input_en = '1' then

-				ddr_data_read_int(15 downto 0) <= sdr_d_in;

-			end if;

-			if read_input_en_del = '1' then

-				ddr_data_read_int(31 downto 16) <= sdr_d_in;

-			end if;

-		end if;

-	end process;

-

-end behave;

-

-

+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity ddr_top is
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	-- Asyncronous reset and clocks
+			areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_clk_4x		: in std_logic;
+			ddr_in_clk		: in std_logic;
+			ddr_in_clk_2x	: in std_logic;
+			
+			-- Command interface
+			ddr_command		: in std_logic_vector(15 downto 0);
+			ddr_command_we	: in std_logic;
+			refresh_en		: in std_logic;
+			
+			-- Data interface signals
+			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
+			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
+			ddr_req_adr		: in std_logic_vector(25 downto 1);		-- Request address
+			ddr_req			: in std_logic;							-- Request DDR SDRAM access
+			ddr_busy		: out std_logic;							-- Request acknowledge
+			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE
+			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)
+			ddr_read_en		: out std_logic;						-- Enable signal for read data
+			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write
+
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
+end ddr_top;
+
+architecture behave of ddr_top is
+
+attribute keep : string;
+
+type	clk4_type			is array(0 to 15) of std_logic_vector(1 downto 0);
+
+signal	cpu_clk_tog			: std_logic;
+signal	ddr_cmd				: std_logic_vector(15 downto 0);
+signal	ddr_cmd_we_smp		: std_logic;
+signal	new_command			: std_logic;
+
+signal	cpu_clk_2x_smp1		: std_logic;		
+signal	cpu_clk_2x_smp2		: std_logic;		
+signal	cpu_clk_4x_smp1		: std_logic;		
+signal	cpu_clk_4x_smp2		: std_logic;
+
+signal	clk2_phase			: std_logic;	
+signal	clk4_phase			: std_logic_vector(3 downto 0);
+signal	clk4_phase_short	: clk4_type;
+attribute keep of clk4_phase_short:signal is "true";
+
+signal	ddr_clk_tog			: std_logic;
+signal	ddr_clk_smp1		: std_logic;
+signal	ddr_clk_smp2		: std_logic;
+signal	ddr_clk_phase		: std_logic;
+
+signal	smp_req_adr			: std_logic_vector(25 downto 1);
+signal	smp_req_type		: std_logic;
+signal	smp_req_len			: std_logic;
+signal	ddr_write_en_int	: std_logic;
+signal	ddr_read_en_int		: std_logic;
+
+signal	dqs_q				: std_logic_vector(1 downto 0);
+signal	dqs_oe_n			: std_logic_vector(1 downto 0);
+attribute keep of dqs_oe_n:signal is "true";
+signal	cas_qn				: std_logic;
+signal	ras_qn				: std_logic;
+signal	we_qn				: std_logic;
+signal	ba_q				: std_logic_vector(1 downto 0);
+signal	sdr_clk				: std_logic;
+signal	sdr_clk_n			: std_logic;
+signal	sdr_a				: std_logic_vector(12 downto 0);
+signal	sdr_d				: std_logic_vector(15 downto 0);
+signal	sdr_smp				: std_logic_vector(35 downto 0);
+signal	sdr_oe_n			: std_logic_vector(15 downto 0);
+attribute keep of sdr_oe_n:signal is "true";
+signal	sdr_oe_ctrl			: std_logic_vector(15 downto 0);
+attribute keep of sdr_oe_ctrl:signal is "true";
+signal	sdr_wr_msw			: std_logic_vector(17 downto 0);
+attribute keep of sdr_wr_msw:signal is "true";
+signal	dm_q				: std_logic_vector(1 downto 0);
+
+signal  nowin_idle_dqs      : std_logic_vector(1 downto 0);
+signal  nowin_wr_nop1_d     : std_logic_vector(15 downto 0);
+signal  nowin_wr_nop1_dqs   : std_logic_vector(1 downto 0);
+signal  nowin_wr_nop1_dm    : std_logic_vector(1 downto 0);
+signal  nowin_wr_nop2_dqs   : std_logic_vector(1 downto 0);
+signal  nowin_wr_nop3_d     : std_logic_vector(15 downto 0);
+signal  nowin_wr_nop3_dqs   : std_logic_vector(1 downto 0);
+attribute keep of nowin_idle_dqs:signal is "true";
+attribute keep of nowin_wr_nop1_d:signal is "true";
+attribute keep of nowin_wr_nop1_dqs:signal is "true";
+attribute keep of nowin_wr_nop1_dm:signal is "true";
+attribute keep of nowin_wr_nop2_dqs:signal is "true";
+attribute keep of nowin_wr_nop3_d:signal is "true";
+attribute keep of nowin_wr_nop3_dqs:signal is "true";
+
+signal	cas_n_smp			: std_logic;
+signal	ras_n_smp			: std_logic;
+signal	we_n_smp			: std_logic;
+signal	read_start_sig		: std_logic;
+signal	sdr_d_in			: std_logic_vector(15 downto 0);
+signal	read_time_cnt		: std_logic_vector(1 downto 0);
+signal	read_input_en		: std_logic;
+signal	read_input_en_del	: std_logic;
+signal	ddr_data_read_int	: std_logic_vector(31 downto 0);
+
+signal	refresh_pend		: std_logic;
+signal	refresh_end			: std_logic;
+signal	refresh_cnt			: std_logic_vector(9 downto 0);
+signal	refresh_wait_cnt	: std_logic_vector(3 downto 0);
+signal	refresh_wait_end	: std_logic;
+
+signal	cas_qn_p_del		: std_logic;
+signal	ras_qn_p_del		: std_logic;
+signal	we_qn_p_del			: std_logic;
+signal	sdr_d_p_del			: std_logic_vector(15 downto 0);
+
+signal	saved_row			: std_logic_vector(26 downto 11);
+signal	operation			: std_logic_vector(1 downto 0);
+
+signal	ddr_req_adr_int		: std_logic_vector(25 downto 1);
+
+type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, 
+					rd_nop2,rd_nop3,rd_nop4, rd_nop5,pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, 
+					wr_nop3, cmd, cpu_pre, refresh, refresh_wait);
+signal	ddr_state			: state_type;
+
+constant	Clk_to_Output	: time := 2.2 ns;
+constant	Input_Setup	: time := 2.5 ns;
+
+constant	Refresh_Interval	: std_logic_vector(9 downto 0) := "1111100110";
+
+begin
+
+	iotimingon:
+	if simulate_io_time generate
+	begin
+		cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup;
+		ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup;
+		we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup;
+		sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup;
+	end generate;
+	
+	iotimingoff:
+	if not simulate_io_time generate
+	begin
+		cas_qn_p_del <= cas_qn_p;
+		ras_qn_p_del <= ras_qn_p;
+		we_qn_p_del <= we_qn_p;
+		sdr_d_p_del <= sdr_d_p;
+	end generate;
+	
+	ddr_write_en <= ddr_write_en_int;
+	ddr_read_en <= ddr_read_en_int;
+	ddr_data_read <= ddr_data_read_int;
+	
+	ddr_req_adr_int <= (ddr_req_adr(24 downto 10) & '0' & ddr_req_adr(9 downto 1)) when (simulate_io_time) else ddr_req_adr;
+
+	process(cpu_clk, areset)	-- Toggle a flip-flop with cpu_clk, in order 
+	begin						-- to find phase relation with 2x and 4x clocks
+		if areset = '1' then
+			cpu_clk_tog <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			cpu_clk_tog <= not(cpu_clk_tog);
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	-- Find phase relation between cpu_clk and cpu_clk_2x
+	begin
+		if areset = '1' then
+			cpu_clk_2x_smp1 <= '0';
+			cpu_clk_2x_smp2 <= '0';
+			clk2_phase <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			cpu_clk_2x_smp1 <= cpu_clk_tog;
+			cpu_clk_2x_smp2 <= cpu_clk_2x_smp1;
+			if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then
+				clk2_phase <= '0';
+			else
+				clk2_phase <= not(clk2_phase);
+			end if;
+		end if;
+	end process;
+	
+	process(cpu_clk_4x, areset)	-- Find phase relation between cpu_clk and cpu_clk_4x
+	begin
+		if areset = '1' then
+			cpu_clk_4x_smp1 <= '0';
+			cpu_clk_4x_smp2 <= '0';
+			clk4_phase <= "0000";
+			clk4_phase_short(0) <= "00";
+			clk4_phase_short(1) <= "00";
+			clk4_phase_short(2) <= "00";
+			clk4_phase_short(3) <= "00";
+			clk4_phase_short(4) <= "00";
+			clk4_phase_short(5) <= "00";
+			clk4_phase_short(6) <= "00";
+			clk4_phase_short(7) <= "00";
+			clk4_phase_short(8) <= "00";
+			clk4_phase_short(9) <= "00";
+			clk4_phase_short(10) <= "00";
+			clk4_phase_short(11) <= "00";
+			clk4_phase_short(12) <= "00";
+			clk4_phase_short(13) <= "00";
+			clk4_phase_short(14) <= "00";
+			clk4_phase_short(15) <= "00";
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+			cpu_clk_4x_smp1 <= cpu_clk_tog;
+			cpu_clk_4x_smp2 <= cpu_clk_4x_smp1;
+			for i in 0 to 15 loop
+				if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then
+					clk4_phase <= "0100";
+					clk4_phase_short(i) <= "01";
+				else
+					clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3));
+					clk4_phase_short(i) <= clk4_phase_short(i)(0) & clk4_phase_short(i)(1);
+				end if;
+			end loop;
+		end if;
+	end process;
+
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+			sdr_clk <= '0';			
+			sdr_clk_n <= '0';			
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+			if clk4_phase_short(0)(0) = '1' then
+				sdr_clk <= '1';
+			else
+				sdr_clk <= '0';
+			end if;
+			if clk4_phase_short(0)(1) = '1' then
+				sdr_clk_n <= '1';
+			else
+				sdr_clk_n <= '0';
+			end if;
+		end if;
+	end process;
+	
+    cke_q_p <= '1' after Clk_to_Output;
+    cs_qn_p <= '0' after Clk_to_Output;
+	
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+		    ras_qn_p <= '1';
+		    cas_qn_p <= '1';
+		    we_qn_p <= '1';
+		    dqs_q_p <= "ZZ";
+		    sdr_a_p <= "0000000000000";
+			ba_q_p <= "00";
+			sdr_clk_p <= '0';
+			sdr_clk_n_p <= '1';
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+		    ras_qn_p <= transport ras_qn after Clk_to_Output;
+		    cas_qn_p <= transport cas_qn after Clk_to_Output;
+		    we_qn_p <= transport we_qn after Clk_to_Output;
+		    if dqs_oe_n(0) = '0' then
+		    	dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output;
+		    else
+		    	dqs_q_p(0) <= transport 'Z' after Clk_to_Output;
+		    end if;
+		    if dqs_oe_n(1) = '0' then
+		    	dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output;
+		    else
+		    	dqs_q_p(1) <= transport 'Z' after Clk_to_Output;
+		    end if;
+		    sdr_a_p <= transport sdr_a after Clk_to_Output;
+		    ba_q_p <= transport ba_q after Clk_to_Output;
+		    sdr_clk_p <= transport sdr_clk after Clk_to_Output;
+		    sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+			ddr_state <= idle;
+			ras_qn <= '1';
+			cas_qn <= '1';
+			we_qn <= '1';
+			smp_req_adr <= (others => '0');
+			smp_req_type <= '0';
+			smp_req_len <= '0';
+			sdr_a <= "XXXXXXXXXXXXX";
+			ba_q <= "00";
+			ddr_busy <= '1';
+			saved_row <= "1000000000000000";
+			ddr_write_en_int <= '0';
+			ddr_read_en_int <= '0';
+			nowin_idle_dqs <= "11";
+			nowin_wr_nop1_d <= "0000000000000000";
+			nowin_wr_nop1_dqs <= "00";
+			nowin_wr_nop1_dm <= "00";
+			nowin_wr_nop2_dqs <= "00";
+			nowin_wr_nop3_d <= "0000000000000000";
+			nowin_wr_nop3_dqs <= "00";
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+		
+			-- Default values
+			ras_qn <= '1';
+			cas_qn <= '1';
+			we_qn <= '1';
+			sdr_a <= "XXXXXXXXXXXXX";
+			ddr_busy <= '1';
+			ddr_write_en_int <= '0';
+			ddr_read_en_int <= '0';
+
+			nowin_idle_dqs <= "00";
+			nowin_wr_nop1_d <= "0000000000000000";
+			nowin_wr_nop1_dqs <= "00";
+			nowin_wr_nop1_dm <= "00";
+			nowin_wr_nop2_dqs <= "00";
+			nowin_wr_nop3_d <= "0000000000000000";
+			nowin_wr_nop3_dqs <= "00";
+		
+			case ddr_state is
+				when idle =>
+					smp_req_adr <= ddr_req_adr_int;
+					smp_req_type <= ddr_rd_wr_n;
+					smp_req_len <= ddr_req_len;
+					ddr_busy <= '0';
+					operation <= "00";
+					if refresh_pend = '1' then
+						operation <= "01";
+						ddr_state <= pre;
+					elsif new_command = '1' then
+						if ddr_cmd(15) = '1' then
+							operation <= "10";
+							ddr_state <= cpu_pre;
+						else
+							ddr_state <= cmd;
+						end if;
+					elsif (ddr_req = '1' and ddr_req_adr_int(25 downto 11) = saved_row(25 downto 11) and saved_row(26) = '0') then
+						operation <= "11";
+						ddr_write_en_int <= not(ddr_rd_wr_n);
+						ddr_state <= rd_wr;
+					elsif ddr_req = '1' then
+						operation <= "11";
+						ddr_state <= pre;
+					else
+						ddr_state <= idle;
+						nowin_idle_dqs <= "11";
+					end if;
+				when act =>
+					sdr_a <= smp_req_adr(23 downto 11);
+					ba_q <= smp_req_adr(25 downto 24);
+					ras_qn <= '0';
+					ddr_write_en_int <= not(smp_req_type);
+					ddr_state <= act_nop1;
+				when act_nop1 =>
+					ddr_state <= act_nop2;
+				when act_nop2 =>
+					ddr_state <= rd_wr;
+				when rd_wr =>
+					sdr_a(10) <= '0';		-- Disable auto precharge
+					sdr_a(9 downto 0) <= smp_req_adr(10 downto 1);
+					ba_q <= smp_req_adr(25 downto 24);
+					saved_row <= '0' & smp_req_adr(25 downto 11);
+					cas_qn <= '0';
+					we_qn <= smp_req_type;
+					if smp_req_type = '1' then
+						ddr_state <= rd_nop1;
+					else
+						ddr_state <= wr_nop1;
+						nowin_wr_nop1_d <= "1111111111111111";
+						nowin_wr_nop1_dqs <= "11";
+						nowin_wr_nop1_dm <= "11";
+					end if;
+				when wr_nop1 =>
+					ddr_state <= wr_nop2;	
+					nowin_wr_nop2_dqs <= "11";
+				when wr_nop2 =>
+					ddr_state <= wr_nop3;
+					nowin_wr_nop3_d <= "1111111111111111";
+					nowin_wr_nop3_dqs <= "11";
+				when wr_nop3 =>
+					nowin_idle_dqs <= "11";
+					ddr_state <= idle;
+				when rd_nop1 =>
+					ddr_state <= rd_nop2;
+				when rd_nop2 =>
+					if operation /= "11" then
+						nowin_idle_dqs <= "11";
+						ddr_state <= idle;
+					else
+						ddr_state <= rd_nop3;
+					end if;
+				when rd_nop3 =>
+					ddr_state <= rd_nop4;
+				when rd_nop4 =>
+					ddr_read_en_int <= '1';
+					ddr_state <= rd_nop5;
+				when rd_nop5 =>
+					nowin_idle_dqs <= "11";
+					ddr_state <= idle;
+				when pre =>					
+					ras_qn <= '0';
+					we_qn <= '0';
+					sdr_a(10) <= '1';	-- Precharge all banks
+					ba_q <= smp_req_adr(25 downto 24);
+					ddr_state <= pre_nop1;
+				when pre_nop1 =>
+					ddr_state <= pre_nop2;
+				when cmd =>
+					cas_qn <= '0';
+					ras_qn <= '0';
+					we_qn <= '0';
+					ba_q <= ddr_cmd(14 downto 13);
+					sdr_a <= ddr_cmd(12 downto 0);
+					nowin_idle_dqs <= "11";
+					ddr_state <= idle;
+				when cpu_pre =>
+					ddr_state <= pre;
+				when refresh =>
+					cas_qn <= '0';
+					ras_qn <= '0';
+					saved_row(26) <= '1';
+					ddr_state <= refresh_wait;
+				when refresh_wait =>
+					if refresh_wait_end = '1' then
+						ddr_state <= pre_nop2;
+					end if;
+				when pre_nop2 =>
+					if operation = "01" then
+						operation <= "10";
+						ddr_state <= refresh;
+					elsif operation = "10" then
+						nowin_idle_dqs <= "11";
+						ddr_state <= idle;
+					else
+						ddr_state <= act;
+					end if;
+				when others =>
+					ddr_state <= idle;
+					nowin_idle_dqs <= "11";
+			end case;
+		end if;
+	end process;
+	
+	process(cpu_clk, areset)	--
+	begin
+		if areset = '1' then
+			ddr_cmd <= "0000000000000000";
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			if ddr_command_we = '1' then
+				ddr_cmd <= ddr_command;
+			else
+				ddr_cmd <= ddr_cmd;
+			end if;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+			ddr_cmd_we_smp <= '0';
+			new_command <= '0';
+			sdr_smp <= "000000000000000000000000000000000000";
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			ddr_cmd_we_smp <= ddr_command_we;
+			if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then
+				new_command <= '1';
+			elsif ddr_state = cmd or ddr_state = cpu_pre then
+				new_command <= '0';
+			else
+				new_command <= new_command;
+			end if;
+			
+			if ddr_write_en_int = '1' then
+			   	sdr_smp <= ddr_data_write;
+			else
+				sdr_smp <= sdr_smp;
+			end if;
+			
+		end if;
+	end process;
+	
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+			dqs_q <= "00";
+			dqs_oe_n <= "11";
+			sdr_oe_ctrl <= "1111111111111111";
+			sdr_wr_msw <= "000000000000000000";
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+		
+			for i in 0 to 15 loop
+				if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(0) = '1' then
+					sdr_oe_ctrl(i) <= '0';
+				elsif nowin_wr_nop3_d(i) = '1' and clk4_phase_short(i)(0) = '1' then
+					sdr_oe_ctrl(i) <= '1';
+				end if;
+			end loop;
+		
+			for i in 0 to 1 loop
+				if nowin_idle_dqs(i) = '1' or nowin_wr_nop3_dqs(i) = '1' then
+					dqs_oe_n(i) <= '1';
+				elsif nowin_wr_nop1_dqs(i) = '1' then
+					dqs_oe_n(i)  <= '0';
+				end if;
+			end loop;
+
+			for i in 0 to 1 loop
+				if (nowin_wr_nop2_dqs(i) = '1' and clk4_phase_short(i)(0) = '1') then
+					dqs_q(i) <= '1';
+				else
+					dqs_q(i) <= '0';
+				end if;
+			end loop;
+
+			for i in 0 to 15 loop
+				if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(1) = '1' then
+					sdr_wr_msw(i) <= '1';
+				else
+					sdr_wr_msw(i) <= '0';
+				end if;
+			end loop;
+			
+			for i in 0 to 1 loop
+				if nowin_wr_nop1_dm(i) = '1' and clk4_phase_short(i)(1) = '1' then
+					sdr_wr_msw(i+16) <= '1';
+				else
+					sdr_wr_msw(i+16) <= '0';
+				end if;
+			end loop;
+
+		end if;
+	end process;
+	
+	-- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+		    sdr_d_p <= "ZZZZZZZZZZZZZZZZ";
+		    dm_q_p <= "11";
+		    sdr_oe_n <= "1111111111111111";
+		    sdr_d <= "0000000000000000";
+		    dm_q <= "11";
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then
+
+			for i in 0 to 15 loop
+				if sdr_oe_n(i) = '0' then
+					sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output;
+				else
+					sdr_d_p(i) <= transport 'Z' after Clk_to_Output;
+				end if;
+		   	end loop;			
+
+			dm_q_p <= transport dm_q after Clk_to_Output;
+
+			for i in 0 to 15 loop
+				if sdr_oe_ctrl(i) = '0' then
+					sdr_oe_n(i) <= '0';
+				else
+					sdr_oe_n(i) <= '1';
+				end if;
+			end loop;
+			
+			for i in 0 to 15 loop
+				if sdr_wr_msw(i) = '1' then
+		   			sdr_d(i) <= sdr_smp(i);
+		   		else
+	   				sdr_d(i) <= sdr_smp(i+16);
+	   			end if;
+		   	end loop;
+		   	
+			for i in 0 to 1 loop
+				if sdr_wr_msw(i+16) = '1' then
+		   			dm_q(i) <= sdr_smp(i+32);
+		   		else
+		   			dm_q(i) <= sdr_smp(i+34);
+		   		end if;
+		   	end loop;
+		   	
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+			refresh_cnt <= "0000000000";
+			refresh_pend <= '0';
+			refresh_end <= '0';
+			refresh_wait_cnt <= "0000";
+			refresh_wait_end <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+		
+			if refresh_cnt = Refresh_Interval then
+				refresh_end <= '1';
+			else
+				refresh_end <= '0';
+			end if;
+			
+			if refresh_end = '1' then
+				refresh_cnt <= "0000000000";
+			else
+				refresh_cnt <= refresh_cnt + '1';
+			end if;
+			
+			if refresh_end = '1' and refresh_en = '1' then
+				refresh_pend <= '1';
+			elsif ddr_state = refresh then
+				refresh_pend <= '0';
+			else
+				refresh_pend <= refresh_pend;
+			end if;
+			
+			if ddr_state = refresh_wait then
+				refresh_wait_cnt <= refresh_wait_cnt + '1';
+			else
+				refresh_wait_cnt <= "0000";
+			end if;
+			
+			if refresh_wait_cnt = "1011" then
+				refresh_wait_end <= '1';
+			else
+				refresh_wait_end <= '0';
+			end if;
+			
+		end if;
+	end process;
+	
+	-- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING
+
+	process(ddr_in_clk, areset)
+	begin
+		if areset = '1' then
+			ddr_clk_tog <= '0';
+		elsif (ddr_in_clk'event and ddr_in_clk = '1') then
+			ddr_clk_tog <= not(ddr_clk_tog);
+		end if;
+	end process;	
+	
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			ddr_clk_smp1 <= '0';
+			ddr_clk_smp2 <= '0';
+			ddr_clk_phase <= '0';
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			ddr_clk_smp1 <= ddr_clk_tog;
+			ddr_clk_smp2 <= ddr_clk_smp1;
+			if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then
+				ddr_clk_phase <= '0';
+			else
+				ddr_clk_phase <= not(ddr_clk_phase);
+			end if;
+		end if;
+	end process;
+
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			cas_n_smp <= '0';
+			ras_n_smp <= '0';
+			we_n_smp <= '0';
+			read_start_sig <= '0';
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			cas_n_smp <= cas_qn_p_del;
+			ras_n_smp <= ras_qn_p_del;
+			we_n_smp <= we_qn_p_del;
+			if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then
+				read_start_sig <= '1';
+			else
+				read_start_sig <= '0';
+			end if;
+		end if;
+	end process;
+
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			sdr_d_in <= "0000000000000000";
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			sdr_d_in <= sdr_d_p_del;
+		end if;
+	end process;
+	
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			read_time_cnt <= "00";
+			read_input_en <= '0';
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+
+			if read_start_sig = '1' then	
+				read_time_cnt <= "01";
+			elsif read_time_cnt = "00" then
+				read_time_cnt <= read_time_cnt;
+			else
+				read_time_cnt <= read_time_cnt + '1';
+			end if;
+
+			if read_time_cnt = "11" then
+				read_input_en <= '1';
+			else
+				read_input_en <= '0';
+			end if;
+			
+			read_input_en_del <= read_input_en;
+
+		end if;
+	end process;
+	
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			ddr_data_read_int <= "00000000000000000000000000000000";
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			if read_input_en = '1' then
+				ddr_data_read_int(15 downto 0) <= sdr_d_in;
+			end if;
+			if read_input_en_del = '1' then
+				ddr_data_read_int(31 downto 16) <= sdr_d_in;
+			end if;
+		end if;
+	end process;
+
+end behave;
+
+
diff --git a/misc/ddrsdram/src/mt46v16m16.vhd b/misc/ddrsdram/src/mt46v16m16.vhd
index 6b89345..356bb28 100644
--- a/misc/ddrsdram/src/mt46v16m16.vhd
+++ b/misc/ddrsdram/src/mt46v16m16.vhd
@@ -1,1320 +1,1320 @@
------------------------------------------------------------------------------------------

---

---     File Name: MT46V16M16.VHD

---       Version: 2.1

---          Date: January 14th, 2002

---         Model: Behavioral

---     Simulator: NCDesktop      - http://www.cadence.com

---                ModelSim PE    - http://www.model.com

---

---  Dependencies: None

---

---        Author: Son P. Huynh

---         Email: sphuynh@micron.com

---         Phone: (208) 368-3825

---       Company: Micron Technology, Inc.

---   Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)

---

---   Description: Micron 256 Mb SDRAM DDR (Double Data Rate)

---

---    Limitation: Doesn't model internal refresh counter

---

---          Note: 

---

---    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 

---                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 

---                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR

---                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.

---

---                Copyright (c) 1998 Micron Semiconductor Products, Inc.

---                All rights researved

---

---  Rev  Author                        Date        Changes

---  ---  ----------------------------  ----------  -------------------------------------

---  2.1  Son P. Huynh                  01/14/2002  - Fix Burst_counter

---       Micron Technology, Inc.

---

---  2.0  Son P. Huynh                  11/08/2001  - Second release

---       Micron Technology, Inc.                   - Rewrote and remove SHARED VARIABLE

---

------------------------------------------------------------------------------------------

-

-LIBRARY IEEE;

-    USE IEEE.STD_LOGIC_1164.ALL;

-    USE IEEE.STD_LOGIC_UNSIGNED.ALL;

-    USE IEEE.STD_LOGIC_ARITH.ALL;

-

-ENTITY MT46V16M16 IS

-    GENERIC (                                   -- Timing for -75Z CL2

-        tCK       : TIME    :=  7.500 ns;

-        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK

-        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK

-        tDH       : TIME    :=  0.500 ns;

-        tDS       : TIME    :=  0.500 ns;

-        tIH       : TIME    :=  0.900 ns;

-        tIS       : TIME    :=  0.900 ns;

-        tMRD      : TIME    := 15.000 ns;

-        tRAS      : TIME    := 40.000 ns;

-        tRAP      : TIME    := 20.000 ns;

-        tRC       : TIME    := 65.000 ns;

-        tRFC      : TIME    := 75.000 ns;

-        tRCD      : TIME    := 20.000 ns;

-        tRP       : TIME    := 20.000 ns;

-        tRRD      : TIME    := 15.000 ns;

-        tWR       : TIME    := 15.000 ns;

-        addr_bits : INTEGER := 13;

-        data_bits : INTEGER := 16;

-        cols_bits : INTEGER :=  9

-    );

-    PORT (

-        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');

-        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";

-        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);

-        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);

-        Clk   : IN    STD_LOGIC;

-        Clk_n : IN    STD_LOGIC;

-        Cke   : IN    STD_LOGIC;

-        Cs_n  : IN    STD_LOGIC;

-        Ras_n : IN    STD_LOGIC;

-        Cas_n : IN    STD_LOGIC;

-        We_n  : IN    STD_LOGIC;

-        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)

-    );

-END MT46V16M16;

-

-ARCHITECTURE behave OF MT46V16M16 IS

-    -- Array for Read pipeline

-    TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;

-    TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);

-    TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);

-

-    -- Array for Write pipeline

-    TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;

-    TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);

-    TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);

-

-    -- Array for Auto Precharge

-    TYPE Array_Read_precharge  IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;

-    TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;

-    TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;

-

-    -- Array for Manual Precharge

-    TYPE Array_A10_precharge  IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;

-    TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);

-    TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;

-    

-    -- Array for Burst Terminate

-    TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;

-

-    -- Array for Memory Access

-    TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);

-    TYPE Array_ram_pntr IS ACCESS Array_ram_type;

-    TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;

-

-    -- Data pair

-    SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);

-    SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);

-

-    -- Mode Register

-    SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');

-    

-    -- Command Decode Variables

-    SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';

-    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';

-    

-    -- Burst Length Decode Variables

-    SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';

-    

-    -- Cas Latency Decode Variables

-    SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';

-

-    -- Internal Control Signals

-    SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';

-

-    -- System Clock

-    SIGNAL Sys_clk : STD_LOGIC := '0';

-

-    -- Dqs buffer

-    SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";

-

-BEGIN

-    -- Strip the strength

-    Cs_in  <= To_X01 (Cs_n);

-    Ras_in <= To_X01 (Ras_n);

-    Cas_in <= To_X01 (Cas_n);

-    We_in  <= To_X01 (We_n);

-    

-    -- Commands Decode

-    Active_enable   <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND     We_in;

-    Aref_enable     <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND     We_in;

-    Burst_term      <= NOT(Cs_in) AND     Ras_in  AND     Cas_in  AND NOT(We_in);

-    Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND     Ba(0)  AND NOT(Ba(1));

-    Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));

-    Prech_enable    <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND NOT(We_in);

-    Read_enable     <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND     We_in;

-    Write_enable    <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND NOT(We_in);

-

-    -- Burst Length Decode

-    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);

-    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));

-    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);

-    Burst_length_f  <=    (Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);

-

-    -- CAS Latency Decode

-    Cas_latency_15  <=     Mode_reg(6)  AND NOT(Mode_reg(5)) AND    (Mode_reg(4));

-    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));

-    Cas_latency_25  <=     Mode_reg(6)  AND     Mode_reg(5)  AND NOT(Mode_reg(4));

-    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);

-    Cas_latency_4   <=    (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));

-

-    -- Dqs buffer

-    Dqs <= Dqs_out;

-

-    --

-    -- System Clock

-    --

-    int_clk : PROCESS (Clk, Clk_n)

-        VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';

-    begin

-        IF Clk = '1' AND Clk_n = '0' THEN

-            ClkZ := '1';

-            CkeZ := Cke;

-        ELSIF Clk = '0' AND Clk_n = '1' THEN

-            ClkZ := '0';

-        END IF;

-        Sys_clk <= CkeZ AND ClkZ;

-    END PROCESS;

-

-    --

-    -- Main Process

-    --

-    state_register : PROCESS

-        -- Precharge Variables

-        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';

-

-        -- Activate Variables

-        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';

-

-        -- Data IO variables

-        VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';

-

-        -- Internal address mux variables

-        VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);

-        VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";

-        VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";

-        VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);

-        VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);

-        VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);

-        VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);

-        VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);

-        VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);

-

-        -- DLL Reset variables

-        VARIABLE DLL_enable : STD_LOGIC := '0';

-        VARIABLE DLL_reset : STD_LOGIC := '0';

-        VARIABLE DLL_done : STD_LOGIC := '0';

-        VARIABLE DLL_count : INTEGER := 0;

-        

-        -- Timing Check

-        VARIABLE MRD_chk : TIME := 0 ns;

-        VARIABLE RFC_chk : TIME := 0 ns;

-        VARIABLE RRD_chk : TIME := 0 ns;

-        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;

-        VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;

-        VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;

-        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;

-        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;

-        VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;

-

-        -- Read pipeline variables

-        VARIABLE Read_cmnd : Array_Read_cmnd;

-        VARIABLE Read_bank : Array_Read_bank;

-        VARIABLE Read_cols : Array_Read_cols;

-

-        -- Write pipeline variables

-        VARIABLE Write_cmnd : Array_Write_cmnd;

-        VARIABLE Write_bank : Array_Write_bank;

-        VARIABLE Write_cols : Array_Write_cols;

-

-        -- Auto Precharge variables

-        VARIABLE Read_precharge  : Array_Read_precharge  := ('0' & '0' & '0' & '0');

-        VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');

-        VARIABLE Count_precharge : Array_Count_precharge := ( 0  &  0  &  0  &  0 );

-

-        -- Manual Precharge variables

-        VARIABLE A10_precharge  : Array_A10_precharge;

-        VARIABLE Bank_precharge : Array_Bank_precharge;

-        VARIABLE Cmnd_precharge : Array_Cmnd_precharge;

-

-        -- Burst Terminate variable

-        VARIABLE Cmnd_bst : Array_Cmnd_bst;

-

-        -- Memory Banks

-        VARIABLE Bank0 : Array_ram_stor;

-        VARIABLE Bank1 : Array_ram_stor;

-        VARIABLE Bank2 : Array_ram_stor;

-        VARIABLE Bank3 : Array_ram_stor;

-

-        -- Burst Counter

-        VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);

-

-        -- Internal Dqs initialize

-        VARIABLE Dqs_int : STD_LOGIC := '0';

-

-        -- Data buffer for DM Mask

-        VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');

-

-        --

-        -- Initialize empty rows

-        --

-        PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS

-            VARIABLE i, j : INTEGER := 0;

-        BEGIN

-            IF Bank = "00" THEN

-                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty

-                    Bank0 (Row_index) := NEW Array_ram_type;            -- Open new row for access

-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP           -- Filled row with zeros

-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP

-                            Bank0 (Row_index) (i) (j) := '0';

-                        END LOOP;

-                    END LOOP;

-                END IF;

-            ELSIF Bank = "01" THEN

-                IF Bank1 (Row_index) = NULL THEN

-                    Bank1 (Row_index) := NEW Array_ram_type;

-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP

-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP

-                            Bank1 (Row_index) (i) (j) := '0';

-                        END LOOP;

-                    END LOOP;

-                END IF;

-            ELSIF Bank = "10" THEN

-                IF Bank2 (Row_index) = NULL THEN

-                    Bank2 (Row_index) := NEW Array_ram_type;

-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP

-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP

-                            Bank2 (Row_index) (i) (j) := '0';

-                        END LOOP;

-                    END LOOP;

-                END IF;

-            ELSIF Bank = "11" THEN

-                IF Bank3 (Row_index) = NULL THEN

-                    Bank3 (Row_index) := NEW Array_ram_type;

-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP

-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP

-                            Bank3 (Row_index) (i) (j) := '0';

-                        END LOOP;

-                    END LOOP;

-                END IF;

-            END IF;

-        END;

-

-        --

-        -- Burst Counter

-        --

-        PROCEDURE Burst_decode IS

-            VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');

-        BEGIN

-            -- Advance burst counter

-            Burst_counter := Burst_counter + 1;

-

-            -- Burst Type

-            IF Mode_reg (3) = '0' THEN

-                Cols_temp := Cols_addr + 1;

-            ELSIF Mode_reg (3) = '1' THEN

-                Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);

-                Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);

-                Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);

-            END IF;

-

-            -- Burst Length

-            IF Burst_length_2 = '1' THEN

-                Cols_addr (0) := Cols_temp (0);

-            ELSIF Burst_length_4 = '1' THEN

-                Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);

-            ELSIF Burst_length_8 = '1' THEN

-                Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);

-            ELSE

-                Cols_addr := Cols_temp;

-            END IF;

-

-            -- Data counter

-            IF Burst_length_2 = '1' THEN

-                IF Burst_counter >= 2 THEN

-                    IF Data_in_enable = '1' THEN

-                        Data_in_enable := '0';

-                    ELSIF Data_out_enable = '1' THEN

-                        Data_out_enable := '0';

-                    END IF;

-                END IF;

-            ELSIF Burst_length_4 = '1' THEN

-                IF Burst_counter >= 4 THEN

-                    IF Data_in_enable = '1' THEN

-                        Data_in_enable := '0';

-                    ELSIF Data_out_enable = '1' THEN

-                        Data_out_enable := '0';

-                    END IF;

-                END IF;

-            ELSIF Burst_length_8 = '1' THEN

-                IF Burst_counter >= 8 THEN

-                    IF Data_in_enable = '1' THEN

-                        Data_in_enable := '0';

-                    ELSIF Data_out_enable = '1' THEN

-                        Data_out_enable := '0';

-                    END IF;

-                END IF;

-            END IF;

-        END;

-

-    BEGIN

-        WAIT ON Sys_clk;

-

-        --

-        -- Manual Precharge Pipeline

-        --

-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN

-            -- A10 Precharge Pipeline

-            A10_precharge(0) := A10_precharge(1);

-            A10_precharge(1) := A10_precharge(2);

-            A10_precharge(2) := A10_precharge(3);

-            A10_precharge(3) := A10_precharge(4);

-            A10_precharge(4) := A10_precharge(5);

-            A10_precharge(5) := A10_precharge(6);

-            A10_precharge(6) := A10_precharge(7);

-            A10_precharge(7) := A10_precharge(8);

-            A10_precharge(8) := '0';

-

-            -- Bank Precharge Pipeline

-            Bank_precharge(0) := Bank_precharge(1);

-            Bank_precharge(1) := Bank_precharge(2);

-            Bank_precharge(2) := Bank_precharge(3);

-            Bank_precharge(3) := Bank_precharge(4);

-            Bank_precharge(4) := Bank_precharge(5);

-            Bank_precharge(5) := Bank_precharge(6);

-            Bank_precharge(6) := Bank_precharge(7);

-            Bank_precharge(7) := Bank_precharge(8);

-            Bank_precharge(8) := "00";

-

-            -- Command Precharge Pipeline

-            Cmnd_precharge(0) := Cmnd_precharge(1);

-            Cmnd_precharge(1) := Cmnd_precharge(2);

-            Cmnd_precharge(2) := Cmnd_precharge(3);

-            Cmnd_precharge(3) := Cmnd_precharge(4);

-            Cmnd_precharge(4) := Cmnd_precharge(5);

-            Cmnd_precharge(5) := Cmnd_precharge(6);

-            Cmnd_precharge(6) := Cmnd_precharge(7);

-            Cmnd_precharge(7) := Cmnd_precharge(8);

-            Cmnd_precharge(8) := '0';

-

-            -- Terminate Read if same bank or all banks

-            IF ((Cmnd_precharge (0) = '1') AND

-                (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND

-                (Data_out_enable = '1')) THEN

-                Data_out_enable := '0';

-            END IF;

-        END IF;

-

-        --

-        -- Burst Terminate Pipeline

-        --

-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN

-            -- Burst Terminate pipeline

-            Cmnd_bst (0) := Cmnd_bst (1);

-            Cmnd_bst (1) := Cmnd_bst (2);

-            Cmnd_bst (2) := Cmnd_bst (3);

-            Cmnd_bst (3) := Cmnd_bst (4);

-            Cmnd_bst (4) := Cmnd_bst (5);

-            Cmnd_bst (5) := Cmnd_bst (6);

-            Cmnd_bst (6) := Cmnd_bst (7);

-            Cmnd_bst (7) := Cmnd_bst (8);

-            Cmnd_bst (8) := '0';

-

-            -- Terminate current Read

-            IF ((Cmnd_bst  (0) = '1') AND (Data_out_enable = '1')) THEN

-                Data_out_enable := '0';

-            END IF;

-        END IF;

-

-        --

-        -- Dq and Dqs Drivers

-        --

-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN

-            -- Read Command Pipeline

-            Read_cmnd (0) := Read_cmnd (1);

-            Read_cmnd (1) := Read_cmnd (2);

-            Read_cmnd (2) := Read_cmnd (3);

-            Read_cmnd (3) := Read_cmnd (4);

-            Read_cmnd (4) := Read_cmnd (5);

-            Read_cmnd (5) := Read_cmnd (6);

-            Read_cmnd (6) := Read_cmnd (7);

-            Read_cmnd (7) := Read_cmnd (8);

-            Read_cmnd (8) := '0';

-

-            -- Read Bank Pipeline

-            Read_bank (0) := Read_bank (1);

-            Read_bank (1) := Read_bank (2);

-            Read_bank (2) := Read_bank (3);

-            Read_bank (3) := Read_bank (4);

-            Read_bank (4) := Read_bank (5);

-            Read_bank (5) := Read_bank (6);

-            Read_bank (6) := Read_bank (7);

-            Read_bank (7) := Read_bank (8);

-            Read_bank (8) := "00";

-

-            -- Read Column Pipeline

-            Read_cols (0) := Read_cols (1);

-            Read_cols (1) := Read_cols (2);

-            Read_cols (2) := Read_cols (3);

-            Read_cols (3) := Read_cols (4);

-            Read_cols (4) := Read_cols (5);

-            Read_cols (5) := Read_cols (6);

-            Read_cols (6) := Read_cols (7);

-            Read_cols (7) := Read_cols (8);

-            Read_cols (8) := (OTHERS => '0');

-

-            -- Initialize Read command

-            IF Read_cmnd (0) = '1' THEN

-                Data_out_enable := '1';

-                Bank_addr := Read_bank (0);

-                Cols_addr := Read_cols (0);

-                Cols_brst := Cols_addr (2 DOWNTO 0);

-                Burst_counter := (OTHERS => '0');

-

-                -- Row address mux

-                CASE Bank_addr IS

-                    WHEN "00"   => Rows_addr := B0_row_addr;

-                    WHEN "01"   => Rows_addr := B1_row_addr;

-                    WHEN "10"   => Rows_addr := B2_row_addr;

-                    WHEN OTHERS => Rows_addr := B3_row_addr;

-                END CASE;

-            END IF;

-

-            -- Toggle Dqs during Read command

-            IF Data_out_enable = '1' THEN

-                Dqs_int := '0';

-                IF Dqs_out = "00" THEN

-                    Dqs_out <= "11";

-                ELSIF Dqs_out = "11" THEN

-                    Dqs_out <= "00";

-                ELSE

-                    Dqs_out <= "00";

-                END IF;

-            ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN

-                Dqs_out <= "ZZ";

-            END IF;

-

-            -- Initialize Dqs for Read command

-            IF Read_cmnd (2) = '1' THEN

-                IF Data_out_enable = '0' THEN

-                    Dqs_int := '1';

-                    Dqs_out <= "00";

-                END IF;

-            END IF;

-

-            -- Read Latch

-            IF Data_out_enable = '1' THEN

-                -- Initialize Memory

-                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));

-                

-                -- Output Data

-                CASE Bank_addr IS

-                    WHEN "00"   => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                    WHEN "01"   => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                    WHEN "10"   => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                    WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                END CASE;

-

-                --  Increase Burst Counter

-                Burst_decode;

-            ELSE

-                Dq <= (OTHERS => 'Z');

-            END IF;

-        END IF;

-

-        --

-        -- Write FIFO and DM Mask Logic

-        --

-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN

-            -- Write command pipeline

-            Write_cmnd (0) := Write_cmnd (1);

-            Write_cmnd (1) := Write_cmnd (2);

-            Write_cmnd (2) := '0';

-

-            -- Write command pipeline

-            Write_bank (0) := Write_bank (1);

-            Write_bank (1) := Write_bank (2);

-            Write_bank (2) := "00";

-

-            -- Write column pipeline

-            Write_cols (0) := Write_cols (1);

-            Write_cols (1) := Write_cols (2);

-            Write_cols (2) := (OTHERS => '0');

-

-            -- Initialize Write command

-            IF Write_cmnd (0) = '1' THEN

-                Data_in_enable := '1';

-                Bank_addr := Write_bank (0);

-                Cols_addr := Write_cols (0);

-                Cols_brst := Cols_addr (2 DOWNTO 0);

-                Burst_counter := (OTHERS => '0');

-

-                -- Row address mux

-                CASE Bank_addr IS

-                    WHEN "00"   => Rows_addr := B0_row_addr;

-                    WHEN "01"   => Rows_addr := B1_row_addr;

-                    WHEN "10"   => Rows_addr := B2_row_addr;

-                    WHEN OTHERS => Rows_addr := B3_row_addr;

-                END CASE;

-            END IF;

-

-            -- Write data

-            IF Data_in_enable = '1' THEN

-                -- Initialize memory

-                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));

-                

-                -- Write first data

-                IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN

-                    -- Data Buffer

-                    CASE Bank_addr IS

-                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                    END CASE;

-

-                    -- Perform DM Mask

-                    IF Dm_pair (0) = '0' THEN

-                        Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);

-                    END IF;

-                    IF Dm_pair (1) = '0' THEN

-                        Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);

-                    END IF;

-

-                    -- Write Data

-                    CASE Bank_addr IS

-                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;

-                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;

-                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;

-                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;

-                    END CASE;

-                END IF;

-

-                --  Increase Burst Counter

-                Burst_decode;

-

-                -- Write second data

-                IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN

-                    -- Data Buffer

-                    CASE Bank_addr IS

-                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));

-                    END CASE;

-

-                    -- Perform DM Mask

-                    IF Dm_pair (2) = '0' THEN

-                        Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);

-                    END IF;

-                    IF Dm_pair (3) = '0' THEN

-                        Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);

-                    END IF;

-

-                    -- Write Data

-                    CASE Bank_addr IS

-                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;

-                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;

-                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;

-                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;

-                    END CASE;

-                END IF;

-                

-                -- Increase Burst Counter

-                Burst_decode;

-

-                -- tWR start and tWTR check

-                IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN

-                    CASE Bank_addr IS

-                        WHEN "00"   => WR_chk0 := NOW;

-                        WHEN "01"   => WR_chk1 := NOW;

-                        WHEN "10"   => WR_chk2 := NOW;

-                        WHEN OTHERS => WR_chk3 := NOW;

-                    END CASE;

-

-                    -- tWTR check

-                    ASSERT (Read_enable = '0')

-                        REPORT "tWTR violation during Read"

-                        SEVERITY WARNING;

-                END IF;

-            END IF;

-        END IF;

-

-        --

-        -- Auto Precharge Calculation

-        --

-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN

-            -- Precharge counter

-            IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN

-                Count_precharge (0) := Count_precharge (0) + 1;

-            END IF;

-            IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN

-                Count_precharge (1) := Count_precharge (1) + 1;

-            END IF;

-            IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN

-                Count_precharge (2) := Count_precharge (2) + 1;

-            END IF;

-            IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN

-                Count_precharge (3) := Count_precharge (3) + 1;

-            END IF;

-

-            -- Read with AutoPrecharge Calculation

-            --      The device start internal precharge when:

-            --          1.  Meet tRAS requirement

-            --          2.  BL/2 cycles after command

-            IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN

-                IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1)  OR

-                    (Burst_length_4 = '1' AND Count_precharge(0) >= 2)  OR

-                    (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN

-                    Pc_b0 := '1';

-                    Act_b0 := '0';

-                    RP_chk0 := NOW;

-                    Read_precharge(0) := '0';

-                END IF;

-            END IF;

-            IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN

-                IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1)  OR

-                    (Burst_length_4 = '1' AND Count_precharge(1) >= 2)  OR

-                    (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN

-                    Pc_b1 := '1';

-                    Act_b1 := '0';

-                    RP_chk1 := NOW;

-                    Read_precharge(1) := '0';

-                END IF;

-            END IF;

-            IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN

-                IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1)  OR

-                    (Burst_length_4 = '1' AND Count_precharge(2) >= 2)  OR

-                    (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN

-                    Pc_b2 := '1';

-                    Act_b2 := '0';

-                    RP_chk2 := NOW;

-                    Read_precharge(2) := '0';

-                END IF;

-            END IF;

-            IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN

-                IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1)  OR

-                    (Burst_length_4 = '1' AND Count_precharge(3) >= 2)  OR

-                    (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN

-                    Pc_b3 := '1';

-                    Act_b3 := '0';

-                    RP_chk3 := NOW;

-                    Read_precharge(3) := '0';

-                END IF;

-            END IF;

-

-            -- Write with AutoPrecharge Calculation

-            --      The device start internal precharge when:

-            --          1.  Meet tRAS requirement

-            --          2.  Two clock after last burst

-            -- Since tWR is time base, the model will compensate tRP

-            IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN

-                IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR

-                    (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR

-                    (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN

-                    Pc_b0 := '1';

-                    Act_b0 := '0';

-                    RP_chk0 := NOW - ((2 * tCK) - tWR);

-                    Write_precharge(0) := '0';

-                END IF;

-            END IF;

-            IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN

-                IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR

-                    (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR

-                    (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN

-                    Pc_b1 := '1';

-                    Act_b1 := '0';

-                    RP_chk1 := NOW - ((2 * tCK) - tWR);

-                    Write_precharge(1) := '0';

-                END IF;

-            END IF;

-            IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN

-                IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR

-                    (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR

-                    (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN

-                    Pc_b2 := '1';

-                    Act_b2 := '0';

-                    RP_chk2 := NOW - ((2 * tCK) - tWR);

-                    Write_precharge(2) := '0';

-                END IF;

-            END IF;

-            IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN

-                IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR

-                    (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR

-                    (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN

-                    Pc_b3 := '1';

-                    Act_b3 := '0';

-                    RP_chk3 := NOW - ((2 * tCK) - tWR);

-                    Write_precharge(3) := '0';

-                END IF;

-            END IF;

-        END IF;

-        

-        --

-        -- DLL Counter

-        --

-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN

-            IF (DLL_Reset = '1' AND DLL_done = '0') THEN

-                DLL_count := DLL_count + 1;

-                IF (DLL_count >= 200) THEN

-                    DLL_done := '1';

-                END IF;

-            END IF;

-        END IF;

-

-        --

-        -- Control Logic

-        --

-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN

-            -- Auto Refresh

-            IF Aref_enable = '1' THEN

-                -- Auto Refresh to Auto Refresh

-                ASSERT (NOW - RFC_chk >= tRFC)

-                    REPORT "tRFC violation during Auto Refresh"

-                    SEVERITY WARNING;

-

-                -- Precharge to Auto Refresh

-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND

-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))

-                    REPORT "tRP violation during Auto Refresh"

-                    SEVERITY WARNING;

-

-                -- Precharge to Auto Refresh

-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')

-                    REPORT "All banks must be Precharge before Auto Refresh"

-                    SEVERITY WARNING;

-

-                -- Record current tRFC time

-                RFC_chk := NOW;

-            END IF;

-

-            -- Extended Load Mode Register

-            IF Ext_mode_enable = '1' THEN

-                IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN

-                    IF (Addr (0) = '0') THEN

-                        DLL_enable := '1';

-                    ELSE

-                        DLL_enable := '0';

-                    END IF;

-                END IF;

-                

-                -- Precharge to EMR

-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')

-                    REPORT "All bank must be Precharged before Extended Mode Register"

-                    SEVERITY WARNING;

-                

-                -- Precharge to EMR

-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND

-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))

-                    REPORT "tRP violation during Extended Load Register"

-                    SEVERITY WARNING;

-

-                -- LMR/EMR to EMR

-                ASSERT (NOW - MRD_chk >= tMRD)

-                    REPORT "tMRD violation during Extended Mode Register"

-                    SEVERITY WARNING;

-

-                -- Record current tMRD time

-                MRD_chk := NOW;

-            END IF;

-

-            -- Load Mode Register

-            IF Mode_reg_enable = '1' THEN

-                -- Register mode

-                Mode_reg <= Addr;

-                

-                -- DLL Reset

-                IF (DLL_enable = '1' AND Addr (8) = '1') THEN

-                    DLL_reset := '1';

-                    DLL_done  := '0';

-                    DLL_count := 0;

-                ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN

-                    ASSERT (FALSE)

-                        REPORT "DLL is ENABLE: DLL RESET is require"

-                        SEVERITY WARNING;

-                ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN

-                    ASSERT (FALSE)

-                        REPORT "DLL is DISABLE: DLL RESET will be ignored"

-                        SEVERITY WARNING;

-                END IF;

-

-                -- Precharge to LMR

-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')

-                    REPORT "All bank must be Precharged before Load Mode Register"

-                    SEVERITY WARNING;

-

-                -- Precharge to EMR

-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND

-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))

-                    REPORT "tRP violation during Load Mode Register"

-                    SEVERITY WARNING;

-

-                -- LMR/ELMR to LMR

-                ASSERT (NOW - MRD_chk >= tMRD)

-                    REPORT "tMRD violation during Load Mode Register"

-                    SEVERITY WARNING;

-

-                -- Check for invalid Burst Length

-                ASSERT ((Addr (2 DOWNTO 0) = "001") OR      -- BL = 2

-                        (Addr (2 DOWNTO 0) = "010") OR      -- BL = 4

-                        (Addr (2 DOWNTO 0) = "011"))        -- BL = 8

-                    REPORT "Invalid Burst Length during Load Mode Register"

-                    SEVERITY WARNING;

-

-                -- Check for invalid CAS Latency

-                ASSERT ((Addr (6 DOWNTO 4) = "010") OR      -- CL = 2.0

-                        (Addr (6 DOWNTO 4) = "110"))        -- CL = 2.5

-                    REPORT "Invalid CAS Latency during Load Mode Register"

-                    SEVERITY WARNING;

-

-                -- Record current tMRD time

-                MRD_chk := NOW;

-            END IF;

-

-            -- Active Block (latch Bank and Row Address)

-            IF Active_enable = '1' THEN

-                -- Activate an OPEN bank can corrupt data

-                ASSERT ((Ba = "00" AND Act_b0 = '0') OR

-                        (Ba = "01" AND Act_b1 = '0') OR

-                        (Ba = "10" AND Act_b2 = '0') OR

-                        (Ba = "11" AND Act_b3 = '0'))

-                    REPORT "Bank is already activated - data can be corrupted"

-                    SEVERITY WARNING;

-

-                -- Activate Bank 0

-                IF Ba = "00" AND Pc_b0 = '1' THEN

-                    -- Activate to Activate (same bank)

-                    ASSERT (NOW - RC_chk0 >= tRC)

-                        REPORT "tRC violation during Activate Bank 0"

-                        SEVERITY WARNING;

-

-                    -- Precharge to Active

-                    ASSERT (NOW - RP_chk0 >= tRP)

-                        REPORT "tRP violation during Activate Bank 0"

-                        SEVERITY WARNING;

-

-                    -- Record Variables for checking violation

-                    Act_b0 := '1';

-                    Pc_b0 := '0';

-                    B0_row_addr := Addr;

-                    RC_chk0 := NOW;

-                    RCD_chk0 := NOW;

-                    RAS_chk0 := NOW;

-                    RAP_chk0 := NOW;

-                END IF;

-

-                -- Activate Bank 1

-                IF Ba = "01" AND Pc_b1 = '1' THEN

-                    -- Activate to Activate (same bank)

-                    ASSERT (NOW - RC_chk1 >= tRC)

-                        REPORT "tRC violation during Activate Bank 1"

-                        SEVERITY WARNING;

-

-                    -- Precharge to Active

-                    ASSERT (NOW - RP_chk1 >= tRP)

-                        REPORT "tRP violation during Activate Bank 1"

-                        SEVERITY WARNING;

-

-                    -- Record Variables for checking violation

-                    Act_b1 := '1';

-                    Pc_b1 := '0';

-                    B1_row_addr := Addr;

-                    RC_chk1 := NOW;

-                    RCD_chk1 := NOW;

-                    RAS_chk1 := NOW;

-                    RAP_chk1 := NOW;

-                END IF;

-

-                -- Activate Bank 2

-                IF Ba = "10" AND Pc_b2 = '1' THEN

-                    -- Activate to Activate (same bank)

-                    ASSERT (NOW - RC_chk2 >= tRC)

-                        REPORT "tRC violation during Activate Bank 2"

-                        SEVERITY WARNING;

-

-                    -- Precharge to Active

-                    ASSERT (NOW - RP_chk2 >= tRP)

-                        REPORT "tRP violation during Activate Bank 2"

-                        SEVERITY WARNING;

-

-                    -- Record Variables for checking violation

-                    Act_b2 := '1';

-                    Pc_b2 := '0';

-                    B2_row_addr := Addr;

-                    RC_chk2 := NOW;

-                    RCD_chk2 := NOW;

-                    RAS_chk2 := NOW;

-                    RAP_chk2 := NOW;

-                END IF;

-

-                -- Activate Bank 3

-                IF Ba = "11" AND Pc_b3 = '1' THEN

-                    -- Activate to Activate (same bank)

-                    ASSERT (NOW - RC_chk3 >= tRC)

-                        REPORT "tRC violation during Activate Bank 3"

-                        SEVERITY WARNING;

-

-                    -- Precharge to Active

-                    ASSERT (NOW - RP_chk3 >= tRP)

-                        REPORT "tRP violation during Activate Bank 3"

-                        SEVERITY WARNING;

-

-                    -- Record Variables for checking violation

-                    Act_b3 := '1';

-                    Pc_b3 := '0';

-                    B3_row_addr := Addr;

-                    RC_chk3 := NOW;

-                    RCD_chk3 := NOW;

-                    RAS_chk3 := NOW;

-                    RAP_chk3 := NOW;

-                END IF;

-

-                -- Activate Bank A to Activate Bank B

-                IF (Prev_bank /= Ba) THEN

-                    ASSERT (NOW - RRD_chk >= tRRD)

-                        REPORT "tRRD violation during Activate"

-                        SEVERITY WARNING;

-                END IF;

-                

-                -- AutoRefresh to Activate

-                ASSERT (NOW - RFC_chk >= tRFC)

-                    REPORT "tRFC violation during Activate"

-                    SEVERITY WARNING;

-                

-                -- Record Variables for Checking Violation

-                RRD_chk := NOW;

-                Prev_bank := Ba;

-            END IF;

-

-            -- Precharge Block - Consider NOP if bank already precharged or in process of precharging

-            IF Prech_enable = '1' THEN

-                -- EMR or LMR to Precharge

-                ASSERT (NOW - MRD_chk >= tMRD)

-                    REPORT "tMRD violation during Precharge"

-                    SEVERITY WARNING;

-

-                -- Precharge Bank 0

-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN

-                    Act_b0 := '0';

-                    Pc_b0 := '1';

-                    RP_chk0 := NOW;

-

-                    -- Activate to Precharge bank 0

-                    ASSERT (NOW - RAS_chk0 >= tRAS)

-                        REPORT "tRAS violation during Precharge"

-                        SEVERITY WARNING;

-

-                    -- tWR violation check for Write

-                    ASSERT (NOW - WR_chk0 >= tWR)

-                        REPORT "tWR violation during Precharge"

-                        SEVERITY WARNING;

-                END IF;

-

-                -- Precharge Bank 1

-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN

-                    Act_b1 := '0';

-                    Pc_b1 := '1';

-                    RP_chk1 := NOW;

-

-                    -- Activate to Precharge

-                    ASSERT (NOW - RAS_chk1 >= tRAS)

-                        REPORT "tRAS violation during Precharge"

-                        SEVERITY WARNING;

-

-                    -- tWR violation check for Write

-                    ASSERT (NOW - WR_chk1 >= tWR)

-                        REPORT "tWR violation during Precharge"

-                        SEVERITY WARNING;

-                END IF;

-

-                -- Precharge Bank 2

-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN

-                    Act_b2 := '0';

-                    Pc_b2 := '1';

-                    RP_chk2 := NOW;

-

-                    -- Activate to Precharge

-                    ASSERT (NOW - RAS_chk2 >= tRAS)

-                        REPORT "tRAS violation during Precharge"

-                        SEVERITY WARNING;

-

-                    -- tWR violation check for Write

-                    ASSERT (NOW - WR_chk2 >= tWR)

-                        REPORT "tWR violation during Precharge"

-                        SEVERITY WARNING;

-                END IF;

-

-                -- Precharge Bank 3

-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN

-                    Act_b3 := '0';

-                    Pc_b3 := '1';

-                    RP_chk3 := NOW;

-

-                    -- Activate to Precharge

-                    ASSERT (NOW - RAS_chk3 >= tRAS)

-                        REPORT "tRAS violation during Precharge"

-                        SEVERITY WARNING;

-

-                    -- tWR violation check for Write

-                    ASSERT (NOW - WR_chk3 >= tWR)

-                        REPORT "tWR violation during Precharge"

-                        SEVERITY WARNING;

-                END IF;

-

-                -- Pipeline for READ

-                IF CAS_latency_15 = '1' THEN

-                    A10_precharge  (3) := Addr(10);

-                    Bank_precharge (3) := Ba;

-                    Cmnd_precharge (3) := '1';

-                ELSIF CAS_latency_2 = '1' THEN

-                    A10_precharge  (4) := Addr(10);

-                    Bank_precharge (4) := Ba;

-                    Cmnd_precharge (4) := '1';

-                ELSIF CAS_latency_25 = '1' THEN

-                    A10_precharge  (5) := Addr(10);

-                    Bank_precharge (5) := Ba;

-                    Cmnd_precharge (5) := '1';

-                ELSIF CAS_latency_3 = '1' THEN

-                    A10_precharge  (6) := Addr(10);

-                    Bank_precharge (6) := Ba;

-                    Cmnd_precharge (6) := '1';

-                ELSIF CAS_latency_4 = '1' THEN

-                    A10_precharge  (8) := Addr(10);

-                    Bank_precharge (8) := Ba;

-                    Cmnd_precharge (8) := '1';

-                END IF;

-            END IF;

-

-            -- Burst Terminate

-            IF Burst_term = '1' THEN

-                -- Pipeline for Read

-                IF CAS_latency_15 = '1' THEN

-                    Cmnd_bst (3) := '1';

-                ELSIF CAS_latency_2 = '1' THEN

-                    Cmnd_bst (4) := '1';

-                ELSIF CAS_latency_25 = '1' THEN

-                    Cmnd_bst (5) := '1';

-                ELSIF CAS_latency_3 = '1' THEN

-                    Cmnd_bst (6) := '1';

-                ELSIF CAS_latency_4 = '1' THEN

-                    Cmnd_bst (8) := '1';

-                END IF;

-

-                -- Terminate Write

-                ASSERT (Data_in_enable = '0')

-                    REPORT "It's illegal to Burst Terminate a Write"

-                    SEVERITY WARNING;

-

-                -- Terminate Read with Auto Precharge

-                ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND

-                        Read_precharge (2) = '0' AND Read_precharge (3) = '0')

-                    REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"

-                    SEVERITY WARNING;

-            END IF;

-

-            -- Read Command

-            IF Read_enable = '1' THEN

-                -- CAS Latency Pipeline

-                IF Cas_latency_15 = '1' THEN

-                    Read_cmnd (3) := '1';

-                    Read_bank (3) := Ba;

-                    Read_cols (3) := Addr (8 DOWNTO 0);

-                ELSIF Cas_latency_2 = '1' THEN

-                    Read_cmnd (4) := '1';

-                    Read_bank (4) := Ba;

-                    Read_cols (4) := Addr (8 DOWNTO 0);

-                ELSIF Cas_latency_25 = '1' THEN

-                    Read_cmnd (5) := '1';

-                    Read_bank (5) := Ba;

-                    Read_cols (5) := Addr (8 DOWNTO 0);

-                ELSIF Cas_latency_3 = '1' THEN

-                    Read_cmnd (6) := '1';

-                    Read_bank (6) := Ba;

-                    Read_cols (6) := Addr (8 DOWNTO 0);

-                ELSIF Cas_latency_4 = '1' THEN

-                    Read_cmnd (8) := '1';

-                    Read_bank (8) := Ba;

-                    Read_cols (8) := Addr (8 DOWNTO 0);

-                END IF;

-

-                -- Write to Read: Terminate Write Immediately

-                IF Data_in_enable = '1' THEN

-                    Data_in_enable := '0';

-                END IF;

-

-                -- Interrupting a Read with Auto Precharge (same bank only)

-                ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')

-                    REPORT "It's illegal to interrupt a Read with Auto Precharge"

-                    SEVERITY WARNING;

-

-                -- Activate to Read

-                ASSERT ((Ba = "00" AND Act_b0 = '1') OR

-                        (Ba = "01" AND Act_b1 = '1') OR

-                        (Ba = "10" AND Act_b2 = '1') OR

-                        (Ba = "11" AND Act_b3 = '1'))

-                    REPORT "Bank is not Activated for Read"

-                    SEVERITY WARNING;

-

-                -- Activate to Read without Auto Precharge

-                IF Addr (10) = '0' THEN

-                    ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR

-                            (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR

-                            (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR

-                            (Ba = "11" AND NOW - RCD_chk3 >= tRCD))

-                        REPORT "tRCD violation during Read"

-                        SEVERITY WARNING;

-                END IF;

-

-                -- Activate to Read with Auto Precharge

-                IF Addr (10) = '1' THEN

-                    ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR

-                            (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR

-                            (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR

-                            (Ba = "11" AND NOW - RAP_chk3 >= tRAP))

-                        REPORT "tRAP violation during Read"

-                        SEVERITY WARNING;

-                END IF;

-

-                -- Auto precharge

-                IF Addr (10) = '1' THEN

-                    Read_precharge (Conv_INTEGER(Ba)) := '1';

-                    Count_precharge (Conv_INTEGER(Ba)) := 0;

-                END IF;

-

-                -- DLL Check

-                IF (DLL_reset = '1') THEN

-                    ASSERT (DLL_done = '1')

-                        REPORT "DLL RESET not complete"

-                        SEVERITY WARNING;

-                END IF;

-            END IF;

-

-            -- Write Command

-            IF Write_enable = '1' THEN

-                -- Pipeline for Write

-                Write_cmnd (2) := '1';

-                Write_bank (2) := Ba;

-                Write_cols (2) := Addr (8 DOWNTO 0);

-

-                -- Interrupting a Write with Auto Precharge (same bank only)

-                ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')

-                    REPORT "It's illegal to interrupt a Write with Auto Precharge"

-                    SEVERITY WARNING;

-

-                -- Activate to Write

-                ASSERT ((Ba = "00" AND Act_b0 = '1') OR

-                        (Ba = "01" AND Act_b1 = '1') OR

-                        (Ba = "10" AND Act_b2 = '1') OR

-                        (Ba = "11" AND Act_b3 = '1'))

-                    REPORT "Bank is not Activated for Write"

-                    SEVERITY WARNING;

-

-                -- Activate to Write

-                ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR

-                        (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR

-                        (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR

-                        (Ba = "11" AND NOW - RCD_chk3 >= tRCD))

-                    REPORT "tRCD violation during Write"

-                    SEVERITY WARNING;

-

-                -- Auto precharge

-                IF Addr (10) = '1' THEN

-                    Write_precharge (Conv_INTEGER(Ba)) := '1';

-                    Count_precharge (Conv_INTEGER(Ba)) := 0;

-                END IF;

-            END IF;

-        END IF;

-    END PROCESS;

-

-    --

-    -- Dqs Receiver

-    --

-    dqs_rcvrs : PROCESS

-        VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);

-        VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);

-    BEGIN

-        WAIT ON Dqs;

-        -- Latch data at posedge Dqs

-        IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN

-            Dq_temp := Dq;

-            Dm_temp := Dm;

-        END IF;

-        -- Latch data at negedge Dqs

-        IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN

-            Dq_pair <= (Dq & Dq_temp);

-            Dm_pair <= (Dm & Dm_temp);

-        END IF;

-    END PROCESS;

-

-    --

-    -- Setup timing checks

-    --

-    Setup_check : PROCESS

-    BEGIN

-        WAIT ON Sys_clk;

-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN

-            ASSERT(Cke'LAST_EVENT >= tIS)

-                REPORT "CKE Setup time violation -- tIS"

-                SEVERITY WARNING;

-            ASSERT(Cs_n'LAST_EVENT >= tIS)

-                REPORT "CS# Setup time violation -- tIS"

-                SEVERITY WARNING;

-            ASSERT(Cas_n'LAST_EVENT >= tIS)

-                REPORT "CAS# Setup time violation -- tIS"

-                SEVERITY WARNING;

-            ASSERT(Ras_n'LAST_EVENT >= tIS)

-                REPORT "RAS# Setup time violation -- tIS"

-                SEVERITY WARNING;

-            ASSERT(We_n'LAST_EVENT >= tIS)

-                REPORT "WE# Setup time violation -- tIS"

-                SEVERITY WARNING;

-            ASSERT(Addr'LAST_EVENT >= tIS)

-                REPORT "ADDR Setup time violation -- tIS"

-                SEVERITY WARNING;

-            ASSERT(Ba'LAST_EVENT >= tIS)

-                REPORT "BA Setup time violation -- tIS"

-                SEVERITY WARNING;

-        END IF;   

-    END PROCESS;

-

-    --

-    -- Hold timing checks

-    --

-    Hold_check : PROCESS

-    BEGIN

-        WAIT ON Sys_clk'DELAYED (tIH);

-        IF Sys_clk'DELAYED (tIH) = '1' THEN

-            ASSERT(Cke'LAST_EVENT >= tIH)

-                REPORT "CKE Hold time violation -- tIH"

-                SEVERITY WARNING;

-            ASSERT(Cs_n'LAST_EVENT >= tIH)

-                REPORT "CS# Hold time violation -- tIH"

-                SEVERITY WARNING;

-            ASSERT(Cas_n'LAST_EVENT >= tIH)

-                REPORT "CAS# Hold time violation -- tIH"

-                SEVERITY WARNING;

-            ASSERT(Ras_n'LAST_EVENT >= tIH)

-                REPORT "RAS# Hold time violation -- tIH"

-                SEVERITY WARNING;

-            ASSERT(We_n'LAST_EVENT >= tIH)

-                REPORT "WE# Hold time violation -- tIH"

-                SEVERITY WARNING;

-            ASSERT(Addr'LAST_EVENT >= tIH)

-                REPORT "ADDR Hold time violation -- tIH"

-                SEVERITY WARNING;

-            ASSERT(Ba'LAST_EVENT >= tIH)

-                REPORT "BA Hold time violation -- tIH"

-                SEVERITY WARNING;

-        END IF;   

-    END PROCESS;

-

-END behave;

+-----------------------------------------------------------------------------------------
+--
+--     File Name: MT46V16M16.VHD
+--       Version: 2.1
+--          Date: January 14th, 2002
+--         Model: Behavioral
+--     Simulator: NCDesktop      - http://www.cadence.com
+--                ModelSim PE    - http://www.model.com
+--
+--  Dependencies: None
+--
+--        Author: Son P. Huynh
+--         Email: sphuynh@micron.com
+--         Phone: (208) 368-3825
+--       Company: Micron Technology, Inc.
+--   Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
+--
+--   Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
+--
+--    Limitation: Doesn't model internal refresh counter
+--
+--          Note: 
+--
+--    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
+--                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
+--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+--
+--                Copyright (c) 1998 Micron Semiconductor Products, Inc.
+--                All rights researved
+--
+--  Rev  Author                        Date        Changes
+--  ---  ----------------------------  ----------  -------------------------------------
+--  2.1  Son P. Huynh                  01/14/2002  - Fix Burst_counter
+--       Micron Technology, Inc.
+--
+--  2.0  Son P. Huynh                  11/08/2001  - Second release
+--       Micron Technology, Inc.                   - Rewrote and remove SHARED VARIABLE
+--
+-----------------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+    USE IEEE.STD_LOGIC_1164.ALL;
+    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+    USE IEEE.STD_LOGIC_ARITH.ALL;
+
+ENTITY MT46V16M16 IS
+    GENERIC (                                   -- Timing for -75Z CL2
+        tCK       : TIME    :=  7.500 ns;
+        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tDH       : TIME    :=  0.500 ns;
+        tDS       : TIME    :=  0.500 ns;
+        tIH       : TIME    :=  0.900 ns;
+        tIS       : TIME    :=  0.900 ns;
+        tMRD      : TIME    := 15.000 ns;
+        tRAS      : TIME    := 40.000 ns;
+        tRAP      : TIME    := 20.000 ns;
+        tRC       : TIME    := 65.000 ns;
+        tRFC      : TIME    := 75.000 ns;
+        tRCD      : TIME    := 20.000 ns;
+        tRP       : TIME    := 20.000 ns;
+        tRRD      : TIME    := 15.000 ns;
+        tWR       : TIME    := 15.000 ns;
+        addr_bits : INTEGER := 13;
+        data_bits : INTEGER := 16;
+        cols_bits : INTEGER :=  9
+    );
+    PORT (
+        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
+        Clk   : IN    STD_LOGIC;
+        Clk_n : IN    STD_LOGIC;
+        Cke   : IN    STD_LOGIC;
+        Cs_n  : IN    STD_LOGIC;
+        Ras_n : IN    STD_LOGIC;
+        Cas_n : IN    STD_LOGIC;
+        We_n  : IN    STD_LOGIC;
+        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
+    );
+END MT46V16M16;
+
+ARCHITECTURE behave OF MT46V16M16 IS
+    -- Array for Read pipeline
+    TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+    TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+    -- Array for Write pipeline
+    TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+    TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+    -- Array for Auto Precharge
+    TYPE Array_Read_precharge  IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
+
+    -- Array for Manual Precharge
+    TYPE Array_A10_precharge  IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+    TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+    
+    -- Array for Burst Terminate
+    TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+
+    -- Array for Memory Access
+    TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+    TYPE Array_ram_pntr IS ACCESS Array_ram_type;
+    TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
+
+    -- Data pair
+    SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
+    SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+    -- Mode Register
+    SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+    
+    -- Command Decode Variables
+    SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
+    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
+    
+    -- Burst Length Decode Variables
+    SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
+    
+    -- Cas Latency Decode Variables
+    SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
+
+    -- Internal Control Signals
+    SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
+
+    -- System Clock
+    SIGNAL Sys_clk : STD_LOGIC := '0';
+
+    -- Dqs buffer
+    SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+
+BEGIN
+    -- Strip the strength
+    Cs_in  <= To_X01 (Cs_n);
+    Ras_in <= To_X01 (Ras_n);
+    Cas_in <= To_X01 (Cas_n);
+    We_in  <= To_X01 (We_n);
+    
+    -- Commands Decode
+    Active_enable   <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND     We_in;
+    Aref_enable     <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND     We_in;
+    Burst_term      <= NOT(Cs_in) AND     Ras_in  AND     Cas_in  AND NOT(We_in);
+    Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND     Ba(0)  AND NOT(Ba(1));
+    Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
+    Prech_enable    <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND NOT(We_in);
+    Read_enable     <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND     We_in;
+    Write_enable    <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND NOT(We_in);
+
+    -- Burst Length Decode
+    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);
+    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));
+    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
+    Burst_length_f  <=    (Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
+
+    -- CAS Latency Decode
+    Cas_latency_15  <=     Mode_reg(6)  AND NOT(Mode_reg(5)) AND    (Mode_reg(4));
+    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));
+    Cas_latency_25  <=     Mode_reg(6)  AND     Mode_reg(5)  AND NOT(Mode_reg(4));
+    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);
+    Cas_latency_4   <=    (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
+
+    -- Dqs buffer
+    Dqs <= Dqs_out;
+
+    --
+    -- System Clock
+    --
+    int_clk : PROCESS (Clk, Clk_n)
+        VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
+    begin
+        IF Clk = '1' AND Clk_n = '0' THEN
+            ClkZ := '1';
+            CkeZ := Cke;
+        ELSIF Clk = '0' AND Clk_n = '1' THEN
+            ClkZ := '0';
+        END IF;
+        Sys_clk <= CkeZ AND ClkZ;
+    END PROCESS;
+
+    --
+    -- Main Process
+    --
+    state_register : PROCESS
+        -- Precharge Variables
+        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
+
+        -- Activate Variables
+        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
+
+        -- Data IO variables
+        VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
+
+        -- Internal address mux variables
+        VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
+        VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+        VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+
+        -- DLL Reset variables
+        VARIABLE DLL_enable : STD_LOGIC := '0';
+        VARIABLE DLL_reset : STD_LOGIC := '0';
+        VARIABLE DLL_done : STD_LOGIC := '0';
+        VARIABLE DLL_count : INTEGER := 0;
+        
+        -- Timing Check
+        VARIABLE MRD_chk : TIME := 0 ns;
+        VARIABLE RFC_chk : TIME := 0 ns;
+        VARIABLE RRD_chk : TIME := 0 ns;
+        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
+        VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
+        VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
+        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
+        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
+        VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
+
+        -- Read pipeline variables
+        VARIABLE Read_cmnd : Array_Read_cmnd;
+        VARIABLE Read_bank : Array_Read_bank;
+        VARIABLE Read_cols : Array_Read_cols;
+
+        -- Write pipeline variables
+        VARIABLE Write_cmnd : Array_Write_cmnd;
+        VARIABLE Write_bank : Array_Write_bank;
+        VARIABLE Write_cols : Array_Write_cols;
+
+        -- Auto Precharge variables
+        VARIABLE Read_precharge  : Array_Read_precharge  := ('0' & '0' & '0' & '0');
+        VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
+        VARIABLE Count_precharge : Array_Count_precharge := ( 0  &  0  &  0  &  0 );
+
+        -- Manual Precharge variables
+        VARIABLE A10_precharge  : Array_A10_precharge;
+        VARIABLE Bank_precharge : Array_Bank_precharge;
+        VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
+
+        -- Burst Terminate variable
+        VARIABLE Cmnd_bst : Array_Cmnd_bst;
+
+        -- Memory Banks
+        VARIABLE Bank0 : Array_ram_stor;
+        VARIABLE Bank1 : Array_ram_stor;
+        VARIABLE Bank2 : Array_ram_stor;
+        VARIABLE Bank3 : Array_ram_stor;
+
+        -- Burst Counter
+        VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+        -- Internal Dqs initialize
+        VARIABLE Dqs_int : STD_LOGIC := '0';
+
+        -- Data buffer for DM Mask
+        VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+
+        --
+        -- Initialize empty rows
+        --
+        PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
+            VARIABLE i, j : INTEGER := 0;
+        BEGIN
+            IF Bank = "00" THEN
+                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty
+                    Bank0 (Row_index) := NEW Array_ram_type;            -- Open new row for access
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP           -- Filled row with zeros
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank0 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "01" THEN
+                IF Bank1 (Row_index) = NULL THEN
+                    Bank1 (Row_index) := NEW Array_ram_type;
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank1 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "10" THEN
+                IF Bank2 (Row_index) = NULL THEN
+                    Bank2 (Row_index) := NEW Array_ram_type;
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank2 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "11" THEN
+                IF Bank3 (Row_index) = NULL THEN
+                    Bank3 (Row_index) := NEW Array_ram_type;
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank3 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            END IF;
+        END;
+
+        --
+        -- Burst Counter
+        --
+        PROCEDURE Burst_decode IS
+            VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        BEGIN
+            -- Advance burst counter
+            Burst_counter := Burst_counter + 1;
+
+            -- Burst Type
+            IF Mode_reg (3) = '0' THEN
+                Cols_temp := Cols_addr + 1;
+            ELSIF Mode_reg (3) = '1' THEN
+                Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
+                Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
+                Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
+            END IF;
+
+            -- Burst Length
+            IF Burst_length_2 = '1' THEN
+                Cols_addr (0) := Cols_temp (0);
+            ELSIF Burst_length_4 = '1' THEN
+                Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
+            ELSIF Burst_length_8 = '1' THEN
+                Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
+            ELSE
+                Cols_addr := Cols_temp;
+            END IF;
+
+            -- Data counter
+            IF Burst_length_2 = '1' THEN
+                IF Burst_counter >= 2 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_4 = '1' THEN
+                IF Burst_counter >= 4 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_8 = '1' THEN
+                IF Burst_counter >= 8 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            END IF;
+        END;
+
+    BEGIN
+        WAIT ON Sys_clk;
+
+        --
+        -- Manual Precharge Pipeline
+        --
+        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+            -- A10 Precharge Pipeline
+            A10_precharge(0) := A10_precharge(1);
+            A10_precharge(1) := A10_precharge(2);
+            A10_precharge(2) := A10_precharge(3);
+            A10_precharge(3) := A10_precharge(4);
+            A10_precharge(4) := A10_precharge(5);
+            A10_precharge(5) := A10_precharge(6);
+            A10_precharge(6) := A10_precharge(7);
+            A10_precharge(7) := A10_precharge(8);
+            A10_precharge(8) := '0';
+
+            -- Bank Precharge Pipeline
+            Bank_precharge(0) := Bank_precharge(1);
+            Bank_precharge(1) := Bank_precharge(2);
+            Bank_precharge(2) := Bank_precharge(3);
+            Bank_precharge(3) := Bank_precharge(4);
+            Bank_precharge(4) := Bank_precharge(5);
+            Bank_precharge(5) := Bank_precharge(6);
+            Bank_precharge(6) := Bank_precharge(7);
+            Bank_precharge(7) := Bank_precharge(8);
+            Bank_precharge(8) := "00";
+
+            -- Command Precharge Pipeline
+            Cmnd_precharge(0) := Cmnd_precharge(1);
+            Cmnd_precharge(1) := Cmnd_precharge(2);
+            Cmnd_precharge(2) := Cmnd_precharge(3);
+            Cmnd_precharge(3) := Cmnd_precharge(4);
+            Cmnd_precharge(4) := Cmnd_precharge(5);
+            Cmnd_precharge(5) := Cmnd_precharge(6);
+            Cmnd_precharge(6) := Cmnd_precharge(7);
+            Cmnd_precharge(7) := Cmnd_precharge(8);
+            Cmnd_precharge(8) := '0';
+
+            -- Terminate Read if same bank or all banks
+            IF ((Cmnd_precharge (0) = '1') AND
+                (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
+                (Data_out_enable = '1')) THEN
+                Data_out_enable := '0';
+            END IF;
+        END IF;
+
+        --
+        -- Burst Terminate Pipeline
+        --
+        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+            -- Burst Terminate pipeline
+            Cmnd_bst (0) := Cmnd_bst (1);
+            Cmnd_bst (1) := Cmnd_bst (2);
+            Cmnd_bst (2) := Cmnd_bst (3);
+            Cmnd_bst (3) := Cmnd_bst (4);
+            Cmnd_bst (4) := Cmnd_bst (5);
+            Cmnd_bst (5) := Cmnd_bst (6);
+            Cmnd_bst (6) := Cmnd_bst (7);
+            Cmnd_bst (7) := Cmnd_bst (8);
+            Cmnd_bst (8) := '0';
+
+            -- Terminate current Read
+            IF ((Cmnd_bst  (0) = '1') AND (Data_out_enable = '1')) THEN
+                Data_out_enable := '0';
+            END IF;
+        END IF;
+
+        --
+        -- Dq and Dqs Drivers
+        --
+        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+            -- Read Command Pipeline
+            Read_cmnd (0) := Read_cmnd (1);
+            Read_cmnd (1) := Read_cmnd (2);
+            Read_cmnd (2) := Read_cmnd (3);
+            Read_cmnd (3) := Read_cmnd (4);
+            Read_cmnd (4) := Read_cmnd (5);
+            Read_cmnd (5) := Read_cmnd (6);
+            Read_cmnd (6) := Read_cmnd (7);
+            Read_cmnd (7) := Read_cmnd (8);
+            Read_cmnd (8) := '0';
+
+            -- Read Bank Pipeline
+            Read_bank (0) := Read_bank (1);
+            Read_bank (1) := Read_bank (2);
+            Read_bank (2) := Read_bank (3);
+            Read_bank (3) := Read_bank (4);
+            Read_bank (4) := Read_bank (5);
+            Read_bank (5) := Read_bank (6);
+            Read_bank (6) := Read_bank (7);
+            Read_bank (7) := Read_bank (8);
+            Read_bank (8) := "00";
+
+            -- Read Column Pipeline
+            Read_cols (0) := Read_cols (1);
+            Read_cols (1) := Read_cols (2);
+            Read_cols (2) := Read_cols (3);
+            Read_cols (3) := Read_cols (4);
+            Read_cols (4) := Read_cols (5);
+            Read_cols (5) := Read_cols (6);
+            Read_cols (6) := Read_cols (7);
+            Read_cols (7) := Read_cols (8);
+            Read_cols (8) := (OTHERS => '0');
+
+            -- Initialize Read command
+            IF Read_cmnd (0) = '1' THEN
+                Data_out_enable := '1';
+                Bank_addr := Read_bank (0);
+                Cols_addr := Read_cols (0);
+                Cols_brst := Cols_addr (2 DOWNTO 0);
+                Burst_counter := (OTHERS => '0');
+
+                -- Row address mux
+                CASE Bank_addr IS
+                    WHEN "00"   => Rows_addr := B0_row_addr;
+                    WHEN "01"   => Rows_addr := B1_row_addr;
+                    WHEN "10"   => Rows_addr := B2_row_addr;
+                    WHEN OTHERS => Rows_addr := B3_row_addr;
+                END CASE;
+            END IF;
+
+            -- Toggle Dqs during Read command
+            IF Data_out_enable = '1' THEN
+                Dqs_int := '0';
+                IF Dqs_out = "00" THEN
+                    Dqs_out <= "11";
+                ELSIF Dqs_out = "11" THEN
+                    Dqs_out <= "00";
+                ELSE
+                    Dqs_out <= "00";
+                END IF;
+            ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
+                Dqs_out <= "ZZ";
+            END IF;
+
+            -- Initialize Dqs for Read command
+            IF Read_cmnd (2) = '1' THEN
+                IF Data_out_enable = '0' THEN
+                    Dqs_int := '1';
+                    Dqs_out <= "00";
+                END IF;
+            END IF;
+
+            -- Read Latch
+            IF Data_out_enable = '1' THEN
+                -- Initialize Memory
+                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
+                
+                -- Output Data
+                CASE Bank_addr IS
+                    WHEN "00"   => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    WHEN "01"   => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    WHEN "10"   => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                END CASE;
+
+                --  Increase Burst Counter
+                Burst_decode;
+            ELSE
+                Dq <= (OTHERS => 'Z');
+            END IF;
+        END IF;
+
+        --
+        -- Write FIFO and DM Mask Logic
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            -- Write command pipeline
+            Write_cmnd (0) := Write_cmnd (1);
+            Write_cmnd (1) := Write_cmnd (2);
+            Write_cmnd (2) := '0';
+
+            -- Write command pipeline
+            Write_bank (0) := Write_bank (1);
+            Write_bank (1) := Write_bank (2);
+            Write_bank (2) := "00";
+
+            -- Write column pipeline
+            Write_cols (0) := Write_cols (1);
+            Write_cols (1) := Write_cols (2);
+            Write_cols (2) := (OTHERS => '0');
+
+            -- Initialize Write command
+            IF Write_cmnd (0) = '1' THEN
+                Data_in_enable := '1';
+                Bank_addr := Write_bank (0);
+                Cols_addr := Write_cols (0);
+                Cols_brst := Cols_addr (2 DOWNTO 0);
+                Burst_counter := (OTHERS => '0');
+
+                -- Row address mux
+                CASE Bank_addr IS
+                    WHEN "00"   => Rows_addr := B0_row_addr;
+                    WHEN "01"   => Rows_addr := B1_row_addr;
+                    WHEN "10"   => Rows_addr := B2_row_addr;
+                    WHEN OTHERS => Rows_addr := B3_row_addr;
+                END CASE;
+            END IF;
+
+            -- Write data
+            IF Data_in_enable = '1' THEN
+                -- Initialize memory
+                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
+                
+                -- Write first data
+                IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
+                    -- Data Buffer
+                    CASE Bank_addr IS
+                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    END CASE;
+
+                    -- Perform DM Mask
+                    IF Dm_pair (0) = '0' THEN
+                        Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
+                    END IF;
+                    IF Dm_pair (1) = '0' THEN
+                        Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
+                    END IF;
+
+                    -- Write Data
+                    CASE Bank_addr IS
+                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                    END CASE;
+                END IF;
+
+                --  Increase Burst Counter
+                Burst_decode;
+
+                -- Write second data
+                IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
+                    -- Data Buffer
+                    CASE Bank_addr IS
+                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    END CASE;
+
+                    -- Perform DM Mask
+                    IF Dm_pair (2) = '0' THEN
+                        Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
+                    END IF;
+                    IF Dm_pair (3) = '0' THEN
+                        Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
+                    END IF;
+
+                    -- Write Data
+                    CASE Bank_addr IS
+                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                    END CASE;
+                END IF;
+                
+                -- Increase Burst Counter
+                Burst_decode;
+
+                -- tWR start and tWTR check
+                IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
+                    CASE Bank_addr IS
+                        WHEN "00"   => WR_chk0 := NOW;
+                        WHEN "01"   => WR_chk1 := NOW;
+                        WHEN "10"   => WR_chk2 := NOW;
+                        WHEN OTHERS => WR_chk3 := NOW;
+                    END CASE;
+
+                    -- tWTR check
+                    ASSERT (Read_enable = '0')
+                        REPORT "tWTR violation during Read"
+                        SEVERITY WARNING;
+                END IF;
+            END IF;
+        END IF;
+
+        --
+        -- Auto Precharge Calculation
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            -- Precharge counter
+            IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
+                Count_precharge (0) := Count_precharge (0) + 1;
+            END IF;
+            IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
+                Count_precharge (1) := Count_precharge (1) + 1;
+            END IF;
+            IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
+                Count_precharge (2) := Count_precharge (2) + 1;
+            END IF;
+            IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
+                Count_precharge (3) := Count_precharge (3) + 1;
+            END IF;
+
+            -- Read with AutoPrecharge Calculation
+            --      The device start internal precharge when:
+            --          1.  Meet tRAS requirement
+            --          2.  BL/2 cycles after command
+            IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(0) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
+                    Pc_b0 := '1';
+                    Act_b0 := '0';
+                    RP_chk0 := NOW;
+                    Read_precharge(0) := '0';
+                END IF;
+            END IF;
+            IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(1) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
+                    Pc_b1 := '1';
+                    Act_b1 := '0';
+                    RP_chk1 := NOW;
+                    Read_precharge(1) := '0';
+                END IF;
+            END IF;
+            IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(2) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
+                    Pc_b2 := '1';
+                    Act_b2 := '0';
+                    RP_chk2 := NOW;
+                    Read_precharge(2) := '0';
+                END IF;
+            END IF;
+            IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(3) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
+                    Pc_b3 := '1';
+                    Act_b3 := '0';
+                    RP_chk3 := NOW;
+                    Read_precharge(3) := '0';
+                END IF;
+            END IF;
+
+            -- Write with AutoPrecharge Calculation
+            --      The device start internal precharge when:
+            --          1.  Meet tRAS requirement
+            --          2.  Two clock after last burst
+            -- Since tWR is time base, the model will compensate tRP
+            IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
+                    Pc_b0 := '1';
+                    Act_b0 := '0';
+                    RP_chk0 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(0) := '0';
+                END IF;
+            END IF;
+            IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
+                    Pc_b1 := '1';
+                    Act_b1 := '0';
+                    RP_chk1 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(1) := '0';
+                END IF;
+            END IF;
+            IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
+                    Pc_b2 := '1';
+                    Act_b2 := '0';
+                    RP_chk2 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(2) := '0';
+                END IF;
+            END IF;
+            IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
+                    Pc_b3 := '1';
+                    Act_b3 := '0';
+                    RP_chk3 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(3) := '0';
+                END IF;
+            END IF;
+        END IF;
+        
+        --
+        -- DLL Counter
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            IF (DLL_Reset = '1' AND DLL_done = '0') THEN
+                DLL_count := DLL_count + 1;
+                IF (DLL_count >= 200) THEN
+                    DLL_done := '1';
+                END IF;
+            END IF;
+        END IF;
+
+        --
+        -- Control Logic
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            -- Auto Refresh
+            IF Aref_enable = '1' THEN
+                -- Auto Refresh to Auto Refresh
+                ASSERT (NOW - RFC_chk >= tRFC)
+                    REPORT "tRFC violation during Auto Refresh"
+                    SEVERITY WARNING;
+
+                -- Precharge to Auto Refresh
+                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+                    REPORT "tRP violation during Auto Refresh"
+                    SEVERITY WARNING;
+
+                -- Precharge to Auto Refresh
+                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+                    REPORT "All banks must be Precharge before Auto Refresh"
+                    SEVERITY WARNING;
+
+                -- Record current tRFC time
+                RFC_chk := NOW;
+            END IF;
+
+            -- Extended Load Mode Register
+            IF Ext_mode_enable = '1' THEN
+                IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
+                    IF (Addr (0) = '0') THEN
+                        DLL_enable := '1';
+                    ELSE
+                        DLL_enable := '0';
+                    END IF;
+                END IF;
+                
+                -- Precharge to EMR
+                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+                    REPORT "All bank must be Precharged before Extended Mode Register"
+                    SEVERITY WARNING;
+                
+                -- Precharge to EMR
+                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+                    REPORT "tRP violation during Extended Load Register"
+                    SEVERITY WARNING;
+
+                -- LMR/EMR to EMR
+                ASSERT (NOW - MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Extended Mode Register"
+                    SEVERITY WARNING;
+
+                -- Record current tMRD time
+                MRD_chk := NOW;
+            END IF;
+
+            -- Load Mode Register
+            IF Mode_reg_enable = '1' THEN
+                -- Register mode
+                Mode_reg <= Addr;
+                
+                -- DLL Reset
+                IF (DLL_enable = '1' AND Addr (8) = '1') THEN
+                    DLL_reset := '1';
+                    DLL_done  := '0';
+                    DLL_count := 0;
+                ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
+                    ASSERT (FALSE)
+                        REPORT "DLL is ENABLE: DLL RESET is require"
+                        SEVERITY WARNING;
+                ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
+                    ASSERT (FALSE)
+                        REPORT "DLL is DISABLE: DLL RESET will be ignored"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge to LMR
+                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+                    REPORT "All bank must be Precharged before Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Precharge to EMR
+                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+                    REPORT "tRP violation during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- LMR/ELMR to LMR
+                ASSERT (NOW - MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Check for invalid Burst Length
+                ASSERT ((Addr (2 DOWNTO 0) = "001") OR      -- BL = 2
+                        (Addr (2 DOWNTO 0) = "010") OR      -- BL = 4
+                        (Addr (2 DOWNTO 0) = "011"))        -- BL = 8
+                    REPORT "Invalid Burst Length during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Check for invalid CAS Latency
+                ASSERT ((Addr (6 DOWNTO 4) = "010") OR      -- CL = 2.0
+                        (Addr (6 DOWNTO 4) = "110"))        -- CL = 2.5
+                    REPORT "Invalid CAS Latency during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Record current tMRD time
+                MRD_chk := NOW;
+            END IF;
+
+            -- Active Block (latch Bank and Row Address)
+            IF Active_enable = '1' THEN
+                -- Activate an OPEN bank can corrupt data
+                ASSERT ((Ba = "00" AND Act_b0 = '0') OR
+                        (Ba = "01" AND Act_b1 = '0') OR
+                        (Ba = "10" AND Act_b2 = '0') OR
+                        (Ba = "11" AND Act_b3 = '0'))
+                    REPORT "Bank is already activated - data can be corrupted"
+                    SEVERITY WARNING;
+
+                -- Activate Bank 0
+                IF Ba = "00" AND Pc_b0 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk0 >= tRC)
+                        REPORT "tRC violation during Activate Bank 0"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk0 >= tRP)
+                        REPORT "tRP violation during Activate Bank 0"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b0 := '1';
+                    Pc_b0 := '0';
+                    B0_row_addr := Addr;
+                    RC_chk0 := NOW;
+                    RCD_chk0 := NOW;
+                    RAS_chk0 := NOW;
+                    RAP_chk0 := NOW;
+                END IF;
+
+                -- Activate Bank 1
+                IF Ba = "01" AND Pc_b1 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk1 >= tRC)
+                        REPORT "tRC violation during Activate Bank 1"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk1 >= tRP)
+                        REPORT "tRP violation during Activate Bank 1"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b1 := '1';
+                    Pc_b1 := '0';
+                    B1_row_addr := Addr;
+                    RC_chk1 := NOW;
+                    RCD_chk1 := NOW;
+                    RAS_chk1 := NOW;
+                    RAP_chk1 := NOW;
+                END IF;
+
+                -- Activate Bank 2
+                IF Ba = "10" AND Pc_b2 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk2 >= tRC)
+                        REPORT "tRC violation during Activate Bank 2"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk2 >= tRP)
+                        REPORT "tRP violation during Activate Bank 2"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b2 := '1';
+                    Pc_b2 := '0';
+                    B2_row_addr := Addr;
+                    RC_chk2 := NOW;
+                    RCD_chk2 := NOW;
+                    RAS_chk2 := NOW;
+                    RAP_chk2 := NOW;
+                END IF;
+
+                -- Activate Bank 3
+                IF Ba = "11" AND Pc_b3 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk3 >= tRC)
+                        REPORT "tRC violation during Activate Bank 3"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk3 >= tRP)
+                        REPORT "tRP violation during Activate Bank 3"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b3 := '1';
+                    Pc_b3 := '0';
+                    B3_row_addr := Addr;
+                    RC_chk3 := NOW;
+                    RCD_chk3 := NOW;
+                    RAS_chk3 := NOW;
+                    RAP_chk3 := NOW;
+                END IF;
+
+                -- Activate Bank A to Activate Bank B
+                IF (Prev_bank /= Ba) THEN
+                    ASSERT (NOW - RRD_chk >= tRRD)
+                        REPORT "tRRD violation during Activate"
+                        SEVERITY WARNING;
+                END IF;
+                
+                -- AutoRefresh to Activate
+                ASSERT (NOW - RFC_chk >= tRFC)
+                    REPORT "tRFC violation during Activate"
+                    SEVERITY WARNING;
+                
+                -- Record Variables for Checking Violation
+                RRD_chk := NOW;
+                Prev_bank := Ba;
+            END IF;
+
+            -- Precharge Block - Consider NOP if bank already precharged or in process of precharging
+            IF Prech_enable = '1' THEN
+                -- EMR or LMR to Precharge
+                ASSERT (NOW - MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Precharge"
+                    SEVERITY WARNING;
+
+                -- Precharge Bank 0
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
+                    Act_b0 := '0';
+                    Pc_b0 := '1';
+                    RP_chk0 := NOW;
+
+                    -- Activate to Precharge bank 0
+                    ASSERT (NOW - RAS_chk0 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk0 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge Bank 1
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
+                    Act_b1 := '0';
+                    Pc_b1 := '1';
+                    RP_chk1 := NOW;
+
+                    -- Activate to Precharge
+                    ASSERT (NOW - RAS_chk1 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk1 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge Bank 2
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
+                    Act_b2 := '0';
+                    Pc_b2 := '1';
+                    RP_chk2 := NOW;
+
+                    -- Activate to Precharge
+                    ASSERT (NOW - RAS_chk2 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk2 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge Bank 3
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
+                    Act_b3 := '0';
+                    Pc_b3 := '1';
+                    RP_chk3 := NOW;
+
+                    -- Activate to Precharge
+                    ASSERT (NOW - RAS_chk3 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk3 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Pipeline for READ
+                IF CAS_latency_15 = '1' THEN
+                    A10_precharge  (3) := Addr(10);
+                    Bank_precharge (3) := Ba;
+                    Cmnd_precharge (3) := '1';
+                ELSIF CAS_latency_2 = '1' THEN
+                    A10_precharge  (4) := Addr(10);
+                    Bank_precharge (4) := Ba;
+                    Cmnd_precharge (4) := '1';
+                ELSIF CAS_latency_25 = '1' THEN
+                    A10_precharge  (5) := Addr(10);
+                    Bank_precharge (5) := Ba;
+                    Cmnd_precharge (5) := '1';
+                ELSIF CAS_latency_3 = '1' THEN
+                    A10_precharge  (6) := Addr(10);
+                    Bank_precharge (6) := Ba;
+                    Cmnd_precharge (6) := '1';
+                ELSIF CAS_latency_4 = '1' THEN
+                    A10_precharge  (8) := Addr(10);
+                    Bank_precharge (8) := Ba;
+                    Cmnd_precharge (8) := '1';
+                END IF;
+            END IF;
+
+            -- Burst Terminate
+            IF Burst_term = '1' THEN
+                -- Pipeline for Read
+                IF CAS_latency_15 = '1' THEN
+                    Cmnd_bst (3) := '1';
+                ELSIF CAS_latency_2 = '1' THEN
+                    Cmnd_bst (4) := '1';
+                ELSIF CAS_latency_25 = '1' THEN
+                    Cmnd_bst (5) := '1';
+                ELSIF CAS_latency_3 = '1' THEN
+                    Cmnd_bst (6) := '1';
+                ELSIF CAS_latency_4 = '1' THEN
+                    Cmnd_bst (8) := '1';
+                END IF;
+
+                -- Terminate Write
+                ASSERT (Data_in_enable = '0')
+                    REPORT "It's illegal to Burst Terminate a Write"
+                    SEVERITY WARNING;
+
+                -- Terminate Read with Auto Precharge
+                ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
+                        Read_precharge (2) = '0' AND Read_precharge (3) = '0')
+                    REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
+                    SEVERITY WARNING;
+            END IF;
+
+            -- Read Command
+            IF Read_enable = '1' THEN
+                -- CAS Latency Pipeline
+                IF Cas_latency_15 = '1' THEN
+                    Read_cmnd (3) := '1';
+                    Read_bank (3) := Ba;
+                    Read_cols (3) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_2 = '1' THEN
+                    Read_cmnd (4) := '1';
+                    Read_bank (4) := Ba;
+                    Read_cols (4) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_25 = '1' THEN
+                    Read_cmnd (5) := '1';
+                    Read_bank (5) := Ba;
+                    Read_cols (5) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_3 = '1' THEN
+                    Read_cmnd (6) := '1';
+                    Read_bank (6) := Ba;
+                    Read_cols (6) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_4 = '1' THEN
+                    Read_cmnd (8) := '1';
+                    Read_bank (8) := Ba;
+                    Read_cols (8) := Addr (8 DOWNTO 0);
+                END IF;
+
+                -- Write to Read: Terminate Write Immediately
+                IF Data_in_enable = '1' THEN
+                    Data_in_enable := '0';
+                END IF;
+
+                -- Interrupting a Read with Auto Precharge (same bank only)
+                ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
+                    REPORT "It's illegal to interrupt a Read with Auto Precharge"
+                    SEVERITY WARNING;
+
+                -- Activate to Read
+                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
+                        (Ba = "01" AND Act_b1 = '1') OR
+                        (Ba = "10" AND Act_b2 = '1') OR
+                        (Ba = "11" AND Act_b3 = '1'))
+                    REPORT "Bank is not Activated for Read"
+                    SEVERITY WARNING;
+
+                -- Activate to Read without Auto Precharge
+                IF Addr (10) = '0' THEN
+                    ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+                            (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+                            (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+                            (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+                        REPORT "tRCD violation during Read"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Activate to Read with Auto Precharge
+                IF Addr (10) = '1' THEN
+                    ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
+                            (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
+                            (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
+                            (Ba = "11" AND NOW - RAP_chk3 >= tRAP))
+                        REPORT "tRAP violation during Read"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Auto precharge
+                IF Addr (10) = '1' THEN
+                    Read_precharge (Conv_INTEGER(Ba)) := '1';
+                    Count_precharge (Conv_INTEGER(Ba)) := 0;
+                END IF;
+
+                -- DLL Check
+                IF (DLL_reset = '1') THEN
+                    ASSERT (DLL_done = '1')
+                        REPORT "DLL RESET not complete"
+                        SEVERITY WARNING;
+                END IF;
+            END IF;
+
+            -- Write Command
+            IF Write_enable = '1' THEN
+                -- Pipeline for Write
+                Write_cmnd (2) := '1';
+                Write_bank (2) := Ba;
+                Write_cols (2) := Addr (8 DOWNTO 0);
+
+                -- Interrupting a Write with Auto Precharge (same bank only)
+                ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
+                    REPORT "It's illegal to interrupt a Write with Auto Precharge"
+                    SEVERITY WARNING;
+
+                -- Activate to Write
+                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
+                        (Ba = "01" AND Act_b1 = '1') OR
+                        (Ba = "10" AND Act_b2 = '1') OR
+                        (Ba = "11" AND Act_b3 = '1'))
+                    REPORT "Bank is not Activated for Write"
+                    SEVERITY WARNING;
+
+                -- Activate to Write
+                ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+                        (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+                        (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+                        (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+                    REPORT "tRCD violation during Write"
+                    SEVERITY WARNING;
+
+                -- Auto precharge
+                IF Addr (10) = '1' THEN
+                    Write_precharge (Conv_INTEGER(Ba)) := '1';
+                    Count_precharge (Conv_INTEGER(Ba)) := 0;
+                END IF;
+            END IF;
+        END IF;
+    END PROCESS;
+
+    --
+    -- Dqs Receiver
+    --
+    dqs_rcvrs : PROCESS
+        VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
+        VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+    BEGIN
+        WAIT ON Dqs;
+        -- Latch data at posedge Dqs
+        IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
+            Dq_temp := Dq;
+            Dm_temp := Dm;
+        END IF;
+        -- Latch data at negedge Dqs
+        IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
+            Dq_pair <= (Dq & Dq_temp);
+            Dm_pair <= (Dm & Dm_temp);
+        END IF;
+    END PROCESS;
+
+    --
+    -- Setup timing checks
+    --
+    Setup_check : PROCESS
+    BEGIN
+        WAIT ON Sys_clk;
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            ASSERT(Cke'LAST_EVENT >= tIS)
+                REPORT "CKE Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Cs_n'LAST_EVENT >= tIS)
+                REPORT "CS# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT >= tIS)
+                REPORT "CAS# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT >= tIS)
+                REPORT "RAS# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT >= tIS)
+                REPORT "WE# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Addr'LAST_EVENT >= tIS)
+                REPORT "ADDR Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT >= tIS)
+                REPORT "BA Setup time violation -- tIS"
+                SEVERITY WARNING;
+        END IF;   
+    END PROCESS;
+
+    --
+    -- Hold timing checks
+    --
+    Hold_check : PROCESS
+    BEGIN
+        WAIT ON Sys_clk'DELAYED (tIH);
+        IF Sys_clk'DELAYED (tIH) = '1' THEN
+            ASSERT(Cke'LAST_EVENT >= tIH)
+                REPORT "CKE Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Cs_n'LAST_EVENT >= tIH)
+                REPORT "CS# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT >= tIH)
+                REPORT "CAS# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT >= tIH)
+                REPORT "RAS# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT >= tIH)
+                REPORT "WE# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Addr'LAST_EVENT >= tIH)
+                REPORT "ADDR Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT >= tIH)
+                REPORT "BA Hold time violation -- tIH"
+                SEVERITY WARNING;
+        END IF;   
+    END PROCESS;
+
+END behave;
diff --git a/misc/wishbone/src/atomic32_access.vhd b/misc/wishbone/src/atomic32_access.vhd
index b062f98..9bc9825 100644
--- a/misc/wishbone/src/atomic32_access.vhd
+++ b/misc/wishbone/src/atomic32_access.vhd
@@ -1,132 +1,132 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.ALL;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-library work;

---use work.phi_config.all;

-use work.wishbone_pkg.all;

-

-entity atomic32_access is

-	port (	cpu_clk			: in std_logic;

-			areset			: in std_logic;

-	

-			-- Wishbone from CPU interface

-			wb_16_i			: in wishbone_bus_in;

-			wb_16_o     	: out wishbone_bus_out;

-			

-			-- Wishbone to FPGA registers and ethernet core

-			wb_32_i			: in wishbone_bus_out;

-			wb_32_o			: out wishbone_bus_in);

-end atomic32_access;

-

-architecture behave of atomic32_access is

-

-type eth_state_wr_type is (idle, lsb_msb, lsb, msb, write, ack, wait_st);

-signal	eth_state_wr : eth_state_wr_type;				

-type eth_state_rd_type is (idle, lsb_msb, lsb_read, lsb, wait_st2, msb);

-signal eth_state_rd : eth_state_rd_type;			

-signal core_data : std_logic_vector(31 downto 0);

-signal core_addr : std_logic_vector(31 downto 0);

-

-begin

-	process(cpu_clk, areset)

-	begin

-		if areset = '1' then

-			eth_state_wr <= idle;

-			eth_state_rd <= idle;

-			wb_32_o.stb <= '0';

-			wb_32_o.cyc <= '0';

-			wb_16_o.ack <= '0';

-			core_data <= (others => '0');

-			core_addr <= (others => '0');

-		elsif (rising_edge(cpu_clk)) then

-			

-			case eth_state_wr is						--write cycle

-				when idle =>

-					if wb_16_i.cyc = '1' and wb_16_i.we = '1' then

-						eth_state_wr <= lsb_msb;						

-					end if;					

-				when lsb_msb =>

-					if wb_16_i.adr(1) = '0' then

-						eth_state_wr <= lsb;

-					end if;

-					if wb_16_i.adr(1) = '1' then

-						eth_state_wr <= msb;

-					end if;

-				when lsb =>

-					core_data(15 downto 0) <= wb_16_i.dat(15 downto 0);

-					wb_16_o.ack <= '1';

-					eth_state_wr <= wait_st;

-				when msb =>

-					core_data(31 downto 16) <= wb_16_i.dat(31 downto 16);

-					core_addr <= wb_16_i.adr(31 downto 2) & "00";

-					eth_state_wr <= write;

-				when write =>

-					wb_32_o.dat <= core_data;

-					wb_32_o.adr <= core_addr;

-					wb_32_o.sel <= "1111";

-					wb_32_o.we <= '1';

-					wb_32_o.stb <= '1';

-					wb_32_o.cyc <= '1';

-					eth_state_wr <= ack;

-				when ack =>

-					if wb_32_i.ack = '1' then

-						wb_16_o.ack <= '1';

-						eth_state_wr <= wait_st;

-						wb_32_o.stb <= '0';	

-						wb_32_o.cyc <= '0';		

-						wb_32_o.sel <= "0000";	

-						wb_32_o.we <= '0';	

-					end if;

-				when wait_st =>

-					wb_16_o.ack <= '0';

-					eth_state_wr <= idle;

-				when others =>

-					eth_state_wr <= idle;

-			end case;

-	

-			case eth_state_rd is						--read cycle

-				when idle =>

-					if wb_16_i.cyc = '1' and wb_16_i.we = '0' then

-						core_addr <= wb_16_i.adr(31 downto 2) & "00";	

-						eth_state_rd <= lsb_msb;

-					end if;

-				when lsb_msb =>

-					if wb_16_i.adr(1) = '0' then

-						wb_32_o.adr <= core_addr;

-						eth_state_rd <= lsb_read;

-					end if;

-					if wb_16_i.adr(1) = '1' then

-						wb_32_o.adr <= core_addr;

-						eth_state_rd <= msb;

-					end if;

-				when lsb_read =>

-					wb_32_o.sel <= "1111";

-					wb_32_o.we <= '0';

-					wb_32_o.stb <= '1';

-					wb_32_o.cyc <= '1';							

-                	eth_state_rd <= lsb;

-				when lsb =>

-					if wb_32_i.ack = '1' then									

-						wb_32_o.sel <= "0000";

-						wb_32_o.stb <= '0';

-						wb_32_o.cyc <= '0';

-						core_data <= wb_32_i.dat;

-						wb_16_o.dat <= x"0000" & wb_32_i.dat(15 downto 0);							

-						wb_16_o.ack <= '1';

-						eth_state_rd <= wait_st2;

-					end if;

-				when wait_st2 =>

-					wb_16_o.ack <= '0';

-					eth_state_rd <= idle;

-				when msb =>

-					wb_16_o.ack <= '1';

-					wb_16_o.dat <= core_data(31 downto 16) & x"0000";

-					eth_state_rd <= wait_st2;

-				when others =>

-					eth_state_rd <= idle;

-			end case;

-		end if;

-	end process;

-

+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+--use work.phi_config.all;
+use work.wishbone_pkg.all;
+
+entity atomic32_access is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from CPU interface
+			wb_16_i			: in wishbone_bus_in;
+			wb_16_o     	: out wishbone_bus_out;
+			
+			-- Wishbone to FPGA registers and ethernet core
+			wb_32_i			: in wishbone_bus_out;
+			wb_32_o			: out wishbone_bus_in);
+end atomic32_access;
+
+architecture behave of atomic32_access is
+
+type eth_state_wr_type is (idle, lsb_msb, lsb, msb, write, ack, wait_st);
+signal	eth_state_wr : eth_state_wr_type;				
+type eth_state_rd_type is (idle, lsb_msb, lsb_read, lsb, wait_st2, msb);
+signal eth_state_rd : eth_state_rd_type;			
+signal core_data : std_logic_vector(31 downto 0);
+signal core_addr : std_logic_vector(31 downto 0);
+
+begin
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			eth_state_wr <= idle;
+			eth_state_rd <= idle;
+			wb_32_o.stb <= '0';
+			wb_32_o.cyc <= '0';
+			wb_16_o.ack <= '0';
+			core_data <= (others => '0');
+			core_addr <= (others => '0');
+		elsif (rising_edge(cpu_clk)) then
+			
+			case eth_state_wr is						--write cycle
+				when idle =>
+					if wb_16_i.cyc = '1' and wb_16_i.we = '1' then
+						eth_state_wr <= lsb_msb;						
+					end if;					
+				when lsb_msb =>
+					if wb_16_i.adr(1) = '0' then
+						eth_state_wr <= lsb;
+					end if;
+					if wb_16_i.adr(1) = '1' then
+						eth_state_wr <= msb;
+					end if;
+				when lsb =>
+					core_data(15 downto 0) <= wb_16_i.dat(15 downto 0);
+					wb_16_o.ack <= '1';
+					eth_state_wr <= wait_st;
+				when msb =>
+					core_data(31 downto 16) <= wb_16_i.dat(31 downto 16);
+					core_addr <= wb_16_i.adr(31 downto 2) & "00";
+					eth_state_wr <= write;
+				when write =>
+					wb_32_o.dat <= core_data;
+					wb_32_o.adr <= core_addr;
+					wb_32_o.sel <= "1111";
+					wb_32_o.we <= '1';
+					wb_32_o.stb <= '1';
+					wb_32_o.cyc <= '1';
+					eth_state_wr <= ack;
+				when ack =>
+					if wb_32_i.ack = '1' then
+						wb_16_o.ack <= '1';
+						eth_state_wr <= wait_st;
+						wb_32_o.stb <= '0';	
+						wb_32_o.cyc <= '0';		
+						wb_32_o.sel <= "0000";	
+						wb_32_o.we <= '0';	
+					end if;
+				when wait_st =>
+					wb_16_o.ack <= '0';
+					eth_state_wr <= idle;
+				when others =>
+					eth_state_wr <= idle;
+			end case;
+	
+			case eth_state_rd is						--read cycle
+				when idle =>
+					if wb_16_i.cyc = '1' and wb_16_i.we = '0' then
+						core_addr <= wb_16_i.adr(31 downto 2) & "00";	
+						eth_state_rd <= lsb_msb;
+					end if;
+				when lsb_msb =>
+					if wb_16_i.adr(1) = '0' then
+						wb_32_o.adr <= core_addr;
+						eth_state_rd <= lsb_read;
+					end if;
+					if wb_16_i.adr(1) = '1' then
+						wb_32_o.adr <= core_addr;
+						eth_state_rd <= msb;
+					end if;
+				when lsb_read =>
+					wb_32_o.sel <= "1111";
+					wb_32_o.we <= '0';
+					wb_32_o.stb <= '1';
+					wb_32_o.cyc <= '1';							
+                	eth_state_rd <= lsb;
+				when lsb =>
+					if wb_32_i.ack = '1' then									
+						wb_32_o.sel <= "0000";
+						wb_32_o.stb <= '0';
+						wb_32_o.cyc <= '0';
+						core_data <= wb_32_i.dat;
+						wb_16_o.dat <= x"0000" & wb_32_i.dat(15 downto 0);							
+						wb_16_o.ack <= '1';
+						eth_state_rd <= wait_st2;
+					end if;
+				when wait_st2 =>
+					wb_16_o.ack <= '0';
+					eth_state_rd <= idle;
+				when msb =>
+					wb_16_o.ack <= '1';
+					wb_16_o.dat <= core_data(31 downto 16) & x"0000";
+					eth_state_rd <= wait_st2;
+				when others =>
+					eth_state_rd <= idle;
+			end case;
+		end if;
+	end process;
+
 end behave;
\ No newline at end of file
diff --git a/misc/wishbone/src/wishbone_pkg.vhd b/misc/wishbone/src/wishbone_pkg.vhd
index c3b0d9b..359a33f 100644
--- a/misc/wishbone/src/wishbone_pkg.vhd
+++ b/misc/wishbone/src/wishbone_pkg.vhd
@@ -1,52 +1,52 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-package wishbone_pkg is

-

-	type wishbone_bus_in is record

-		adr			: std_logic_vector(31 downto 0); 

-		sel			: std_logic_vector(3 downto 0); 

-		we			: std_logic;

-		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'

-		cyc			: std_logic; 

-		stb			: std_logic;

-	end record;

-

-	type wishbone_bus_out is record

-		dat		: std_logic_vector(31 downto 0);

-		ack			: std_logic;

-	end record;

-	

-	type wishbone_bus is record

-		insig		: wishbone_bus_in;

-		outsig  	: wishbone_bus_out;

-	end record;

-

-	component atomic32_access is

-	port (	cpu_clk			: in std_logic;

-			areset			: in std_logic;

-	

-			-- Wishbone from CPU interface

-			wb_16_i			: in wishbone_bus_in;

-			wb_16_o     	: out wishbone_bus_out;

-			-- Wishbone to FPGA registers and ethernet core

-			wb_32_i			: in wishbone_bus_out;

-			wb_32_o			: out wishbone_bus_in);

-	end component;

-	

-	component eth_access_corr is

-	port (	cpu_clk			: in std_logic;

-			areset			: in std_logic;

-	

-			-- Wishbone from Wishbone MUX

-			eth_raw_o		: out wishbone_bus_out;

-			eth_raw_i		: in wishbone_bus_in;

-			

-			-- Wishbone ethernet core

-			eth_slave_i 	: in wishbone_bus_out;

-			eth_slave_o		: out wishbone_bus_in);

-	end component;

-

-

-end wishbone_pkg;

+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+	type wishbone_bus_in is record
+		adr			: std_logic_vector(31 downto 0); 
+		sel			: std_logic_vector(3 downto 0); 
+		we			: std_logic;
+		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'
+		cyc			: std_logic; 
+		stb			: std_logic;
+	end record;
+
+	type wishbone_bus_out is record
+		dat		: std_logic_vector(31 downto 0);
+		ack			: std_logic;
+	end record;
+	
+	type wishbone_bus is record
+		insig		: wishbone_bus_in;
+		outsig  	: wishbone_bus_out;
+	end record;
+
+	component atomic32_access is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from CPU interface
+			wb_16_i			: in wishbone_bus_in;
+			wb_16_o     	: out wishbone_bus_out;
+			-- Wishbone to FPGA registers and ethernet core
+			wb_32_i			: in wishbone_bus_out;
+			wb_32_o			: out wishbone_bus_in);
+	end component;
+	
+	component eth_access_corr is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from Wishbone MUX
+			eth_raw_o		: out wishbone_bus_out;
+			eth_raw_i		: in wishbone_bus_in;
+			
+			-- Wishbone ethernet core
+			eth_slave_i 	: in wishbone_bus_out;
+			eth_slave_o		: out wishbone_bus_in);
+	end component;
+
+
+end wishbone_pkg;
diff --git a/zpu/hdl/example/bram_dmips.vhd b/zpu/hdl/example/bram_dmips.vhd
index 733560e..07b19f4 100644
--- a/zpu/hdl/example/bram_dmips.vhd
+++ b/zpu/hdl/example/bram_dmips.vhd
@@ -1,3356 +1,3356 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.numeric_std.all;

-

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-entity dualport_ram is

-port (clk : in std_logic;

-	memAWriteEnable : in std_logic;

-	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);

-	memAWrite : in std_logic_vector(wordSize-1 downto 0);

-	memARead : out std_logic_vector(wordSize-1 downto 0);

-	memBWriteEnable : in std_logic;

-	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);

-	memBWrite : in std_logic_vector(wordSize-1 downto 0);

-	memBRead : out std_logic_vector(wordSize-1 downto 0));

-end dualport_ram;

-

-architecture dualport_ram_arch of dualport_ram is

-

-

-type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);

-

-shared variable ram : ram_type :=

-(

-     0 => x"0b0b0b0b",

-     1 => x"82700b0b",

-     2 => x"80d5f40c",

-     3 => x"3a0b0b80",

-     4 => x"c4fb0400",

-     5 => x"00000000",

-     6 => x"00000000",

-     7 => x"00000000",

-     8 => x"80088408",

-     9 => x"88080b0b",

-    10 => x"80c5c22d",

-    11 => x"880c840c",

-    12 => x"800c0400",

-    13 => x"00000000",

-    14 => x"00000000",

-    15 => x"00000000",

-    16 => x"71fd0608",

-    17 => x"72830609",

-    18 => x"81058205",

-    19 => x"832b2a83",

-    20 => x"ffff0652",

-    21 => x"04000000",

-    22 => x"00000000",

-    23 => x"00000000",

-    24 => x"71fd0608",

-    25 => x"83ffff73",

-    26 => x"83060981",

-    27 => x"05820583",

-    28 => x"2b2b0906",

-    29 => x"7383ffff",

-    30 => x"0b0b0b0b",

-    31 => x"83a70400",

-    32 => x"72098105",

-    33 => x"72057373",

-    34 => x"09060906",

-    35 => x"73097306",

-    36 => x"070a8106",

-    37 => x"53510400",

-    38 => x"00000000",

-    39 => x"00000000",

-    40 => x"72722473",

-    41 => x"732e0753",

-    42 => x"51040000",

-    43 => x"00000000",

-    44 => x"00000000",

-    45 => x"00000000",

-    46 => x"00000000",

-    47 => x"00000000",

-    48 => x"71737109",

-    49 => x"71068106",

-    50 => x"30720a10",

-    51 => x"0a720a10",

-    52 => x"0a31050a",

-    53 => x"81065151",

-    54 => x"53510400",

-    55 => x"00000000",

-    56 => x"72722673",

-    57 => x"732e0753",

-    58 => x"51040000",

-    59 => x"00000000",

-    60 => x"00000000",

-    61 => x"00000000",

-    62 => x"00000000",

-    63 => x"00000000",

-    64 => x"00000000",

-    65 => x"00000000",

-    66 => x"00000000",

-    67 => x"00000000",

-    68 => x"00000000",

-    69 => x"00000000",

-    70 => x"00000000",

-    71 => x"00000000",

-    72 => x"0b0b0b88",

-    73 => x"c3040000",

-    74 => x"00000000",

-    75 => x"00000000",

-    76 => x"00000000",

-    77 => x"00000000",

-    78 => x"00000000",

-    79 => x"00000000",

-    80 => x"720a722b",

-    81 => x"0a535104",

-    82 => x"00000000",

-    83 => x"00000000",

-    84 => x"00000000",

-    85 => x"00000000",

-    86 => x"00000000",

-    87 => x"00000000",

-    88 => x"72729f06",

-    89 => x"0981050b",

-    90 => x"0b0b88a6",

-    91 => x"05040000",

-    92 => x"00000000",

-    93 => x"00000000",

-    94 => x"00000000",

-    95 => x"00000000",

-    96 => x"72722aff",

-    97 => x"739f062a",

-    98 => x"0974090a",

-    99 => x"8106ff05",

-   100 => x"06075351",

-   101 => x"04000000",

-   102 => x"00000000",

-   103 => x"00000000",

-   104 => x"71715351",

-   105 => x"020d0406",

-   106 => x"73830609",

-   107 => x"81058205",

-   108 => x"832b0b2b",

-   109 => x"0772fc06",

-   110 => x"0c515104",

-   111 => x"00000000",

-   112 => x"72098105",

-   113 => x"72050970",

-   114 => x"81050906",

-   115 => x"0a810653",

-   116 => x"51040000",

-   117 => x"00000000",

-   118 => x"00000000",

-   119 => x"00000000",

-   120 => x"72098105",

-   121 => x"72050970",

-   122 => x"81050906",

-   123 => x"0a098106",

-   124 => x"53510400",

-   125 => x"00000000",

-   126 => x"00000000",

-   127 => x"00000000",

-   128 => x"71098105",

-   129 => x"52040000",

-   130 => x"00000000",

-   131 => x"00000000",

-   132 => x"00000000",

-   133 => x"00000000",

-   134 => x"00000000",

-   135 => x"00000000",

-   136 => x"72720981",

-   137 => x"05055351",

-   138 => x"04000000",

-   139 => x"00000000",

-   140 => x"00000000",

-   141 => x"00000000",

-   142 => x"00000000",

-   143 => x"00000000",

-   144 => x"72097206",

-   145 => x"73730906",

-   146 => x"07535104",

-   147 => x"00000000",

-   148 => x"00000000",

-   149 => x"00000000",

-   150 => x"00000000",

-   151 => x"00000000",

-   152 => x"71fc0608",

-   153 => x"72830609",

-   154 => x"81058305",

-   155 => x"1010102a",

-   156 => x"81ff0652",

-   157 => x"04000000",

-   158 => x"00000000",

-   159 => x"00000000",

-   160 => x"71fc0608",

-   161 => x"0b0b80d5",

-   162 => x"e0738306",

-   163 => x"10100508",

-   164 => x"060b0b0b",

-   165 => x"88a90400",

-   166 => x"00000000",

-   167 => x"00000000",

-   168 => x"80088408",

-   169 => x"88087575",

-   170 => x"0b0b0bad",

-   171 => x"aa2d5050",

-   172 => x"80085688",

-   173 => x"0c840c80",

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-  3124 => x"00000000",

-  3125 => x"00000000",

-  3126 => x"00000000",

-  3127 => x"00000000",

-  3128 => x"00000000",

-  3129 => x"00000000",

-  3130 => x"00000000",

-  3131 => x"00000000",

-  3132 => x"00000000",

-  3133 => x"00000000",

-  3134 => x"00000000",

-  3135 => x"00000000",

-  3136 => x"00000000",

-  3137 => x"00000000",

-  3138 => x"00000000",

-  3139 => x"00000000",

-  3140 => x"00000000",

-  3141 => x"00000000",

-  3142 => x"00000000",

-  3143 => x"00000000",

-  3144 => x"00000000",

-  3145 => x"00000000",

-  3146 => x"00000000",

-  3147 => x"00000000",

-  3148 => x"00000000",

-  3149 => x"00000000",

-  3150 => x"00000000",

-  3151 => x"00000000",

-  3152 => x"00000000",

-  3153 => x"00000000",

-  3154 => x"00000000",

-  3155 => x"00000000",

-  3156 => x"00000000",

-  3157 => x"00000000",

-  3158 => x"00000000",

-  3159 => x"00000000",

-  3160 => x"00000000",

-  3161 => x"00000000",

-  3162 => x"00000000",

-  3163 => x"00000000",

-  3164 => x"00000000",

-  3165 => x"00000000",

-  3166 => x"00000000",

-  3167 => x"00000000",

-  3168 => x"00000000",

-  3169 => x"00000000",

-  3170 => x"00000000",

-  3171 => x"00000000",

-  3172 => x"00000000",

-  3173 => x"00000000",

-  3174 => x"00000000",

-  3175 => x"00000000",

-  3176 => x"00000000",

-  3177 => x"00000000",

-  3178 => x"00000000",

-  3179 => x"00000000",

-  3180 => x"00000000",

-  3181 => x"00000000",

-  3182 => x"00000000",

-  3183 => x"00000000",

-  3184 => x"00000000",

-  3185 => x"00000000",

-  3186 => x"00000000",

-  3187 => x"00000000",

-  3188 => x"00000000",

-  3189 => x"00000000",

-  3190 => x"00000000",

-  3191 => x"00000000",

-  3192 => x"00000000",

-  3193 => x"00000000",

-  3194 => x"00000000",

-  3195 => x"00000000",

-  3196 => x"00000000",

-  3197 => x"00000000",

-  3198 => x"00000000",

-  3199 => x"00000000",

-  3200 => x"00000000",

-  3201 => x"00000000",

-  3202 => x"00000000",

-  3203 => x"00000000",

-  3204 => x"00000000",

-  3205 => x"00000000",

-  3206 => x"00000000",

-  3207 => x"00000000",

-  3208 => x"00000000",

-  3209 => x"00000000",

-  3210 => x"00000000",

-  3211 => x"00000000",

-  3212 => x"00000000",

-  3213 => x"00000000",

-  3214 => x"00000000",

-  3215 => x"00000000",

-  3216 => x"00000000",

-  3217 => x"00000000",

-  3218 => x"00000000",

-  3219 => x"00000000",

-  3220 => x"00000000",

-  3221 => x"00000000",

-  3222 => x"00000000",

-  3223 => x"00000000",

-  3224 => x"00000000",

-  3225 => x"00000000",

-  3226 => x"00000000",

-  3227 => x"00000000",

-  3228 => x"00000000",

-  3229 => x"00000000",

-  3230 => x"00000000",

-  3231 => x"00000000",

-  3232 => x"00000000",

-  3233 => x"00000000",

-  3234 => x"00000000",

-  3235 => x"00000000",

-  3236 => x"00000000",

-  3237 => x"00000000",

-  3238 => x"00000000",

-  3239 => x"00000000",

-  3240 => x"00000000",

-  3241 => x"00000000",

-  3242 => x"00000000",

-  3243 => x"00000000",

-  3244 => x"00000000",

-  3245 => x"00000000",

-  3246 => x"00000000",

-  3247 => x"00000000",

-  3248 => x"00000000",

-  3249 => x"00000000",

-  3250 => x"00000000",

-  3251 => x"00002ad4",

-  3252 => x"ffffffff",

-  3253 => x"00000000",

-  3254 => x"ffffffff",

-  3255 => x"00000000",

-  3256 => x"00000000",

-	others => x"00000000"

-);

-

-begin

-

-process (clk)

-begin

-	if (clk'event and clk = '1') then

-		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then

-			report "write collision" severity failure;

-		end if;

-	

-		if (memAWriteEnable = '1') then

-			ram(to_integer(unsigned(memAAddr))) := memAWrite;

-			memARead <= memAWrite;

-		else

-			memARead <= ram(to_integer(unsigned(memAAddr)));

-		end if;

-	end if;

-end process;

-

-process (clk)

-begin

-	if (clk'event and clk = '1') then

-		if (memBWriteEnable = '1') then

-			ram(to_integer(unsigned(memBAddr))) := memBWrite;

-			memBRead <= memBWrite;

-		else

-			memBRead <= ram(to_integer(unsigned(memBAddr)));

-		end if;

-	end if;

-end process;

-

-

-

-

-end dualport_ram_arch;

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+     0 => x"0b0b0b0b",
+     1 => x"82700b0b",
+     2 => x"80d5f40c",
+     3 => x"3a0b0b80",
+     4 => x"c4fb0400",
+     5 => x"00000000",
+     6 => x"00000000",
+     7 => x"00000000",
+     8 => x"80088408",
+     9 => x"88080b0b",
+    10 => x"80c5c22d",
+    11 => x"880c840c",
+    12 => x"800c0400",
+    13 => x"00000000",
+    14 => x"00000000",
+    15 => x"00000000",
+    16 => x"71fd0608",
+    17 => x"72830609",
+    18 => x"81058205",
+    19 => x"832b2a83",
+    20 => x"ffff0652",
+    21 => x"04000000",
+    22 => x"00000000",
+    23 => x"00000000",
+    24 => x"71fd0608",
+    25 => x"83ffff73",
+    26 => x"83060981",
+    27 => x"05820583",
+    28 => x"2b2b0906",
+    29 => x"7383ffff",
+    30 => x"0b0b0b0b",
+    31 => x"83a70400",
+    32 => x"72098105",
+    33 => x"72057373",
+    34 => x"09060906",
+    35 => x"73097306",
+    36 => x"070a8106",
+    37 => x"53510400",
+    38 => x"00000000",
+    39 => x"00000000",
+    40 => x"72722473",
+    41 => x"732e0753",
+    42 => x"51040000",
+    43 => x"00000000",
+    44 => x"00000000",
+    45 => x"00000000",
+    46 => x"00000000",
+    47 => x"00000000",
+    48 => x"71737109",
+    49 => x"71068106",
+    50 => x"30720a10",
+    51 => x"0a720a10",
+    52 => x"0a31050a",
+    53 => x"81065151",
+    54 => x"53510400",
+    55 => x"00000000",
+    56 => x"72722673",
+    57 => x"732e0753",
+    58 => x"51040000",
+    59 => x"00000000",
+    60 => x"00000000",
+    61 => x"00000000",
+    62 => x"00000000",
+    63 => x"00000000",
+    64 => x"00000000",
+    65 => x"00000000",
+    66 => x"00000000",
+    67 => x"00000000",
+    68 => x"00000000",
+    69 => x"00000000",
+    70 => x"00000000",
+    71 => x"00000000",
+    72 => x"0b0b0b88",
+    73 => x"c3040000",
+    74 => x"00000000",
+    75 => x"00000000",
+    76 => x"00000000",
+    77 => x"00000000",
+    78 => x"00000000",
+    79 => x"00000000",
+    80 => x"720a722b",
+    81 => x"0a535104",
+    82 => x"00000000",
+    83 => x"00000000",
+    84 => x"00000000",
+    85 => x"00000000",
+    86 => x"00000000",
+    87 => x"00000000",
+    88 => x"72729f06",
+    89 => x"0981050b",
+    90 => x"0b0b88a6",
+    91 => x"05040000",
+    92 => x"00000000",
+    93 => x"00000000",
+    94 => x"00000000",
+    95 => x"00000000",
+    96 => x"72722aff",
+    97 => x"739f062a",
+    98 => x"0974090a",
+    99 => x"8106ff05",
+   100 => x"06075351",
+   101 => x"04000000",
+   102 => x"00000000",
+   103 => x"00000000",
+   104 => x"71715351",
+   105 => x"020d0406",
+   106 => x"73830609",
+   107 => x"81058205",
+   108 => x"832b0b2b",
+   109 => x"0772fc06",
+   110 => x"0c515104",
+   111 => x"00000000",
+   112 => x"72098105",
+   113 => x"72050970",
+   114 => x"81050906",
+   115 => x"0a810653",
+   116 => x"51040000",
+   117 => x"00000000",
+   118 => x"00000000",
+   119 => x"00000000",
+   120 => x"72098105",
+   121 => x"72050970",
+   122 => x"81050906",
+   123 => x"0a098106",
+   124 => x"53510400",
+   125 => x"00000000",
+   126 => x"00000000",
+   127 => x"00000000",
+   128 => x"71098105",
+   129 => x"52040000",
+   130 => x"00000000",
+   131 => x"00000000",
+   132 => x"00000000",
+   133 => x"00000000",
+   134 => x"00000000",
+   135 => x"00000000",
+   136 => x"72720981",
+   137 => x"05055351",
+   138 => x"04000000",
+   139 => x"00000000",
+   140 => x"00000000",
+   141 => x"00000000",
+   142 => x"00000000",
+   143 => x"00000000",
+   144 => x"72097206",
+   145 => x"73730906",
+   146 => x"07535104",
+   147 => x"00000000",
+   148 => x"00000000",
+   149 => x"00000000",
+   150 => x"00000000",
+   151 => x"00000000",
+   152 => x"71fc0608",
+   153 => x"72830609",
+   154 => x"81058305",
+   155 => x"1010102a",
+   156 => x"81ff0652",
+   157 => x"04000000",
+   158 => x"00000000",
+   159 => x"00000000",
+   160 => x"71fc0608",
+   161 => x"0b0b80d5",
+   162 => x"e0738306",
+   163 => x"10100508",
+   164 => x"060b0b0b",
+   165 => x"88a90400",
+   166 => x"00000000",
+   167 => x"00000000",
+   168 => x"80088408",
+   169 => x"88087575",
+   170 => x"0b0b0bad",
+   171 => x"aa2d5050",
+   172 => x"80085688",
+   173 => x"0c840c80",
+   174 => x"0c510400",
+   175 => x"00000000",
+   176 => x"80088408",
+   177 => x"88087575",
+   178 => x"0b0b0bad",
+   179 => x"ee2d5050",
+   180 => x"80085688",
+   181 => x"0c840c80",
+   182 => x"0c510400",
+   183 => x"00000000",
+   184 => x"72097081",
+   185 => x"0509060a",
+   186 => x"8106ff05",
+   187 => x"70547106",
+   188 => x"73097274",
+   189 => x"05ff0506",
+   190 => x"07515151",
+   191 => x"04000000",
+   192 => x"72097081",
+   193 => x"0509060a",
+   194 => x"098106ff",
+   195 => x"05705471",
+   196 => x"06730972",
+   197 => x"7405ff05",
+   198 => x"06075151",
+   199 => x"51040000",
+   200 => x"05ff0504",
+   201 => x"00000000",
+   202 => x"00000000",
+   203 => x"00000000",
+   204 => x"00000000",
+   205 => x"00000000",
+   206 => x"00000000",
+   207 => x"00000000",
+   208 => x"810b0b0b",
+   209 => x"80d5f00c",
+   210 => x"51040000",
+   211 => x"00000000",
+   212 => x"00000000",
+   213 => x"00000000",
+   214 => x"00000000",
+   215 => x"00000000",
+   216 => x"71810552",
+   217 => x"04000000",
+   218 => x"00000000",
+   219 => x"00000000",
+   220 => x"00000000",
+   221 => x"00000000",
+   222 => x"00000000",
+   223 => x"00000000",
+   224 => x"00000000",
+   225 => x"00000000",
+   226 => x"00000000",
+   227 => x"00000000",
+   228 => x"00000000",
+   229 => x"00000000",
+   230 => x"00000000",
+   231 => x"00000000",
+   232 => x"02840572",
+   233 => x"10100552",
+   234 => x"04000000",
+   235 => x"00000000",
+   236 => x"00000000",
+   237 => x"00000000",
+   238 => x"00000000",
+   239 => x"00000000",
+   240 => x"00000000",
+   241 => x"00000000",
+   242 => x"00000000",
+   243 => x"00000000",
+   244 => x"00000000",
+   245 => x"00000000",
+   246 => x"00000000",
+   247 => x"00000000",
+   248 => x"717105ff",
+   249 => x"05715351",
+   250 => x"020d0400",
+   251 => x"00000000",
+   252 => x"00000000",
+   253 => x"00000000",
+   254 => x"00000000",
+   255 => x"00000000",
+   256 => x"82fd3fbf",
+   257 => x"a03f0410",
+   258 => x"10101010",
+   259 => x"10101010",
+   260 => x"10101010",
+   261 => x"10101010",
+   262 => x"10101010",
+   263 => x"10101010",
+   264 => x"10101010",
+   265 => x"10105351",
+   266 => x"047381ff",
+   267 => x"06738306",
+   268 => x"09810583",
+   269 => x"05101010",
+   270 => x"2b0772fc",
+   271 => x"060c5151",
+   272 => x"043c0472",
+   273 => x"72807281",
+   274 => x"06ff0509",
+   275 => x"72060571",
+   276 => x"1052720a",
+   277 => x"100a5372",
+   278 => x"ed385151",
+   279 => x"535104ff",
+   280 => x"3d0d0b0b",
+   281 => x"80e5e408",
+   282 => x"52710870",
+   283 => x"882a8132",
+   284 => x"70810651",
+   285 => x"515170f1",
+   286 => x"3873720c",
+   287 => x"833d0d04",
+   288 => x"80d5f008",
+   289 => x"802ea438",
+   290 => x"80d5f408",
+   291 => x"822ebd38",
+   292 => x"8380800b",
+   293 => x"0b0b80e5",
+   294 => x"e40c82a0",
+   295 => x"800b80e5",
+   296 => x"e80c8290",
+   297 => x"800b80e5",
+   298 => x"ec0c04f8",
+   299 => x"808080a4",
+   300 => x"0b0b0b80",
+   301 => x"e5e40cf8",
+   302 => x"80808280",
+   303 => x"0b80e5e8",
+   304 => x"0cf88080",
+   305 => x"84800b80",
+   306 => x"e5ec0c04",
+   307 => x"80c0a880",
+   308 => x"8c0b0b0b",
+   309 => x"80e5e40c",
+   310 => x"80c0a880",
+   311 => x"940b80e5",
+   312 => x"e80c0b0b",
+   313 => x"80c7d00b",
+   314 => x"80e5ec0c",
+   315 => x"04f23d0d",
+   316 => x"6080e5e8",
+   317 => x"08565d82",
+   318 => x"750c8059",
+   319 => x"805a800b",
+   320 => x"8f3d5d5b",
+   321 => x"7a101015",
+   322 => x"70087108",
+   323 => x"719f2c7e",
+   324 => x"852b5855",
+   325 => x"557d5359",
+   326 => x"5799993f",
+   327 => x"7d7f7a72",
+   328 => x"077c7207",
+   329 => x"71716081",
+   330 => x"05415f5d",
+   331 => x"5b595755",
+   332 => x"817b278f",
+   333 => x"38767d0c",
+   334 => x"77841e0c",
+   335 => x"7c800c90",
+   336 => x"3d0d0480",
+   337 => x"e5e80855",
+   338 => x"ffba3970",
+   339 => x"7080e5f0",
+   340 => x"335170a7",
+   341 => x"3880d5fc",
+   342 => x"08700852",
+   343 => x"5270802e",
+   344 => x"94388412",
+   345 => x"80d5fc0c",
+   346 => x"702d80d5",
+   347 => x"fc087008",
+   348 => x"525270ee",
+   349 => x"38810b80",
+   350 => x"e5f03450",
+   351 => x"50040470",
+   352 => x"0b0b80e5",
+   353 => x"e008802e",
+   354 => x"8e380b0b",
+   355 => x"0b0b800b",
+   356 => x"802e0981",
+   357 => x"06833850",
+   358 => x"040b0b80",
+   359 => x"e5e0510b",
+   360 => x"0b0bf4dc",
+   361 => x"3f500404",
+   362 => x"ff3d0d02",
+   363 => x"8f053352",
+   364 => x"718a2e8a",
+   365 => x"387151fd",
+   366 => x"a63f833d",
+   367 => x"0d048d51",
+   368 => x"fd9d3f71",
+   369 => x"51fd983f",
+   370 => x"833d0d04",
+   371 => x"ce3d0db5",
+   372 => x"3d707084",
+   373 => x"0552088b",
+   374 => x"a85c56a5",
+   375 => x"3d5e5c80",
+   376 => x"75708105",
+   377 => x"5733765b",
+   378 => x"55587378",
+   379 => x"2e80c138",
+   380 => x"8e3d5b73",
+   381 => x"a52e0981",
+   382 => x"0680c538",
+   383 => x"78708105",
+   384 => x"5a335473",
+   385 => x"80e42e81",
+   386 => x"b6387380",
+   387 => x"e42480c6",
+   388 => x"387380e3",
+   389 => x"2ea13880",
+   390 => x"52a55179",
+   391 => x"2d805273",
+   392 => x"51792d82",
+   393 => x"18587870",
+   394 => x"81055a33",
+   395 => x"5473c438",
+   396 => x"77800cb4",
+   397 => x"3d0d047b",
+   398 => x"841d8312",
+   399 => x"33565d57",
+   400 => x"80527351",
+   401 => x"792d8118",
+   402 => x"79708105",
+   403 => x"5b335558",
+   404 => x"73ffa038",
+   405 => x"db397380",
+   406 => x"f32e0981",
+   407 => x"06ffb838",
+   408 => x"7b841d71",
+   409 => x"08595d56",
+   410 => x"80773355",
+   411 => x"5673762e",
+   412 => x"8d388116",
+   413 => x"70187033",
+   414 => x"57555674",
+   415 => x"f538ff16",
+   416 => x"55807625",
+   417 => x"ffa03876",
+   418 => x"70810558",
+   419 => x"33548052",
+   420 => x"7351792d",
+   421 => x"811875ff",
+   422 => x"17575758",
+   423 => x"807625ff",
+   424 => x"85387670",
+   425 => x"81055833",
+   426 => x"54805273",
+   427 => x"51792d81",
+   428 => x"1875ff17",
+   429 => x"57575875",
+   430 => x"8024cc38",
+   431 => x"fee8397b",
+   432 => x"841d7108",
+   433 => x"70719f2c",
+   434 => x"5953595d",
+   435 => x"56807524",
+   436 => x"81913875",
+   437 => x"7d7c5856",
+   438 => x"54805773",
+   439 => x"772e0981",
+   440 => x"06b638b0",
+   441 => x"7b3402b5",
+   442 => x"05567a76",
+   443 => x"2e9738ff",
+   444 => x"16567533",
+   445 => x"75708105",
+   446 => x"57348117",
+   447 => x"577a762e",
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+  2778 => x"00002b5c",
+  2779 => x"00002b64",
+  2780 => x"00002b64",
+  2781 => x"00002b6c",
+  2782 => x"00002b6c",
+  2783 => x"00002b74",
+  2784 => x"00002b74",
+  2785 => x"00002b7c",
+  2786 => x"00002b7c",
+  2787 => x"00002b84",
+  2788 => x"00002b84",
+  2789 => x"00002b8c",
+  2790 => x"00002b8c",
+  2791 => x"00002b94",
+  2792 => x"00002b94",
+  2793 => x"00002b9c",
+  2794 => x"00002b9c",
+  2795 => x"00002ba4",
+  2796 => x"00002ba4",
+  2797 => x"00002bac",
+  2798 => x"00002bac",
+  2799 => x"00002bb4",
+  2800 => x"00002bb4",
+  2801 => x"00002bbc",
+  2802 => x"00002bbc",
+  2803 => x"00002bc4",
+  2804 => x"00002bc4",
+  2805 => x"00002bcc",
+  2806 => x"00002bcc",
+  2807 => x"00002bd4",
+  2808 => x"00002bd4",
+  2809 => x"00002bdc",
+  2810 => x"00002bdc",
+  2811 => x"00002be4",
+  2812 => x"00002be4",
+  2813 => x"00002bec",
+  2814 => x"00002bec",
+  2815 => x"00002bf4",
+  2816 => x"00002bf4",
+  2817 => x"00002bfc",
+  2818 => x"00002bfc",
+  2819 => x"00002c04",
+  2820 => x"00002c04",
+  2821 => x"00002c0c",
+  2822 => x"00002c0c",
+  2823 => x"00002c14",
+  2824 => x"00002c14",
+  2825 => x"00002c1c",
+  2826 => x"00002c1c",
+  2827 => x"00002c24",
+  2828 => x"00002c24",
+  2829 => x"00002c2c",
+  2830 => x"00002c2c",
+  2831 => x"00002c34",
+  2832 => x"00002c34",
+  2833 => x"00002c3c",
+  2834 => x"00002c3c",
+  2835 => x"00002c44",
+  2836 => x"00002c44",
+  2837 => x"00002c4c",
+  2838 => x"00002c4c",
+  2839 => x"00002c54",
+  2840 => x"00002c54",
+  2841 => x"00002c5c",
+  2842 => x"00002c5c",
+  2843 => x"00002c64",
+  2844 => x"00002c64",
+  2845 => x"00002c6c",
+  2846 => x"00002c6c",
+  2847 => x"00002c74",
+  2848 => x"00002c74",
+  2849 => x"00002c7c",
+  2850 => x"00002c7c",
+  2851 => x"00002c84",
+  2852 => x"00002c84",
+  2853 => x"00002c8c",
+  2854 => x"00002c8c",
+  2855 => x"00002c94",
+  2856 => x"00002c94",
+  2857 => x"00002c9c",
+  2858 => x"00002c9c",
+  2859 => x"00002ca4",
+  2860 => x"00002ca4",
+  2861 => x"00002cac",
+  2862 => x"00002cac",
+  2863 => x"00002cb4",
+  2864 => x"00002cb4",
+  2865 => x"00002cbc",
+  2866 => x"00002cbc",
+  2867 => x"00002cc4",
+  2868 => x"00002cc4",
+  2869 => x"00002ccc",
+  2870 => x"00002ccc",
+  2871 => x"00002cd4",
+  2872 => x"00002cd4",
+  2873 => x"00002cdc",
+  2874 => x"00002cdc",
+  2875 => x"00002ce4",
+  2876 => x"00002ce4",
+  2877 => x"00002cec",
+  2878 => x"00002cec",
+  2879 => x"00002cf4",
+  2880 => x"00002cf4",
+  2881 => x"00002cfc",
+  2882 => x"00002cfc",
+  2883 => x"00002d04",
+  2884 => x"00002d04",
+  2885 => x"00002d0c",
+  2886 => x"00002d0c",
+  2887 => x"00002d14",
+  2888 => x"00002d14",
+  2889 => x"00002d1c",
+  2890 => x"00002d1c",
+  2891 => x"00002d24",
+  2892 => x"00002d24",
+  2893 => x"00002d2c",
+  2894 => x"00002d2c",
+  2895 => x"00002d34",
+  2896 => x"00002d34",
+  2897 => x"00002d3c",
+  2898 => x"00002d3c",
+  2899 => x"00002d44",
+  2900 => x"00002d44",
+  2901 => x"00002d4c",
+  2902 => x"00002d4c",
+  2903 => x"00002d54",
+  2904 => x"00002d54",
+  2905 => x"00002d5c",
+  2906 => x"00002d5c",
+  2907 => x"00002d64",
+  2908 => x"00002d64",
+  2909 => x"00002d6c",
+  2910 => x"00002d6c",
+  2911 => x"00002d74",
+  2912 => x"00002d74",
+  2913 => x"00002d7c",
+  2914 => x"00002d7c",
+  2915 => x"00002d84",
+  2916 => x"00002d84",
+  2917 => x"00002d8c",
+  2918 => x"00002d8c",
+  2919 => x"00002d94",
+  2920 => x"00002d94",
+  2921 => x"00002d9c",
+  2922 => x"00002d9c",
+  2923 => x"00002da4",
+  2924 => x"00002da4",
+  2925 => x"00002dac",
+  2926 => x"00002dac",
+  2927 => x"00002db4",
+  2928 => x"00002db4",
+  2929 => x"00002dbc",
+  2930 => x"00002dbc",
+  2931 => x"00002dc4",
+  2932 => x"00002dc4",
+  2933 => x"00002dcc",
+  2934 => x"00002dcc",
+  2935 => x"00002dd4",
+  2936 => x"00002dd4",
+  2937 => x"00002ddc",
+  2938 => x"00002ddc",
+  2939 => x"00002de4",
+  2940 => x"00002de4",
+  2941 => x"00002dec",
+  2942 => x"00002dec",
+  2943 => x"00002df4",
+  2944 => x"00002df4",
+  2945 => x"00002dfc",
+  2946 => x"00002dfc",
+  2947 => x"00002e04",
+  2948 => x"00002e04",
+  2949 => x"00002e0c",
+  2950 => x"00002e0c",
+  2951 => x"00002e14",
+  2952 => x"00002e14",
+  2953 => x"00002e1c",
+  2954 => x"00002e1c",
+  2955 => x"00002e24",
+  2956 => x"00002e24",
+  2957 => x"00002e2c",
+  2958 => x"00002e2c",
+  2959 => x"00002e34",
+  2960 => x"00002e34",
+  2961 => x"00002e3c",
+  2962 => x"00002e3c",
+  2963 => x"00002e44",
+  2964 => x"00002e44",
+  2965 => x"00002e4c",
+  2966 => x"00002e4c",
+  2967 => x"00002e54",
+  2968 => x"00002e54",
+  2969 => x"00002e5c",
+  2970 => x"00002e5c",
+  2971 => x"00002e64",
+  2972 => x"00002e64",
+  2973 => x"00002e6c",
+  2974 => x"00002e6c",
+  2975 => x"00002e74",
+  2976 => x"00002e74",
+  2977 => x"00002e7c",
+  2978 => x"00002e7c",
+  2979 => x"00002e84",
+  2980 => x"00002e84",
+  2981 => x"00002e8c",
+  2982 => x"00002e8c",
+  2983 => x"00002e94",
+  2984 => x"00002e94",
+  2985 => x"00002e9c",
+  2986 => x"00002e9c",
+  2987 => x"00002ea4",
+  2988 => x"00002ea4",
+  2989 => x"00002eac",
+  2990 => x"00002eac",
+  2991 => x"00002eb4",
+  2992 => x"00002eb4",
+  2993 => x"00002ebc",
+  2994 => x"00002ebc",
+  2995 => x"00002ec4",
+  2996 => x"00002ec4",
+  2997 => x"00002ecc",
+  2998 => x"00002ecc",
+  2999 => x"00002ed4",
+  3000 => x"00002ed4",
+  3001 => x"00002edc",
+  3002 => x"00002edc",
+  3003 => x"00002ee4",
+  3004 => x"00002ee4",
+  3005 => x"00002eec",
+  3006 => x"00002eec",
+  3007 => x"00002ef4",
+  3008 => x"00002ef4",
+  3009 => x"00002efc",
+  3010 => x"00002efc",
+  3011 => x"00002f04",
+  3012 => x"00002f04",
+  3013 => x"00002f0c",
+  3014 => x"00002f0c",
+  3015 => x"00002f14",
+  3016 => x"00002f14",
+  3017 => x"00002f1c",
+  3018 => x"00002f1c",
+  3019 => x"00002f24",
+  3020 => x"00002f24",
+  3021 => x"00002f2c",
+  3022 => x"00002f2c",
+  3023 => x"00002f34",
+  3024 => x"00002f34",
+  3025 => x"00002f3c",
+  3026 => x"00002f3c",
+  3027 => x"00002f50",
+  3028 => x"00000000",
+  3029 => x"000031b8",
+  3030 => x"00003214",
+  3031 => x"00003270",
+  3032 => x"00000000",
+  3033 => x"00000000",
+  3034 => x"00000000",
+  3035 => x"00000000",
+  3036 => x"00000000",
+  3037 => x"00000000",
+  3038 => x"00000000",
+  3039 => x"00000000",
+  3040 => x"00000000",
+  3041 => x"00002ad0",
+  3042 => x"00000000",
+  3043 => x"00000000",
+  3044 => x"00000000",
+  3045 => x"00000000",
+  3046 => x"00000000",
+  3047 => x"00000000",
+  3048 => x"00000000",
+  3049 => x"00000000",
+  3050 => x"00000000",
+  3051 => x"00000000",
+  3052 => x"00000000",
+  3053 => x"00000000",
+  3054 => x"00000000",
+  3055 => x"00000000",
+  3056 => x"00000000",
+  3057 => x"00000000",
+  3058 => x"00000000",
+  3059 => x"00000000",
+  3060 => x"00000000",
+  3061 => x"00000000",
+  3062 => x"00000000",
+  3063 => x"00000000",
+  3064 => x"00000000",
+  3065 => x"00000000",
+  3066 => x"00000000",
+  3067 => x"00000000",
+  3068 => x"00000000",
+  3069 => x"00000000",
+  3070 => x"00000001",
+  3071 => x"330eabcd",
+  3072 => x"1234e66d",
+  3073 => x"deec0005",
+  3074 => x"000b0000",
+  3075 => x"00000000",
+  3076 => x"00000000",
+  3077 => x"00000000",
+  3078 => x"00000000",
+  3079 => x"00000000",
+  3080 => x"00000000",
+  3081 => x"00000000",
+  3082 => x"00000000",
+  3083 => x"00000000",
+  3084 => x"00000000",
+  3085 => x"00000000",
+  3086 => x"00000000",
+  3087 => x"00000000",
+  3088 => x"00000000",
+  3089 => x"00000000",
+  3090 => x"00000000",
+  3091 => x"00000000",
+  3092 => x"00000000",
+  3093 => x"00000000",
+  3094 => x"00000000",
+  3095 => x"00000000",
+  3096 => x"00000000",
+  3097 => x"00000000",
+  3098 => x"00000000",
+  3099 => x"00000000",
+  3100 => x"00000000",
+  3101 => x"00000000",
+  3102 => x"00000000",
+  3103 => x"00000000",
+  3104 => x"00000000",
+  3105 => x"00000000",
+  3106 => x"00000000",
+  3107 => x"00000000",
+  3108 => x"00000000",
+  3109 => x"00000000",
+  3110 => x"00000000",
+  3111 => x"00000000",
+  3112 => x"00000000",
+  3113 => x"00000000",
+  3114 => x"00000000",
+  3115 => x"00000000",
+  3116 => x"00000000",
+  3117 => x"00000000",
+  3118 => x"00000000",
+  3119 => x"00000000",
+  3120 => x"00000000",
+  3121 => x"00000000",
+  3122 => x"00000000",
+  3123 => x"00000000",
+  3124 => x"00000000",
+  3125 => x"00000000",
+  3126 => x"00000000",
+  3127 => x"00000000",
+  3128 => x"00000000",
+  3129 => x"00000000",
+  3130 => x"00000000",
+  3131 => x"00000000",
+  3132 => x"00000000",
+  3133 => x"00000000",
+  3134 => x"00000000",
+  3135 => x"00000000",
+  3136 => x"00000000",
+  3137 => x"00000000",
+  3138 => x"00000000",
+  3139 => x"00000000",
+  3140 => x"00000000",
+  3141 => x"00000000",
+  3142 => x"00000000",
+  3143 => x"00000000",
+  3144 => x"00000000",
+  3145 => x"00000000",
+  3146 => x"00000000",
+  3147 => x"00000000",
+  3148 => x"00000000",
+  3149 => x"00000000",
+  3150 => x"00000000",
+  3151 => x"00000000",
+  3152 => x"00000000",
+  3153 => x"00000000",
+  3154 => x"00000000",
+  3155 => x"00000000",
+  3156 => x"00000000",
+  3157 => x"00000000",
+  3158 => x"00000000",
+  3159 => x"00000000",
+  3160 => x"00000000",
+  3161 => x"00000000",
+  3162 => x"00000000",
+  3163 => x"00000000",
+  3164 => x"00000000",
+  3165 => x"00000000",
+  3166 => x"00000000",
+  3167 => x"00000000",
+  3168 => x"00000000",
+  3169 => x"00000000",
+  3170 => x"00000000",
+  3171 => x"00000000",
+  3172 => x"00000000",
+  3173 => x"00000000",
+  3174 => x"00000000",
+  3175 => x"00000000",
+  3176 => x"00000000",
+  3177 => x"00000000",
+  3178 => x"00000000",
+  3179 => x"00000000",
+  3180 => x"00000000",
+  3181 => x"00000000",
+  3182 => x"00000000",
+  3183 => x"00000000",
+  3184 => x"00000000",
+  3185 => x"00000000",
+  3186 => x"00000000",
+  3187 => x"00000000",
+  3188 => x"00000000",
+  3189 => x"00000000",
+  3190 => x"00000000",
+  3191 => x"00000000",
+  3192 => x"00000000",
+  3193 => x"00000000",
+  3194 => x"00000000",
+  3195 => x"00000000",
+  3196 => x"00000000",
+  3197 => x"00000000",
+  3198 => x"00000000",
+  3199 => x"00000000",
+  3200 => x"00000000",
+  3201 => x"00000000",
+  3202 => x"00000000",
+  3203 => x"00000000",
+  3204 => x"00000000",
+  3205 => x"00000000",
+  3206 => x"00000000",
+  3207 => x"00000000",
+  3208 => x"00000000",
+  3209 => x"00000000",
+  3210 => x"00000000",
+  3211 => x"00000000",
+  3212 => x"00000000",
+  3213 => x"00000000",
+  3214 => x"00000000",
+  3215 => x"00000000",
+  3216 => x"00000000",
+  3217 => x"00000000",
+  3218 => x"00000000",
+  3219 => x"00000000",
+  3220 => x"00000000",
+  3221 => x"00000000",
+  3222 => x"00000000",
+  3223 => x"00000000",
+  3224 => x"00000000",
+  3225 => x"00000000",
+  3226 => x"00000000",
+  3227 => x"00000000",
+  3228 => x"00000000",
+  3229 => x"00000000",
+  3230 => x"00000000",
+  3231 => x"00000000",
+  3232 => x"00000000",
+  3233 => x"00000000",
+  3234 => x"00000000",
+  3235 => x"00000000",
+  3236 => x"00000000",
+  3237 => x"00000000",
+  3238 => x"00000000",
+  3239 => x"00000000",
+  3240 => x"00000000",
+  3241 => x"00000000",
+  3242 => x"00000000",
+  3243 => x"00000000",
+  3244 => x"00000000",
+  3245 => x"00000000",
+  3246 => x"00000000",
+  3247 => x"00000000",
+  3248 => x"00000000",
+  3249 => x"00000000",
+  3250 => x"00000000",
+  3251 => x"00002ad4",
+  3252 => x"ffffffff",
+  3253 => x"00000000",
+  3254 => x"ffffffff",
+  3255 => x"00000000",
+  3256 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(to_integer(unsigned(memAAddr))) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(to_integer(unsigned(memAAddr)));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(to_integer(unsigned(memBAddr))) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(to_integer(unsigned(memBAddr)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd
index a11bbb7..cc8d8c6 100644
--- a/zpu/hdl/example/helloworld.vhd
+++ b/zpu/hdl/example/helloworld.vhd
@@ -1,3154 +1,3154 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.numeric_std.all;

-

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-entity dualport_ram is

-port (clk : in std_logic;

-	memAWriteEnable : in std_logic;

-	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);

-	memAWrite : in std_logic_vector(wordSize-1 downto 0);

-	memARead : out std_logic_vector(wordSize-1 downto 0);

-	memBWriteEnable : in std_logic;

-	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);

-	memBWrite : in std_logic_vector(wordSize-1 downto 0);

-	memBRead : out std_logic_vector(wordSize-1 downto 0));

-end dualport_ram;

-

-architecture dualport_ram_arch of dualport_ram is

-

-

-type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);

-

-shared variable ram : ram_type :=

-(

-0 => x"0b0b0b0b",

-1 => x"82700b0b",

-2 => x"80cfd80c",

-3 => x"3a0b0b80",

-4 => x"c6d00400",

-5 => x"00000000",

-6 => x"00000000",

-7 => x"00000000",

-8 => x"80088408",

-9 => x"88080b0b",

-10 => x"80c7972d",

-11 => x"880c840c",

-12 => x"800c0400",

-13 => x"00000000",

-14 => x"00000000",

-15 => x"00000000",

-16 => x"71fd0608",

-17 => x"72830609",

-18 => x"81058205",

-19 => x"832b2a83",

-20 => x"ffff0652",

-21 => x"04000000",

-22 => x"00000000",

-23 => x"00000000",

-24 => x"71fd0608",

-25 => x"83ffff73",

-26 => x"83060981",

-27 => x"05820583",

-28 => x"2b2b0906",

-29 => x"7383ffff",

-30 => x"0b0b0b0b",

-31 => x"83a70400",

-32 => x"72098105",

-33 => x"72057373",

-34 => x"09060906",

-35 => x"73097306",

-36 => x"070a8106",

-37 => x"53510400",

-38 => x"00000000",

-39 => x"00000000",

-40 => x"72722473",

-41 => x"732e0753",

-42 => x"51040000",

-43 => x"00000000",

-44 => x"00000000",

-45 => x"00000000",

-46 => x"00000000",

-47 => x"00000000",

-48 => x"71737109",

-49 => x"71068106",

-50 => x"30720a10",

-51 => x"0a720a10",

-52 => x"0a31050a",

-53 => x"81065151",

-54 => x"53510400",

-55 => x"00000000",

-56 => x"72722673",

-57 => x"732e0753",

-58 => x"51040000",

-59 => x"00000000",

-60 => x"00000000",

-61 => x"00000000",

-62 => x"00000000",

-63 => x"00000000",

-64 => x"00000000",

-65 => x"00000000",

-66 => x"00000000",

-67 => x"00000000",

-68 => x"00000000",

-69 => x"00000000",

-70 => x"00000000",

-71 => x"00000000",

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-2647 => x"00000000",

-2648 => x"00000000",

-2649 => x"00000000",

-2650 => x"00000000",

-2651 => x"00000000",

-2652 => x"00000000",

-2653 => x"00000000",

-2654 => x"00000000",

-2655 => x"00000000",

-2656 => x"00000000",

-2657 => x"00000000",

-2658 => x"00000000",

-2659 => x"00000000",

-2660 => x"00000000",

-2661 => x"00000000",

-2662 => x"00000000",

-2663 => x"00000000",

-2664 => x"00000000",

-2665 => x"00000000",

-2666 => x"00000000",

-2667 => x"00000000",

-2668 => x"00000000",

-2669 => x"00000000",

-2670 => x"00000000",

-2671 => x"00000000",

-2672 => x"00000000",

-2673 => x"00000000",

-2674 => x"00000000",

-2675 => x"00000000",

-2676 => x"00000000",

-2677 => x"00000000",

-2678 => x"00000000",

-2679 => x"00000000",

-2680 => x"00000000",

-2681 => x"00000000",

-2682 => x"00000000",

-2683 => x"00000000",

-2684 => x"00000000",

-2685 => x"00000000",

-2686 => x"00000000",

-2687 => x"00000000",

-2688 => x"00000000",

-2689 => x"00000000",

-2690 => x"00000000",

-2691 => x"00000000",

-2692 => x"00000000",

-2693 => x"00000000",

-2694 => x"00000000",

-2695 => x"00000000",

-2696 => x"00000000",

-2697 => x"00000000",

-2698 => x"00000000",

-2699 => x"00000000",

-2700 => x"00000000",

-2701 => x"00000000",

-2702 => x"00000000",

-2703 => x"00000000",

-2704 => x"00000000",

-2705 => x"00000000",

-2706 => x"00000000",

-2707 => x"00000000",

-2708 => x"00000000",

-2709 => x"00000000",

-2710 => x"00000000",

-2711 => x"00000000",

-2712 => x"00000000",

-2713 => x"00000000",

-2714 => x"00000000",

-2715 => x"00000000",

-2716 => x"00000000",

-2717 => x"00000000",

-2718 => x"00000000",

-2719 => x"00000000",

-2720 => x"00000000",

-2721 => x"00000000",

-2722 => x"00000000",

-2723 => x"00000000",

-2724 => x"00000000",

-2725 => x"00000000",

-2726 => x"00000000",

-2727 => x"00000000",

-2728 => x"00000000",

-2729 => x"00000000",

-2730 => x"00000000",

-2731 => x"00000000",

-2732 => x"00000000",

-2733 => x"00000000",

-2734 => x"00000000",

-2735 => x"00000000",

-2736 => x"00000000",

-2737 => x"00000000",

-2738 => x"00000000",

-2739 => x"00000000",

-2740 => x"00000000",

-2741 => x"00000000",

-2742 => x"00000000",

-2743 => x"00000000",

-2744 => x"00000000",

-2745 => x"00000000",

-2746 => x"00000000",

-2747 => x"00000000",

-2748 => x"00000000",

-2749 => x"00000000",

-2750 => x"00000000",

-2751 => x"00000000",

-2752 => x"00000000",

-2753 => x"00000000",

-2754 => x"00000000",

-2755 => x"00000000",

-2756 => x"00000000",

-2757 => x"00000000",

-2758 => x"00000000",

-2759 => x"00000000",

-2760 => x"00000000",

-2761 => x"00000000",

-2762 => x"00000000",

-2763 => x"00000000",

-2764 => x"00000000",

-2765 => x"00000000",

-2766 => x"00000000",

-2767 => x"00000000",

-2768 => x"00000000",

-2769 => x"00000000",

-2770 => x"00000000",

-2771 => x"00000000",

-2772 => x"00000000",

-2773 => x"00000000",

-2774 => x"00000000",

-2775 => x"00000000",

-2776 => x"00000000",

-2777 => x"00000000",

-2778 => x"00000000",

-2779 => x"00000000",

-2780 => x"00000000",

-2781 => x"00000000",

-2782 => x"00000000",

-2783 => x"00000000",

-2784 => x"00000000",

-2785 => x"00000000",

-2786 => x"00000000",

-2787 => x"00000000",

-2788 => x"00000000",

-2789 => x"ffffffff",

-2790 => x"00000000",

-2791 => x"00020000",

-2792 => x"00000000",

-2793 => x"00000000",

-2794 => x"00002ba0",

-2795 => x"00002ba0",

-2796 => x"00002ba8",

-2797 => x"00002ba8",

-2798 => x"00002bb0",

-2799 => x"00002bb0",

-2800 => x"00002bb8",

-2801 => x"00002bb8",

-2802 => x"00002bc0",

-2803 => x"00002bc0",

-2804 => x"00002bc8",

-2805 => x"00002bc8",

-2806 => x"00002bd0",

-2807 => x"00002bd0",

-2808 => x"00002bd8",

-2809 => x"00002bd8",

-2810 => x"00002be0",

-2811 => x"00002be0",

-2812 => x"00002be8",

-2813 => x"00002be8",

-2814 => x"00002bf0",

-2815 => x"00002bf0",

-2816 => x"00002bf8",

-2817 => x"00002bf8",

-2818 => x"00002c00",

-2819 => x"00002c00",

-2820 => x"00002c08",

-2821 => x"00002c08",

-2822 => x"00002c10",

-2823 => x"00002c10",

-2824 => x"00002c18",

-2825 => x"00002c18",

-2826 => x"00002c20",

-2827 => x"00002c20",

-2828 => x"00002c28",

-2829 => x"00002c28",

-2830 => x"00002c30",

-2831 => x"00002c30",

-2832 => x"00002c38",

-2833 => x"00002c38",

-2834 => x"00002c40",

-2835 => x"00002c40",

-2836 => x"00002c48",

-2837 => x"00002c48",

-2838 => x"00002c50",

-2839 => x"00002c50",

-2840 => x"00002c58",

-2841 => x"00002c58",

-2842 => x"00002c60",

-2843 => x"00002c60",

-2844 => x"00002c68",

-2845 => x"00002c68",

-2846 => x"00002c70",

-2847 => x"00002c70",

-2848 => x"00002c78",

-2849 => x"00002c78",

-2850 => x"00002c80",

-2851 => x"00002c80",

-2852 => x"00002c88",

-2853 => x"00002c88",

-2854 => x"00002c90",

-2855 => x"00002c90",

-2856 => x"00002c98",

-2857 => x"00002c98",

-2858 => x"00002ca0",

-2859 => x"00002ca0",

-2860 => x"00002ca8",

-2861 => x"00002ca8",

-2862 => x"00002cb0",

-2863 => x"00002cb0",

-2864 => x"00002cb8",

-2865 => x"00002cb8",

-2866 => x"00002cc0",

-2867 => x"00002cc0",

-2868 => x"00002cc8",

-2869 => x"00002cc8",

-2870 => x"00002cd0",

-2871 => x"00002cd0",

-2872 => x"00002cd8",

-2873 => x"00002cd8",

-2874 => x"00002ce0",

-2875 => x"00002ce0",

-2876 => x"00002ce8",

-2877 => x"00002ce8",

-2878 => x"00002cf0",

-2879 => x"00002cf0",

-2880 => x"00002cf8",

-2881 => x"00002cf8",

-2882 => x"00002d00",

-2883 => x"00002d00",

-2884 => x"00002d08",

-2885 => x"00002d08",

-2886 => x"00002d10",

-2887 => x"00002d10",

-2888 => x"00002d18",

-2889 => x"00002d18",

-2890 => x"00002d20",

-2891 => x"00002d20",

-2892 => x"00002d28",

-2893 => x"00002d28",

-2894 => x"00002d30",

-2895 => x"00002d30",

-2896 => x"00002d38",

-2897 => x"00002d38",

-2898 => x"00002d40",

-2899 => x"00002d40",

-2900 => x"00002d48",

-2901 => x"00002d48",

-2902 => x"00002d50",

-2903 => x"00002d50",

-2904 => x"00002d58",

-2905 => x"00002d58",

-2906 => x"00002d60",

-2907 => x"00002d60",

-2908 => x"00002d68",

-2909 => x"00002d68",

-2910 => x"00002d70",

-2911 => x"00002d70",

-2912 => x"00002d78",

-2913 => x"00002d78",

-2914 => x"00002d80",

-2915 => x"00002d80",

-2916 => x"00002d88",

-2917 => x"00002d88",

-2918 => x"00002d90",

-2919 => x"00002d90",

-2920 => x"00002d98",

-2921 => x"00002d98",

-2922 => x"00002da0",

-2923 => x"00002da0",

-2924 => x"00002da8",

-2925 => x"00002da8",

-2926 => x"00002db0",

-2927 => x"00002db0",

-2928 => x"00002db8",

-2929 => x"00002db8",

-2930 => x"00002dc0",

-2931 => x"00002dc0",

-2932 => x"00002dc8",

-2933 => x"00002dc8",

-2934 => x"00002dd0",

-2935 => x"00002dd0",

-2936 => x"00002dd8",

-2937 => x"00002dd8",

-2938 => x"00002de0",

-2939 => x"00002de0",

-2940 => x"00002de8",

-2941 => x"00002de8",

-2942 => x"00002df0",

-2943 => x"00002df0",

-2944 => x"00002df8",

-2945 => x"00002df8",

-2946 => x"00002e00",

-2947 => x"00002e00",

-2948 => x"00002e08",

-2949 => x"00002e08",

-2950 => x"00002e10",

-2951 => x"00002e10",

-2952 => x"00002e18",

-2953 => x"00002e18",

-2954 => x"00002e20",

-2955 => x"00002e20",

-2956 => x"00002e28",

-2957 => x"00002e28",

-2958 => x"00002e30",

-2959 => x"00002e30",

-2960 => x"00002e38",

-2961 => x"00002e38",

-2962 => x"00002e40",

-2963 => x"00002e40",

-2964 => x"00002e48",

-2965 => x"00002e48",

-2966 => x"00002e50",

-2967 => x"00002e50",

-2968 => x"00002e58",

-2969 => x"00002e58",

-2970 => x"00002e60",

-2971 => x"00002e60",

-2972 => x"00002e68",

-2973 => x"00002e68",

-2974 => x"00002e70",

-2975 => x"00002e70",

-2976 => x"00002e78",

-2977 => x"00002e78",

-2978 => x"00002e80",

-2979 => x"00002e80",

-2980 => x"00002e88",

-2981 => x"00002e88",

-2982 => x"00002e90",

-2983 => x"00002e90",

-2984 => x"00002e98",

-2985 => x"00002e98",

-2986 => x"00002ea0",

-2987 => x"00002ea0",

-2988 => x"00002ea8",

-2989 => x"00002ea8",

-2990 => x"00002eb0",

-2991 => x"00002eb0",

-2992 => x"00002eb8",

-2993 => x"00002eb8",

-2994 => x"00002ec0",

-2995 => x"00002ec0",

-2996 => x"00002ec8",

-2997 => x"00002ec8",

-2998 => x"00002ed0",

-2999 => x"00002ed0",

-3000 => x"00002ed8",

-3001 => x"00002ed8",

-3002 => x"00002ee0",

-3003 => x"00002ee0",

-3004 => x"00002ee8",

-3005 => x"00002ee8",

-3006 => x"00002ef0",

-3007 => x"00002ef0",

-3008 => x"00002ef8",

-3009 => x"00002ef8",

-3010 => x"00002f00",

-3011 => x"00002f00",

-3012 => x"00002f08",

-3013 => x"00002f08",

-3014 => x"00002f10",

-3015 => x"00002f10",

-3016 => x"00002f18",

-3017 => x"00002f18",

-3018 => x"00002f20",

-3019 => x"00002f20",

-3020 => x"00002f28",

-3021 => x"00002f28",

-3022 => x"00002f30",

-3023 => x"00002f30",

-3024 => x"00002f38",

-3025 => x"00002f38",

-3026 => x"00002f40",

-3027 => x"00002f40",

-3028 => x"00002f48",

-3029 => x"00002f48",

-3030 => x"00002f50",

-3031 => x"00002f50",

-3032 => x"00002f58",

-3033 => x"00002f58",

-3034 => x"00002f60",

-3035 => x"00002f60",

-3036 => x"00002f68",

-3037 => x"00002f68",

-3038 => x"00002f70",

-3039 => x"00002f70",

-3040 => x"00002f78",

-3041 => x"00002f78",

-3042 => x"00002f80",

-3043 => x"00002f80",

-3044 => x"00002f88",

-3045 => x"00002f88",

-3046 => x"00002f90",

-3047 => x"00002f90",

-3048 => x"00002f98",

-3049 => x"00002f98",

-3050 => x"000027b8",

-3051 => x"ffffffff",

-3052 => x"00000000",

-3053 => x"ffffffff",

-3054 => x"00000000",

-	others => x"00000000"

-);

-

-begin

-

-process (clk)

-begin

-	if (clk'event and clk = '1') then

-		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then

-			report "write collision" severity failure;

-		end if;

-	

-		if (memAWriteEnable = '1') then

-			ram(to_integer(unsigned(memAAddr))) := memAWrite;

-			memARead <= memAWrite;

-		else

-			memARead <= ram(to_integer(unsigned(memAAddr)));

-		end if;

-	end if;

-end process;

-

-process (clk)

-begin

-	if (clk'event and clk = '1') then

-		if (memBWriteEnable = '1') then

-			ram(to_integer(unsigned(memBAddr))) := memBWrite;

-			memBRead <= memBWrite;

-		else

-			memBRead <= ram(to_integer(unsigned(memBAddr)));

-		end if;

-	end if;

-end process;

-

-

-

-

-end dualport_ram_arch;

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"c4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"9f2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"e32d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
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+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"ffffffff",
+2790 => x"00000000",
+2791 => x"00020000",
+2792 => x"00000000",
+2793 => x"00000000",
+2794 => x"00002ba0",
+2795 => x"00002ba0",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(to_integer(unsigned(memAAddr))) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(to_integer(unsigned(memAAddr)));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(to_integer(unsigned(memBAddr))) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(to_integer(unsigned(memBAddr)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/interrupt.vhd b/zpu/hdl/example/interrupt.vhd
index ededf85..d2bc709 100644
--- a/zpu/hdl/example/interrupt.vhd
+++ b/zpu/hdl/example/interrupt.vhd
@@ -1,3156 +1,3156 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.numeric_std.all;

-

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-entity dualport_ram is

-port (clk : in std_logic;

-	memAWriteEnable : in std_logic;

-	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);

-	memAWrite : in std_logic_vector(wordSize-1 downto 0);

-	memARead : out std_logic_vector(wordSize-1 downto 0);

-	memBWriteEnable : in std_logic;

-	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);

-	memBWrite : in std_logic_vector(wordSize-1 downto 0);

-	memBRead : out std_logic_vector(wordSize-1 downto 0));

-end dualport_ram;

-

-architecture dualport_ram_arch of dualport_ram is

-

-

-type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);

-

-shared variable ram : ram_type :=

-(

-0 => x"0b0b0b0b",

-1 => x"82700b0b",

-2 => x"80cfe00c",

-3 => x"3a0b0b80",

-4 => x"c6e00400",

-5 => x"00000000",

-6 => x"00000000",

-7 => x"00000000",

-8 => x"80088408",

-9 => x"88080b0b",

-10 => x"0b8af02d",

-11 => x"880c840c",

-12 => x"800c0400",

-13 => x"00000000",

-14 => x"00000000",

-15 => x"00000000",

-16 => x"71fd0608",

-17 => x"72830609",

-18 => x"81058205",

-19 => x"832b2a83",

-20 => x"ffff0652",

-21 => x"04000000",

-22 => x"00000000",

-23 => x"00000000",

-24 => x"71fd0608",

-25 => x"83ffff73",

-26 => x"83060981",

-27 => x"05820583",

-28 => x"2b2b0906",

-29 => x"7383ffff",

-30 => x"0b0b0b0b",

-31 => x"83a70400",

-32 => x"72098105",

-33 => x"72057373",

-34 => x"09060906",

-35 => x"73097306",

-36 => x"070a8106",

-37 => x"53510400",

-38 => x"00000000",

-39 => x"00000000",

-40 => x"72722473",

-41 => x"732e0753",

-42 => x"51040000",

-43 => x"00000000",

-44 => x"00000000",

-45 => x"00000000",

-46 => x"00000000",

-47 => x"00000000",

-48 => x"71737109",

-49 => x"71068106",

-50 => x"30720a10",

-51 => x"0a720a10",

-52 => x"0a31050a",

-53 => x"81065151",

-54 => x"53510400",

-55 => x"00000000",

-56 => x"72722673",

-57 => x"732e0753",

-58 => x"51040000",

-59 => x"00000000",

-60 => x"00000000",

-61 => x"00000000",

-62 => x"00000000",

-63 => x"00000000",

-64 => x"00000000",

-65 => x"00000000",

-66 => x"00000000",

-67 => x"00000000",

-68 => x"00000000",

-69 => x"00000000",

-70 => x"00000000",

-71 => x"00000000",

-72 => x"0b0b0b88",

-73 => x"c4040000",

-74 => x"00000000",

-75 => x"00000000",

-76 => x"00000000",

-77 => x"00000000",

-78 => x"00000000",

-79 => x"00000000",

-80 => x"720a722b",

-81 => x"0a535104",

-82 => x"00000000",

-83 => x"00000000",

-84 => x"00000000",

-85 => x"00000000",

-86 => x"00000000",

-87 => x"00000000",

-88 => x"72729f06",

-89 => x"0981050b",

-90 => x"0b0b88a7",

-91 => x"05040000",

-92 => x"00000000",

-93 => x"00000000",

-94 => x"00000000",

-95 => x"00000000",

-96 => x"72722aff",

-97 => x"739f062a",

-98 => x"0974090a",

-99 => x"8106ff05",

-100 => x"06075351",

-101 => x"04000000",

-102 => x"00000000",

-103 => x"00000000",

-104 => x"71715351",

-105 => x"020d0406",

-106 => x"73830609",

-107 => x"81058205",

-108 => x"832b0b2b",

-109 => x"0772fc06",

-110 => x"0c515104",

-111 => x"00000000",

-112 => x"72098105",

-113 => x"72050970",

-114 => x"81050906",

-115 => x"0a810653",

-116 => x"51040000",

-117 => x"00000000",

-118 => x"00000000",

-119 => x"00000000",

-120 => x"72098105",

-121 => x"72050970",

-122 => x"81050906",

-123 => x"0a098106",

-124 => x"53510400",

-125 => x"00000000",

-126 => x"00000000",

-127 => x"00000000",

-128 => x"71098105",

-129 => x"52040000",

-130 => x"00000000",

-131 => x"00000000",

-132 => x"00000000",

-133 => x"00000000",

-134 => x"00000000",

-135 => x"00000000",

-136 => x"72720981",

-137 => x"05055351",

-138 => x"04000000",

-139 => x"00000000",

-140 => x"00000000",

-141 => x"00000000",

-142 => x"00000000",

-143 => x"00000000",

-144 => x"72097206",

-145 => x"73730906",

-146 => x"07535104",

-147 => x"00000000",

-148 => x"00000000",

-149 => x"00000000",

-150 => x"00000000",

-151 => x"00000000",

-152 => x"71fc0608",

-153 => x"72830609",

-154 => x"81058305",

-155 => x"1010102a",

-156 => x"81ff0652",

-157 => x"04000000",

-158 => x"00000000",

-159 => x"00000000",

-160 => x"71fc0608",

-161 => x"0b0b80cf",

-162 => x"cc738306",

-163 => x"10100508",

-164 => x"060b0b0b",

-165 => x"88aa0400",

-166 => x"00000000",

-167 => x"00000000",

-168 => x"80088408",

-169 => x"88087575",

-170 => x"0b0b0b8b",

-171 => x"ab2d5050",

-172 => x"80085688",

-173 => x"0c840c80",

-174 => x"0c510400",

-175 => x"00000000",

-176 => x"80088408",

-177 => x"88087575",

-178 => x"0b0b0b8b",

-179 => x"ef2d5050",

-180 => x"80085688",

-181 => x"0c840c80",

-182 => x"0c510400",

-183 => x"00000000",

-184 => x"72097081",

-185 => x"0509060a",

-186 => x"8106ff05",

-187 => x"70547106",

-188 => x"73097274",

-189 => x"05ff0506",

-190 => x"07515151",

-191 => x"04000000",

-192 => x"72097081",

-193 => x"0509060a",

-194 => x"098106ff",

-195 => x"05705471",

-196 => x"06730972",

-197 => x"7405ff05",

-198 => x"06075151",

-199 => x"51040000",

-200 => x"05ff0504",

-201 => x"00000000",

-202 => x"00000000",

-203 => x"00000000",

-204 => x"00000000",

-205 => x"00000000",

-206 => x"00000000",

-207 => x"00000000",

-208 => x"810b0b0b",

-209 => x"80cfdc0c",

-210 => x"51040000",

-211 => x"00000000",

-212 => x"00000000",

-213 => x"00000000",

-214 => x"00000000",

-215 => x"00000000",

-216 => x"71810552",

-217 => x"04000000",

-218 => x"00000000",

-219 => x"00000000",

-220 => x"00000000",

-221 => x"00000000",

-222 => x"00000000",

-223 => x"00000000",

-224 => x"00000000",

-225 => x"00000000",

-226 => x"00000000",

-227 => x"00000000",

-228 => x"00000000",

-229 => x"00000000",

-230 => x"00000000",

-231 => x"00000000",

-232 => x"02840572",

-233 => x"10100552",

-234 => x"04000000",

-235 => x"00000000",

-236 => x"00000000",

-237 => x"00000000",

-238 => x"00000000",

-239 => x"00000000",

-240 => x"00000000",

-241 => x"00000000",

-242 => x"00000000",

-243 => x"00000000",

-244 => x"00000000",

-245 => x"00000000",

-246 => x"00000000",

-247 => x"00000000",

-248 => x"717105ff",

-249 => x"05715351",

-250 => x"020d0400",

-251 => x"00000000",

-252 => x"00000000",

-253 => x"00000000",

-254 => x"00000000",

-255 => x"00000000",

-256 => x"82c53f80",

-257 => x"c6e63f04",

-258 => x"10101010",

-259 => x"10101010",

-260 => x"10101010",

-261 => x"10101010",

-262 => x"10101010",

-263 => x"10101010",

-264 => x"10101010",

-265 => x"10101053",

-266 => x"51047381",

-267 => x"ff067383",

-268 => x"06098105",

-269 => x"83051010",

-270 => x"102b0772",

-271 => x"fc060c51",

-272 => x"51043c04",

-273 => x"72728072",

-274 => x"8106ff05",

-275 => x"09720605",

-276 => x"71105272",

-277 => x"0a100a53",

-278 => x"72ed3851",

-279 => x"51535104",

-280 => x"fe3d0d0b",

-281 => x"0b80dfc8",

-282 => x"08538413",

-283 => x"0870882a",

-284 => x"70810651",

-285 => x"52527080",

-286 => x"2ef03871",

-287 => x"81ff0680",

-288 => x"0c843d0d",

-289 => x"04ff3d0d",

-290 => x"0b0b80df",

-291 => x"c8085271",

-292 => x"0870882a",

-293 => x"81327081",

-294 => x"06515151",

-295 => x"70f13873",

-296 => x"720c833d",

-297 => x"0d0480cf",

-298 => x"dc08802e",

-299 => x"a43880cf",

-300 => x"e008822e",

-301 => x"bd388380",

-302 => x"800b0b0b",

-303 => x"80dfc80c",

-304 => x"82a0800b",

-305 => x"80dfcc0c",

-306 => x"8290800b",

-307 => x"80dfd00c",

-308 => x"04f88080",

-309 => x"80a40b0b",

-310 => x"0b80dfc8",

-311 => x"0cf88080",

-312 => x"82800b80",

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-2883 => x"00002d00",

-2884 => x"00002d08",

-2885 => x"00002d08",

-2886 => x"00002d10",

-2887 => x"00002d10",

-2888 => x"00002d18",

-2889 => x"00002d18",

-2890 => x"00002d20",

-2891 => x"00002d20",

-2892 => x"00002d28",

-2893 => x"00002d28",

-2894 => x"00002d30",

-2895 => x"00002d30",

-2896 => x"00002d38",

-2897 => x"00002d38",

-2898 => x"00002d40",

-2899 => x"00002d40",

-2900 => x"00002d48",

-2901 => x"00002d48",

-2902 => x"00002d50",

-2903 => x"00002d50",

-2904 => x"00002d58",

-2905 => x"00002d58",

-2906 => x"00002d60",

-2907 => x"00002d60",

-2908 => x"00002d68",

-2909 => x"00002d68",

-2910 => x"00002d70",

-2911 => x"00002d70",

-2912 => x"00002d78",

-2913 => x"00002d78",

-2914 => x"00002d80",

-2915 => x"00002d80",

-2916 => x"00002d88",

-2917 => x"00002d88",

-2918 => x"00002d90",

-2919 => x"00002d90",

-2920 => x"00002d98",

-2921 => x"00002d98",

-2922 => x"00002da0",

-2923 => x"00002da0",

-2924 => x"00002da8",

-2925 => x"00002da8",

-2926 => x"00002db0",

-2927 => x"00002db0",

-2928 => x"00002db8",

-2929 => x"00002db8",

-2930 => x"00002dc0",

-2931 => x"00002dc0",

-2932 => x"00002dc8",

-2933 => x"00002dc8",

-2934 => x"00002dd0",

-2935 => x"00002dd0",

-2936 => x"00002dd8",

-2937 => x"00002dd8",

-2938 => x"00002de0",

-2939 => x"00002de0",

-2940 => x"00002de8",

-2941 => x"00002de8",

-2942 => x"00002df0",

-2943 => x"00002df0",

-2944 => x"00002df8",

-2945 => x"00002df8",

-2946 => x"00002e00",

-2947 => x"00002e00",

-2948 => x"00002e08",

-2949 => x"00002e08",

-2950 => x"00002e10",

-2951 => x"00002e10",

-2952 => x"00002e18",

-2953 => x"00002e18",

-2954 => x"00002e20",

-2955 => x"00002e20",

-2956 => x"00002e28",

-2957 => x"00002e28",

-2958 => x"00002e30",

-2959 => x"00002e30",

-2960 => x"00002e38",

-2961 => x"00002e38",

-2962 => x"00002e40",

-2963 => x"00002e40",

-2964 => x"00002e48",

-2965 => x"00002e48",

-2966 => x"00002e50",

-2967 => x"00002e50",

-2968 => x"00002e58",

-2969 => x"00002e58",

-2970 => x"00002e60",

-2971 => x"00002e60",

-2972 => x"00002e68",

-2973 => x"00002e68",

-2974 => x"00002e70",

-2975 => x"00002e70",

-2976 => x"00002e78",

-2977 => x"00002e78",

-2978 => x"00002e80",

-2979 => x"00002e80",

-2980 => x"00002e88",

-2981 => x"00002e88",

-2982 => x"00002e90",

-2983 => x"00002e90",

-2984 => x"00002e98",

-2985 => x"00002e98",

-2986 => x"00002ea0",

-2987 => x"00002ea0",

-2988 => x"00002ea8",

-2989 => x"00002ea8",

-2990 => x"00002eb0",

-2991 => x"00002eb0",

-2992 => x"00002eb8",

-2993 => x"00002eb8",

-2994 => x"00002ec0",

-2995 => x"00002ec0",

-2996 => x"00002ec8",

-2997 => x"00002ec8",

-2998 => x"00002ed0",

-2999 => x"00002ed0",

-3000 => x"00002ed8",

-3001 => x"00002ed8",

-3002 => x"00002ee0",

-3003 => x"00002ee0",

-3004 => x"00002ee8",

-3005 => x"00002ee8",

-3006 => x"00002ef0",

-3007 => x"00002ef0",

-3008 => x"00002ef8",

-3009 => x"00002ef8",

-3010 => x"00002f00",

-3011 => x"00002f00",

-3012 => x"00002f08",

-3013 => x"00002f08",

-3014 => x"00002f10",

-3015 => x"00002f10",

-3016 => x"00002f18",

-3017 => x"00002f18",

-3018 => x"00002f20",

-3019 => x"00002f20",

-3020 => x"00002f28",

-3021 => x"00002f28",

-3022 => x"00002f30",

-3023 => x"00002f30",

-3024 => x"00002f38",

-3025 => x"00002f38",

-3026 => x"00002f40",

-3027 => x"00002f40",

-3028 => x"00002f48",

-3029 => x"00002f48",

-3030 => x"00002f50",

-3031 => x"00002f50",

-3032 => x"00002f58",

-3033 => x"00002f58",

-3034 => x"00002f60",

-3035 => x"00002f60",

-3036 => x"00002f68",

-3037 => x"00002f68",

-3038 => x"00002f70",

-3039 => x"00002f70",

-3040 => x"00002f78",

-3041 => x"00002f78",

-3042 => x"00002f80",

-3043 => x"00002f80",

-3044 => x"00002f88",

-3045 => x"00002f88",

-3046 => x"00002f90",

-3047 => x"00002f90",

-3048 => x"00002f98",

-3049 => x"00002f98",

-3050 => x"00002fa0",

-3051 => x"00002fa0",

-3052 => x"000027c0",

-3053 => x"ffffffff",

-3054 => x"00000000",

-3055 => x"ffffffff",

-3056 => x"00000000",

-	others => x"00000000"

-);

-

-begin

-

-process (clk)

-begin

-	if (clk'event and clk = '1') then

-		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then

-			report "write collision" severity failure;

-		end if;

-	

-		if (memAWriteEnable = '1') then

-			ram(to_integer(unsigned(memAAddr))) := memAWrite;

-			memARead <= memAWrite;

-		else

-			memARead <= ram(to_integer(unsigned(memAAddr)));

-		end if;

-	end if;

-end process;

-

-process (clk)

-begin

-	if (clk'event and clk = '1') then

-		if (memBWriteEnable = '1') then

-			ram(to_integer(unsigned(memBAddr))) := memBWrite;

-			memBRead <= memBWrite;

-		else

-			memBRead <= ram(to_integer(unsigned(memBAddr)));

-		end if;

-	end if;

-end process;

-

-

-

-

-end dualport_ram_arch;

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfe00c",
+3 => x"3a0b0b80",
+4 => x"c6e00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0b8af02d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"cc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"ab2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"ef2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfdc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6e63f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc8",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c8085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"dc08802e",
+299 => x"a43880cf",
+300 => x"e008822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc80c",
+304 => x"82a0800b",
+305 => x"80dfcc0c",
+306 => x"8290800b",
+307 => x"80dfd00c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc8",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfcc0cf8",
+314 => x"80808480",
+315 => x"0b80dfd0",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c80c80c0",
+320 => x"a880940b",
+321 => x"80dfcc0c",
+322 => x"0b0b80cf",
+323 => x"980b80df",
+324 => x"d00c0470",
+325 => x"7080dfd4",
+326 => x"335170a7",
+327 => x"3880cfe8",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe80c",
+332 => x"702d80cf",
+333 => x"e8087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfd43450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"c408802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
+342 => x"802e0981",
+343 => x"06833850",
+344 => x"040b0b80",
+345 => x"dfc4510b",
+346 => x"0b0bf594",
+347 => x"3f500404",
+348 => x"803d0d80",
+349 => x"dfe00881",
+350 => x"1180dfe0",
+351 => x"0c51823d",
+352 => x"0d04fe3d",
+353 => x"0d80dfe0",
+354 => x"085380df",
+355 => x"e0085272",
+356 => x"722e8f38",
+357 => x"80cf9c51",
+358 => x"82b03f80",
+359 => x"dfe00853",
+360 => x"e93980cf",
+361 => x"ac5182a2",
+362 => x"3fe039fb",
+363 => x"3d0d7779",
+364 => x"55558056",
+365 => x"757524ab",
+366 => x"38807424",
+367 => x"9d388053",
+368 => x"73527451",
+369 => x"80e13f80",
+370 => x"08547580",
+371 => x"2e853880",
+372 => x"08305473",
+373 => x"800c873d",
+374 => x"0d047330",
+375 => x"76813257",
+376 => x"54dc3974",
+377 => x"30558156",
+378 => x"738025d2",
+379 => x"38ec39fa",
+380 => x"3d0d787a",
+381 => x"57558057",
+382 => x"767524a4",
+383 => x"38759f2c",
+384 => x"54815375",
+385 => x"74327431",
+386 => x"5274519b",
+387 => x"3f800854",
+388 => x"76802e85",
+389 => x"38800830",
+390 => x"5473800c",
+391 => x"883d0d04",
+392 => x"74305581",
+393 => x"57d739fc",
+394 => x"3d0d7678",
+395 => x"53548153",
+396 => x"80747326",
+397 => x"52557280",
+398 => x"2e983870",
+399 => x"802eab38",
+400 => x"807224a6",
+401 => x"38711073",
+402 => x"10757226",
+403 => x"53545272",
+404 => x"ea387351",
+405 => x"78833874",
+406 => x"5170800c",
+407 => x"863d0d04",
+408 => x"720a100a",
+409 => x"720a100a",
+410 => x"53537280",
+411 => x"2ee43871",
+412 => x"7426ed38",
+413 => x"73723175",
+414 => x"7407740a",
+415 => x"100a740a",
+416 => x"100a5555",
+417 => x"5654e339",
+418 => x"f73d0d7c",
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+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"00002fa0",
+3051 => x"00002fa0",
+3052 => x"000027c0",
+3053 => x"ffffffff",
+3054 => x"00000000",
+3055 => x"ffffffff",
+3056 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(to_integer(unsigned(memAAddr))) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(to_integer(unsigned(memAAddr)));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(to_integer(unsigned(memBAddr))) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(to_integer(unsigned(memBAddr)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd
index f36a285..e671460 100644
--- a/zpu/hdl/example/sim_small_fpga_top.vhd
+++ b/zpu/hdl/example/sim_small_fpga_top.vhd
@@ -1,207 +1,207 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.--------------------------------------------------------------------------------

-

-library IEEE;

-use IEEE.STD_LOGIC_1164.ALL;

-use ieee.numeric_std.all;

-

----- Uncomment the following library declaration if instantiating

----- any Xilinx primitives in this code.

---library UNISIM;

---use UNISIM.VComponents.all;

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-entity fpga_top is

-end fpga_top;

-

-architecture behave of fpga_top is

-

-

-signal clk : std_logic;

-

-signal	areset			: std_logic := '1';

-

-

-component  zpu_io is

-  generic (

-           log_file:       string  := "log.txt"

-          );

-  port(

-       	clk         : in std_logic;

-       	areset        : in std_logic;

-		busy : out std_logic;

-		writeEnable : in std_logic;

-		readEnable : in std_logic;

-		write	: in std_logic_vector(wordSize-1 downto 0);

-		read	: out std_logic_vector(wordSize-1 downto 0);

-		addr : in std_logic_vector(maxAddrBit downto minAddrBit)

-		);

-end component;

-

-

-

-

-

-signal			  mem_busy : std_logic;

-signal			  mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);

-signal			  mem_writeEnable : std_logic; 

-signal			  mem_readEnable : std_logic;

-signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-signal			  enable : std_logic;

-

-signal			  dram_mem_busy : std_logic;

-signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_writeEnable : std_logic; 

-signal			  dram_mem_readEnable : std_logic;

-signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-

-signal	 		  io_busy : std_logic;

-

-signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  io_mem_writeEnable : std_logic; 

-signal			  io_mem_readEnable : std_logic;

-

-

-signal			  dram_ready : std_logic;

-signal			  io_ready : std_logic;

-signal			  io_reading : std_logic;

-signal			  interruptcounter : unsigned(15 downto 0);

-signal			  interrupt : std_logic;

-

-

-

-signal break : std_logic;

-

-begin

-

-	zpu: zpu_core port map (

-		clk => clk ,

-	 	areset => areset,

-	 	enable => enable,

- 		in_mem_busy => mem_busy, 

- 		mem_read => mem_read,

- 		mem_write => mem_write, 

-		out_mem_addr => mem_addr, 

-		out_mem_writeEnable => mem_writeEnable,  

-		out_mem_readEnable => mem_readEnable,

- 		mem_writeMask => mem_writeMask, 

- 		interrupt => interrupt,

- 		break  => break);

-

-

-	ioMap: zpu_io port map (

-       	clk => clk,

-	 	areset => areset,

-		busy => io_busy,

-		writeEnable => io_mem_writeEnable,

-		readEnable => io_mem_readEnable,

-		write	=> mem_write,

-		read	=> io_mem_read,

-		addr => mem_addr(maxAddrBit downto minAddrBit)

-	);

-

-	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);

-	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);

-	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);

-	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);

-	mem_busy <= io_busy;

-	

-	

-

-	-- Memory reads either come from IO or DRAM. We need to pick the right one.

-	memorycontrol:

-	process(dram_mem_read, dram_ready, io_ready, io_mem_read)

-	begin

-		mem_read <= (others => 'U');

-		if dram_ready='1' then

-			mem_read <= dram_mem_read;

-		end if;

-			 

-		if io_ready='1' then

-			mem_read <= (others => '0');

-			mem_read <= io_mem_read;

-		end if;

-	end process;

-

-

-	

-	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;

-

-	memoryControlSync:

-	process(clk, areset)

-	begin

-		if areset = '1' then

-			enable <= '0';

-			io_reading <= '0';

-			dram_ready <= '0';

-			

-		    interruptcounter <= to_unsigned(0, 16);

-			interrupt <= '0'; 

-		    

-		elsif (clk'event and clk = '1') then

-			enable <= '1';

-			io_reading <= io_busy or io_mem_readEnable; 

-			dram_ready<=dram_mem_readEnable;

-			

-			-- keep interrupt signal high for 16 cycles

-		    interruptcounter <= interruptcounter + 1;

-			if (interruptcounter < 16) then

-  				report "Interrupt asserted!" severity note;

-				interrupt <='1';

-			else

-				interrupt <='0';

-			end if;

-		end if;

-	end process;

-

-	-- wiggle the clock @ 100MHz

-	clock : PROCESS

-	   begin

-   			clk <= '0';

-		   wait for 5 ns; 

-   			clk <= '1';

-		   wait for 5 ns; 

-		   areset <= '0';

-	end PROCESS clock;

-

-

-end behave;

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity fpga_top is
+end fpga_top;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal	areset			: std_logic := '1';
+
+
+component  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end component;
+
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  enable : std_logic;
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+signal	 		  io_busy : std_logic;
+
+signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  io_mem_writeEnable : std_logic; 
+signal			  io_mem_readEnable : std_logic;
+
+
+signal			  dram_ready : std_logic;
+signal			  io_ready : std_logic;
+signal			  io_reading : std_logic;
+signal			  interruptcounter : unsigned(15 downto 0);
+signal			  interrupt : std_logic;
+
+
+
+signal break : std_logic;
+
+begin
+
+	zpu: zpu_core port map (
+		clk => clk ,
+	 	areset => areset,
+	 	enable => enable,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => interrupt,
+ 		break  => break);
+
+
+	ioMap: zpu_io port map (
+       	clk => clk,
+	 	areset => areset,
+		busy => io_busy,
+		writeEnable => io_mem_writeEnable,
+		readEnable => io_mem_readEnable,
+		write	=> mem_write,
+		read	=> io_mem_read,
+		addr => mem_addr(maxAddrBit downto minAddrBit)
+	);
+
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy;
+	
+	
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+	begin
+		mem_read <= (others => 'U');
+		if dram_ready='1' then
+			mem_read <= dram_mem_read;
+		end if;
+			 
+		if io_ready='1' then
+			mem_read <= (others => '0');
+			mem_read <= io_mem_read;
+		end if;
+	end process;
+
+
+	
+	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+	memoryControlSync:
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			enable <= '0';
+			io_reading <= '0';
+			dram_ready <= '0';
+			
+		    interruptcounter <= to_unsigned(0, 16);
+			interrupt <= '0'; 
+		    
+		elsif (clk'event and clk = '1') then
+			enable <= '1';
+			io_reading <= io_busy or io_mem_readEnable; 
+			dram_ready<=dram_mem_readEnable;
+			
+			-- keep interrupt signal high for 16 cycles
+		    interruptcounter <= interruptcounter + 1;
+			if (interruptcounter < 16) then
+  				report "Interrupt asserted!" severity note;
+				interrupt <='1';
+			else
+				interrupt <='0';
+			end if;
+		end if;
+	end process;
+
+	-- wiggle the clock @ 100MHz
+	clock : PROCESS
+	   begin
+   			clk <= '0';
+		   wait for 5 ns; 
+   			clk <= '1';
+		   wait for 5 ns; 
+		   areset <= '0';
+	end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/example/sim_small_fpga_top_noint.vhd b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
index b342d26..0edb8c7 100644
--- a/zpu/hdl/example/sim_small_fpga_top_noint.vhd
+++ b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
@@ -1,193 +1,193 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library IEEE;

-use IEEE.STD_LOGIC_1164.ALL;

-use ieee.numeric_std.all;

-

----- Uncomment the following library declaration if instantiating

----- any Xilinx primitives in this code.

---library UNISIM;

---use UNISIM.VComponents.all;

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-entity fpga_top is

-end fpga_top;

-

-architecture behave of fpga_top is

-

-

-signal clk : std_logic;

-

-signal	areset			: std_logic := '1';

-

-

-component  zpu_io is

-  generic (

-           log_file:       string  := "log.txt"

-          );

-  port(

-       	clk         : in std_logic;

-       	areset        : in std_logic;

-		busy : out std_logic;

-		writeEnable : in std_logic;

-		readEnable : in std_logic;

-		write	: in std_logic_vector(wordSize-1 downto 0);

-		read	: out std_logic_vector(wordSize-1 downto 0);

-		addr : in std_logic_vector(maxAddrBit downto minAddrBit)

-		);

-end component;

-

-

-

-

-

-signal			  mem_busy : std_logic;

-signal			  mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);

-signal			  mem_writeEnable : std_logic; 

-signal			  mem_readEnable : std_logic;

-signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-signal			  enable : std_logic;

-

-signal			  dram_mem_busy : std_logic;

-signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_writeEnable : std_logic; 

-signal			  dram_mem_readEnable : std_logic;

-signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-

-signal	 		  io_busy : std_logic;

-

-signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  io_mem_writeEnable : std_logic; 

-signal			  io_mem_readEnable : std_logic;

-

-

-signal			  dram_ready : std_logic;

-signal			  io_ready : std_logic;

-signal			  io_reading : std_logic;

-

-

-

-signal break : std_logic;

-

-begin

-

-	zpu: zpu_core port map (

-		clk => clk ,

-	 	areset => areset,

-	 	enable => enable,

- 		in_mem_busy => mem_busy, 

- 		mem_read => mem_read,

- 		mem_write => mem_write, 

-		out_mem_addr => mem_addr, 

-		out_mem_writeEnable => mem_writeEnable,  

-		out_mem_readEnable => mem_readEnable,

- 		mem_writeMask => mem_writeMask, 

- 		interrupt => '0',

- 		break  => break);

-

-

-	ioMap: zpu_io port map (

-       	clk => clk,

-	 	areset => areset,

-		busy => io_busy,

-		writeEnable => io_mem_writeEnable,

-		readEnable => io_mem_readEnable,

-		write	=> mem_write,

-		read	=> io_mem_read,

-		addr => mem_addr(maxAddrBit downto minAddrBit)

-	);

-

-	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);

-	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);

-	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);

-	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);

-	mem_busy <= io_busy;

-	

-	

-

-	-- Memory reads either come from IO or DRAM. We need to pick the right one.

-	memorycontrol:

-	process(dram_mem_read, dram_ready, io_ready, io_mem_read)

-	begin

-		mem_read <= (others => 'U');

-		if dram_ready='1' then

-			mem_read <= dram_mem_read;

-		end if;

-			 

-		if io_ready='1' then

-			mem_read <= (others => '0');

-			mem_read <= io_mem_read;

-		end if;

-	end process;

-

-

-	

-	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;

-

-	memoryControlSync:

-	process(clk, areset)

-	begin

-		if areset = '1' then

-			enable <= '0';

-			io_reading <= '0';

-			dram_ready <= '0';

-			

-		elsif (clk'event and clk = '1') then

-			enable <= '1';

-			io_reading <= io_busy or io_mem_readEnable; 

-			dram_ready<=dram_mem_readEnable;

-		end if;

-	end process;

-

-	-- wiggle the clock @ 100MHz

-	clock : PROCESS

-	   begin

-   			clk <= '0';

-		   wait for 5 ns; 

-   			clk <= '1';

-		   wait for 5 ns; 

-		   areset <= '0';

-	end PROCESS clock;

-

-

-end behave;

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity fpga_top is
+end fpga_top;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal	areset			: std_logic := '1';
+
+
+component  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end component;
+
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  enable : std_logic;
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+signal	 		  io_busy : std_logic;
+
+signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  io_mem_writeEnable : std_logic; 
+signal			  io_mem_readEnable : std_logic;
+
+
+signal			  dram_ready : std_logic;
+signal			  io_ready : std_logic;
+signal			  io_reading : std_logic;
+
+
+
+signal break : std_logic;
+
+begin
+
+	zpu: zpu_core port map (
+		clk => clk ,
+	 	areset => areset,
+	 	enable => enable,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+
+	ioMap: zpu_io port map (
+       	clk => clk,
+	 	areset => areset,
+		busy => io_busy,
+		writeEnable => io_mem_writeEnable,
+		readEnable => io_mem_readEnable,
+		write	=> mem_write,
+		read	=> io_mem_read,
+		addr => mem_addr(maxAddrBit downto minAddrBit)
+	);
+
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy;
+	
+	
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+	begin
+		mem_read <= (others => 'U');
+		if dram_ready='1' then
+			mem_read <= dram_mem_read;
+		end if;
+			 
+		if io_ready='1' then
+			mem_read <= (others => '0');
+			mem_read <= io_mem_read;
+		end if;
+	end process;
+
+
+	
+	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+	memoryControlSync:
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			enable <= '0';
+			io_reading <= '0';
+			dram_ready <= '0';
+			
+		elsif (clk'event and clk = '1') then
+			enable <= '1';
+			io_reading <= io_busy or io_mem_readEnable; 
+			dram_ready<=dram_mem_readEnable;
+		end if;
+	end process;
+
+	-- wiggle the clock @ 100MHz
+	clock : PROCESS
+	   begin
+   			clk <= '0';
+		   wait for 5 ns; 
+   			clk <= '1';
+		   wait for 5 ns; 
+		   areset <= '0';
+	end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd
index c4c09b5..c3c60c1 100644
--- a/zpu/hdl/example/zpu_config.vhd
+++ b/zpu/hdl/example/zpu_config.vhd
@@ -1,56 +1,56 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.std_logic_unsigned.all;

-use ieee.std_logic_arith.all;

-

-package zpu_config is

-	-- generate trace output

-	constant	Generate_Trace		: boolean := true;

-	constant 	wordPower			: integer := 5;

-	-- during simulation, set this to '0' to get matching trace.txt 

-	constant	DontCareValue		: std_logic := '0';

-	-- Clock frequency in MHz.

-	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";

-	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)

-	constant 	maxAddrBitIncIO		: integer := 27;

-	constant 	maxAddrBitBRAM		: integer := 16;

-		

-	-- start byte address of stack. 

-	-- point to top of RAM - 2*words

-	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) :=

-					conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);

-end zpu_config;

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+package zpu_config is
+	-- generate trace output
+	constant	Generate_Trace		: boolean := true;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 27;
+	constant 	maxAddrBitBRAM		: integer := 16;
+		
+	-- start byte address of stack. 
+	-- point to top of RAM - 2*words
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) :=
+					conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
+end zpu_config;
diff --git a/zpu/hdl/example_medium/dram_dmips.vhd b/zpu/hdl/example_medium/dram_dmips.vhd
index a9fd59e..0437adc 100644
--- a/zpu/hdl/example_medium/dram_dmips.vhd
+++ b/zpu/hdl/example_medium/dram_dmips.vhd
@@ -1,3308 +1,3308 @@
-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.numeric_std.all;

-

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-entity dram is

-port (clk : in std_logic;

-areset : std_logic;

-		mem_writeEnable : in std_logic;

-		mem_readEnable : in std_logic;

-		mem_addr : in std_logic_vector(maxAddrBit downto 0);

-		mem_write : in std_logic_vector(wordSize-1 downto 0);

-		mem_read : out std_logic_vector(wordSize-1 downto 0);

-		mem_busy : out std_logic;

-		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));

-end dram;

-

-architecture dram_arch of dram is

-

-

-type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);

-

-shared variable ram : ram_type :=

-(

-0 => x"0b0b0b0b",

-1 => x"82700b0b",

-2 => x"80d5f40c",

-3 => x"3a0b0b80",

-4 => x"c4fb0400",

-5 => x"00000000",

-6 => x"00000000",

-7 => x"00000000",

-8 => x"80088408",

-9 => x"88080b0b",

-10 => x"80c5c22d",

-11 => x"880c840c",

-12 => x"800c0400",

-13 => x"00000000",

-14 => x"00000000",

-15 => x"00000000",

-16 => x"71fd0608",

-17 => x"72830609",

-18 => x"81058205",

-19 => x"832b2a83",

-20 => x"ffff0652",

-21 => x"04000000",

-22 => x"00000000",

-23 => x"00000000",

-24 => x"71fd0608",

-25 => x"83ffff73",

-26 => x"83060981",

-27 => x"05820583",

-28 => x"2b2b0906",

-29 => x"7383ffff",

-30 => x"0b0b0b0b",

-31 => x"83a70400",

-32 => x"72098105",

-33 => x"72057373",

-34 => x"09060906",

-35 => x"73097306",

-36 => x"070a8106",

-37 => x"53510400",

-38 => x"00000000",

-39 => x"00000000",

-40 => x"72722473",

-41 => x"732e0753",

-42 => x"51040000",

-43 => x"00000000",

-44 => x"00000000",

-45 => x"00000000",

-46 => x"00000000",

-47 => x"00000000",

-48 => x"71737109",

-49 => x"71068106",

-50 => x"30720a10",

-51 => x"0a720a10",

-52 => x"0a31050a",

-53 => x"81065151",

-54 => x"53510400",

-55 => x"00000000",

-56 => x"72722673",

-57 => x"732e0753",

-58 => x"51040000",

-59 => x"00000000",

-60 => x"00000000",

-61 => x"00000000",

-62 => x"00000000",

-63 => x"00000000",

-64 => x"00000000",

-65 => x"00000000",

-66 => x"00000000",

-67 => x"00000000",

-68 => x"00000000",

-69 => x"00000000",

-70 => x"00000000",

-71 => x"00000000",

-72 => x"0b0b0b88",

-73 => x"c3040000",

-74 => x"00000000",

-75 => x"00000000",

-76 => x"00000000",

-77 => x"00000000",

-78 => x"00000000",

-79 => x"00000000",

-80 => x"720a722b",

-81 => x"0a535104",

-82 => x"00000000",

-83 => x"00000000",

-84 => x"00000000",

-85 => x"00000000",

-86 => x"00000000",

-87 => x"00000000",

-88 => x"72729f06",

-89 => x"0981050b",

-90 => x"0b0b88a6",

-91 => x"05040000",

-92 => x"00000000",

-93 => x"00000000",

-94 => x"00000000",

-95 => x"00000000",

-96 => x"72722aff",

-97 => x"739f062a",

-98 => x"0974090a",

-99 => x"8106ff05",

-100 => x"06075351",

-101 => x"04000000",

-102 => x"00000000",

-103 => x"00000000",

-104 => x"71715351",

-105 => x"020d0406",

-106 => x"73830609",

-107 => x"81058205",

-108 => x"832b0b2b",

-109 => x"0772fc06",

-110 => x"0c515104",

-111 => x"00000000",

-112 => x"72098105",

-113 => x"72050970",

-114 => x"81050906",

-115 => x"0a810653",

-116 => x"51040000",

-117 => x"00000000",

-118 => x"00000000",

-119 => x"00000000",

-120 => x"72098105",

-121 => x"72050970",

-122 => x"81050906",

-123 => x"0a098106",

-124 => x"53510400",

-125 => x"00000000",

-126 => x"00000000",

-127 => x"00000000",

-128 => x"71098105",

-129 => x"52040000",

-130 => x"00000000",

-131 => x"00000000",

-132 => x"00000000",

-133 => x"00000000",

-134 => x"00000000",

-135 => x"00000000",

-136 => x"72720981",

-137 => x"05055351",

-138 => x"04000000",

-139 => x"00000000",

-140 => x"00000000",

-141 => x"00000000",

-142 => x"00000000",

-143 => x"00000000",

-144 => x"72097206",

-145 => x"73730906",

-146 => x"07535104",

-147 => x"00000000",

-148 => x"00000000",

-149 => x"00000000",

-150 => x"00000000",

-151 => x"00000000",

-152 => x"71fc0608",

-153 => x"72830609",

-154 => x"81058305",

-155 => x"1010102a",

-156 => x"81ff0652",

-157 => x"04000000",

-158 => x"00000000",

-159 => x"00000000",

-160 => x"71fc0608",

-161 => x"0b0b80d5",

-162 => x"e0738306",

-163 => x"10100508",

-164 => x"060b0b0b",

-165 => x"88a90400",

-166 => x"00000000",

-167 => x"00000000",

-168 => x"80088408",

-169 => x"88087575",

-170 => x"0b0b0bad",

-171 => x"aa2d5050",

-172 => x"80085688",

-173 => x"0c840c80",

-174 => x"0c510400",

-175 => x"00000000",

-176 => x"80088408",

-177 => x"88087575",

-178 => x"0b0b0bad",

-179 => x"ee2d5050",

-180 => x"80085688",

-181 => x"0c840c80",

-182 => x"0c510400",

-183 => x"00000000",

-184 => x"72097081",

-185 => x"0509060a",

-186 => x"8106ff05",

-187 => x"70547106",

-188 => x"73097274",

-189 => x"05ff0506",

-190 => x"07515151",

-191 => x"04000000",

-192 => x"72097081",

-193 => x"0509060a",

-194 => x"098106ff",

-195 => x"05705471",

-196 => x"06730972",

-197 => x"7405ff05",

-198 => x"06075151",

-199 => x"51040000",

-200 => x"05ff0504",

-201 => x"00000000",

-202 => x"00000000",

-203 => x"00000000",

-204 => x"00000000",

-205 => x"00000000",

-206 => x"00000000",

-207 => x"00000000",

-208 => x"810b0b0b",

-209 => x"80d5f00c",

-210 => x"51040000",

-211 => x"00000000",

-212 => x"00000000",

-213 => x"00000000",

-214 => x"00000000",

-215 => x"00000000",

-216 => x"71810552",

-217 => x"04000000",

-218 => x"00000000",

-219 => x"00000000",

-220 => x"00000000",

-221 => x"00000000",

-222 => x"00000000",

-223 => x"00000000",

-224 => x"00000000",

-225 => x"00000000",

-226 => x"00000000",

-227 => x"00000000",

-228 => x"00000000",

-229 => x"00000000",

-230 => x"00000000",

-231 => x"00000000",

-232 => x"02840572",

-233 => x"10100552",

-234 => x"04000000",

-235 => x"00000000",

-236 => x"00000000",

-237 => x"00000000",

-238 => x"00000000",

-239 => x"00000000",

-240 => x"00000000",

-241 => x"00000000",

-242 => x"00000000",

-243 => x"00000000",

-244 => x"00000000",

-245 => x"00000000",

-246 => x"00000000",

-247 => x"00000000",

-248 => x"717105ff",

-249 => x"05715351",

-250 => x"020d0400",

-251 => x"00000000",

-252 => x"00000000",

-253 => x"00000000",

-254 => x"00000000",

-255 => x"00000000",

-256 => x"82fd3fbf",

-257 => x"a03f0410",

-258 => x"10101010",

-259 => x"10101010",

-260 => x"10101010",

-261 => x"10101010",

-262 => x"10101010",

-263 => x"10101010",

-264 => x"10101010",

-265 => x"10105351",

-266 => x"047381ff",

-267 => x"06738306",

-268 => x"09810583",

-269 => x"05101010",

-270 => x"2b0772fc",

-271 => x"060c5151",

-272 => x"043c0472",

-273 => x"72807281",

-274 => x"06ff0509",

-275 => x"72060571",

-276 => x"1052720a",

-277 => x"100a5372",

-278 => x"ed385151",

-279 => x"535104ff",

-280 => x"3d0d0b0b",

-281 => x"80e5e408",

-282 => x"52710870",

-283 => x"882a8132",

-284 => x"70810651",

-285 => x"515170f1",

-286 => x"3873720c",

-287 => x"833d0d04",

-288 => x"80d5f008",

-289 => x"802ea438",

-290 => x"80d5f408",

-291 => x"822ebd38",

-292 => x"8380800b",

-293 => x"0b0b80e5",

-294 => x"e40c82a0",

-295 => x"800b80e5",

-296 => x"e80c8290",

-297 => x"800b80e5",

-298 => x"ec0c04f8",

-299 => x"808080a4",

-300 => x"0b0b0b80",

-301 => x"e5e40cf8",

-302 => x"80808280",

-303 => x"0b80e5e8",

-304 => x"0cf88080",

-305 => x"84800b80",

-306 => x"e5ec0c04",

-307 => x"80c0a880",

-308 => x"8c0b0b0b",

-309 => x"80e5e40c",

-310 => x"80c0a880",

-311 => x"940b80e5",

-312 => x"e80c0b0b",

-313 => x"80c7d00b",

-314 => x"80e5ec0c",

-315 => x"04f23d0d",

-316 => x"6080e5e8",

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-2834 => x"00002c3c",

-2835 => x"00002c44",

-2836 => x"00002c44",

-2837 => x"00002c4c",

-2838 => x"00002c4c",

-2839 => x"00002c54",

-2840 => x"00002c54",

-2841 => x"00002c5c",

-2842 => x"00002c5c",

-2843 => x"00002c64",

-2844 => x"00002c64",

-2845 => x"00002c6c",

-2846 => x"00002c6c",

-2847 => x"00002c74",

-2848 => x"00002c74",

-2849 => x"00002c7c",

-2850 => x"00002c7c",

-2851 => x"00002c84",

-2852 => x"00002c84",

-2853 => x"00002c8c",

-2854 => x"00002c8c",

-2855 => x"00002c94",

-2856 => x"00002c94",

-2857 => x"00002c9c",

-2858 => x"00002c9c",

-2859 => x"00002ca4",

-2860 => x"00002ca4",

-2861 => x"00002cac",

-2862 => x"00002cac",

-2863 => x"00002cb4",

-2864 => x"00002cb4",

-2865 => x"00002cbc",

-2866 => x"00002cbc",

-2867 => x"00002cc4",

-2868 => x"00002cc4",

-2869 => x"00002ccc",

-2870 => x"00002ccc",

-2871 => x"00002cd4",

-2872 => x"00002cd4",

-2873 => x"00002cdc",

-2874 => x"00002cdc",

-2875 => x"00002ce4",

-2876 => x"00002ce4",

-2877 => x"00002cec",

-2878 => x"00002cec",

-2879 => x"00002cf4",

-2880 => x"00002cf4",

-2881 => x"00002cfc",

-2882 => x"00002cfc",

-2883 => x"00002d04",

-2884 => x"00002d04",

-2885 => x"00002d0c",

-2886 => x"00002d0c",

-2887 => x"00002d14",

-2888 => x"00002d14",

-2889 => x"00002d1c",

-2890 => x"00002d1c",

-2891 => x"00002d24",

-2892 => x"00002d24",

-2893 => x"00002d2c",

-2894 => x"00002d2c",

-2895 => x"00002d34",

-2896 => x"00002d34",

-2897 => x"00002d3c",

-2898 => x"00002d3c",

-2899 => x"00002d44",

-2900 => x"00002d44",

-2901 => x"00002d4c",

-2902 => x"00002d4c",

-2903 => x"00002d54",

-2904 => x"00002d54",

-2905 => x"00002d5c",

-2906 => x"00002d5c",

-2907 => x"00002d64",

-2908 => x"00002d64",

-2909 => x"00002d6c",

-2910 => x"00002d6c",

-2911 => x"00002d74",

-2912 => x"00002d74",

-2913 => x"00002d7c",

-2914 => x"00002d7c",

-2915 => x"00002d84",

-2916 => x"00002d84",

-2917 => x"00002d8c",

-2918 => x"00002d8c",

-2919 => x"00002d94",

-2920 => x"00002d94",

-2921 => x"00002d9c",

-2922 => x"00002d9c",

-2923 => x"00002da4",

-2924 => x"00002da4",

-2925 => x"00002dac",

-2926 => x"00002dac",

-2927 => x"00002db4",

-2928 => x"00002db4",

-2929 => x"00002dbc",

-2930 => x"00002dbc",

-2931 => x"00002dc4",

-2932 => x"00002dc4",

-2933 => x"00002dcc",

-2934 => x"00002dcc",

-2935 => x"00002dd4",

-2936 => x"00002dd4",

-2937 => x"00002ddc",

-2938 => x"00002ddc",

-2939 => x"00002de4",

-2940 => x"00002de4",

-2941 => x"00002dec",

-2942 => x"00002dec",

-2943 => x"00002df4",

-2944 => x"00002df4",

-2945 => x"00002dfc",

-2946 => x"00002dfc",

-2947 => x"00002e04",

-2948 => x"00002e04",

-2949 => x"00002e0c",

-2950 => x"00002e0c",

-2951 => x"00002e14",

-2952 => x"00002e14",

-2953 => x"00002e1c",

-2954 => x"00002e1c",

-2955 => x"00002e24",

-2956 => x"00002e24",

-2957 => x"00002e2c",

-2958 => x"00002e2c",

-2959 => x"00002e34",

-2960 => x"00002e34",

-2961 => x"00002e3c",

-2962 => x"00002e3c",

-2963 => x"00002e44",

-2964 => x"00002e44",

-2965 => x"00002e4c",

-2966 => x"00002e4c",

-2967 => x"00002e54",

-2968 => x"00002e54",

-2969 => x"00002e5c",

-2970 => x"00002e5c",

-2971 => x"00002e64",

-2972 => x"00002e64",

-2973 => x"00002e6c",

-2974 => x"00002e6c",

-2975 => x"00002e74",

-2976 => x"00002e74",

-2977 => x"00002e7c",

-2978 => x"00002e7c",

-2979 => x"00002e84",

-2980 => x"00002e84",

-2981 => x"00002e8c",

-2982 => x"00002e8c",

-2983 => x"00002e94",

-2984 => x"00002e94",

-2985 => x"00002e9c",

-2986 => x"00002e9c",

-2987 => x"00002ea4",

-2988 => x"00002ea4",

-2989 => x"00002eac",

-2990 => x"00002eac",

-2991 => x"00002eb4",

-2992 => x"00002eb4",

-2993 => x"00002ebc",

-2994 => x"00002ebc",

-2995 => x"00002ec4",

-2996 => x"00002ec4",

-2997 => x"00002ecc",

-2998 => x"00002ecc",

-2999 => x"00002ed4",

-3000 => x"00002ed4",

-3001 => x"00002edc",

-3002 => x"00002edc",

-3003 => x"00002ee4",

-3004 => x"00002ee4",

-3005 => x"00002eec",

-3006 => x"00002eec",

-3007 => x"00002ef4",

-3008 => x"00002ef4",

-3009 => x"00002efc",

-3010 => x"00002efc",

-3011 => x"00002f04",

-3012 => x"00002f04",

-3013 => x"00002f0c",

-3014 => x"00002f0c",

-3015 => x"00002f14",

-3016 => x"00002f14",

-3017 => x"00002f1c",

-3018 => x"00002f1c",

-3019 => x"00002f24",

-3020 => x"00002f24",

-3021 => x"00002f2c",

-3022 => x"00002f2c",

-3023 => x"00002f34",

-3024 => x"00002f34",

-3025 => x"00002f3c",

-3026 => x"00002f3c",

-3027 => x"00002f50",

-3028 => x"00000000",

-3029 => x"000031b8",

-3030 => x"00003214",

-3031 => x"00003270",

-3032 => x"00000000",

-3033 => x"00000000",

-3034 => x"00000000",

-3035 => x"00000000",

-3036 => x"00000000",

-3037 => x"00000000",

-3038 => x"00000000",

-3039 => x"00000000",

-3040 => x"00000000",

-3041 => x"00002ad0",

-3042 => x"00000000",

-3043 => x"00000000",

-3044 => x"00000000",

-3045 => x"00000000",

-3046 => x"00000000",

-3047 => x"00000000",

-3048 => x"00000000",

-3049 => x"00000000",

-3050 => x"00000000",

-3051 => x"00000000",

-3052 => x"00000000",

-3053 => x"00000000",

-3054 => x"00000000",

-3055 => x"00000000",

-3056 => x"00000000",

-3057 => x"00000000",

-3058 => x"00000000",

-3059 => x"00000000",

-3060 => x"00000000",

-3061 => x"00000000",

-3062 => x"00000000",

-3063 => x"00000000",

-3064 => x"00000000",

-3065 => x"00000000",

-3066 => x"00000000",

-3067 => x"00000000",

-3068 => x"00000000",

-3069 => x"00000000",

-3070 => x"00000001",

-3071 => x"330eabcd",

-3072 => x"1234e66d",

-3073 => x"deec0005",

-3074 => x"000b0000",

-3075 => x"00000000",

-3076 => x"00000000",

-3077 => x"00000000",

-3078 => x"00000000",

-3079 => x"00000000",

-3080 => x"00000000",

-3081 => x"00000000",

-3082 => x"00000000",

-3083 => x"00000000",

-3084 => x"00000000",

-3085 => x"00000000",

-3086 => x"00000000",

-3087 => x"00000000",

-3088 => x"00000000",

-3089 => x"00000000",

-3090 => x"00000000",

-3091 => x"00000000",

-3092 => x"00000000",

-3093 => x"00000000",

-3094 => x"00000000",

-3095 => x"00000000",

-3096 => x"00000000",

-3097 => x"00000000",

-3098 => x"00000000",

-3099 => x"00000000",

-3100 => x"00000000",

-3101 => x"00000000",

-3102 => x"00000000",

-3103 => x"00000000",

-3104 => x"00000000",

-3105 => x"00000000",

-3106 => x"00000000",

-3107 => x"00000000",

-3108 => x"00000000",

-3109 => x"00000000",

-3110 => x"00000000",

-3111 => x"00000000",

-3112 => x"00000000",

-3113 => x"00000000",

-3114 => x"00000000",

-3115 => x"00000000",

-3116 => x"00000000",

-3117 => x"00000000",

-3118 => x"00000000",

-3119 => x"00000000",

-3120 => x"00000000",

-3121 => x"00000000",

-3122 => x"00000000",

-3123 => x"00000000",

-3124 => x"00000000",

-3125 => x"00000000",

-3126 => x"00000000",

-3127 => x"00000000",

-3128 => x"00000000",

-3129 => x"00000000",

-3130 => x"00000000",

-3131 => x"00000000",

-3132 => x"00000000",

-3133 => x"00000000",

-3134 => x"00000000",

-3135 => x"00000000",

-3136 => x"00000000",

-3137 => x"00000000",

-3138 => x"00000000",

-3139 => x"00000000",

-3140 => x"00000000",

-3141 => x"00000000",

-3142 => x"00000000",

-3143 => x"00000000",

-3144 => x"00000000",

-3145 => x"00000000",

-3146 => x"00000000",

-3147 => x"00000000",

-3148 => x"00000000",

-3149 => x"00000000",

-3150 => x"00000000",

-3151 => x"00000000",

-3152 => x"00000000",

-3153 => x"00000000",

-3154 => x"00000000",

-3155 => x"00000000",

-3156 => x"00000000",

-3157 => x"00000000",

-3158 => x"00000000",

-3159 => x"00000000",

-3160 => x"00000000",

-3161 => x"00000000",

-3162 => x"00000000",

-3163 => x"00000000",

-3164 => x"00000000",

-3165 => x"00000000",

-3166 => x"00000000",

-3167 => x"00000000",

-3168 => x"00000000",

-3169 => x"00000000",

-3170 => x"00000000",

-3171 => x"00000000",

-3172 => x"00000000",

-3173 => x"00000000",

-3174 => x"00000000",

-3175 => x"00000000",

-3176 => x"00000000",

-3177 => x"00000000",

-3178 => x"00000000",

-3179 => x"00000000",

-3180 => x"00000000",

-3181 => x"00000000",

-3182 => x"00000000",

-3183 => x"00000000",

-3184 => x"00000000",

-3185 => x"00000000",

-3186 => x"00000000",

-3187 => x"00000000",

-3188 => x"00000000",

-3189 => x"00000000",

-3190 => x"00000000",

-3191 => x"00000000",

-3192 => x"00000000",

-3193 => x"00000000",

-3194 => x"00000000",

-3195 => x"00000000",

-3196 => x"00000000",

-3197 => x"00000000",

-3198 => x"00000000",

-3199 => x"00000000",

-3200 => x"00000000",

-3201 => x"00000000",

-3202 => x"00000000",

-3203 => x"00000000",

-3204 => x"00000000",

-3205 => x"00000000",

-3206 => x"00000000",

-3207 => x"00000000",

-3208 => x"00000000",

-3209 => x"00000000",

-3210 => x"00000000",

-3211 => x"00000000",

-3212 => x"00000000",

-3213 => x"00000000",

-3214 => x"00000000",

-3215 => x"00000000",

-3216 => x"00000000",

-3217 => x"00000000",

-3218 => x"00000000",

-3219 => x"00000000",

-3220 => x"00000000",

-3221 => x"00000000",

-3222 => x"00000000",

-3223 => x"00000000",

-3224 => x"00000000",

-3225 => x"00000000",

-3226 => x"00000000",

-3227 => x"00000000",

-3228 => x"00000000",

-3229 => x"00000000",

-3230 => x"00000000",

-3231 => x"00000000",

-3232 => x"00000000",

-3233 => x"00000000",

-3234 => x"00000000",

-3235 => x"00000000",

-3236 => x"00000000",

-3237 => x"00000000",

-3238 => x"00000000",

-3239 => x"00000000",

-3240 => x"00000000",

-3241 => x"00000000",

-3242 => x"00000000",

-3243 => x"00000000",

-3244 => x"00000000",

-3245 => x"00000000",

-3246 => x"00000000",

-3247 => x"00000000",

-3248 => x"00000000",

-3249 => x"00000000",

-3250 => x"00000000",

-3251 => x"00002ad4",

-3252 => x"ffffffff",

-3253 => x"00000000",

-3254 => x"ffffffff",

-3255 => x"00000000",

-	others => x"00000000"

-);

-

-begin

-

-mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request

-

-process (clk, areset)

-begin

-		if areset = '1' then

-		elsif (clk'event and clk = '1') then

-			if (mem_writeEnable = '1') then

-				ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;

-			end if;

-		if (mem_readEnable = '1') then

-			mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));

-		end if;

-	end if;

-end process;

-

-

-

-

-end dram_arch;

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+areset : std_logic;
+		mem_writeEnable : in std_logic;
+		mem_readEnable : in std_logic;
+		mem_addr : in std_logic_vector(maxAddrBit downto 0);
+		mem_write : in std_logic_vector(wordSize-1 downto 0);
+		mem_read : out std_logic_vector(wordSize-1 downto 0);
+		mem_busy : out std_logic;
+		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80d5f40c",
+3 => x"3a0b0b80",
+4 => x"c4fb0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c5c22d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c3040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a6",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80d5",
+162 => x"e0738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88a90400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0bad",
+171 => x"aa2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0bad",
+179 => x"ee2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80d5f00c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
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+2776 => x"00002b54",
+2777 => x"00002b5c",
+2778 => x"00002b5c",
+2779 => x"00002b64",
+2780 => x"00002b64",
+2781 => x"00002b6c",
+2782 => x"00002b6c",
+2783 => x"00002b74",
+2784 => x"00002b74",
+2785 => x"00002b7c",
+2786 => x"00002b7c",
+2787 => x"00002b84",
+2788 => x"00002b84",
+2789 => x"00002b8c",
+2790 => x"00002b8c",
+2791 => x"00002b94",
+2792 => x"00002b94",
+2793 => x"00002b9c",
+2794 => x"00002b9c",
+2795 => x"00002ba4",
+2796 => x"00002ba4",
+2797 => x"00002bac",
+2798 => x"00002bac",
+2799 => x"00002bb4",
+2800 => x"00002bb4",
+2801 => x"00002bbc",
+2802 => x"00002bbc",
+2803 => x"00002bc4",
+2804 => x"00002bc4",
+2805 => x"00002bcc",
+2806 => x"00002bcc",
+2807 => x"00002bd4",
+2808 => x"00002bd4",
+2809 => x"00002bdc",
+2810 => x"00002bdc",
+2811 => x"00002be4",
+2812 => x"00002be4",
+2813 => x"00002bec",
+2814 => x"00002bec",
+2815 => x"00002bf4",
+2816 => x"00002bf4",
+2817 => x"00002bfc",
+2818 => x"00002bfc",
+2819 => x"00002c04",
+2820 => x"00002c04",
+2821 => x"00002c0c",
+2822 => x"00002c0c",
+2823 => x"00002c14",
+2824 => x"00002c14",
+2825 => x"00002c1c",
+2826 => x"00002c1c",
+2827 => x"00002c24",
+2828 => x"00002c24",
+2829 => x"00002c2c",
+2830 => x"00002c2c",
+2831 => x"00002c34",
+2832 => x"00002c34",
+2833 => x"00002c3c",
+2834 => x"00002c3c",
+2835 => x"00002c44",
+2836 => x"00002c44",
+2837 => x"00002c4c",
+2838 => x"00002c4c",
+2839 => x"00002c54",
+2840 => x"00002c54",
+2841 => x"00002c5c",
+2842 => x"00002c5c",
+2843 => x"00002c64",
+2844 => x"00002c64",
+2845 => x"00002c6c",
+2846 => x"00002c6c",
+2847 => x"00002c74",
+2848 => x"00002c74",
+2849 => x"00002c7c",
+2850 => x"00002c7c",
+2851 => x"00002c84",
+2852 => x"00002c84",
+2853 => x"00002c8c",
+2854 => x"00002c8c",
+2855 => x"00002c94",
+2856 => x"00002c94",
+2857 => x"00002c9c",
+2858 => x"00002c9c",
+2859 => x"00002ca4",
+2860 => x"00002ca4",
+2861 => x"00002cac",
+2862 => x"00002cac",
+2863 => x"00002cb4",
+2864 => x"00002cb4",
+2865 => x"00002cbc",
+2866 => x"00002cbc",
+2867 => x"00002cc4",
+2868 => x"00002cc4",
+2869 => x"00002ccc",
+2870 => x"00002ccc",
+2871 => x"00002cd4",
+2872 => x"00002cd4",
+2873 => x"00002cdc",
+2874 => x"00002cdc",
+2875 => x"00002ce4",
+2876 => x"00002ce4",
+2877 => x"00002cec",
+2878 => x"00002cec",
+2879 => x"00002cf4",
+2880 => x"00002cf4",
+2881 => x"00002cfc",
+2882 => x"00002cfc",
+2883 => x"00002d04",
+2884 => x"00002d04",
+2885 => x"00002d0c",
+2886 => x"00002d0c",
+2887 => x"00002d14",
+2888 => x"00002d14",
+2889 => x"00002d1c",
+2890 => x"00002d1c",
+2891 => x"00002d24",
+2892 => x"00002d24",
+2893 => x"00002d2c",
+2894 => x"00002d2c",
+2895 => x"00002d34",
+2896 => x"00002d34",
+2897 => x"00002d3c",
+2898 => x"00002d3c",
+2899 => x"00002d44",
+2900 => x"00002d44",
+2901 => x"00002d4c",
+2902 => x"00002d4c",
+2903 => x"00002d54",
+2904 => x"00002d54",
+2905 => x"00002d5c",
+2906 => x"00002d5c",
+2907 => x"00002d64",
+2908 => x"00002d64",
+2909 => x"00002d6c",
+2910 => x"00002d6c",
+2911 => x"00002d74",
+2912 => x"00002d74",
+2913 => x"00002d7c",
+2914 => x"00002d7c",
+2915 => x"00002d84",
+2916 => x"00002d84",
+2917 => x"00002d8c",
+2918 => x"00002d8c",
+2919 => x"00002d94",
+2920 => x"00002d94",
+2921 => x"00002d9c",
+2922 => x"00002d9c",
+2923 => x"00002da4",
+2924 => x"00002da4",
+2925 => x"00002dac",
+2926 => x"00002dac",
+2927 => x"00002db4",
+2928 => x"00002db4",
+2929 => x"00002dbc",
+2930 => x"00002dbc",
+2931 => x"00002dc4",
+2932 => x"00002dc4",
+2933 => x"00002dcc",
+2934 => x"00002dcc",
+2935 => x"00002dd4",
+2936 => x"00002dd4",
+2937 => x"00002ddc",
+2938 => x"00002ddc",
+2939 => x"00002de4",
+2940 => x"00002de4",
+2941 => x"00002dec",
+2942 => x"00002dec",
+2943 => x"00002df4",
+2944 => x"00002df4",
+2945 => x"00002dfc",
+2946 => x"00002dfc",
+2947 => x"00002e04",
+2948 => x"00002e04",
+2949 => x"00002e0c",
+2950 => x"00002e0c",
+2951 => x"00002e14",
+2952 => x"00002e14",
+2953 => x"00002e1c",
+2954 => x"00002e1c",
+2955 => x"00002e24",
+2956 => x"00002e24",
+2957 => x"00002e2c",
+2958 => x"00002e2c",
+2959 => x"00002e34",
+2960 => x"00002e34",
+2961 => x"00002e3c",
+2962 => x"00002e3c",
+2963 => x"00002e44",
+2964 => x"00002e44",
+2965 => x"00002e4c",
+2966 => x"00002e4c",
+2967 => x"00002e54",
+2968 => x"00002e54",
+2969 => x"00002e5c",
+2970 => x"00002e5c",
+2971 => x"00002e64",
+2972 => x"00002e64",
+2973 => x"00002e6c",
+2974 => x"00002e6c",
+2975 => x"00002e74",
+2976 => x"00002e74",
+2977 => x"00002e7c",
+2978 => x"00002e7c",
+2979 => x"00002e84",
+2980 => x"00002e84",
+2981 => x"00002e8c",
+2982 => x"00002e8c",
+2983 => x"00002e94",
+2984 => x"00002e94",
+2985 => x"00002e9c",
+2986 => x"00002e9c",
+2987 => x"00002ea4",
+2988 => x"00002ea4",
+2989 => x"00002eac",
+2990 => x"00002eac",
+2991 => x"00002eb4",
+2992 => x"00002eb4",
+2993 => x"00002ebc",
+2994 => x"00002ebc",
+2995 => x"00002ec4",
+2996 => x"00002ec4",
+2997 => x"00002ecc",
+2998 => x"00002ecc",
+2999 => x"00002ed4",
+3000 => x"00002ed4",
+3001 => x"00002edc",
+3002 => x"00002edc",
+3003 => x"00002ee4",
+3004 => x"00002ee4",
+3005 => x"00002eec",
+3006 => x"00002eec",
+3007 => x"00002ef4",
+3008 => x"00002ef4",
+3009 => x"00002efc",
+3010 => x"00002efc",
+3011 => x"00002f04",
+3012 => x"00002f04",
+3013 => x"00002f0c",
+3014 => x"00002f0c",
+3015 => x"00002f14",
+3016 => x"00002f14",
+3017 => x"00002f1c",
+3018 => x"00002f1c",
+3019 => x"00002f24",
+3020 => x"00002f24",
+3021 => x"00002f2c",
+3022 => x"00002f2c",
+3023 => x"00002f34",
+3024 => x"00002f34",
+3025 => x"00002f3c",
+3026 => x"00002f3c",
+3027 => x"00002f50",
+3028 => x"00000000",
+3029 => x"000031b8",
+3030 => x"00003214",
+3031 => x"00003270",
+3032 => x"00000000",
+3033 => x"00000000",
+3034 => x"00000000",
+3035 => x"00000000",
+3036 => x"00000000",
+3037 => x"00000000",
+3038 => x"00000000",
+3039 => x"00000000",
+3040 => x"00000000",
+3041 => x"00002ad0",
+3042 => x"00000000",
+3043 => x"00000000",
+3044 => x"00000000",
+3045 => x"00000000",
+3046 => x"00000000",
+3047 => x"00000000",
+3048 => x"00000000",
+3049 => x"00000000",
+3050 => x"00000000",
+3051 => x"00000000",
+3052 => x"00000000",
+3053 => x"00000000",
+3054 => x"00000000",
+3055 => x"00000000",
+3056 => x"00000000",
+3057 => x"00000000",
+3058 => x"00000000",
+3059 => x"00000000",
+3060 => x"00000000",
+3061 => x"00000000",
+3062 => x"00000000",
+3063 => x"00000000",
+3064 => x"00000000",
+3065 => x"00000000",
+3066 => x"00000000",
+3067 => x"00000000",
+3068 => x"00000000",
+3069 => x"00000000",
+3070 => x"00000001",
+3071 => x"330eabcd",
+3072 => x"1234e66d",
+3073 => x"deec0005",
+3074 => x"000b0000",
+3075 => x"00000000",
+3076 => x"00000000",
+3077 => x"00000000",
+3078 => x"00000000",
+3079 => x"00000000",
+3080 => x"00000000",
+3081 => x"00000000",
+3082 => x"00000000",
+3083 => x"00000000",
+3084 => x"00000000",
+3085 => x"00000000",
+3086 => x"00000000",
+3087 => x"00000000",
+3088 => x"00000000",
+3089 => x"00000000",
+3090 => x"00000000",
+3091 => x"00000000",
+3092 => x"00000000",
+3093 => x"00000000",
+3094 => x"00000000",
+3095 => x"00000000",
+3096 => x"00000000",
+3097 => x"00000000",
+3098 => x"00000000",
+3099 => x"00000000",
+3100 => x"00000000",
+3101 => x"00000000",
+3102 => x"00000000",
+3103 => x"00000000",
+3104 => x"00000000",
+3105 => x"00000000",
+3106 => x"00000000",
+3107 => x"00000000",
+3108 => x"00000000",
+3109 => x"00000000",
+3110 => x"00000000",
+3111 => x"00000000",
+3112 => x"00000000",
+3113 => x"00000000",
+3114 => x"00000000",
+3115 => x"00000000",
+3116 => x"00000000",
+3117 => x"00000000",
+3118 => x"00000000",
+3119 => x"00000000",
+3120 => x"00000000",
+3121 => x"00000000",
+3122 => x"00000000",
+3123 => x"00000000",
+3124 => x"00000000",
+3125 => x"00000000",
+3126 => x"00000000",
+3127 => x"00000000",
+3128 => x"00000000",
+3129 => x"00000000",
+3130 => x"00000000",
+3131 => x"00000000",
+3132 => x"00000000",
+3133 => x"00000000",
+3134 => x"00000000",
+3135 => x"00000000",
+3136 => x"00000000",
+3137 => x"00000000",
+3138 => x"00000000",
+3139 => x"00000000",
+3140 => x"00000000",
+3141 => x"00000000",
+3142 => x"00000000",
+3143 => x"00000000",
+3144 => x"00000000",
+3145 => x"00000000",
+3146 => x"00000000",
+3147 => x"00000000",
+3148 => x"00000000",
+3149 => x"00000000",
+3150 => x"00000000",
+3151 => x"00000000",
+3152 => x"00000000",
+3153 => x"00000000",
+3154 => x"00000000",
+3155 => x"00000000",
+3156 => x"00000000",
+3157 => x"00000000",
+3158 => x"00000000",
+3159 => x"00000000",
+3160 => x"00000000",
+3161 => x"00000000",
+3162 => x"00000000",
+3163 => x"00000000",
+3164 => x"00000000",
+3165 => x"00000000",
+3166 => x"00000000",
+3167 => x"00000000",
+3168 => x"00000000",
+3169 => x"00000000",
+3170 => x"00000000",
+3171 => x"00000000",
+3172 => x"00000000",
+3173 => x"00000000",
+3174 => x"00000000",
+3175 => x"00000000",
+3176 => x"00000000",
+3177 => x"00000000",
+3178 => x"00000000",
+3179 => x"00000000",
+3180 => x"00000000",
+3181 => x"00000000",
+3182 => x"00000000",
+3183 => x"00000000",
+3184 => x"00000000",
+3185 => x"00000000",
+3186 => x"00000000",
+3187 => x"00000000",
+3188 => x"00000000",
+3189 => x"00000000",
+3190 => x"00000000",
+3191 => x"00000000",
+3192 => x"00000000",
+3193 => x"00000000",
+3194 => x"00000000",
+3195 => x"00000000",
+3196 => x"00000000",
+3197 => x"00000000",
+3198 => x"00000000",
+3199 => x"00000000",
+3200 => x"00000000",
+3201 => x"00000000",
+3202 => x"00000000",
+3203 => x"00000000",
+3204 => x"00000000",
+3205 => x"00000000",
+3206 => x"00000000",
+3207 => x"00000000",
+3208 => x"00000000",
+3209 => x"00000000",
+3210 => x"00000000",
+3211 => x"00000000",
+3212 => x"00000000",
+3213 => x"00000000",
+3214 => x"00000000",
+3215 => x"00000000",
+3216 => x"00000000",
+3217 => x"00000000",
+3218 => x"00000000",
+3219 => x"00000000",
+3220 => x"00000000",
+3221 => x"00000000",
+3222 => x"00000000",
+3223 => x"00000000",
+3224 => x"00000000",
+3225 => x"00000000",
+3226 => x"00000000",
+3227 => x"00000000",
+3228 => x"00000000",
+3229 => x"00000000",
+3230 => x"00000000",
+3231 => x"00000000",
+3232 => x"00000000",
+3233 => x"00000000",
+3234 => x"00000000",
+3235 => x"00000000",
+3236 => x"00000000",
+3237 => x"00000000",
+3238 => x"00000000",
+3239 => x"00000000",
+3240 => x"00000000",
+3241 => x"00000000",
+3242 => x"00000000",
+3243 => x"00000000",
+3244 => x"00000000",
+3245 => x"00000000",
+3246 => x"00000000",
+3247 => x"00000000",
+3248 => x"00000000",
+3249 => x"00000000",
+3250 => x"00000000",
+3251 => x"00002ad4",
+3252 => x"ffffffff",
+3253 => x"00000000",
+3254 => x"ffffffff",
+3255 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
+
+process (clk, areset)
+begin
+		if areset = '1' then
+		elsif (clk'event and clk = '1') then
+			if (mem_writeEnable = '1') then
+				ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
+			end if;
+		if (mem_readEnable = '1') then
+			mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/example_medium/dram_hello.vhd b/zpu/hdl/example_medium/dram_hello.vhd
index 4f02cca..aae18fd 100644
--- a/zpu/hdl/example_medium/dram_hello.vhd
+++ b/zpu/hdl/example_medium/dram_hello.vhd
@@ -1,3107 +1,3107 @@
-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.numeric_std.all;

-

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-entity dram is

-port (clk : in std_logic;

-areset : std_logic;

-		mem_writeEnable : in std_logic;

-		mem_readEnable : in std_logic;

-		mem_addr : in std_logic_vector(maxAddrBit downto 0);

-		mem_write : in std_logic_vector(wordSize-1 downto 0);

-		mem_read : out std_logic_vector(wordSize-1 downto 0);

-		mem_busy : out std_logic;

-		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));

-end dram;

-

-architecture dram_arch of dram is

-

-

-type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);

-

-shared variable ram : ram_type :=

-(

-0 => x"0b0b0b0b",

-1 => x"82700b0b",

-2 => x"80cfd80c",

-3 => x"3a0b0b80",

-4 => x"c6d00400",

-5 => x"00000000",

-6 => x"00000000",

-7 => x"00000000",

-8 => x"80088408",

-9 => x"88080b0b",

-10 => x"80c7972d",

-11 => x"880c840c",

-12 => x"800c0400",

-13 => x"00000000",

-14 => x"00000000",

-15 => x"00000000",

-16 => x"71fd0608",

-17 => x"72830609",

-18 => x"81058205",

-19 => x"832b2a83",

-20 => x"ffff0652",

-21 => x"04000000",

-22 => x"00000000",

-23 => x"00000000",

-24 => x"71fd0608",

-25 => x"83ffff73",

-26 => x"83060981",

-27 => x"05820583",

-28 => x"2b2b0906",

-29 => x"7383ffff",

-30 => x"0b0b0b0b",

-31 => x"83a70400",

-32 => x"72098105",

-33 => x"72057373",

-34 => x"09060906",

-35 => x"73097306",

-36 => x"070a8106",

-37 => x"53510400",

-38 => x"00000000",

-39 => x"00000000",

-40 => x"72722473",

-41 => x"732e0753",

-42 => x"51040000",

-43 => x"00000000",

-44 => x"00000000",

-45 => x"00000000",

-46 => x"00000000",

-47 => x"00000000",

-48 => x"71737109",

-49 => x"71068106",

-50 => x"30720a10",

-51 => x"0a720a10",

-52 => x"0a31050a",

-53 => x"81065151",

-54 => x"53510400",

-55 => x"00000000",

-56 => x"72722673",

-57 => x"732e0753",

-58 => x"51040000",

-59 => x"00000000",

-60 => x"00000000",

-61 => x"00000000",

-62 => x"00000000",

-63 => x"00000000",

-64 => x"00000000",

-65 => x"00000000",

-66 => x"00000000",

-67 => x"00000000",

-68 => x"00000000",

-69 => x"00000000",

-70 => x"00000000",

-71 => x"00000000",

-72 => x"0b0b0b88",

-73 => x"c4040000",

-74 => x"00000000",

-75 => x"00000000",

-76 => x"00000000",

-77 => x"00000000",

-78 => x"00000000",

-79 => x"00000000",

-80 => x"720a722b",

-81 => x"0a535104",

-82 => x"00000000",

-83 => x"00000000",

-84 => x"00000000",

-85 => x"00000000",

-86 => x"00000000",

-87 => x"00000000",

-88 => x"72729f06",

-89 => x"0981050b",

-90 => x"0b0b88a7",

-91 => x"05040000",

-92 => x"00000000",

-93 => x"00000000",

-94 => x"00000000",

-95 => x"00000000",

-96 => x"72722aff",

-97 => x"739f062a",

-98 => x"0974090a",

-99 => x"8106ff05",

-100 => x"06075351",

-101 => x"04000000",

-102 => x"00000000",

-103 => x"00000000",

-104 => x"71715351",

-105 => x"020d0406",

-106 => x"73830609",

-107 => x"81058205",

-108 => x"832b0b2b",

-109 => x"0772fc06",

-110 => x"0c515104",

-111 => x"00000000",

-112 => x"72098105",

-113 => x"72050970",

-114 => x"81050906",

-115 => x"0a810653",

-116 => x"51040000",

-117 => x"00000000",

-118 => x"00000000",

-119 => x"00000000",

-120 => x"72098105",

-121 => x"72050970",

-122 => x"81050906",

-123 => x"0a098106",

-124 => x"53510400",

-125 => x"00000000",

-126 => x"00000000",

-127 => x"00000000",

-128 => x"71098105",

-129 => x"52040000",

-130 => x"00000000",

-131 => x"00000000",

-132 => x"00000000",

-133 => x"00000000",

-134 => x"00000000",

-135 => x"00000000",

-136 => x"72720981",

-137 => x"05055351",

-138 => x"04000000",

-139 => x"00000000",

-140 => x"00000000",

-141 => x"00000000",

-142 => x"00000000",

-143 => x"00000000",

-144 => x"72097206",

-145 => x"73730906",

-146 => x"07535104",

-147 => x"00000000",

-148 => x"00000000",

-149 => x"00000000",

-150 => x"00000000",

-151 => x"00000000",

-152 => x"71fc0608",

-153 => x"72830609",

-154 => x"81058305",

-155 => x"1010102a",

-156 => x"81ff0652",

-157 => x"04000000",

-158 => x"00000000",

-159 => x"00000000",

-160 => x"71fc0608",

-161 => x"0b0b80cf",

-162 => x"c4738306",

-163 => x"10100508",

-164 => x"060b0b0b",

-165 => x"88aa0400",

-166 => x"00000000",

-167 => x"00000000",

-168 => x"80088408",

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-2750 => x"00000000",

-2751 => x"00000000",

-2752 => x"00000000",

-2753 => x"00000000",

-2754 => x"00000000",

-2755 => x"00000000",

-2756 => x"00000000",

-2757 => x"00000000",

-2758 => x"00000000",

-2759 => x"00000000",

-2760 => x"00000000",

-2761 => x"00000000",

-2762 => x"00000000",

-2763 => x"00000000",

-2764 => x"00000000",

-2765 => x"00000000",

-2766 => x"00000000",

-2767 => x"00000000",

-2768 => x"00000000",

-2769 => x"00000000",

-2770 => x"00000000",

-2771 => x"00000000",

-2772 => x"00000000",

-2773 => x"00000000",

-2774 => x"00000000",

-2775 => x"00000000",

-2776 => x"00000000",

-2777 => x"00000000",

-2778 => x"00000000",

-2779 => x"00000000",

-2780 => x"00000000",

-2781 => x"00000000",

-2782 => x"00000000",

-2783 => x"00000000",

-2784 => x"00000000",

-2785 => x"00000000",

-2786 => x"00000000",

-2787 => x"00000000",

-2788 => x"00000000",

-2789 => x"ffffffff",

-2790 => x"00000000",

-2791 => x"00020000",

-2792 => x"00000000",

-2793 => x"00000000",

-2794 => x"00002ba0",

-2795 => x"00002ba0",

-2796 => x"00002ba8",

-2797 => x"00002ba8",

-2798 => x"00002bb0",

-2799 => x"00002bb0",

-2800 => x"00002bb8",

-2801 => x"00002bb8",

-2802 => x"00002bc0",

-2803 => x"00002bc0",

-2804 => x"00002bc8",

-2805 => x"00002bc8",

-2806 => x"00002bd0",

-2807 => x"00002bd0",

-2808 => x"00002bd8",

-2809 => x"00002bd8",

-2810 => x"00002be0",

-2811 => x"00002be0",

-2812 => x"00002be8",

-2813 => x"00002be8",

-2814 => x"00002bf0",

-2815 => x"00002bf0",

-2816 => x"00002bf8",

-2817 => x"00002bf8",

-2818 => x"00002c00",

-2819 => x"00002c00",

-2820 => x"00002c08",

-2821 => x"00002c08",

-2822 => x"00002c10",

-2823 => x"00002c10",

-2824 => x"00002c18",

-2825 => x"00002c18",

-2826 => x"00002c20",

-2827 => x"00002c20",

-2828 => x"00002c28",

-2829 => x"00002c28",

-2830 => x"00002c30",

-2831 => x"00002c30",

-2832 => x"00002c38",

-2833 => x"00002c38",

-2834 => x"00002c40",

-2835 => x"00002c40",

-2836 => x"00002c48",

-2837 => x"00002c48",

-2838 => x"00002c50",

-2839 => x"00002c50",

-2840 => x"00002c58",

-2841 => x"00002c58",

-2842 => x"00002c60",

-2843 => x"00002c60",

-2844 => x"00002c68",

-2845 => x"00002c68",

-2846 => x"00002c70",

-2847 => x"00002c70",

-2848 => x"00002c78",

-2849 => x"00002c78",

-2850 => x"00002c80",

-2851 => x"00002c80",

-2852 => x"00002c88",

-2853 => x"00002c88",

-2854 => x"00002c90",

-2855 => x"00002c90",

-2856 => x"00002c98",

-2857 => x"00002c98",

-2858 => x"00002ca0",

-2859 => x"00002ca0",

-2860 => x"00002ca8",

-2861 => x"00002ca8",

-2862 => x"00002cb0",

-2863 => x"00002cb0",

-2864 => x"00002cb8",

-2865 => x"00002cb8",

-2866 => x"00002cc0",

-2867 => x"00002cc0",

-2868 => x"00002cc8",

-2869 => x"00002cc8",

-2870 => x"00002cd0",

-2871 => x"00002cd0",

-2872 => x"00002cd8",

-2873 => x"00002cd8",

-2874 => x"00002ce0",

-2875 => x"00002ce0",

-2876 => x"00002ce8",

-2877 => x"00002ce8",

-2878 => x"00002cf0",

-2879 => x"00002cf0",

-2880 => x"00002cf8",

-2881 => x"00002cf8",

-2882 => x"00002d00",

-2883 => x"00002d00",

-2884 => x"00002d08",

-2885 => x"00002d08",

-2886 => x"00002d10",

-2887 => x"00002d10",

-2888 => x"00002d18",

-2889 => x"00002d18",

-2890 => x"00002d20",

-2891 => x"00002d20",

-2892 => x"00002d28",

-2893 => x"00002d28",

-2894 => x"00002d30",

-2895 => x"00002d30",

-2896 => x"00002d38",

-2897 => x"00002d38",

-2898 => x"00002d40",

-2899 => x"00002d40",

-2900 => x"00002d48",

-2901 => x"00002d48",

-2902 => x"00002d50",

-2903 => x"00002d50",

-2904 => x"00002d58",

-2905 => x"00002d58",

-2906 => x"00002d60",

-2907 => x"00002d60",

-2908 => x"00002d68",

-2909 => x"00002d68",

-2910 => x"00002d70",

-2911 => x"00002d70",

-2912 => x"00002d78",

-2913 => x"00002d78",

-2914 => x"00002d80",

-2915 => x"00002d80",

-2916 => x"00002d88",

-2917 => x"00002d88",

-2918 => x"00002d90",

-2919 => x"00002d90",

-2920 => x"00002d98",

-2921 => x"00002d98",

-2922 => x"00002da0",

-2923 => x"00002da0",

-2924 => x"00002da8",

-2925 => x"00002da8",

-2926 => x"00002db0",

-2927 => x"00002db0",

-2928 => x"00002db8",

-2929 => x"00002db8",

-2930 => x"00002dc0",

-2931 => x"00002dc0",

-2932 => x"00002dc8",

-2933 => x"00002dc8",

-2934 => x"00002dd0",

-2935 => x"00002dd0",

-2936 => x"00002dd8",

-2937 => x"00002dd8",

-2938 => x"00002de0",

-2939 => x"00002de0",

-2940 => x"00002de8",

-2941 => x"00002de8",

-2942 => x"00002df0",

-2943 => x"00002df0",

-2944 => x"00002df8",

-2945 => x"00002df8",

-2946 => x"00002e00",

-2947 => x"00002e00",

-2948 => x"00002e08",

-2949 => x"00002e08",

-2950 => x"00002e10",

-2951 => x"00002e10",

-2952 => x"00002e18",

-2953 => x"00002e18",

-2954 => x"00002e20",

-2955 => x"00002e20",

-2956 => x"00002e28",

-2957 => x"00002e28",

-2958 => x"00002e30",

-2959 => x"00002e30",

-2960 => x"00002e38",

-2961 => x"00002e38",

-2962 => x"00002e40",

-2963 => x"00002e40",

-2964 => x"00002e48",

-2965 => x"00002e48",

-2966 => x"00002e50",

-2967 => x"00002e50",

-2968 => x"00002e58",

-2969 => x"00002e58",

-2970 => x"00002e60",

-2971 => x"00002e60",

-2972 => x"00002e68",

-2973 => x"00002e68",

-2974 => x"00002e70",

-2975 => x"00002e70",

-2976 => x"00002e78",

-2977 => x"00002e78",

-2978 => x"00002e80",

-2979 => x"00002e80",

-2980 => x"00002e88",

-2981 => x"00002e88",

-2982 => x"00002e90",

-2983 => x"00002e90",

-2984 => x"00002e98",

-2985 => x"00002e98",

-2986 => x"00002ea0",

-2987 => x"00002ea0",

-2988 => x"00002ea8",

-2989 => x"00002ea8",

-2990 => x"00002eb0",

-2991 => x"00002eb0",

-2992 => x"00002eb8",

-2993 => x"00002eb8",

-2994 => x"00002ec0",

-2995 => x"00002ec0",

-2996 => x"00002ec8",

-2997 => x"00002ec8",

-2998 => x"00002ed0",

-2999 => x"00002ed0",

-3000 => x"00002ed8",

-3001 => x"00002ed8",

-3002 => x"00002ee0",

-3003 => x"00002ee0",

-3004 => x"00002ee8",

-3005 => x"00002ee8",

-3006 => x"00002ef0",

-3007 => x"00002ef0",

-3008 => x"00002ef8",

-3009 => x"00002ef8",

-3010 => x"00002f00",

-3011 => x"00002f00",

-3012 => x"00002f08",

-3013 => x"00002f08",

-3014 => x"00002f10",

-3015 => x"00002f10",

-3016 => x"00002f18",

-3017 => x"00002f18",

-3018 => x"00002f20",

-3019 => x"00002f20",

-3020 => x"00002f28",

-3021 => x"00002f28",

-3022 => x"00002f30",

-3023 => x"00002f30",

-3024 => x"00002f38",

-3025 => x"00002f38",

-3026 => x"00002f40",

-3027 => x"00002f40",

-3028 => x"00002f48",

-3029 => x"00002f48",

-3030 => x"00002f50",

-3031 => x"00002f50",

-3032 => x"00002f58",

-3033 => x"00002f58",

-3034 => x"00002f60",

-3035 => x"00002f60",

-3036 => x"00002f68",

-3037 => x"00002f68",

-3038 => x"00002f70",

-3039 => x"00002f70",

-3040 => x"00002f78",

-3041 => x"00002f78",

-3042 => x"00002f80",

-3043 => x"00002f80",

-3044 => x"00002f88",

-3045 => x"00002f88",

-3046 => x"00002f90",

-3047 => x"00002f90",

-3048 => x"00002f98",

-3049 => x"00002f98",

-3050 => x"000027b8",

-3051 => x"ffffffff",

-3052 => x"00000000",

-3053 => x"ffffffff",

-3054 => x"00000000",

-	others => x"00000000"

-);

-

-begin

-

-mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request

-

-process (clk, areset)

-begin

-		if areset = '1' then

-		elsif (clk'event and clk = '1') then

-			if (mem_writeEnable = '1') then

-				ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;

-			end if;

-		if (mem_readEnable = '1') then

-			mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));

-		end if;

-	end if;

-end process;

-

-

-

-

-end dram_arch;

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+areset : std_logic;
+		mem_writeEnable : in std_logic;
+		mem_readEnable : in std_logic;
+		mem_addr : in std_logic_vector(maxAddrBit downto 0);
+		mem_write : in std_logic_vector(wordSize-1 downto 0);
+		mem_read : out std_logic_vector(wordSize-1 downto 0);
+		mem_busy : out std_logic;
+		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"c4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"9f2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"e32d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfd40c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6d93f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc0",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c0085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"d408802e",
+299 => x"a43880cf",
+300 => x"d808822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc00c",
+304 => x"82a0800b",
+305 => x"80dfc40c",
+306 => x"8290800b",
+307 => x"80dfc80c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc0",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfc40cf8",
+314 => x"80808480",
+315 => x"0b80dfc8",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c00c80c0",
+320 => x"a880940b",
+321 => x"80dfc40c",
+322 => x"0b0b80cf",
+323 => x"8c0b80df",
+324 => x"c80c0470",
+325 => x"7080dfcc",
+326 => x"335170a7",
+327 => x"3880cfe0",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe00c",
+332 => x"702d80cf",
+333 => x"e0087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfcc3450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"bc08802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
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+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
+
+process (clk, areset)
+begin
+		if areset = '1' then
+		elsif (clk'event and clk = '1') then
+			if (mem_writeEnable = '1') then
+				ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
+			end if;
+		if (mem_readEnable = '1') then
+			mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/example_medium/sim_fpga_top.vhd b/zpu/hdl/example_medium/sim_fpga_top.vhd
index 2191889..a10da37 100644
--- a/zpu/hdl/example_medium/sim_fpga_top.vhd
+++ b/zpu/hdl/example_medium/sim_fpga_top.vhd
@@ -1,185 +1,185 @@
---------------------------------------------------------------------------------

--- Company: 

--- Engineer:

---

--- Create Date:    20:15:31 04/14/05

--- Design Name:    

--- Module Name:    fpga_top - behave

--- Project Name:   

--- Target Device:  

--- Tool versions:  

--- Description:

---

--- Dependencies:

--- 

--- Revision:

--- Revision 0.01 - File Created

--- Additional Comments:

--- 

---------------------------------------------------------------------------------

-library IEEE;

-use IEEE.STD_LOGIC_1164.ALL;

-

----- Uncomment the following library declaration if instantiating

----- any Xilinx primitives in this code.

---library UNISIM;

---use UNISIM.VComponents.all;

-

-library work;

-use work.zpu_config.all;

-

-entity fpga_top is

-end fpga_top;

-

-use work.zpupkg.all;

-

-architecture behave of fpga_top is

-

-

-signal clk : std_logic;

-

-signal	areset			: std_logic := '1';

-

-

-component  zpu_io is

-  generic (

-           log_file:       string  := "log.txt"

-          );

-  port(

-       	clk         : in std_logic;

-       	areset        : in std_logic;

-		busy : out std_logic;

-		writeEnable : in std_logic;

-		readEnable : in std_logic;

-		write	: in std_logic_vector(wordSize-1 downto 0);

-		read	: out std_logic_vector(wordSize-1 downto 0);

-		addr : in std_logic_vector(maxAddrBit downto minAddrBit)

-		);

-end component;

-

-

-

-

-

-signal			  mem_busy : std_logic;

-signal			  mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);

-signal			  mem_writeEnable : std_logic; 

-signal			  mem_readEnable : std_logic;

-signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-signal			  enable : std_logic;

-

-signal			  dram_mem_busy : std_logic;

-signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_writeEnable : std_logic; 

-signal			  dram_mem_readEnable : std_logic;

-signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-

-signal	 		  io_busy : std_logic;

-

-signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  io_mem_writeEnable : std_logic; 

-signal			  io_mem_readEnable : std_logic;

-

-

-signal			  dram_ready : std_logic;

-signal			  io_ready : std_logic;

-signal			  io_reading : std_logic;

-

-

-signal break : std_logic;

-

-begin

-	zpu: zpu_core port map (

-		clk => clk ,

-	 	areset => areset,

-	 	enable => enable,

- 		in_mem_busy => mem_busy, 

- 		mem_read => mem_read,

- 		mem_write => mem_write, 

-		out_mem_addr => mem_addr, 

-		out_mem_writeEnable => mem_writeEnable,  

-		out_mem_readEnable => mem_readEnable,

- 		mem_writeMask => mem_writeMask, 

- 		interrupt => '0',

- 		break  => break);

-

-	dram_imp: dram port map (

-		clk => clk ,

-		areset => areset,

- 		mem_busy => dram_mem_busy, 

- 		mem_read => dram_mem_read,

- 		mem_write => mem_write, 

-		mem_addr => mem_addr(maxAddrBit downto 0), 

-		mem_writeEnable => dram_mem_writeEnable,  

-		mem_readEnable => dram_mem_readEnable,

- 		mem_writeMask => mem_writeMask);

-

-

-	ioMap: zpu_io port map (

-       	clk => clk,

-	 	areset => areset,

-		busy => io_busy,

-		writeEnable => io_mem_writeEnable,

-		readEnable => io_mem_readEnable,

-		write	=> mem_write(wordSize-1 downto 0),

-		read	=> io_mem_read,

-		addr => mem_addr(maxAddrBit downto minAddrBit)

-	);

-

-	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);

-	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);

-	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);

-	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);

-	mem_busy <= io_busy or dram_mem_busy or io_busy;

-	

-	

-

-	-- Memory reads either come from IO or DRAM. We need to pick the right one.

-	memorycontrol:

-	process(dram_mem_read, dram_ready, io_ready, io_mem_read)

-	begin

-		mem_read <= (others => 'U');

-		if dram_ready='1' then

-			mem_read <= dram_mem_read;

-		end if;

-			 

-		if io_ready='1' then

-			mem_read <= io_mem_read;

-		end if;

-	end process;

-

-	

-	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;

-

-	memoryControlSync:

-	process(clk, areset)

-	begin

-		if areset = '1' then

-			enable <= '0';

-			io_reading <= '0';

-			dram_ready <= '0';

-		elsif (clk'event and clk = '1') then

-			enable <= '1';

-			io_reading <= io_busy or io_mem_readEnable; 

-			dram_ready<=dram_mem_readEnable;

-			

-		end if;

-	end process;

-

-	-- wiggle the clock @ 100MHz

-	clock : PROCESS

-	   begin

-   			clk <= '0';

-		   wait for 5 ns; 

-   			clk <= '1';

-		   wait for 5 ns; 

-		   areset <= '0';

-	end PROCESS clock;

-

-

-end behave;

+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    20:15:31 04/14/05
+-- Design Name:    
+-- Module Name:    fpga_top - behave
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+library work;
+use work.zpu_config.all;
+
+entity fpga_top is
+end fpga_top;
+
+use work.zpupkg.all;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal	areset			: std_logic := '1';
+
+
+component  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end component;
+
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  enable : std_logic;
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+signal	 		  io_busy : std_logic;
+
+signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  io_mem_writeEnable : std_logic; 
+signal			  io_mem_readEnable : std_logic;
+
+
+signal			  dram_ready : std_logic;
+signal			  io_ready : std_logic;
+signal			  io_reading : std_logic;
+
+
+signal break : std_logic;
+
+begin
+	zpu: zpu_core port map (
+		clk => clk ,
+	 	areset => areset,
+	 	enable => enable,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+	dram_imp: dram port map (
+		clk => clk ,
+		areset => areset,
+ 		mem_busy => dram_mem_busy, 
+ 		mem_read => dram_mem_read,
+ 		mem_write => mem_write, 
+		mem_addr => mem_addr(maxAddrBit downto 0), 
+		mem_writeEnable => dram_mem_writeEnable,  
+		mem_readEnable => dram_mem_readEnable,
+ 		mem_writeMask => mem_writeMask);
+
+
+	ioMap: zpu_io port map (
+       	clk => clk,
+	 	areset => areset,
+		busy => io_busy,
+		writeEnable => io_mem_writeEnable,
+		readEnable => io_mem_readEnable,
+		write	=> mem_write(wordSize-1 downto 0),
+		read	=> io_mem_read,
+		addr => mem_addr(maxAddrBit downto minAddrBit)
+	);
+
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy or dram_mem_busy or io_busy;
+	
+	
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+	begin
+		mem_read <= (others => 'U');
+		if dram_ready='1' then
+			mem_read <= dram_mem_read;
+		end if;
+			 
+		if io_ready='1' then
+			mem_read <= io_mem_read;
+		end if;
+	end process;
+
+	
+	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+	memoryControlSync:
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			enable <= '0';
+			io_reading <= '0';
+			dram_ready <= '0';
+		elsif (clk'event and clk = '1') then
+			enable <= '1';
+			io_reading <= io_busy or io_mem_readEnable; 
+			dram_ready<=dram_mem_readEnable;
+			
+		end if;
+	end process;
+
+	-- wiggle the clock @ 100MHz
+	clock : PROCESS
+	   begin
+   			clk <= '0';
+		   wait for 5 ns; 
+   			clk <= '1';
+		   wait for 5 ns; 
+		   areset <= '0';
+	end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/example_medium/zpu_config_trace.vhd b/zpu/hdl/example_medium/zpu_config_trace.vhd
index d765d9a..a5b9192 100644
--- a/zpu/hdl/example_medium/zpu_config_trace.vhd
+++ b/zpu/hdl/example_medium/zpu_config_trace.vhd
@@ -1,17 +1,17 @@
-library ieee;

-use ieee.std_logic_1164.all;

-

-package zpu_config is

-

-	constant	Generate_Trace		: boolean := true;

-	constant 	wordPower			: integer := 5;

-	-- during simulation, set this to '0' to get matching trace.txt 

-	constant	DontCareValue		: std_logic := '0';

-	-- Clock frequency in MHz.

-	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";

-	constant 	maxAddrBitIncIO		: integer := 27;

-	constant 	maxAddrBitDRAM		: integer := 16;

-	constant 	maxAddrBitBRAM		: integer := 16;

-	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; 	

-	

-end zpu_config;

+library ieee;
+use ieee.std_logic_1164.all;
+
+package zpu_config is
+
+	constant	Generate_Trace		: boolean := true;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
+	constant 	maxAddrBitIncIO		: integer := 27;
+	constant 	maxAddrBitDRAM		: integer := 16;
+	constant 	maxAddrBitBRAM		: integer := 16;
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; 	
+	
+end zpu_config;
diff --git a/zpu/hdl/wishbone/wishbone_pkg.vhd b/zpu/hdl/wishbone/wishbone_pkg.vhd
index 97240de..b6d30ee 100644
--- a/zpu/hdl/wishbone/wishbone_pkg.vhd
+++ b/zpu/hdl/wishbone/wishbone_pkg.vhd
@@ -1,86 +1,86 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library IEEE;

-use IEEE.STD_LOGIC_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-package wishbone_pkg is

-

-	type wishbone_bus_in is record

-		adr			: std_logic_vector(31 downto 0); 

-		sel			: std_logic_vector(3 downto 0); 

-		we			: std_logic;

-		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'

-		cyc			: std_logic; 

-		stb			: std_logic;

-	end record;

-

-	type wishbone_bus_out is record

-		dat		: std_logic_vector(31 downto 0);

-		ack			: std_logic;

-	end record;

-	

-	type wishbone_bus is record

-		insig		: wishbone_bus_in;

-		outsig  	: wishbone_bus_out;

-	end record;

-

-	component atomic32_access is

-	port (	cpu_clk			: in std_logic;

-			areset			: in std_logic;

-	

-			-- Wishbone from CPU interface

-			wb_16_i			: in wishbone_bus_in;

-			wb_16_o     	: out wishbone_bus_out;

-			-- Wishbone to FPGA registers and ethernet core

-			wb_32_i			: in wishbone_bus_out;

-			wb_32_o			: out wishbone_bus_in);

-	end component;

-	

-	component eth_access_corr is

-	port (	cpu_clk			: in std_logic;

-			areset			: in std_logic;

-	

-			-- Wishbone from Wishbone MUX

-			eth_raw_o		: out wishbone_bus_out;

-			eth_raw_i		: in wishbone_bus_in;

-			

-			-- Wishbone ethernet core

-			eth_slave_i 	: in wishbone_bus_out;

-			eth_slave_o		: out wishbone_bus_in);

-	end component;

-

-

-end wishbone_pkg;

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+	type wishbone_bus_in is record
+		adr			: std_logic_vector(31 downto 0); 
+		sel			: std_logic_vector(3 downto 0); 
+		we			: std_logic;
+		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'
+		cyc			: std_logic; 
+		stb			: std_logic;
+	end record;
+
+	type wishbone_bus_out is record
+		dat		: std_logic_vector(31 downto 0);
+		ack			: std_logic;
+	end record;
+	
+	type wishbone_bus is record
+		insig		: wishbone_bus_in;
+		outsig  	: wishbone_bus_out;
+	end record;
+
+	component atomic32_access is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from CPU interface
+			wb_16_i			: in wishbone_bus_in;
+			wb_16_o     	: out wishbone_bus_out;
+			-- Wishbone to FPGA registers and ethernet core
+			wb_32_i			: in wishbone_bus_out;
+			wb_32_o			: out wishbone_bus_in);
+	end component;
+	
+	component eth_access_corr is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from Wishbone MUX
+			eth_raw_o		: out wishbone_bus_out;
+			eth_raw_i		: in wishbone_bus_in;
+			
+			-- Wishbone ethernet core
+			eth_slave_i 	: in wishbone_bus_out;
+			eth_slave_o		: out wishbone_bus_in);
+	end component;
+
+
+end wishbone_pkg;
diff --git a/zpu/hdl/wishbone/zpu_system.vhd b/zpu/hdl/wishbone/zpu_system.vhd
index 5b95a80..07c5bdc 100644
--- a/zpu/hdl/wishbone/zpu_system.vhd
+++ b/zpu/hdl/wishbone/zpu_system.vhd
@@ -1,104 +1,104 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library IEEE;

-use IEEE.STD_LOGIC_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.all; 

-

-library work;

-use work.wishbone_pkg.all;

-use work.zpupkg.all;

-use work.zpu_config.all;

-

-entity zpu_system is

-	generic(

-			simulate		: boolean := false);

-	port (	areset			: in std_logic;

-			cpu_clk			: in std_logic;

-

-			-- ZPU Control signals

-			enable			: in std_logic;

-			interrupt		: in std_logic;

-

-			zpu_status		: out std_logic_vector(63 downto 0);

-

-			-- wishbone interfaces

-			zpu_wb_i		: in wishbone_bus_out;

-			zpu_wb_o		: out wishbone_bus_in);

-end zpu_system;

-

-architecture behave of zpu_system is

-

-signal	mem_req					: std_logic;

-signal	mem_we 					: std_logic;

-signal	mem_ack 				: std_logic; 

-signal	mem_read 				: std_logic_vector(wordSize-1 downto 0);

-signal	mem_write 				: std_logic_vector(wordSize-1 downto 0);

-signal	out_mem_addr 			: std_logic_vector(maxAddrBitIncIO downto 0);

-signal	mem_writeMask			: std_logic_vector(wordBytes-1 downto 0);

-

-

-begin

-

-	my_zpu_core:

-	zpu_core port map (

-    	clk 				=> cpu_clk, 

-		areset 				=> areset,

-	 	enable 				=> enable,

-	  	mem_req 			=> mem_req,

-	 	mem_we 				=> mem_we,

-	 	mem_ack 			=> mem_ack, 

-	 	mem_read 			=> mem_read,

-	 	mem_write 			=> mem_write,

-		out_mem_addr 		=> out_mem_addr,

-	 	mem_writeMask		=> mem_writeMask,

-	 	interrupt			=> interrupt,

-	 	zpu_status			=> zpu_status,

-	 	break				=> open);

-

-	my_zpu_wb_bridge:

-	zpu_wb_bridge port map (

-		clk 				=> cpu_clk,

-	 	areset 				=> areset,

-	  	mem_req 			=> mem_req,

-	 	mem_we 				=> mem_we,

-	 	mem_ack 			=> mem_ack, 

-	 	mem_read 			=> mem_read,

-	 	mem_write 			=> mem_write,

-		out_mem_addr 		=> out_mem_addr,

-	 	mem_writeMask		=> mem_writeMask,

-		zpu_wb_i			=> zpu_wb_i,

-		zpu_wb_o			=> zpu_wb_o);

-

-end behave;

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all; 
+
+library work;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_system is
+	generic(
+			simulate		: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+
+			-- ZPU Control signals
+			enable			: in std_logic;
+			interrupt		: in std_logic;
+
+			zpu_status		: out std_logic_vector(63 downto 0);
+
+			-- wishbone interfaces
+			zpu_wb_i		: in wishbone_bus_out;
+			zpu_wb_o		: out wishbone_bus_in);
+end zpu_system;
+
+architecture behave of zpu_system is
+
+signal	mem_req					: std_logic;
+signal	mem_we 					: std_logic;
+signal	mem_ack 				: std_logic; 
+signal	mem_read 				: std_logic_vector(wordSize-1 downto 0);
+signal	mem_write 				: std_logic_vector(wordSize-1 downto 0);
+signal	out_mem_addr 			: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	mem_writeMask			: std_logic_vector(wordBytes-1 downto 0);
+
+
+begin
+
+	my_zpu_core:
+	zpu_core port map (
+    	clk 				=> cpu_clk, 
+		areset 				=> areset,
+	 	enable 				=> enable,
+	  	mem_req 			=> mem_req,
+	 	mem_we 				=> mem_we,
+	 	mem_ack 			=> mem_ack, 
+	 	mem_read 			=> mem_read,
+	 	mem_write 			=> mem_write,
+		out_mem_addr 		=> out_mem_addr,
+	 	mem_writeMask		=> mem_writeMask,
+	 	interrupt			=> interrupt,
+	 	zpu_status			=> zpu_status,
+	 	break				=> open);
+
+	my_zpu_wb_bridge:
+	zpu_wb_bridge port map (
+		clk 				=> cpu_clk,
+	 	areset 				=> areset,
+	  	mem_req 			=> mem_req,
+	 	mem_we 				=> mem_we,
+	 	mem_ack 			=> mem_ack, 
+	 	mem_read 			=> mem_read,
+	 	mem_write 			=> mem_write,
+		out_mem_addr 		=> out_mem_addr,
+	 	mem_writeMask		=> mem_writeMask,
+		zpu_wb_i			=> zpu_wb_i,
+		zpu_wb_o			=> zpu_wb_o);
+
+end behave;
diff --git a/zpu/hdl/wishbone/zpu_wb_bridge.vhd b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
index 226d839..086ae11 100644
--- a/zpu/hdl/wishbone/zpu_wb_bridge.vhd
+++ b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
@@ -1,83 +1,83 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library IEEE;

-use IEEE.STD_LOGIC_1164.ALL;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-library work;

-use work.phi_config.all;

-use work.wishbone_pkg.all;

-use work.zpupkg.all;

-use work.zpu_config.all;

-

-entity zpu_wb_bridge is

-	port (	-- Native ZPU interface

- 			clk 				: in std_logic;

-	 		areset 				: in std_logic;

-

-	 		mem_req 			: in std_logic;

-	 		mem_we				: in std_logic;

-	 		mem_ack				: out std_logic; 

-	 		mem_read 			: out std_logic_vector(wordSize-1 downto 0);

-	 		mem_write 			: in std_logic_vector(wordSize-1 downto 0);

-			out_mem_addr 		: in std_logic_vector(maxAddrBitIncIO downto 0);

-	 		mem_writeMask		: in std_logic_vector(wordBytes-1 downto 0);

-			

-			-- Wishbone from ZPU

-			zpu_wb_i			: in wishbone_bus_out;

-			zpu_wb_o			: out wishbone_bus_in);

-

-end zpu_wb_bridge;

-

-architecture behave of zpu_wb_bridge is

-

-begin

-

-	mem_read <= zpu_wb_i.dat;

-	mem_ack <= zpu_wb_i.ack;

-	

-	zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0);

-	zpu_wb_o.dat <= mem_write;

-	zpu_wb_o.sel <= mem_writeMask;

-	zpu_wb_o.stb <= mem_req;

-	zpu_wb_o.cyc <= mem_req;

-	zpu_wb_o.we <= mem_we;

-

-end behave;

-

-			

-

-	

-

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.phi_config.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_wb_bridge is
+	port (	-- Native ZPU interface
+ 			clk 				: in std_logic;
+	 		areset 				: in std_logic;
+
+	 		mem_req 			: in std_logic;
+	 		mem_we				: in std_logic;
+	 		mem_ack				: out std_logic; 
+	 		mem_read 			: out std_logic_vector(wordSize-1 downto 0);
+	 		mem_write 			: in std_logic_vector(wordSize-1 downto 0);
+			out_mem_addr 		: in std_logic_vector(maxAddrBitIncIO downto 0);
+	 		mem_writeMask		: in std_logic_vector(wordBytes-1 downto 0);
+			
+			-- Wishbone from ZPU
+			zpu_wb_i			: in wishbone_bus_out;
+			zpu_wb_o			: out wishbone_bus_in);
+
+end zpu_wb_bridge;
+
+architecture behave of zpu_wb_bridge is
+
+begin
+
+	mem_read <= zpu_wb_i.dat;
+	mem_ack <= zpu_wb_i.ack;
+	
+	zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0);
+	zpu_wb_o.dat <= mem_write;
+	zpu_wb_o.sel <= mem_writeMask;
+	zpu_wb_o.stb <= mem_req;
+	zpu_wb_o.cyc <= mem_req;
+	zpu_wb_o.we <= mem_we;
+
+end behave;
+
+			
+
+	
+
diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd
index 112dd01..5b3110c 100644
--- a/zpu/hdl/zpu4/core/zpu_config.vhd
+++ b/zpu/hdl/zpu4/core/zpu_config.vhd
@@ -1,44 +1,44 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-

-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.std_logic_unsigned.all;

-use ieee.std_logic_arith.all;

-

-package zpu_config is

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+package zpu_config is
 
   -- generate trace output or not.
   constant Generate_Trace  : boolean                      := false;
@@ -56,4 +56,4 @@ package zpu_config is
   constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
     conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
 
-end zpu_config;

+end zpu_config;
diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd
index ff9449f..e2e4781 100644
--- a/zpu/hdl/zpu4/core/zpu_core.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core.vhd
@@ -1,68 +1,68 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-

--- mem_writeEnable - set to '1' for a single cycle to send off a write request.

---                   mem_write is valid only while mem_writeEnable='1'.

--- mem_readEnable - set to '1' for a single cycle to send off a read request.

--- 

--- mem_busy - It is illegal to send off a read/write request when mem_busy='1'.

---            Set to '0' when mem_read  is valid after a read request.

---            If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable

---            is '1'.

--- mem_addr - address for read/write request

--- mem_read - read data. Valid only on the cycle after mem_busy='0' after 

---            mem_readEnable='1' for a single cycle.

--- mem_write - data to write

--- mem_writeMask - set to '1' for those bits that are to be written to memory upon

---                 write request

--- break - set to '1' when CPU hits break instruction

--- interrupt - set to '1' until interrupts are cleared by CPU. 

-
-

-

-

-entity zpu_core is

+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+-- mem_writeEnable - set to '1' for a single cycle to send off a write request.
+--                   mem_write is valid only while mem_writeEnable='1'.
+-- mem_readEnable - set to '1' for a single cycle to send off a read request.
+-- 
+-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'.
+--            Set to '0' when mem_read  is valid after a read request.
+--            If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable
+--            is '1'.
+-- mem_addr - address for read/write request
+-- mem_read - read data. Valid only on the cycle after mem_busy='0' after 
+--            mem_readEnable='1' for a single cycle.
+-- mem_write - data to write
+-- mem_writeMask - set to '1' for those bits that are to be written to memory upon
+--                 write request
+-- break - set to '1' when CPU hits break instruction
+-- interrupt - set to '1' until interrupts are cleared by CPU. 
+
+
+
+
+entity zpu_core is
   port (
     clk                 : in  std_logic;
     areset              : in  std_logic;
@@ -77,10 +77,10 @@ entity zpu_core is
     interrupt           : in  std_logic;
     break               : out std_logic
     );
-end zpu_core;

-

-architecture behave of zpu_core is

-

+end zpu_core;
+
+architecture behave of zpu_core is
+
   type InsnType is (
     State_AddTop,
     State_Dup,
@@ -196,12 +196,12 @@ architecture behave of zpu_core is
   signal trace_sp          : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
   signal trace_topOfStack  : std_logic_vector(wordSize-1 downto 0);
   signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
-

--- state machine.

-

-begin

-

-

+
+-- state machine.
+
+begin
+
+
   traceFileGenerate :
   if Generate_Trace generate
     trace_file : trace port map (
@@ -1009,7 +1009,7 @@ begin
       end case; -- state
     end if; -- clk'event
   end process;
-

-

-

-end behave;

+
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd
index 1df9546..757d056 100644
--- a/zpu/hdl/zpu4/core/zpu_core_small.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd
@@ -1,47 +1,47 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-

-entity zpu_core is

+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity zpu_core is
   port ( 
     clk                 : in std_logic;
     -- asynchronous reset signal
@@ -67,12 +67,12 @@ entity zpu_core is
     -- in simulation to stop simulation
     break               : out std_logic
     );
-end zpu_core;

-

-

-

+end zpu_core;
+
+
+
 architecture behave of zpu_core is
-

+
   signal memAWriteEnable : std_logic;
   signal memAAddr        : unsigned(maxAddrBit downto minAddrBit);
   signal memAWrite       : unsigned(wordSize-1 downto 0);
@@ -171,11 +171,11 @@ architecture behave of zpu_core is
   signal  tOpcode_sel        : index;
   --
   signal  inInterrupt        : std_logic;
-

-

-

-begin

-

+
+
+
+begin
+
   -- generate a trace file.
   -- 
   -- This is only used in simulation to see what instructions are
@@ -596,7 +596,7 @@ begin
       
     end if;  -- reset, enable
   end process;
-

-

-

-end behave;

+
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd
index f6823f5..a6e749d 100644
--- a/zpu/hdl/zpu4/core/zpupkg.vhd
+++ b/zpu/hdl/zpu4/core/zpupkg.vhd
@@ -1,47 +1,47 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;

-

-library work;

-use work.zpu_config.all;

-

-
-package zpupkg is

-

+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+
+
+package zpupkg is
+
   -- This bit is set for read/writes to IO
   -- FIX!!! eventually this should be set to wordSize-1 so as to
   -- to make the address of IO independent of amount of memory
@@ -215,4 +215,4 @@ package zpupkg is
 
 
   
-end zpupkg;

+end zpupkg;
diff --git a/zpu/hdl/zpu4/src/clocks.vhd b/zpu/hdl/zpu4/src/clocks.vhd
index a352b3c..704d790 100644
--- a/zpu/hdl/zpu4/src/clocks.vhd
+++ b/zpu/hdl/zpu4/src/clocks.vhd
@@ -1,246 +1,246 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.ALL;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-library UNISIM;

-use UNISIM.vcomponents.all;

-

-entity clocks is

-	port (	areset			: in std_logic;

-			cpu_clk_p		: in std_logic;

-			sdr_clk_fb_p	: in std_logic;

-			cpu_clk			: out std_logic;

-			cpu_clk_2x		: out std_logic;

-			cpu_clk_4x		: out std_logic;

-			ddr_in_clk		: out std_logic;

-			ddr_in_clk_2x	: out std_logic;

-			locked			: out std_logic_vector(2 downto 0));

-end clocks;

-

-architecture behave of clocks is

-

-signal	low					: std_logic;

-

-signal	cpu_clk_in			: std_logic;

-signal	sdr_clk_fb_in		: std_logic;

-

-signal	dcm_cpu1			: std_logic;

-signal	dcm_cpu2			: std_logic;

-signal	dcm_cpu2_dum		: std_logic;

-signal	dcm_cpu4			: std_logic;

-signal	dcm_ddr2			: std_logic;

-signal	dcm_ddr2_2x			: std_logic;

-

-signal	cpu_clk_int			: std_logic;

-signal	cpu_clk_2x_int		: std_logic;

-signal	cpu_clk_2x_dum_int	: std_logic;

-signal	cpu_clk_4x_int		: std_logic;

-signal	ddr_in_clk_int		: std_logic;

-signal	ddr_in_clk_2x_int	: std_logic;

-

-signal	dcm1_locked_del		: std_logic;

-signal	dcm2_locked_del		: std_logic;

-signal	dcm2_reset			: std_logic;

-signal	dcm3_reset			: std_logic;

-

-signal	locked_int			: std_logic_vector(2 downto 0);

-signal	del_addr			: std_logic_vector(3 downto 0);

-

-begin

-

-	low <= '0';				

-	del_addr <= "1111";

-	

-	cpu_clk <= cpu_clk_int;

-	cpu_clk_2x <= cpu_clk_2x_int;

-	cpu_clk_4x <= cpu_clk_4x_int;

-	ddr_in_clk <= ddr_in_clk_int;

-	ddr_in_clk_2x <= ddr_in_clk_2x_int;

-	locked <= locked_int;

-	

-

-   	CPU_IBUFG: 

-   	IBUFG port map (

-      	O => cpu_clk_in,

-      	I => cpu_clk_p);

-	

-   	SDR_FB_IBUFG: 

-   	IBUFG port map (

-      	O => sdr_clk_fb_in,

-      	I => sdr_clk_fb_p);

-      	

-   dcm2_rst: 

-   SRL16 generic map (

-      	INIT => X"0000")

-   port map (

-      	Q => dcm1_locked_del,

-      	A0 => del_addr(0),

-      	A1 => del_addr(1),

-      	A2 => del_addr(2),

-      	A3 => del_addr(3),

-      	CLK => cpu_clk_int,

-      	D => locked_int(0));

-      	

-	dcm2_reset <= not(dcm1_locked_del);      	

-	

-   dcm3_rst: 

-   SRL16 generic map (

-      	INIT => X"0000")

-   port map (

-      	Q => dcm2_locked_del,

-      	A0 => del_addr(0),

-      	A1 => del_addr(1),

-      	A2 => del_addr(2),

-      	A3 => del_addr(3),

-      	CLK => cpu_clk_int,

-      	D => locked_int(1));

-      	

-	dcm3_reset <= not(dcm2_locked_del);      	

-	

-   	cpu1_dcm: 

-   	DCM generic map (

-      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5

-                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0

-      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32

-      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32

-      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature

-      	CLKIN_PERIOD => 15.625,          --  Specify period of input clock

-      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE

-      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X

-      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or

-                                             --     an integer from 0 to 15

-      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis

-      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL

-      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE

-      	FACTORY_JF => X"8080",          --  FACTORY JF Values

-      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255

-      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE

-   	port map (

-      	CLK0 => dcm_cpu1,   -- 0 degree DCM CLK ouptput

-      	CLK180 => open, 	-- 180 degree DCM CLK output

-      	CLK270 => open,	 	-- 270 degree DCM CLK output

-      	CLK2X => dcm_cpu2, 	-- 2X DCM CLK output

-      	CLK2X180 => open, -- 2X, 180 degree DCM CLK out

-      	CLK90 => open,   	-- 90 degree DCM CLK output

-      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)

-      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)

-      	CLKFX180 => open, 	-- 180 degree CLK synthesis out

-      	LOCKED => locked_int(0), -- DCM LOCK status output

-      	PSDONE => open, 	-- Dynamic phase adjust done output

-      	STATUS => open, 	-- 8-bit DCM status bits output

-      	CLKFB => cpu_clk_int,   -- DCM clock feedback

-      	CLKIN => cpu_clk_in,   -- Clock input (from IBUFG, BUFG or DCM)

-      	PSCLK => low,   	-- Dynamic phase adjust clock input

-      	PSEN => low,     	-- Dynamic phase adjust enable input

-      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement

-      	RST => areset);     -- DCM asynchronous reset input

-   

-   	cpu2_dcm: 

-   	DCM generic map (

-      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5

-                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0

-      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32

-      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32

-      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature

-      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock

-      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE

-      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X

-      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or

-                                             --     an integer from 0 to 15

-      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis

-      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL

-      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE

-      	FACTORY_JF => X"8080",          --  FACTORY JF Values

-      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255

-      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE

-   	port map (

-      	CLK0 => dcm_cpu2_dum,     	-- 0 degree DCM CLK ouptput

-      	CLK180 => open,		 -- 180 degree DCM CLK output

-      	CLK270 => open,	 	-- 270 degree DCM CLK output

-      	CLK2X => dcm_cpu4,  -- 2X DCM CLK output

-      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out

-      	CLK90 => open,   	-- 90 degree DCM CLK output

-      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)

-      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)

-      	CLKFX180 => open, 	-- 180 degree CLK synthesis out

-      	LOCKED => locked_int(1), -- DCM LOCK status output

-      	PSDONE => open, 	-- Dynamic phase adjust done output

-      	STATUS => open, 	-- 8-bit DCM status bits output

-      	CLKFB => cpu_clk_2x_dum_int,   -- DCM clock feedback

-      	CLKIN => cpu_clk_2x_int,   -- Clock input (from IBUFG, BUFG or DCM)

-      	PSCLK => low,   	-- Dynamic phase adjust clock input

-      	PSEN => low,     	-- Dynamic phase adjust enable input

-      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement

-      	RST => dcm2_reset);     -- DCM asynchronous reset input

-   

-   	ddr_read_dcm: 

-   	DCM generic map (

-      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5

-                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0

-      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32

-      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32

-      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature

-      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock

-     	CLKOUT_PHASE_SHIFT => "FIXED", --  Specify phase shift of NONE, FIXED or VARIABLE

---      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE

-      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X

-      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or

-                                             --     an integer from 0 to 15

-      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis

-      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL

-      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE

-      	FACTORY_JF => X"8080",          --  FACTORY JF Values

-      	PHASE_SHIFT => 103,        --  Amount of fixed phase shift from -255 to 255

---      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255

-      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE

-   	port map (

-      	CLK0 => dcm_ddr2,     	-- 0 degree DCM CLK ouptput

-      	CLK180 => open,		 -- 180 degree DCM CLK output

-      	CLK270 => open,	 	-- 270 degree DCM CLK output

-      	CLK2X => dcm_ddr2_2x,  -- 2X DCM CLK output

-      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out

-      	CLK90 => open,   	-- 90 degree DCM CLK output

-      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)

-      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)

-      	CLKFX180 => open, 	-- 180 degree CLK synthesis out

-      	LOCKED => locked_int(2), -- DCM LOCK status output

-      	PSDONE => open, 	-- Dynamic phase adjust done output

-      	STATUS => open, 	-- 8-bit DCM status bits output

-      	CLKFB => ddr_in_clk_int,   -- DCM clock feedback

-      	CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)

-      	PSCLK => low,   	-- Dynamic phase adjust clock input

-      	PSEN => low,     	-- Dynamic phase adjust enable input

-      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement

-      	RST => dcm3_reset);     -- DCM asynchronous reset input

-   

-   	cpu1:

-	BUFG port map (

-		I => dcm_cpu1,

-		O => cpu_clk_int);

-		

-   	cpu2:

-	BUFG port map (

-		I => dcm_cpu2,

-		O => cpu_clk_2x_int);

-		

-   	cpu2_dum:

-	BUFG port map (

-		I => dcm_cpu2_dum,

-		O => cpu_clk_2x_dum_int);

-		

-   	cpu4:

-	BUFG port map (

-		I => dcm_cpu4,

-		O => cpu_clk_4x_int);

-		

-   	ddr_clk:

-	BUFG port map (

-		I => dcm_ddr2,

-		O => ddr_in_clk_int);

-

-   	ddr_clk_2x:

-	BUFG port map (

-		I => dcm_ddr2_2x,

-		O => ddr_in_clk_2x_int);

-

+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clocks is
+	port (	areset			: in std_logic;
+			cpu_clk_p		: in std_logic;
+			sdr_clk_fb_p	: in std_logic;
+			cpu_clk			: out std_logic;
+			cpu_clk_2x		: out std_logic;
+			cpu_clk_4x		: out std_logic;
+			ddr_in_clk		: out std_logic;
+			ddr_in_clk_2x	: out std_logic;
+			locked			: out std_logic_vector(2 downto 0));
+end clocks;
+
+architecture behave of clocks is
+
+signal	low					: std_logic;
+
+signal	cpu_clk_in			: std_logic;
+signal	sdr_clk_fb_in		: std_logic;
+
+signal	dcm_cpu1			: std_logic;
+signal	dcm_cpu2			: std_logic;
+signal	dcm_cpu2_dum		: std_logic;
+signal	dcm_cpu4			: std_logic;
+signal	dcm_ddr2			: std_logic;
+signal	dcm_ddr2_2x			: std_logic;
+
+signal	cpu_clk_int			: std_logic;
+signal	cpu_clk_2x_int		: std_logic;
+signal	cpu_clk_2x_dum_int	: std_logic;
+signal	cpu_clk_4x_int		: std_logic;
+signal	ddr_in_clk_int		: std_logic;
+signal	ddr_in_clk_2x_int	: std_logic;
+
+signal	dcm1_locked_del		: std_logic;
+signal	dcm2_locked_del		: std_logic;
+signal	dcm2_reset			: std_logic;
+signal	dcm3_reset			: std_logic;
+
+signal	locked_int			: std_logic_vector(2 downto 0);
+signal	del_addr			: std_logic_vector(3 downto 0);
+
+begin
+
+	low <= '0';				
+	del_addr <= "1111";
+	
+	cpu_clk <= cpu_clk_int;
+	cpu_clk_2x <= cpu_clk_2x_int;
+	cpu_clk_4x <= cpu_clk_4x_int;
+	ddr_in_clk <= ddr_in_clk_int;
+	ddr_in_clk_2x <= ddr_in_clk_2x_int;
+	locked <= locked_int;
+	
+
+   	CPU_IBUFG: 
+   	IBUFG port map (
+      	O => cpu_clk_in,
+      	I => cpu_clk_p);
+	
+   	SDR_FB_IBUFG: 
+   	IBUFG port map (
+      	O => sdr_clk_fb_in,
+      	I => sdr_clk_fb_p);
+      	
+   dcm2_rst: 
+   SRL16 generic map (
+      	INIT => X"0000")
+   port map (
+      	Q => dcm1_locked_del,
+      	A0 => del_addr(0),
+      	A1 => del_addr(1),
+      	A2 => del_addr(2),
+      	A3 => del_addr(3),
+      	CLK => cpu_clk_int,
+      	D => locked_int(0));
+      	
+	dcm2_reset <= not(dcm1_locked_del);      	
+	
+   dcm3_rst: 
+   SRL16 generic map (
+      	INIT => X"0000")
+   port map (
+      	Q => dcm2_locked_del,
+      	A0 => del_addr(0),
+      	A1 => del_addr(1),
+      	A2 => del_addr(2),
+      	A3 => del_addr(3),
+      	CLK => cpu_clk_int,
+      	D => locked_int(1));
+      	
+	dcm3_reset <= not(dcm2_locked_del);      	
+	
+   	cpu1_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 15.625,          --  Specify period of input clock
+      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_cpu1,   -- 0 degree DCM CLK ouptput
+      	CLK180 => open, 	-- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_cpu2, 	-- 2X DCM CLK output
+      	CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(0), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => cpu_clk_int,   -- DCM clock feedback
+      	CLKIN => cpu_clk_in,   -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => areset);     -- DCM asynchronous reset input
+   
+   	cpu2_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
+      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_cpu2_dum,     	-- 0 degree DCM CLK ouptput
+      	CLK180 => open,		 -- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_cpu4,  -- 2X DCM CLK output
+      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(1), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => cpu_clk_2x_dum_int,   -- DCM clock feedback
+      	CLKIN => cpu_clk_2x_int,   -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => dcm2_reset);     -- DCM asynchronous reset input
+   
+   	ddr_read_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
+     	CLKOUT_PHASE_SHIFT => "FIXED", --  Specify phase shift of NONE, FIXED or VARIABLE
+--      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 103,        --  Amount of fixed phase shift from -255 to 255
+--      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_ddr2,     	-- 0 degree DCM CLK ouptput
+      	CLK180 => open,		 -- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_ddr2_2x,  -- 2X DCM CLK output
+      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(2), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => ddr_in_clk_int,   -- DCM clock feedback
+      	CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => dcm3_reset);     -- DCM asynchronous reset input
+   
+   	cpu1:
+	BUFG port map (
+		I => dcm_cpu1,
+		O => cpu_clk_int);
+		
+   	cpu2:
+	BUFG port map (
+		I => dcm_cpu2,
+		O => cpu_clk_2x_int);
+		
+   	cpu2_dum:
+	BUFG port map (
+		I => dcm_cpu2_dum,
+		O => cpu_clk_2x_dum_int);
+		
+   	cpu4:
+	BUFG port map (
+		I => dcm_cpu4,
+		O => cpu_clk_4x_int);
+		
+   	ddr_clk:
+	BUFG port map (
+		I => dcm_ddr2,
+		O => ddr_in_clk_int);
+
+   	ddr_clk_2x:
+	BUFG port map (
+		I => dcm_ddr2_2x,
+		O => ddr_in_clk_2x_int);
+
 end behave;
\ No newline at end of file
diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd
index a0e494a..159df6f 100644
--- a/zpu/hdl/zpu4/src/io.vhd
+++ b/zpu/hdl/zpu4/src/io.vhd
@@ -1,112 +1,112 @@
-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.numeric_std.all;

-

-use std.textio.all;

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-use work.txt_util.all;

- 

-entity  zpu_io is

-  generic (

-           log_file:       string  := "log.txt"

-          );

-  port(

-       	clk         : in std_logic;

-       	areset        : in std_logic;

-		busy : out std_logic;

-		writeEnable : in std_logic;

-		readEnable : in std_logic;

-		write	: in std_logic_vector(wordSize-1 downto 0);

-		read	: out std_logic_vector(wordSize-1 downto 0);

-		addr : in std_logic_vector(maxAddrBit downto minAddrBit)

-		);

-end zpu_io;

-   

-   

-architecture behave of zpu_io is

-

-

-

-signal timer_read : std_logic_vector(7 downto 0);

---signal timer_write : std_logic_vector(7 downto 0);

-signal timer_we : std_logic;

-

-signal serving : std_logic;

-

-file 		l_file		: TEXT open write_mode is log_file;

-constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0');

-constant tx_full: std_logic := '0';

-constant rx_empty: std_logic := '1';

-

-begin

-

-	

-	timerinst: timer port map (

-       clk => clk,

-		 areset => areset,

-		 we => timer_we,

-		 din => write(7 downto 0),

-		 adr => addr(4 downto 2),

-		 dout => timer_read);

-	

-	busy <= writeEnable or readEnable;

-	timer_we <= writeEnable and addr(12);

-	

-	process(areset, clk)

-	variable taddr  : std_logic_vector(maxAddrBit downto 0);

-	begin

-		taddr := (others => '0');

-		taddr(maxAddrBit downto minAddrBit) := addr;

-

-		if (areset = '1') then

---			timer_we <= '0';

-		elsif (clk'event and clk = '1') then

---			timer_we <= '0';

-			if writeEnable = '1' then

-				-- external interface (fixed address)

-				--<JK> extend compare to avoid waring messages

-				if ("1" & addr & lowAddrBits)=x"80a000c" then

-					report "Write to UART[0]" & " :0x" & hstr(write);

-					-- Write to UART

-					-- report "" & character'image(conv_integer(memBint)) severity note;

-				    print(l_file, character'val(to_integer(unsigned(write))));

-				elsif addr(12)='1' then

-					report "Write to TIMER" & " :0x" & hstr(write);

---				    report "xxx" severity failure;

--- 					timer_we <= '1';

-				else

-					print(l_file, character'val(to_integer(unsigned(write))));

-					report "Illegal IO write @" & "0x" & hstr(taddr) severity warning;

-				end if;

-				

-			end if;

-			read <= (others => '0');

-			if (readEnable = '1') then

-				--<JK> extend compare to avoid waring messages

-				if ("1" & addr & lowAddrBits)=x"80a000c" then

-					report "Read UART[0]";

-					read(8) <= not tx_full; -- output fifo not full

-					read(9) <= not rx_empty; -- receiver not empty

-				elsif ("1" & addr & lowAddrBits)=x"80a0010" then

-					report "Read UART[1]";

-					read(8) <= not rx_empty; -- receiver not empty

-					read(7 downto 0) <= (others => '0');

- 				elsif addr(12)='1' then

-					report "Read TIMER";

- 					read(7 downto 0) <= timer_read;

- 				elsif addr(11)='1' then

-					report "Read ZPU Freq";

- 					read(7 downto 0) <= ZPU_Frequency;

-				else

-					report "Illegal IO read @" & "0x" & hstr(taddr) severity warning;

-				end if;

-			end if;

-		end if;

-	end process;

-

-

-end behave;

- 

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+ 
+entity  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end zpu_io;
+   
+   
+architecture behave of zpu_io is
+
+
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+signal serving : std_logic;
+
+file 		l_file		: TEXT open write_mode is log_file;
+constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0');
+constant tx_full: std_logic := '0';
+constant rx_empty: std_logic := '1';
+
+begin
+
+	
+	timerinst: timer port map (
+       clk => clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => write(7 downto 0),
+		 adr => addr(4 downto 2),
+		 dout => timer_read);
+	
+	busy <= writeEnable or readEnable;
+	timer_we <= writeEnable and addr(12);
+	
+	process(areset, clk)
+	variable taddr  : std_logic_vector(maxAddrBit downto 0);
+	begin
+		taddr := (others => '0');
+		taddr(maxAddrBit downto minAddrBit) := addr;
+
+		if (areset = '1') then
+--			timer_we <= '0';
+		elsif (clk'event and clk = '1') then
+--			timer_we <= '0';
+			if writeEnable = '1' then
+				-- external interface (fixed address)
+				--<JK> extend compare to avoid waring messages
+				if ("1" & addr & lowAddrBits)=x"80a000c" then
+					report "Write to UART[0]" & " :0x" & hstr(write);
+					-- Write to UART
+					-- report "" & character'image(conv_integer(memBint)) severity note;
+				    print(l_file, character'val(to_integer(unsigned(write))));
+				elsif addr(12)='1' then
+					report "Write to TIMER" & " :0x" & hstr(write);
+--				    report "xxx" severity failure;
+-- 					timer_we <= '1';
+				else
+					print(l_file, character'val(to_integer(unsigned(write))));
+					report "Illegal IO write @" & "0x" & hstr(taddr) severity warning;
+				end if;
+				
+			end if;
+			read <= (others => '0');
+			if (readEnable = '1') then
+				--<JK> extend compare to avoid waring messages
+				if ("1" & addr & lowAddrBits)=x"80a000c" then
+					report "Read UART[0]";
+					read(8) <= not tx_full; -- output fifo not full
+					read(9) <= not rx_empty; -- receiver not empty
+				elsif ("1" & addr & lowAddrBits)=x"80a0010" then
+					report "Read UART[1]";
+					read(8) <= not rx_empty; -- receiver not empty
+					read(7 downto 0) <= (others => '0');
+ 				elsif addr(12)='1' then
+					report "Read TIMER";
+ 					read(7 downto 0) <= timer_read;
+ 				elsif addr(11)='1' then
+					report "Read ZPU Freq";
+ 					read(7 downto 0) <= ZPU_Frequency;
+				else
+					report "Illegal IO read @" & "0x" & hstr(taddr) severity warning;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd
index be1dbb8..c60c172 100644
--- a/zpu/hdl/zpu4/src/timer.vhd
+++ b/zpu/hdl/zpu4/src/timer.vhd
@@ -1,61 +1,61 @@
-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.numeric_std.all;

- 

-entity timer is

-  port(

-       clk              : in std_logic;

-		 areset				: in std_logic;

-		 we					: in std_logic;

-		 din					: in std_logic_vector(7 downto 0);

-		 adr					: in std_logic_vector(2 downto 0);

-		 dout					: out std_logic_vector(7 downto 0));

-end timer;

-   

-   

-architecture behave of timer is

-

-signal	sample	: std_logic;

-signal	reset		: std_logic;

-

-

-signal	cnt		: unsigned(63 downto 0);

-signal	cnt_smp	: std_logic_vector(63 downto 0);

-

-begin

-

-	reset <= '1' when (we = '1' and din(0) = '1') else '0';

-	sample <= '1' when (we = '1' and din(1) = '1') else '0';

-

-	process(clk, areset)	-- Carry generation

-	begin

-		if areset = '1' then

-			cnt <= (others => '0');

-			cnt_smp <= (others => '0');

-		elsif (clk'event and clk = '1') then

-			cnt <= cnt + 1;

-			if sample = '1' then

---				report "sampling" severity failure;

-				cnt_smp <= std_logic_vector(cnt);

-			end if;

-		end if;

-	end process;

-	

-	

-	process(cnt_smp, adr)

-	begin

-		case adr is

-			when "000"	=> dout <= cnt_smp(7 downto 0);

-			when "001"	=> dout <= cnt_smp(15 downto 8);

-			when "010"	=> dout <= cnt_smp(23 downto 16);

-			when "011"	=> dout <= cnt_smp(31 downto 24);

-			when "100"	=> dout <= cnt_smp(39 downto 32);

-			when "101"	=> dout <= cnt_smp(47 downto 40);

-			when "110"	=> dout <= cnt_smp(55 downto 48);

-			when others	=> dout <= cnt_smp(63 downto 56);

-		end case;

-	end process;

-	

-

-end behave;

- 

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity timer is
+  port(
+       clk              : in std_logic;
+		 areset				: in std_logic;
+		 we					: in std_logic;
+		 din					: in std_logic_vector(7 downto 0);
+		 adr					: in std_logic_vector(2 downto 0);
+		 dout					: out std_logic_vector(7 downto 0));
+end timer;
+   
+   
+architecture behave of timer is
+
+signal	sample	: std_logic;
+signal	reset		: std_logic;
+
+
+signal	cnt		: unsigned(63 downto 0);
+signal	cnt_smp	: std_logic_vector(63 downto 0);
+
+begin
+
+	reset <= '1' when (we = '1' and din(0) = '1') else '0';
+	sample <= '1' when (we = '1' and din(1) = '1') else '0';
+
+	process(clk, areset)	-- Carry generation
+	begin
+		if areset = '1' then
+			cnt <= (others => '0');
+			cnt_smp <= (others => '0');
+		elsif (clk'event and clk = '1') then
+			cnt <= cnt + 1;
+			if sample = '1' then
+--				report "sampling" severity failure;
+				cnt_smp <= std_logic_vector(cnt);
+			end if;
+		end if;
+	end process;
+	
+	
+	process(cnt_smp, adr)
+	begin
+		case adr is
+			when "000"	=> dout <= cnt_smp(7 downto 0);
+			when "001"	=> dout <= cnt_smp(15 downto 8);
+			when "010"	=> dout <= cnt_smp(23 downto 16);
+			when "011"	=> dout <= cnt_smp(31 downto 24);
+			when "100"	=> dout <= cnt_smp(39 downto 32);
+			when "101"	=> dout <= cnt_smp(47 downto 40);
+			when "110"	=> dout <= cnt_smp(55 downto 48);
+			when others	=> dout <= cnt_smp(63 downto 56);
+		end case;
+	end process;
+	
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd
index 2413970..00ac3a8 100644
--- a/zpu/hdl/zpu4/src/trace.vhd
+++ b/zpu/hdl/zpu4/src/trace.vhd
@@ -1,117 +1,117 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.numeric_std.all;

-

-use std.textio.all;

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-use work.txt_util.all;

- 

- 

-entity trace is

-  generic (

-           log_file:       string  := "trace.txt"

-          );

-  port(

-       	clk         : in std_logic;

-       	begin_inst  : in std_logic;

-       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);

-		opcode		: in std_logic_vector(7 downto 0);

-		sp			: in std_logic_vector(maxAddrBitIncIO downto 2);

-		memA		: in std_logic_vector(wordSize-1 downto 0);

-		memB		: in std_logic_vector(wordSize-1 downto 0);

-		busy  : in std_logic;

-		intSp		: in std_logic_vector(stack_bits-1 downto 0)

-		);

-end trace;

-   

-   

-architecture behave of trace is

-  

-  

-file 		l_file		: TEXT open write_mode is log_file;

-

-

-begin

-

-

--- write data and control information to a file

-

-receive_data: process

-

-variable l: line;

-variable t	: std_logic_vector(wordSize-1 downto 0);

-variable t2	: std_logic_vector(maxAddrBitIncIO downto 0);

-variable counter : unsigned(63 downto 0);

-   

-   

-   

-begin                                       

-

-	t:= (others => '0');

-	t2:= (others => '0');

-

-counter := (others => '0');

-   -- print header for the logfile

-   print(l_file, "#pc,opcode,sp,top_of_stack ");

-   print(l_file, "#----------");

-   print(l_file, " ");

-

-	wait until clk = '1';

-	wait until clk = '0'; 

-

-   while true loop

-

-		counter := counter + 1;

-		if begin_inst = '1' then

-			t(maxAddrBitIncIO downto 2):=sp;

-			t2:=pc;

-     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter)));

-		end if;

-		

-     	wait until clk = '0';

-    

-   end loop;

-

- end process receive_data;

-

-

-

-end behave;

- 

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+ 
+ 
+entity trace is
+  generic (
+           log_file:       string  := "trace.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	begin_inst  : in std_logic;
+       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
+		opcode		: in std_logic_vector(7 downto 0);
+		sp			: in std_logic_vector(maxAddrBitIncIO downto 2);
+		memA		: in std_logic_vector(wordSize-1 downto 0);
+		memB		: in std_logic_vector(wordSize-1 downto 0);
+		busy  : in std_logic;
+		intSp		: in std_logic_vector(stack_bits-1 downto 0)
+		);
+end trace;
+   
+   
+architecture behave of trace is
+  
+  
+file 		l_file		: TEXT open write_mode is log_file;
+
+
+begin
+
+
+-- write data and control information to a file
+
+receive_data: process
+
+variable l: line;
+variable t	: std_logic_vector(wordSize-1 downto 0);
+variable t2	: std_logic_vector(maxAddrBitIncIO downto 0);
+variable counter : unsigned(63 downto 0);
+   
+   
+   
+begin                                       
+
+	t:= (others => '0');
+	t2:= (others => '0');
+
+counter := (others => '0');
+   -- print header for the logfile
+   print(l_file, "#pc,opcode,sp,top_of_stack ");
+   print(l_file, "#----------");
+   print(l_file, " ");
+
+	wait until clk = '1';
+	wait until clk = '0'; 
+
+   while true loop
+
+		counter := counter + 1;
+		if begin_inst = '1' then
+			t(maxAddrBitIncIO downto 2):=sp;
+			t2:=pc;
+     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter)));
+		end if;
+		
+     	wait until clk = '0';
+    
+   end loop;
+
+ end process receive_data;
+
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd
index 3d5297a..6432294 100644
--- a/zpu/hdl/zpu4/src/txt_util.vhd
+++ b/zpu/hdl/zpu4/src/txt_util.vhd
@@ -1,621 +1,621 @@
--- ZPU

---

--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

--- 

--- The FreeBSD license

--- 

--- Redistribution and use in source and binary forms, with or without

--- modification, are permitted provided that the following conditions

--- are met:

--- 

--- 1. Redistributions of source code must retain the above copyright

---    notice, this list of conditions and the following disclaimer.

--- 2. Redistributions in binary form must reproduce the above

---    copyright notice, this list of conditions and the following

---    disclaimer in the documentation and/or other materials

---    provided with the distribution.

--- 

--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--- 

--- The views and conclusions contained in the software and documentation

--- are those of the authors and should not be interpreted as representing

--- official policies, either expressed or implied, of the ZPU Project.

-

-library ieee;

-use ieee.std_logic_1164.all;

-use std.textio.all;

-

-library work;

-

-package txt_util is

-

-    -- prints a message to the screen

-    procedure print(text: string);

-

-    -- prints the message when active

-    -- useful for debug switches

-    procedure print(active: boolean; text: string);

-

-    -- converts std_logic into a character

-    function chr(sl: std_logic) return character;

-

-    -- converts std_logic into a string (1 to 1)

-    function str(sl: std_logic) return string;

-

-    -- converts std_logic_vector into a string (binary base)

-    function str(slv: std_logic_vector) return string;

-

-    -- converts boolean into a string

-    function str(b: boolean) return string;

-

-    -- converts an integer into a single character

-    -- (can also be used for hex conversion and other bases)

-    function chr(int: integer) return character;

-

-    -- converts integer into string using specified base

-    function str(int: integer; base: integer) return string;

-

-    -- converts integer to string, using base 10

-    function str(int: integer) return string;

-

-    -- convert std_logic_vector into a string in hex format

-    function hstr(slv: std_logic_vector) return string;

-

-

-    -- functions to manipulate strings

-    -----------------------------------

-

-    -- convert a character to upper case

-    function to_upper(c: character) return character;

-

-    -- convert a character to lower case

-    function to_lower(c: character) return character;

-

-    -- convert a string to upper case

-    function to_upper(s: string) return string;

-

-    -- convert a string to lower case

-    function to_lower(s: string) return string;

-

-   

-    

-    -- functions to convert strings into other formats

-    --------------------------------------------------

-    

-    -- converts a character into std_logic

-    function to_std_logic(c: character) return std_logic; 

-    

-    -- converts a string into std_logic_vector

-    function to_std_logic_vector(s: string) return std_logic_vector; 

-

-

-  

-    -- file I/O

-    -----------

-       

-    -- read variable length string from input file

-    procedure str_read(file in_file: TEXT; 

-                       res_string: out string);

-        

-    -- print string to a file and start new line

-    procedure print(file out_file: TEXT;

-                    new_string: in  string);

-    

-    -- print character to a file and start new line

-    procedure print(file out_file: TEXT;

-                    char:       in  character);

-                    

-end txt_util;

-

-

-

-

-package body txt_util is

-

-

-

-

-   -- prints text to the screen

-

-   procedure print(text: string) is

-     variable msg_line: line;

-     begin

-       write(msg_line, text);

-       writeline(output, msg_line);

-   end print;

-

-

-

-

-   -- prints text to the screen when active

-

-   procedure print(active: boolean; text: string)  is

-     begin

-      if active then

-         print(text);

-      end if;

-   end print;

-

-

-   -- converts std_logic into a character

-

-   function chr(sl: std_logic) return character is

-    variable c: character;

-    begin

-      case sl is

-         when 'U' => c:= 'U';

-         when 'X' => c:= 'X';

-         when '0' => c:= '0';

-         when '1' => c:= '1';

-         when 'Z' => c:= 'Z';

-         when 'W' => c:= 'W';

-         when 'L' => c:= 'L';

-         when 'H' => c:= 'H';

-         when '-' => c:= '-';

-      end case;

-    return c;

-   end chr;

-

-

-

-   -- converts std_logic into a string (1 to 1)

-

-   function str(sl: std_logic) return string is

-    variable s: string(1 to 1);

-    begin

-        s(1) := chr(sl);

-        return s;

-   end str;

-

-

-

-   -- converts std_logic_vector into a string (binary base)

-   -- (this also takes care of the fact that the range of

-   --  a string is natural while a std_logic_vector may

-   --  have an integer range)

-

-   function str(slv: std_logic_vector) return string is

-     variable result : string (1 to slv'length);

-     variable r : integer;

-   begin

-     r := 1;

-     for i in slv'range loop

-        result(r) := chr(slv(i));

-        r := r + 1;

-     end loop;

-     return result;

-   end str;

-

-

-   function str(b: boolean) return string is

-

-    begin

-       if b then

-          return "true";

-      else

-        return "false";

-       end if;

-    end str;

-

-

-   -- converts an integer into a character

-   -- for 0 to 9 the obvious mapping is used, higher

-   -- values are mapped to the characters A-Z

-   -- (this is usefull for systems with base > 10)

-   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)

-

-   function chr(int: integer) return character is

-    variable c: character;

-   begin

-        case int is

-          when  0 => c := '0';

-          when  1 => c := '1';

-          when  2 => c := '2';

-          when  3 => c := '3';

-          when  4 => c := '4';

-          when  5 => c := '5';

-          when  6 => c := '6';

-          when  7 => c := '7';

-          when  8 => c := '8';

-          when  9 => c := '9';

-          when 10 => c := 'A';

-          when 11 => c := 'B';

-          when 12 => c := 'C';

-          when 13 => c := 'D';

-          when 14 => c := 'E';

-          when 15 => c := 'F';

-          when 16 => c := 'G';

-          when 17 => c := 'H';

-          when 18 => c := 'I';

-          when 19 => c := 'J';

-          when 20 => c := 'K';

-          when 21 => c := 'L';

-          when 22 => c := 'M';

-          when 23 => c := 'N';

-          when 24 => c := 'O';

-          when 25 => c := 'P';

-          when 26 => c := 'Q';

-          when 27 => c := 'R';

-          when 28 => c := 'S';

-          when 29 => c := 'T';

-          when 30 => c := 'U';

-          when 31 => c := 'V';

-          when 32 => c := 'W';

-          when 33 => c := 'X';

-          when 34 => c := 'Y';

-          when 35 => c := 'Z';

-          when others => c := '?';

-        end case;

-        return c;

-    end chr;

-

-

-

-   -- convert integer to string using specified base

-   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)

-

-   function str(int: integer; base: integer) return string is

-

-    variable temp:      string(1 to 10);

-    variable num:       integer;

-    variable abs_int:   integer;

-    variable len:       integer := 1;

-    variable power:     integer := 1;

-

-   begin

-

-    -- bug fix for negative numbers

-    abs_int := abs(int);

-

-    num     := abs_int;

-

-    while num >= base loop                     -- Determine how many

-      len := len + 1;                          -- characters required

-      num := num / base;                       -- to represent the

-    end loop ;                                 -- number.

-

-    for i in len downto 1 loop                 -- Convert the number to

-      temp(i) := chr(abs_int/power mod base);  -- a string starting

-      power := power * base;                   -- with the right hand

-    end loop ;                                 -- side.

-

-    -- return result and add sign if required

-    if int < 0 then

-       return '-'& temp(1 to len);

-     else

-       return temp(1 to len);

-    end if;

-

-   end str;

-

-

-  -- convert integer to string, using base 10

-  function str(int: integer) return string is

-

-   begin

-

-    return str(int, 10) ;

-

-   end str;

-

-

-

-   -- converts a std_logic_vector into a hex string.

-   function hstr(slv: std_logic_vector) return string is

-       variable hexlen: integer;

-       variable longslv : std_logic_vector(67 downto 0) := (others => '0');

-       variable hex : string(1 to 16);

-       variable fourbit : std_logic_vector(3 downto 0);

-     begin

-       hexlen := (slv'left+1)/4;

-       if (slv'left+1) mod 4 /= 0 then

-         hexlen := hexlen + 1;

-       end if;

-       longslv(slv'left downto 0) := slv;

-       for i in (hexlen -1) downto 0 loop

-         fourbit := longslv(((i*4)+3) downto (i*4));

-         case fourbit is

-           when "0000" => hex(hexlen -I) := '0';

-           when "0001" => hex(hexlen -I) := '1';

-           when "0010" => hex(hexlen -I) := '2';

-           when "0011" => hex(hexlen -I) := '3';

-           when "0100" => hex(hexlen -I) := '4';

-           when "0101" => hex(hexlen -I) := '5';

-           when "0110" => hex(hexlen -I) := '6';

-           when "0111" => hex(hexlen -I) := '7';

-           when "1000" => hex(hexlen -I) := '8';

-           when "1001" => hex(hexlen -I) := '9';

-           when "1010" => hex(hexlen -I) := 'A';

-           when "1011" => hex(hexlen -I) := 'B';

-           when "1100" => hex(hexlen -I) := 'C';

-           when "1101" => hex(hexlen -I) := 'D';

-           when "1110" => hex(hexlen -I) := 'E';

-           when "1111" => hex(hexlen -I) := 'F';

-           when "ZZZZ" => hex(hexlen -I) := 'z';

-           when "UUUU" => hex(hexlen -I) := 'u';

-           when "XXXX" => hex(hexlen -I) := 'x';

-           when others => hex(hexlen -I) := '?';

-         end case;

-       end loop;

-       return hex(1 to hexlen);

-     end hstr;

-

-

-

-   -- functions to manipulate strings

-   -----------------------------------

-

-

-   -- convert a character to upper case

-

-   function to_upper(c: character) return character is

-

-      variable u: character;

-

-    begin

-

-       case c is

-        when 'a' => u := 'A';

-        when 'b' => u := 'B';

-        when 'c' => u := 'C';

-        when 'd' => u := 'D';

-        when 'e' => u := 'E';

-        when 'f' => u := 'F';

-        when 'g' => u := 'G';

-        when 'h' => u := 'H';

-        when 'i' => u := 'I';

-        when 'j' => u := 'J';

-        when 'k' => u := 'K';

-        when 'l' => u := 'L';

-        when 'm' => u := 'M';

-        when 'n' => u := 'N';

-        when 'o' => u := 'O';

-        when 'p' => u := 'P';

-        when 'q' => u := 'Q';

-        when 'r' => u := 'R';

-        when 's' => u := 'S';

-        when 't' => u := 'T';

-        when 'u' => u := 'U';

-        when 'v' => u := 'V';

-        when 'w' => u := 'W';

-        when 'x' => u := 'X';

-        when 'y' => u := 'Y';

-        when 'z' => u := 'Z';

-        when others => u := c;

-    end case;

-

-      return u;

-

-   end to_upper;

-

-

-   -- convert a character to lower case

-

-   function to_lower(c: character) return character is

-

-      variable l: character;

-

-    begin

-

-       case c is

-        when 'A' => l := 'a';

-        when 'B' => l := 'b';

-        when 'C' => l := 'c';

-        when 'D' => l := 'd';

-        when 'E' => l := 'e';

-        when 'F' => l := 'f';

-        when 'G' => l := 'g';

-        when 'H' => l := 'h';

-        when 'I' => l := 'i';

-        when 'J' => l := 'j';

-        when 'K' => l := 'k';

-        when 'L' => l := 'l';

-        when 'M' => l := 'm';

-        when 'N' => l := 'n';

-        when 'O' => l := 'o';

-        when 'P' => l := 'p';

-        when 'Q' => l := 'q';

-        when 'R' => l := 'r';

-        when 'S' => l := 's';

-        when 'T' => l := 't';

-        when 'U' => l := 'u';

-        when 'V' => l := 'v';

-        when 'W' => l := 'w';

-        when 'X' => l := 'x';

-        when 'Y' => l := 'y';

-        when 'Z' => l := 'z';

-        when others => l := c;

-    end case;

-

-      return l;

-

-   end to_lower;

-

-

-

-   -- convert a string to upper case

-

-   function to_upper(s: string) return string is

-

-     variable uppercase: string (s'range);

-

-   begin

-

-     for i in s'range loop

-        uppercase(i):= to_upper(s(i));

-     end loop;

-     return uppercase;

-

-   end to_upper;

-

-

-

-   -- convert a string to lower case

-

-   function to_lower(s: string) return string is

-

-     variable lowercase: string (s'range);

-

-   begin

-

-     for i in s'range loop

-        lowercase(i):= to_lower(s(i));

-     end loop;

-     return lowercase;

-

-   end to_lower;

-

-

-

--- functions to convert strings into other types

-

-

--- converts a character into a std_logic

-

-function to_std_logic(c: character) return std_logic is 

-    variable sl: std_logic;

-    begin

-      case c is

-        when 'U' => 

-           sl := 'U'; 

-        when 'X' =>

-           sl := 'X';

-        when '0' => 

-           sl := '0';

-        when '1' => 

-           sl := '1';

-        when 'Z' => 

-           sl := 'Z';

-        when 'W' => 

-           sl := 'W';

-        when 'L' => 

-           sl := 'L';

-        when 'H' => 

-           sl := 'H';

-        when '-' => 

-           sl := '-';

-        when others =>

-           sl := 'X'; 

-    end case;

-   return sl;

-  end to_std_logic;

-

-

--- converts a string into std_logic_vector

-

-function to_std_logic_vector(s: string) return std_logic_vector is 

-  variable slv: std_logic_vector(s'high-s'low downto 0);

-  variable k: integer;

-begin

-   k := s'high-s'low;

-  for i in s'range loop

-     slv(k) := to_std_logic(s(i));

-     k      := k - 1;

-  end loop;

-  return slv;

-end to_std_logic_vector;                                       

-                                       

-                                       

-                                       

-                                       

-                                       

-                                       

-----------------

---  file I/O  --

-----------------

-

-

-

--- read variable length string from input file

-     

-procedure str_read(file in_file: TEXT; 

-                   res_string: out string) is

-       

-       variable l:         line;

-       variable c:         character;

-       variable is_string: boolean;

-       

-   begin

-           

-     readline(in_file, l);

-     -- clear the contents of the result string

-     for i in res_string'range loop

-         res_string(i) := ' ';

-     end loop;   

-     -- read all characters of the line, up to the length  

-     -- of the results string

-     for i in res_string'range loop

-        read(l, c, is_string);

-        res_string(i) := c;

-        if not is_string then -- found end of line

-           exit;

-        end if;   

-     end loop; 

-                     

-end str_read;

-

-

--- print string to a file

-procedure print(file out_file: TEXT;

-                new_string: in  string) is

-       

-       variable l: line;

-       

-   begin

-      

-     write(l, new_string);

-     writeline(out_file, l);

-                     

-end print;

-

-

--- print character to a file and start new line

-procedure print(file out_file: TEXT;

-                char: in  character) is

-       

-       variable l: line;

-       

-   begin

-      

-     write(l, char);

-     writeline(out_file, l);

-                     

-end print;

-

-

-

--- appends contents of a string to a file until line feed occurs

--- (LF is considered to be the end of the string)

-

-procedure str_write(file out_file: TEXT; 

-                    new_string: in  string) is

- begin

-      

-   for i in new_string'range loop

-      print(out_file, new_string(i));

-      if new_string(i) = LF then -- end of string

-         exit;

-      end if;

-   end loop;               

-                     

-end str_write;

-

-

-

-

-end txt_util;

-

-

-

-

+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+
+library work;
+
+package txt_util is
+
+    -- prints a message to the screen
+    procedure print(text: string);
+
+    -- prints the message when active
+    -- useful for debug switches
+    procedure print(active: boolean; text: string);
+
+    -- converts std_logic into a character
+    function chr(sl: std_logic) return character;
+
+    -- converts std_logic into a string (1 to 1)
+    function str(sl: std_logic) return string;
+
+    -- converts std_logic_vector into a string (binary base)
+    function str(slv: std_logic_vector) return string;
+
+    -- converts boolean into a string
+    function str(b: boolean) return string;
+
+    -- converts an integer into a single character
+    -- (can also be used for hex conversion and other bases)
+    function chr(int: integer) return character;
+
+    -- converts integer into string using specified base
+    function str(int: integer; base: integer) return string;
+
+    -- converts integer to string, using base 10
+    function str(int: integer) return string;
+
+    -- convert std_logic_vector into a string in hex format
+    function hstr(slv: std_logic_vector) return string;
+
+
+    -- functions to manipulate strings
+    -----------------------------------
+
+    -- convert a character to upper case
+    function to_upper(c: character) return character;
+
+    -- convert a character to lower case
+    function to_lower(c: character) return character;
+
+    -- convert a string to upper case
+    function to_upper(s: string) return string;
+
+    -- convert a string to lower case
+    function to_lower(s: string) return string;
+
+   
+    
+    -- functions to convert strings into other formats
+    --------------------------------------------------
+    
+    -- converts a character into std_logic
+    function to_std_logic(c: character) return std_logic; 
+    
+    -- converts a string into std_logic_vector
+    function to_std_logic_vector(s: string) return std_logic_vector; 
+
+
+  
+    -- file I/O
+    -----------
+       
+    -- read variable length string from input file
+    procedure str_read(file in_file: TEXT; 
+                       res_string: out string);
+        
+    -- print string to a file and start new line
+    procedure print(file out_file: TEXT;
+                    new_string: in  string);
+    
+    -- print character to a file and start new line
+    procedure print(file out_file: TEXT;
+                    char:       in  character);
+                    
+end txt_util;
+
+
+
+
+package body txt_util is
+
+
+
+
+   -- prints text to the screen
+
+   procedure print(text: string) is
+     variable msg_line: line;
+     begin
+       write(msg_line, text);
+       writeline(output, msg_line);
+   end print;
+
+
+
+
+   -- prints text to the screen when active
+
+   procedure print(active: boolean; text: string)  is
+     begin
+      if active then
+         print(text);
+      end if;
+   end print;
+
+
+   -- converts std_logic into a character
+
+   function chr(sl: std_logic) return character is
+    variable c: character;
+    begin
+      case sl is
+         when 'U' => c:= 'U';
+         when 'X' => c:= 'X';
+         when '0' => c:= '0';
+         when '1' => c:= '1';
+         when 'Z' => c:= 'Z';
+         when 'W' => c:= 'W';
+         when 'L' => c:= 'L';
+         when 'H' => c:= 'H';
+         when '-' => c:= '-';
+      end case;
+    return c;
+   end chr;
+
+
+
+   -- converts std_logic into a string (1 to 1)
+
+   function str(sl: std_logic) return string is
+    variable s: string(1 to 1);
+    begin
+        s(1) := chr(sl);
+        return s;
+   end str;
+
+
+
+   -- converts std_logic_vector into a string (binary base)
+   -- (this also takes care of the fact that the range of
+   --  a string is natural while a std_logic_vector may
+   --  have an integer range)
+
+   function str(slv: std_logic_vector) return string is
+     variable result : string (1 to slv'length);
+     variable r : integer;
+   begin
+     r := 1;
+     for i in slv'range loop
+        result(r) := chr(slv(i));
+        r := r + 1;
+     end loop;
+     return result;
+   end str;
+
+
+   function str(b: boolean) return string is
+
+    begin
+       if b then
+          return "true";
+      else
+        return "false";
+       end if;
+    end str;
+
+
+   -- converts an integer into a character
+   -- for 0 to 9 the obvious mapping is used, higher
+   -- values are mapped to the characters A-Z
+   -- (this is usefull for systems with base > 10)
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function chr(int: integer) return character is
+    variable c: character;
+   begin
+        case int is
+          when  0 => c := '0';
+          when  1 => c := '1';
+          when  2 => c := '2';
+          when  3 => c := '3';
+          when  4 => c := '4';
+          when  5 => c := '5';
+          when  6 => c := '6';
+          when  7 => c := '7';
+          when  8 => c := '8';
+          when  9 => c := '9';
+          when 10 => c := 'A';
+          when 11 => c := 'B';
+          when 12 => c := 'C';
+          when 13 => c := 'D';
+          when 14 => c := 'E';
+          when 15 => c := 'F';
+          when 16 => c := 'G';
+          when 17 => c := 'H';
+          when 18 => c := 'I';
+          when 19 => c := 'J';
+          when 20 => c := 'K';
+          when 21 => c := 'L';
+          when 22 => c := 'M';
+          when 23 => c := 'N';
+          when 24 => c := 'O';
+          when 25 => c := 'P';
+          when 26 => c := 'Q';
+          when 27 => c := 'R';
+          when 28 => c := 'S';
+          when 29 => c := 'T';
+          when 30 => c := 'U';
+          when 31 => c := 'V';
+          when 32 => c := 'W';
+          when 33 => c := 'X';
+          when 34 => c := 'Y';
+          when 35 => c := 'Z';
+          when others => c := '?';
+        end case;
+        return c;
+    end chr;
+
+
+
+   -- convert integer to string using specified base
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function str(int: integer; base: integer) return string is
+
+    variable temp:      string(1 to 10);
+    variable num:       integer;
+    variable abs_int:   integer;
+    variable len:       integer := 1;
+    variable power:     integer := 1;
+
+   begin
+
+    -- bug fix for negative numbers
+    abs_int := abs(int);
+
+    num     := abs_int;
+
+    while num >= base loop                     -- Determine how many
+      len := len + 1;                          -- characters required
+      num := num / base;                       -- to represent the
+    end loop ;                                 -- number.
+
+    for i in len downto 1 loop                 -- Convert the number to
+      temp(i) := chr(abs_int/power mod base);  -- a string starting
+      power := power * base;                   -- with the right hand
+    end loop ;                                 -- side.
+
+    -- return result and add sign if required
+    if int < 0 then
+       return '-'& temp(1 to len);
+     else
+       return temp(1 to len);
+    end if;
+
+   end str;
+
+
+  -- convert integer to string, using base 10
+  function str(int: integer) return string is
+
+   begin
+
+    return str(int, 10) ;
+
+   end str;
+
+
+
+   -- converts a std_logic_vector into a hex string.
+   function hstr(slv: std_logic_vector) return string is
+       variable hexlen: integer;
+       variable longslv : std_logic_vector(67 downto 0) := (others => '0');
+       variable hex : string(1 to 16);
+       variable fourbit : std_logic_vector(3 downto 0);
+     begin
+       hexlen := (slv'left+1)/4;
+       if (slv'left+1) mod 4 /= 0 then
+         hexlen := hexlen + 1;
+       end if;
+       longslv(slv'left downto 0) := slv;
+       for i in (hexlen -1) downto 0 loop
+         fourbit := longslv(((i*4)+3) downto (i*4));
+         case fourbit is
+           when "0000" => hex(hexlen -I) := '0';
+           when "0001" => hex(hexlen -I) := '1';
+           when "0010" => hex(hexlen -I) := '2';
+           when "0011" => hex(hexlen -I) := '3';
+           when "0100" => hex(hexlen -I) := '4';
+           when "0101" => hex(hexlen -I) := '5';
+           when "0110" => hex(hexlen -I) := '6';
+           when "0111" => hex(hexlen -I) := '7';
+           when "1000" => hex(hexlen -I) := '8';
+           when "1001" => hex(hexlen -I) := '9';
+           when "1010" => hex(hexlen -I) := 'A';
+           when "1011" => hex(hexlen -I) := 'B';
+           when "1100" => hex(hexlen -I) := 'C';
+           when "1101" => hex(hexlen -I) := 'D';
+           when "1110" => hex(hexlen -I) := 'E';
+           when "1111" => hex(hexlen -I) := 'F';
+           when "ZZZZ" => hex(hexlen -I) := 'z';
+           when "UUUU" => hex(hexlen -I) := 'u';
+           when "XXXX" => hex(hexlen -I) := 'x';
+           when others => hex(hexlen -I) := '?';
+         end case;
+       end loop;
+       return hex(1 to hexlen);
+     end hstr;
+
+
+
+   -- functions to manipulate strings
+   -----------------------------------
+
+
+   -- convert a character to upper case
+
+   function to_upper(c: character) return character is
+
+      variable u: character;
+
+    begin
+
+       case c is
+        when 'a' => u := 'A';
+        when 'b' => u := 'B';
+        when 'c' => u := 'C';
+        when 'd' => u := 'D';
+        when 'e' => u := 'E';
+        when 'f' => u := 'F';
+        when 'g' => u := 'G';
+        when 'h' => u := 'H';
+        when 'i' => u := 'I';
+        when 'j' => u := 'J';
+        when 'k' => u := 'K';
+        when 'l' => u := 'L';
+        when 'm' => u := 'M';
+        when 'n' => u := 'N';
+        when 'o' => u := 'O';
+        when 'p' => u := 'P';
+        when 'q' => u := 'Q';
+        when 'r' => u := 'R';
+        when 's' => u := 'S';
+        when 't' => u := 'T';
+        when 'u' => u := 'U';
+        when 'v' => u := 'V';
+        when 'w' => u := 'W';
+        when 'x' => u := 'X';
+        when 'y' => u := 'Y';
+        when 'z' => u := 'Z';
+        when others => u := c;
+    end case;
+
+      return u;
+
+   end to_upper;
+
+
+   -- convert a character to lower case
+
+   function to_lower(c: character) return character is
+
+      variable l: character;
+
+    begin
+
+       case c is
+        when 'A' => l := 'a';
+        when 'B' => l := 'b';
+        when 'C' => l := 'c';
+        when 'D' => l := 'd';
+        when 'E' => l := 'e';
+        when 'F' => l := 'f';
+        when 'G' => l := 'g';
+        when 'H' => l := 'h';
+        when 'I' => l := 'i';
+        when 'J' => l := 'j';
+        when 'K' => l := 'k';
+        when 'L' => l := 'l';
+        when 'M' => l := 'm';
+        when 'N' => l := 'n';
+        when 'O' => l := 'o';
+        when 'P' => l := 'p';
+        when 'Q' => l := 'q';
+        when 'R' => l := 'r';
+        when 'S' => l := 's';
+        when 'T' => l := 't';
+        when 'U' => l := 'u';
+        when 'V' => l := 'v';
+        when 'W' => l := 'w';
+        when 'X' => l := 'x';
+        when 'Y' => l := 'y';
+        when 'Z' => l := 'z';
+        when others => l := c;
+    end case;
+
+      return l;
+
+   end to_lower;
+
+
+
+   -- convert a string to upper case
+
+   function to_upper(s: string) return string is
+
+     variable uppercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        uppercase(i):= to_upper(s(i));
+     end loop;
+     return uppercase;
+
+   end to_upper;
+
+
+
+   -- convert a string to lower case
+
+   function to_lower(s: string) return string is
+
+     variable lowercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        lowercase(i):= to_lower(s(i));
+     end loop;
+     return lowercase;
+
+   end to_lower;
+
+
+
+-- functions to convert strings into other types
+
+
+-- converts a character into a std_logic
+
+function to_std_logic(c: character) return std_logic is 
+    variable sl: std_logic;
+    begin
+      case c is
+        when 'U' => 
+           sl := 'U'; 
+        when 'X' =>
+           sl := 'X';
+        when '0' => 
+           sl := '0';
+        when '1' => 
+           sl := '1';
+        when 'Z' => 
+           sl := 'Z';
+        when 'W' => 
+           sl := 'W';
+        when 'L' => 
+           sl := 'L';
+        when 'H' => 
+           sl := 'H';
+        when '-' => 
+           sl := '-';
+        when others =>
+           sl := 'X'; 
+    end case;
+   return sl;
+  end to_std_logic;
+
+
+-- converts a string into std_logic_vector
+
+function to_std_logic_vector(s: string) return std_logic_vector is 
+  variable slv: std_logic_vector(s'high-s'low downto 0);
+  variable k: integer;
+begin
+   k := s'high-s'low;
+  for i in s'range loop
+     slv(k) := to_std_logic(s(i));
+     k      := k - 1;
+  end loop;
+  return slv;
+end to_std_logic_vector;                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+----------------
+--  file I/O  --
+----------------
+
+
+
+-- read variable length string from input file
+     
+procedure str_read(file in_file: TEXT; 
+                   res_string: out string) is
+       
+       variable l:         line;
+       variable c:         character;
+       variable is_string: boolean;
+       
+   begin
+           
+     readline(in_file, l);
+     -- clear the contents of the result string
+     for i in res_string'range loop
+         res_string(i) := ' ';
+     end loop;   
+     -- read all characters of the line, up to the length  
+     -- of the results string
+     for i in res_string'range loop
+        read(l, c, is_string);
+        res_string(i) := c;
+        if not is_string then -- found end of line
+           exit;
+        end if;   
+     end loop; 
+                     
+end str_read;
+
+
+-- print string to a file
+procedure print(file out_file: TEXT;
+                new_string: in  string) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, new_string);
+     writeline(out_file, l);
+                     
+end print;
+
+
+-- print character to a file and start new line
+procedure print(file out_file: TEXT;
+                char: in  character) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, char);
+     writeline(out_file, l);
+                     
+end print;
+
+
+
+-- appends contents of a string to a file until line feed occurs
+-- (LF is considered to be the end of the string)
+
+procedure str_write(file out_file: TEXT; 
+                    new_string: in  string) is
+ begin
+      
+   for i in new_string'range loop
+      print(out_file, new_string(i));
+      if new_string(i) = LF then -- end of string
+         exit;
+      end if;
+   end loop;               
+                     
+end str_write;
+
+
+
+
+end txt_util;
+
+
+
+
diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd
index 09a1ddd..2c7fd41 100644
--- a/zpu/hdl/zpu4/src/zpuio.vhd
+++ b/zpu/hdl/zpu4/src/zpuio.vhd
@@ -1,232 +1,232 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.ALL;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-entity zpuio is

-	port (	areset			: in std_logic;

-			cpu_clk			: in std_logic;

-			clk_status		: in std_logic_vector(2 downto 0);

-			cpu_din			: in std_logic_vector(15 downto 0);

-			cpu_a			: in std_logic_vector(20 downto 0);

-			cpu_we			: in std_logic_vector(1 downto 0);

-			cpu_re			: in std_logic;

-			cpu_dout		: inout std_logic_vector(15 downto 0));

-end zpuio;

-

-architecture behave of zpuio is

-

-signal timer_read : std_logic_vector(7 downto 0);

---signal timer_write : std_logic_vector(7 downto 0);

-signal timer_we : std_logic;

-

-

-signal io_busy : std_logic;

-signal io_read : std_logic_vector(7 downto 0);

---signal io_write : std_logic_vector(7 downto 0);

-signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);

-signal io_writeEnable : std_logic;

-signal Enable : std_logic;

-

-signal		  din :  std_logic_vector(7 downto 0);

-signal	 		  dout : std_logic_vector(7 downto 0);

-signal			  adr : std_logic_vector(15 downto 0);

-signal			  break : std_logic;

-signal			  we : std_logic;

-signal			  re : std_logic;

-

-

--- uart forwarding...

-

-signal uartTXPending : std_logic;

-signal uartTXCleared : std_logic;

-signal uartData : std_logic_vector(7 downto 0);

-

-signal readingTimer : std_logic;

-

-

-

-

-signal			  mem_busy : std_logic;

-signal			  mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);

-signal			  mem_writeEnable : std_logic; 

-signal			  mem_readEnable : std_logic;

-signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-signal			  dram_mem_busy : std_logic;

-signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_writeEnable : std_logic; 

-signal			  dram_mem_readEnable : std_logic;

-signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-

-

---signal			  io_mem_read : std_logic_vector(7 downto 0);

---signal			  io_mem_writeEnable : std_logic; 

---signal			  io_mem_readEnable : std_logic;

-signal			  io_readEnable : std_logic;

-

-

-signal			  dram_read : std_logic;

-

-

-

-begin

-

-	io_addr <= mem_addr(maxAddrBit downto minAddrBit);

-	

-	timerinst: timer port map (

-       clk => cpu_clk,

-		 areset => areset,

-		 we => timer_we,

-		 din => mem_write(7 downto 0),

-		 adr => io_addr(4 downto 2),

-		 dout => timer_read);

-

-		zpu: zpu_core port map (

-		clk => cpu_clk ,

-	 	areset => areset,

- 		in_mem_busy => mem_busy, 

- 		mem_read => mem_read,

- 		mem_write => mem_write, 

-		out_mem_addr => mem_addr, 

-		out_mem_writeEnable => mem_writeEnable,  

-		out_mem_readEnable => mem_readEnable,

- 		mem_writeMask => mem_writeMask, 

- 		interrupt => '0',

- 		break  => break);

-

-

-ram_imp: dram port map (

-		clk => cpu_clk ,

-		areset => areset,

- 		mem_busy => dram_mem_busy, 

- 		mem_read => dram_mem_read,

- 		mem_write => mem_write, 

-		mem_addr => mem_addr(maxAddrBit downto 0), 

-		mem_writeEnable => dram_mem_writeEnable,  

-		mem_readEnable => dram_mem_readEnable,

- 		mem_writeMask => mem_writeMask);

-

-

-	

-	fauxUart:

-	process(cpu_clk, areset)

-	begin

-		if areset = '1' then

-			io_busy <= '0';

-			uartTXPending <= '0';

-			timer_we <= '0';

-			io_busy <= '0';

-			uartData <= x"58"; -- 'X'

-			readingTimer <= '0';

-		elsif (cpu_clk'event and cpu_clk = '1') then

-			timer_we <= '0';

-			io_busy <= '0';

-			if uartTXCleared = '1' then

-				uartTXPending <= '0';

-			end if;

-		

-			if io_writeEnable = '1' then

-				if io_addr=x"2028003" then

-					-- Write to UART

-					uartData <= mem_write(7 downto 0);

-					uartTXPending <= '1';

-					io_busy <= '1';

- 				elsif io_addr(12)='1' then

- 					timer_we <= '1';

-					io_busy <= '1';

-				else

---					report "Illegal IO write" severity failure;

-				end if;

-			end if;

-			if (io_readEnable = '1') then

-				if io_addr=x"2028003" then

-					io_read <= (0=>'1',  		-- recieve empty

- 					            1 => uartTXPending,   -- tx full

- 					            others => '0');

- 					io_busy <= '1';

- 				elsif io_addr(12)='1' then

- 					readingTimer <= '1';

- 					io_busy <= '1';

- 				elsif io_addr(11)='1' then

- 					io_read <= ZPU_Frequency;

- 					io_busy <= '1';

-				else

---					report "Illegal IO read" severity failure;

-				end if;

-				

-			else 

-				if (readingTimer = '1') then

-					readingTimer <= '0';

- 					io_read <= timer_read;

- 					io_busy <= '0';

- 				else

-					io_read <= (others => '1');

- 				end if;

-			end if;

-		end if;

-	end process;

-

-

-	forwardUARTOutputToARM:

-	process(cpu_clk, areset)

-	begin

-		if areset = '1' then

-			uartTXCleared <= '0';

-		elsif (cpu_clk = '1' and cpu_clk'event) then

-			if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then

-				uartTXCleared <= cpu_din(0);

-			else

-				uartTXCleared <= uartTXCleared;

-			end if;

-		end if;

-	end process;	

-

-	cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');

-	cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');

-	

-	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);

-	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);

-	io_writeEnable <= mem_writeEnable and mem_addr(ioBit);

---	io_readEnable <= mem_readEnable and mem_addr(ioBit);

-	mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable;

-

-	-- Memory reads either come from IO or DRAM. We need to pick the right one.

-	memorycontrol:

-	process(cpu_clk, areset)

-	begin

-		if areset = '1' then

-			dram_read <= '0';

-			io_readEnable <= '0';

-

-		

-		elsif (cpu_clk'event and cpu_clk = '1') then

-			mem_read <= (others => '0');

-			if mem_addr(ioBit)='0' and mem_readEnable='1' then

-				dram_read <= '1';

-			end if;

-			if dram_read='1' and dram_mem_busy='0' then

-				dram_read <= '0';

-				mem_read <= dram_mem_read;

-			end if;

-			 

-			if mem_addr(ioBit)='1' and mem_readEnable='1' then

-				io_readEnable <= '1';

-			end if;

-			if io_readEnable='1' and io_busy='0' then

-				io_readEnable <= '0';

-				mem_read(7 downto 0) <= io_read;

-			end if;

-			

-		end if;

-	end process;

-

-

-end behave;

+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity zpuio is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			clk_status		: in std_logic_vector(2 downto 0);
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_dout		: inout std_logic_vector(15 downto 0));
+end zpuio;
+
+architecture behave of zpuio is
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+
+signal io_busy : std_logic;
+signal io_read : std_logic_vector(7 downto 0);
+--signal io_write : std_logic_vector(7 downto 0);
+signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal io_writeEnable : std_logic;
+signal Enable : std_logic;
+
+signal		  din :  std_logic_vector(7 downto 0);
+signal	 		  dout : std_logic_vector(7 downto 0);
+signal			  adr : std_logic_vector(15 downto 0);
+signal			  break : std_logic;
+signal			  we : std_logic;
+signal			  re : std_logic;
+
+
+-- uart forwarding...
+
+signal uartTXPending : std_logic;
+signal uartTXCleared : std_logic;
+signal uartData : std_logic_vector(7 downto 0);
+
+signal readingTimer : std_logic;
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+
+--signal			  io_mem_read : std_logic_vector(7 downto 0);
+--signal			  io_mem_writeEnable : std_logic; 
+--signal			  io_mem_readEnable : std_logic;
+signal			  io_readEnable : std_logic;
+
+
+signal			  dram_read : std_logic;
+
+
+
+begin
+
+	io_addr <= mem_addr(maxAddrBit downto minAddrBit);
+	
+	timerinst: timer port map (
+       clk => cpu_clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => mem_write(7 downto 0),
+		 adr => io_addr(4 downto 2),
+		 dout => timer_read);
+
+		zpu: zpu_core port map (
+		clk => cpu_clk ,
+	 	areset => areset,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+
+ram_imp: dram port map (
+		clk => cpu_clk ,
+		areset => areset,
+ 		mem_busy => dram_mem_busy, 
+ 		mem_read => dram_mem_read,
+ 		mem_write => mem_write, 
+		mem_addr => mem_addr(maxAddrBit downto 0), 
+		mem_writeEnable => dram_mem_writeEnable,  
+		mem_readEnable => dram_mem_readEnable,
+ 		mem_writeMask => mem_writeMask);
+
+
+	
+	fauxUart:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			io_busy <= '0';
+			uartTXPending <= '0';
+			timer_we <= '0';
+			io_busy <= '0';
+			uartData <= x"58"; -- 'X'
+			readingTimer <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			timer_we <= '0';
+			io_busy <= '0';
+			if uartTXCleared = '1' then
+				uartTXPending <= '0';
+			end if;
+		
+			if io_writeEnable = '1' then
+				if io_addr=x"2028003" then
+					-- Write to UART
+					uartData <= mem_write(7 downto 0);
+					uartTXPending <= '1';
+					io_busy <= '1';
+ 				elsif io_addr(12)='1' then
+ 					timer_we <= '1';
+					io_busy <= '1';
+				else
+--					report "Illegal IO write" severity failure;
+				end if;
+			end if;
+			if (io_readEnable = '1') then
+				if io_addr=x"2028003" then
+					io_read <= (0=>'1',  		-- recieve empty
+ 					            1 => uartTXPending,   -- tx full
+ 					            others => '0');
+ 					io_busy <= '1';
+ 				elsif io_addr(12)='1' then
+ 					readingTimer <= '1';
+ 					io_busy <= '1';
+ 				elsif io_addr(11)='1' then
+ 					io_read <= ZPU_Frequency;
+ 					io_busy <= '1';
+				else
+--					report "Illegal IO read" severity failure;
+				end if;
+				
+			else 
+				if (readingTimer = '1') then
+					readingTimer <= '0';
+ 					io_read <= timer_read;
+ 					io_busy <= '0';
+ 				else
+					io_read <= (others => '1');
+ 				end if;
+			end if;
+		end if;
+	end process;
+
+
+	forwardUARTOutputToARM:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			uartTXCleared <= '0';
+		elsif (cpu_clk = '1' and cpu_clk'event) then
+			if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
+				uartTXCleared <= cpu_din(0);
+			else
+				uartTXCleared <= uartTXCleared;
+			end if;
+		end if;
+	end process;	
+
+	cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
+	cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
+	
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+--	io_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable;
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			dram_read <= '0';
+			io_readEnable <= '0';
+
+		
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			mem_read <= (others => '0');
+			if mem_addr(ioBit)='0' and mem_readEnable='1' then
+				dram_read <= '1';
+			end if;
+			if dram_read='1' and dram_mem_busy='0' then
+				dram_read <= '0';
+				mem_read <= dram_mem_read;
+			end if;
+			 
+			if mem_addr(ioBit)='1' and mem_readEnable='1' then
+				io_readEnable <= '1';
+			end if;
+			if io_readEnable='1' and io_busy='0' then
+				io_readEnable <= '0';
+				mem_read(7 downto 0) <= io_read;
+			end if;
+			
+		end if;
+	end process;
+
+
+end behave;
diff --git a/zpu/hdl/zy2000/timer.vhd b/zpu/hdl/zy2000/timer.vhd
index bff82f2..735d55c 100644
--- a/zpu/hdl/zy2000/timer.vhd
+++ b/zpu/hdl/zy2000/timer.vhd
@@ -1,137 +1,137 @@
-library ieee;

-use ieee.std_logic_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

- 

-entity timer is

-  port(

-       	clk             : in std_logic;

-		areset			: in std_logic;

-		sample			: in std_logic;

-		reset			: in std_logic;

-		counter			: out std_logic_vector(63 downto 0));

-end timer;

-   

-   

-architecture behave of timer is

-

-signal	c			: std_logic_vector(1 to 7);

-

-signal	cnt		: std_logic_vector(63 downto 0);

-signal	cnt_smp	: std_logic_vector(63 downto 0);

-

-begin

-

-	counter <= cnt_smp;

-

-	process(clk, areset)	-- Carry generation

-	begin

-		if areset = '1' then

-			c <= "0000000";

-		elsif (clk'event and clk = '1') then

-			if reset = '1' then

-				c <= "0000000";

-			else

-				if cnt(7 downto 0) = "11111110" then

-					c(1) <= '1';

-				else

-					c(1) <= '0';

-				end if;

-				if cnt(15 downto 8) = "11111111" then

-					c(2) <= '1';

-				else

-					c(2) <= '0';

-				end if;

-				if cnt(23 downto 16) = "11111111" and c(2) = '1' then

-					c(3) <= '1';

-				else

-					c(3) <= '0';

-				end if;

-				if cnt(31 downto 24) = "11111111" and c(3) = '1' then

-					c(4) <= '1';

-				else

-					c(4) <= '0';

-				end if;

-				if cnt(39 downto 32) = "11111111" and c(4) = '1' then

-					c(5) <= '1';

-				else

-					c(5) <= '0';

-				end if;

-				if cnt(47 downto 40) = "11111111" and c(5) = '1' then

-					c(6) <= '1';

-				else

-					c(6) <= '0';

-				end if;

-				if cnt(55 downto 48) = "11111111" and c(6) = '1' then

-					c(7) <= '1';

-				else

-					c(7) <= '0';

-				end if;

-			end if;	

-		end if;

-	end process;

-	

-	process(clk, areset)

-	begin

-		if areset = '1' then

-			cnt <= (others=>'0');

-		elsif (clk'event and clk = '1') then

-			if reset = '1' then

-				cnt <= (others=>'0');

-			else

-				cnt(7 downto 0) <= cnt(7 downto 0) + '1';

-				if c(1) = '1' then

-					cnt(15 downto 8) <= cnt(15 downto 8) + '1';

-				else

-					cnt(15 downto 8) <= cnt(15 downto 8);

-				end if;

-				if c(2) = '1' and c(1) = '1' then

-					cnt(23 downto 16) <= cnt(23 downto 16) + '1';

-				else

-					cnt(23 downto 16) <= cnt(23 downto 16);

-				end if;

-				if c(3) = '1' and c(1) = '1' then

-					cnt(31 downto 24) <= cnt(31 downto 24) + '1';

-				else

-					cnt(31 downto 24) <= cnt(31 downto 24);

-				end if;

-				if c(4) = '1' and c(1) = '1' then

-					cnt(39 downto 32) <= cnt(39 downto 32) + '1';

-				else

-					cnt(39 downto 32) <= cnt(39 downto 32);

-				end if;

-				if c(5) = '1' and c(1) = '1' then

-					cnt(47 downto 40) <= cnt(47 downto 40) + '1';

-				else

-					cnt(47 downto 40) <= cnt(47 downto 40);

-				end if;

-				if c(6) = '1' and c(1) = '1' then

-					cnt(55 downto 48) <= cnt(55 downto 48) + '1';

-				else

-					cnt(55 downto 48) <= cnt(55 downto 48);

-				end if;

-				if c(7) = '1' and c(1) = '1' then

-					cnt(63 downto 56) <= cnt(63 downto 56) + '1';

-				else

-					cnt(63 downto 56) <= cnt(63 downto 56);

-				end if;

-			end if;

-		end if;

-	end process;

-	

-	process(clk, areset)

-	begin

-		if areset = '1' then

-			cnt_smp <= (others=>'0');

-		elsif (clk'event and clk = '1') then

-			if reset = '1' then

-				cnt_smp <= (others=>'0');

-			elsif sample = '1' then

-				cnt_smp <= cnt;

-			else

-				cnt_smp <= cnt_smp;

-			end if;

-		end if;

-	end process;

-	

-end behave;

- 

+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+ 
+entity timer is
+  port(
+       	clk             : in std_logic;
+		areset			: in std_logic;
+		sample			: in std_logic;
+		reset			: in std_logic;
+		counter			: out std_logic_vector(63 downto 0));
+end timer;
+   
+   
+architecture behave of timer is
+
+signal	c			: std_logic_vector(1 to 7);
+
+signal	cnt		: std_logic_vector(63 downto 0);
+signal	cnt_smp	: std_logic_vector(63 downto 0);
+
+begin
+
+	counter <= cnt_smp;
+
+	process(clk, areset)	-- Carry generation
+	begin
+		if areset = '1' then
+			c <= "0000000";
+		elsif (clk'event and clk = '1') then
+			if reset = '1' then
+				c <= "0000000";
+			else
+				if cnt(7 downto 0) = "11111110" then
+					c(1) <= '1';
+				else
+					c(1) <= '0';
+				end if;
+				if cnt(15 downto 8) = "11111111" then
+					c(2) <= '1';
+				else
+					c(2) <= '0';
+				end if;
+				if cnt(23 downto 16) = "11111111" and c(2) = '1' then
+					c(3) <= '1';
+				else
+					c(3) <= '0';
+				end if;
+				if cnt(31 downto 24) = "11111111" and c(3) = '1' then
+					c(4) <= '1';
+				else
+					c(4) <= '0';
+				end if;
+				if cnt(39 downto 32) = "11111111" and c(4) = '1' then
+					c(5) <= '1';
+				else
+					c(5) <= '0';
+				end if;
+				if cnt(47 downto 40) = "11111111" and c(5) = '1' then
+					c(6) <= '1';
+				else
+					c(6) <= '0';
+				end if;
+				if cnt(55 downto 48) = "11111111" and c(6) = '1' then
+					c(7) <= '1';
+				else
+					c(7) <= '0';
+				end if;
+			end if;	
+		end if;
+	end process;
+	
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			cnt <= (others=>'0');
+		elsif (clk'event and clk = '1') then
+			if reset = '1' then
+				cnt <= (others=>'0');
+			else
+				cnt(7 downto 0) <= cnt(7 downto 0) + '1';
+				if c(1) = '1' then
+					cnt(15 downto 8) <= cnt(15 downto 8) + '1';
+				else
+					cnt(15 downto 8) <= cnt(15 downto 8);
+				end if;
+				if c(2) = '1' and c(1) = '1' then
+					cnt(23 downto 16) <= cnt(23 downto 16) + '1';
+				else
+					cnt(23 downto 16) <= cnt(23 downto 16);
+				end if;
+				if c(3) = '1' and c(1) = '1' then
+					cnt(31 downto 24) <= cnt(31 downto 24) + '1';
+				else
+					cnt(31 downto 24) <= cnt(31 downto 24);
+				end if;
+				if c(4) = '1' and c(1) = '1' then
+					cnt(39 downto 32) <= cnt(39 downto 32) + '1';
+				else
+					cnt(39 downto 32) <= cnt(39 downto 32);
+				end if;
+				if c(5) = '1' and c(1) = '1' then
+					cnt(47 downto 40) <= cnt(47 downto 40) + '1';
+				else
+					cnt(47 downto 40) <= cnt(47 downto 40);
+				end if;
+				if c(6) = '1' and c(1) = '1' then
+					cnt(55 downto 48) <= cnt(55 downto 48) + '1';
+				else
+					cnt(55 downto 48) <= cnt(55 downto 48);
+				end if;
+				if c(7) = '1' and c(1) = '1' then
+					cnt(63 downto 56) <= cnt(63 downto 56) + '1';
+				else
+					cnt(63 downto 56) <= cnt(63 downto 56);
+				end if;
+			end if;
+		end if;
+	end process;
+	
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			cnt_smp <= (others=>'0');
+		elsif (clk'event and clk = '1') then
+			if reset = '1' then
+				cnt_smp <= (others=>'0');
+			elsif sample = '1' then
+				cnt_smp <= cnt;
+			else
+				cnt_smp <= cnt_smp;
+			end if;
+		end if;
+	end process;
+	
+end behave;
+ 
diff --git a/zpu/hdl/zy2000/trace.vhd b/zpu/hdl/zy2000/trace.vhd
index bc5279f..ec6be57 100644
--- a/zpu/hdl/zy2000/trace.vhd
+++ b/zpu/hdl/zy2000/trace.vhd
@@ -1,84 +1,84 @@
-library ieee;

-use ieee.std_logic_1164.all;

---use IEEE.STD_LOGIC_ARITH.ALL;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-use std.textio.all;

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-use work.txt_util.all;

- 

- 

-entity trace is

-  generic (

-           log_file:       string  := "trace.txt"

-          );

-  port(

-       	clk         : in std_logic;

-       	begin_inst  : in std_logic;

-       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);

-		opcode		: in std_logic_vector(7 downto 0);

-		sp			: in std_logic_vector(maxAddrBitIncIO downto 2);

-		memA		: in std_logic_vector(wordSize-1 downto 0);

-		memB		: in std_logic_vector(wordSize-1 downto 0);

-		busy  : in std_logic;

-		intSp		: in std_logic_vector(stack_bits-1 downto 0)

-		);

-end trace;

-   

-   

-architecture behave of trace is

-  

-  

-file 		l_file		: TEXT open write_mode is log_file;

-

-

-begin

-

-

--- write data and control information to a file

-

-receive_data: process

-

-variable l: line;

-variable t	: std_logic_vector(wordSize-1 downto 0);

-variable t2	: std_logic_vector(maxAddrBitIncIO downto 0);

-variable counter : std_logic_vector(63 downto 0);

-   

-   

-   

-begin                                       

-

-	t:= (others => '0');

-	t2:= (others => '0');

-

-counter := (others => '0');

-   -- print header for the logfile

-   print(l_file, "#pc,opcode,sp,top_of_stack ");

-   print(l_file, "#----------");

-   print(l_file, " ");

-

-	wait until clk = '1';

-	wait until clk = '0'; 

-

-   while true loop

-

-		counter := counter + 1;

-		if begin_inst = '1' then

-			t(maxAddrBitIncIO downto 2):=sp;

-			t2:=pc;

-     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter));

-		end if;

-		

-     	wait until clk = '0';

-    

-   end loop;

-

- end process receive_data;

-

-

-

-end behave;

- 

+library ieee;
+use ieee.std_logic_1164.all;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+ 
+ 
+entity trace is
+  generic (
+           log_file:       string  := "trace.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	begin_inst  : in std_logic;
+       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
+		opcode		: in std_logic_vector(7 downto 0);
+		sp			: in std_logic_vector(maxAddrBitIncIO downto 2);
+		memA		: in std_logic_vector(wordSize-1 downto 0);
+		memB		: in std_logic_vector(wordSize-1 downto 0);
+		busy  : in std_logic;
+		intSp		: in std_logic_vector(stack_bits-1 downto 0)
+		);
+end trace;
+   
+   
+architecture behave of trace is
+  
+  
+file 		l_file		: TEXT open write_mode is log_file;
+
+
+begin
+
+
+-- write data and control information to a file
+
+receive_data: process
+
+variable l: line;
+variable t	: std_logic_vector(wordSize-1 downto 0);
+variable t2	: std_logic_vector(maxAddrBitIncIO downto 0);
+variable counter : std_logic_vector(63 downto 0);
+   
+   
+   
+begin                                       
+
+	t:= (others => '0');
+	t2:= (others => '0');
+
+counter := (others => '0');
+   -- print header for the logfile
+   print(l_file, "#pc,opcode,sp,top_of_stack ");
+   print(l_file, "#----------");
+   print(l_file, " ");
+
+	wait until clk = '1';
+	wait until clk = '0'; 
+
+   while true loop
+
+		counter := counter + 1;
+		if begin_inst = '1' then
+			t(maxAddrBitIncIO downto 2):=sp;
+			t2:=pc;
+     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter));
+		end if;
+		
+     	wait until clk = '0';
+    
+   end loop;
+
+ end process receive_data;
+
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zy2000/txt_util.vhd b/zpu/hdl/zy2000/txt_util.vhd
index d3bf01a..40d39b9 100644
--- a/zpu/hdl/zy2000/txt_util.vhd
+++ b/zpu/hdl/zy2000/txt_util.vhd
@@ -1,587 +1,587 @@
-library ieee;

-use ieee.std_logic_1164.all;

-use std.textio.all;

-

-library work;

-

-package txt_util is

-

-    -- prints a message to the screen

-    procedure print(text: string);

-

-    -- prints the message when active

-    -- useful for debug switches

-    procedure print(active: boolean; text: string);

-

-    -- converts std_logic into a character

-    function chr(sl: std_logic) return character;

-

-    -- converts std_logic into a string (1 to 1)

-    function str(sl: std_logic) return string;

-

-    -- converts std_logic_vector into a string (binary base)

-    function str(slv: std_logic_vector) return string;

-

-    -- converts boolean into a string

-    function str(b: boolean) return string;

-

-    -- converts an integer into a single character

-    -- (can also be used for hex conversion and other bases)

-    function chr(int: integer) return character;

-

-    -- converts integer into string using specified base

-    function str(int: integer; base: integer) return string;

-

-    -- converts integer to string, using base 10

-    function str(int: integer) return string;

-

-    -- convert std_logic_vector into a string in hex format

-    function hstr(slv: std_logic_vector) return string;

-

-

-    -- functions to manipulate strings

-    -----------------------------------

-

-    -- convert a character to upper case

-    function to_upper(c: character) return character;

-

-    -- convert a character to lower case

-    function to_lower(c: character) return character;

-

-    -- convert a string to upper case

-    function to_upper(s: string) return string;

-

-    -- convert a string to lower case

-    function to_lower(s: string) return string;

-

-   

-    

-    -- functions to convert strings into other formats

-    --------------------------------------------------

-    

-    -- converts a character into std_logic

-    function to_std_logic(c: character) return std_logic; 

-    

-    -- converts a string into std_logic_vector

-    function to_std_logic_vector(s: string) return std_logic_vector; 

-

-

-  

-    -- file I/O

-    -----------

-       

-    -- read variable length string from input file

-    procedure str_read(file in_file: TEXT; 

-                       res_string: out string);

-        

-    -- print string to a file and start new line

-    procedure print(file out_file: TEXT;

-                    new_string: in  string);

-    

-    -- print character to a file and start new line

-    procedure print(file out_file: TEXT;

-                    char:       in  character);

-                    

-end txt_util;

-

-

-

-

-package body txt_util is

-

-

-

-

-   -- prints text to the screen

-

-   procedure print(text: string) is

-     variable msg_line: line;

-     begin

-       write(msg_line, text);

-       writeline(output, msg_line);

-   end print;

-

-

-

-

-   -- prints text to the screen when active

-

-   procedure print(active: boolean; text: string)  is

-     begin

-      if active then

-         print(text);

-      end if;

-   end print;

-

-

-   -- converts std_logic into a character

-

-   function chr(sl: std_logic) return character is

-    variable c: character;

-    begin

-      case sl is

-         when 'U' => c:= 'U';

-         when 'X' => c:= 'X';

-         when '0' => c:= '0';

-         when '1' => c:= '1';

-         when 'Z' => c:= 'Z';

-         when 'W' => c:= 'W';

-         when 'L' => c:= 'L';

-         when 'H' => c:= 'H';

-         when '-' => c:= '-';

-      end case;

-    return c;

-   end chr;

-

-

-

-   -- converts std_logic into a string (1 to 1)

-

-   function str(sl: std_logic) return string is

-    variable s: string(1 to 1);

-    begin

-        s(1) := chr(sl);

-        return s;

-   end str;

-

-

-

-   -- converts std_logic_vector into a string (binary base)

-   -- (this also takes care of the fact that the range of

-   --  a string is natural while a std_logic_vector may

-   --  have an integer range)

-

-   function str(slv: std_logic_vector) return string is

-     variable result : string (1 to slv'length);

-     variable r : integer;

-   begin

-     r := 1;

-     for i in slv'range loop

-        result(r) := chr(slv(i));

-        r := r + 1;

-     end loop;

-     return result;

-   end str;

-

-

-   function str(b: boolean) return string is

-

-    begin

-       if b then

-          return "true";

-      else

-        return "false";

-       end if;

-    end str;

-

-

-   -- converts an integer into a character

-   -- for 0 to 9 the obvious mapping is used, higher

-   -- values are mapped to the characters A-Z

-   -- (this is usefull for systems with base > 10)

-   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)

-

-   function chr(int: integer) return character is

-    variable c: character;

-   begin

-        case int is

-          when  0 => c := '0';

-          when  1 => c := '1';

-          when  2 => c := '2';

-          when  3 => c := '3';

-          when  4 => c := '4';

-          when  5 => c := '5';

-          when  6 => c := '6';

-          when  7 => c := '7';

-          when  8 => c := '8';

-          when  9 => c := '9';

-          when 10 => c := 'A';

-          when 11 => c := 'B';

-          when 12 => c := 'C';

-          when 13 => c := 'D';

-          when 14 => c := 'E';

-          when 15 => c := 'F';

-          when 16 => c := 'G';

-          when 17 => c := 'H';

-          when 18 => c := 'I';

-          when 19 => c := 'J';

-          when 20 => c := 'K';

-          when 21 => c := 'L';

-          when 22 => c := 'M';

-          when 23 => c := 'N';

-          when 24 => c := 'O';

-          when 25 => c := 'P';

-          when 26 => c := 'Q';

-          when 27 => c := 'R';

-          when 28 => c := 'S';

-          when 29 => c := 'T';

-          when 30 => c := 'U';

-          when 31 => c := 'V';

-          when 32 => c := 'W';

-          when 33 => c := 'X';

-          when 34 => c := 'Y';

-          when 35 => c := 'Z';

-          when others => c := '?';

-        end case;

-        return c;

-    end chr;

-

-

-

-   -- convert integer to string using specified base

-   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)

-

-   function str(int: integer; base: integer) return string is

-

-    variable temp:      string(1 to 10);

-    variable num:       integer;

-    variable abs_int:   integer;

-    variable len:       integer := 1;

-    variable power:     integer := 1;

-

-   begin

-

-    -- bug fix for negative numbers

-    abs_int := abs(int);

-

-    num     := abs_int;

-

-    while num >= base loop                     -- Determine how many

-      len := len + 1;                          -- characters required

-      num := num / base;                       -- to represent the

-    end loop ;                                 -- number.

-

-    for i in len downto 1 loop                 -- Convert the number to

-      temp(i) := chr(abs_int/power mod base);  -- a string starting

-      power := power * base;                   -- with the right hand

-    end loop ;                                 -- side.

-

-    -- return result and add sign if required

-    if int < 0 then

-       return '-'& temp(1 to len);

-     else

-       return temp(1 to len);

-    end if;

-

-   end str;

-

-

-  -- convert integer to string, using base 10

-  function str(int: integer) return string is

-

-   begin

-

-    return str(int, 10) ;

-

-   end str;

-

-

-

-   -- converts a std_logic_vector into a hex string.

-   function hstr(slv: std_logic_vector) return string is

-       variable hexlen: integer;

-       variable longslv : std_logic_vector(67 downto 0) := (others => '0');

-       variable hex : string(1 to 16);

-       variable fourbit : std_logic_vector(3 downto 0);

-     begin

-       hexlen := (slv'left+1)/4;

-       if (slv'left+1) mod 4 /= 0 then

-         hexlen := hexlen + 1;

-       end if;

-       longslv(slv'left downto 0) := slv;

-       for i in (hexlen -1) downto 0 loop

-         fourbit := longslv(((i*4)+3) downto (i*4));

-         case fourbit is

-           when "0000" => hex(hexlen -I) := '0';

-           when "0001" => hex(hexlen -I) := '1';

-           when "0010" => hex(hexlen -I) := '2';

-           when "0011" => hex(hexlen -I) := '3';

-           when "0100" => hex(hexlen -I) := '4';

-           when "0101" => hex(hexlen -I) := '5';

-           when "0110" => hex(hexlen -I) := '6';

-           when "0111" => hex(hexlen -I) := '7';

-           when "1000" => hex(hexlen -I) := '8';

-           when "1001" => hex(hexlen -I) := '9';

-           when "1010" => hex(hexlen -I) := 'A';

-           when "1011" => hex(hexlen -I) := 'B';

-           when "1100" => hex(hexlen -I) := 'C';

-           when "1101" => hex(hexlen -I) := 'D';

-           when "1110" => hex(hexlen -I) := 'E';

-           when "1111" => hex(hexlen -I) := 'F';

-           when "ZZZZ" => hex(hexlen -I) := 'z';

-           when "UUUU" => hex(hexlen -I) := 'u';

-           when "XXXX" => hex(hexlen -I) := 'x';

-           when others => hex(hexlen -I) := '?';

-         end case;

-       end loop;

-       return hex(1 to hexlen);

-     end hstr;

-

-

-

-   -- functions to manipulate strings

-   -----------------------------------

-

-

-   -- convert a character to upper case

-

-   function to_upper(c: character) return character is

-

-      variable u: character;

-

-    begin

-

-       case c is

-        when 'a' => u := 'A';

-        when 'b' => u := 'B';

-        when 'c' => u := 'C';

-        when 'd' => u := 'D';

-        when 'e' => u := 'E';

-        when 'f' => u := 'F';

-        when 'g' => u := 'G';

-        when 'h' => u := 'H';

-        when 'i' => u := 'I';

-        when 'j' => u := 'J';

-        when 'k' => u := 'K';

-        when 'l' => u := 'L';

-        when 'm' => u := 'M';

-        when 'n' => u := 'N';

-        when 'o' => u := 'O';

-        when 'p' => u := 'P';

-        when 'q' => u := 'Q';

-        when 'r' => u := 'R';

-        when 's' => u := 'S';

-        when 't' => u := 'T';

-        when 'u' => u := 'U';

-        when 'v' => u := 'V';

-        when 'w' => u := 'W';

-        when 'x' => u := 'X';

-        when 'y' => u := 'Y';

-        when 'z' => u := 'Z';

-        when others => u := c;

-    end case;

-

-      return u;

-

-   end to_upper;

-

-

-   -- convert a character to lower case

-

-   function to_lower(c: character) return character is

-

-      variable l: character;

-

-    begin

-

-       case c is

-        when 'A' => l := 'a';

-        when 'B' => l := 'b';

-        when 'C' => l := 'c';

-        when 'D' => l := 'd';

-        when 'E' => l := 'e';

-        when 'F' => l := 'f';

-        when 'G' => l := 'g';

-        when 'H' => l := 'h';

-        when 'I' => l := 'i';

-        when 'J' => l := 'j';

-        when 'K' => l := 'k';

-        when 'L' => l := 'l';

-        when 'M' => l := 'm';

-        when 'N' => l := 'n';

-        when 'O' => l := 'o';

-        when 'P' => l := 'p';

-        when 'Q' => l := 'q';

-        when 'R' => l := 'r';

-        when 'S' => l := 's';

-        when 'T' => l := 't';

-        when 'U' => l := 'u';

-        when 'V' => l := 'v';

-        when 'W' => l := 'w';

-        when 'X' => l := 'x';

-        when 'Y' => l := 'y';

-        when 'Z' => l := 'z';

-        when others => l := c;

-    end case;

-

-      return l;

-

-   end to_lower;

-

-

-

-   -- convert a string to upper case

-

-   function to_upper(s: string) return string is

-

-     variable uppercase: string (s'range);

-

-   begin

-

-     for i in s'range loop

-        uppercase(i):= to_upper(s(i));

-     end loop;

-     return uppercase;

-

-   end to_upper;

-

-

-

-   -- convert a string to lower case

-

-   function to_lower(s: string) return string is

-

-     variable lowercase: string (s'range);

-

-   begin

-

-     for i in s'range loop

-        lowercase(i):= to_lower(s(i));

-     end loop;

-     return lowercase;

-

-   end to_lower;

-

-

-

--- functions to convert strings into other types

-

-

--- converts a character into a std_logic

-

-function to_std_logic(c: character) return std_logic is 

-    variable sl: std_logic;

-    begin

-      case c is

-        when 'U' => 

-           sl := 'U'; 

-        when 'X' =>

-           sl := 'X';

-        when '0' => 

-           sl := '0';

-        when '1' => 

-           sl := '1';

-        when 'Z' => 

-           sl := 'Z';

-        when 'W' => 

-           sl := 'W';

-        when 'L' => 

-           sl := 'L';

-        when 'H' => 

-           sl := 'H';

-        when '-' => 

-           sl := '-';

-        when others =>

-           sl := 'X'; 

-    end case;

-   return sl;

-  end to_std_logic;

-

-

--- converts a string into std_logic_vector

-

-function to_std_logic_vector(s: string) return std_logic_vector is 

-  variable slv: std_logic_vector(s'high-s'low downto 0);

-  variable k: integer;

-begin

-   k := s'high-s'low;

-  for i in s'range loop

-     slv(k) := to_std_logic(s(i));

-     k      := k - 1;

-  end loop;

-  return slv;

-end to_std_logic_vector;                                       

-                                       

-                                       

-                                       

-                                       

-                                       

-                                       

-----------------

---  file I/O  --

-----------------

-

-

-

--- read variable length string from input file

-     

-procedure str_read(file in_file: TEXT; 

-                   res_string: out string) is

-       

-       variable l:         line;

-       variable c:         character;

-       variable is_string: boolean;

-       

-   begin

-           

-     readline(in_file, l);

-     -- clear the contents of the result string

-     for i in res_string'range loop

-         res_string(i) := ' ';

-     end loop;   

-     -- read all characters of the line, up to the length  

-     -- of the results string

-     for i in res_string'range loop

-        read(l, c, is_string);

-        res_string(i) := c;

-        if not is_string then -- found end of line

-           exit;

-        end if;   

-     end loop; 

-                     

-end str_read;

-

-

--- print string to a file

-procedure print(file out_file: TEXT;

-                new_string: in  string) is

-       

-       variable l: line;

-       

-   begin

-      

-     write(l, new_string);

-     writeline(out_file, l);

-                     

-end print;

-

-

--- print character to a file and start new line

-procedure print(file out_file: TEXT;

-                char: in  character) is

-       

-       variable l: line;

-       

-   begin

-      

-     write(l, char);

-     writeline(out_file, l);

-                     

-end print;

-

-

-

--- appends contents of a string to a file until line feed occurs

--- (LF is considered to be the end of the string)

-

-procedure str_write(file out_file: TEXT; 

-                    new_string: in  string) is

- begin

-      

-   for i in new_string'range loop

-      print(out_file, new_string(i));

-      if new_string(i) = LF then -- end of string

-         exit;

-      end if;

-   end loop;               

-                     

-end str_write;

-

-

-

-

-end txt_util;

-

-

-

-

+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+
+library work;
+
+package txt_util is
+
+    -- prints a message to the screen
+    procedure print(text: string);
+
+    -- prints the message when active
+    -- useful for debug switches
+    procedure print(active: boolean; text: string);
+
+    -- converts std_logic into a character
+    function chr(sl: std_logic) return character;
+
+    -- converts std_logic into a string (1 to 1)
+    function str(sl: std_logic) return string;
+
+    -- converts std_logic_vector into a string (binary base)
+    function str(slv: std_logic_vector) return string;
+
+    -- converts boolean into a string
+    function str(b: boolean) return string;
+
+    -- converts an integer into a single character
+    -- (can also be used for hex conversion and other bases)
+    function chr(int: integer) return character;
+
+    -- converts integer into string using specified base
+    function str(int: integer; base: integer) return string;
+
+    -- converts integer to string, using base 10
+    function str(int: integer) return string;
+
+    -- convert std_logic_vector into a string in hex format
+    function hstr(slv: std_logic_vector) return string;
+
+
+    -- functions to manipulate strings
+    -----------------------------------
+
+    -- convert a character to upper case
+    function to_upper(c: character) return character;
+
+    -- convert a character to lower case
+    function to_lower(c: character) return character;
+
+    -- convert a string to upper case
+    function to_upper(s: string) return string;
+
+    -- convert a string to lower case
+    function to_lower(s: string) return string;
+
+   
+    
+    -- functions to convert strings into other formats
+    --------------------------------------------------
+    
+    -- converts a character into std_logic
+    function to_std_logic(c: character) return std_logic; 
+    
+    -- converts a string into std_logic_vector
+    function to_std_logic_vector(s: string) return std_logic_vector; 
+
+
+  
+    -- file I/O
+    -----------
+       
+    -- read variable length string from input file
+    procedure str_read(file in_file: TEXT; 
+                       res_string: out string);
+        
+    -- print string to a file and start new line
+    procedure print(file out_file: TEXT;
+                    new_string: in  string);
+    
+    -- print character to a file and start new line
+    procedure print(file out_file: TEXT;
+                    char:       in  character);
+                    
+end txt_util;
+
+
+
+
+package body txt_util is
+
+
+
+
+   -- prints text to the screen
+
+   procedure print(text: string) is
+     variable msg_line: line;
+     begin
+       write(msg_line, text);
+       writeline(output, msg_line);
+   end print;
+
+
+
+
+   -- prints text to the screen when active
+
+   procedure print(active: boolean; text: string)  is
+     begin
+      if active then
+         print(text);
+      end if;
+   end print;
+
+
+   -- converts std_logic into a character
+
+   function chr(sl: std_logic) return character is
+    variable c: character;
+    begin
+      case sl is
+         when 'U' => c:= 'U';
+         when 'X' => c:= 'X';
+         when '0' => c:= '0';
+         when '1' => c:= '1';
+         when 'Z' => c:= 'Z';
+         when 'W' => c:= 'W';
+         when 'L' => c:= 'L';
+         when 'H' => c:= 'H';
+         when '-' => c:= '-';
+      end case;
+    return c;
+   end chr;
+
+
+
+   -- converts std_logic into a string (1 to 1)
+
+   function str(sl: std_logic) return string is
+    variable s: string(1 to 1);
+    begin
+        s(1) := chr(sl);
+        return s;
+   end str;
+
+
+
+   -- converts std_logic_vector into a string (binary base)
+   -- (this also takes care of the fact that the range of
+   --  a string is natural while a std_logic_vector may
+   --  have an integer range)
+
+   function str(slv: std_logic_vector) return string is
+     variable result : string (1 to slv'length);
+     variable r : integer;
+   begin
+     r := 1;
+     for i in slv'range loop
+        result(r) := chr(slv(i));
+        r := r + 1;
+     end loop;
+     return result;
+   end str;
+
+
+   function str(b: boolean) return string is
+
+    begin
+       if b then
+          return "true";
+      else
+        return "false";
+       end if;
+    end str;
+
+
+   -- converts an integer into a character
+   -- for 0 to 9 the obvious mapping is used, higher
+   -- values are mapped to the characters A-Z
+   -- (this is usefull for systems with base > 10)
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function chr(int: integer) return character is
+    variable c: character;
+   begin
+        case int is
+          when  0 => c := '0';
+          when  1 => c := '1';
+          when  2 => c := '2';
+          when  3 => c := '3';
+          when  4 => c := '4';
+          when  5 => c := '5';
+          when  6 => c := '6';
+          when  7 => c := '7';
+          when  8 => c := '8';
+          when  9 => c := '9';
+          when 10 => c := 'A';
+          when 11 => c := 'B';
+          when 12 => c := 'C';
+          when 13 => c := 'D';
+          when 14 => c := 'E';
+          when 15 => c := 'F';
+          when 16 => c := 'G';
+          when 17 => c := 'H';
+          when 18 => c := 'I';
+          when 19 => c := 'J';
+          when 20 => c := 'K';
+          when 21 => c := 'L';
+          when 22 => c := 'M';
+          when 23 => c := 'N';
+          when 24 => c := 'O';
+          when 25 => c := 'P';
+          when 26 => c := 'Q';
+          when 27 => c := 'R';
+          when 28 => c := 'S';
+          when 29 => c := 'T';
+          when 30 => c := 'U';
+          when 31 => c := 'V';
+          when 32 => c := 'W';
+          when 33 => c := 'X';
+          when 34 => c := 'Y';
+          when 35 => c := 'Z';
+          when others => c := '?';
+        end case;
+        return c;
+    end chr;
+
+
+
+   -- convert integer to string using specified base
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function str(int: integer; base: integer) return string is
+
+    variable temp:      string(1 to 10);
+    variable num:       integer;
+    variable abs_int:   integer;
+    variable len:       integer := 1;
+    variable power:     integer := 1;
+
+   begin
+
+    -- bug fix for negative numbers
+    abs_int := abs(int);
+
+    num     := abs_int;
+
+    while num >= base loop                     -- Determine how many
+      len := len + 1;                          -- characters required
+      num := num / base;                       -- to represent the
+    end loop ;                                 -- number.
+
+    for i in len downto 1 loop                 -- Convert the number to
+      temp(i) := chr(abs_int/power mod base);  -- a string starting
+      power := power * base;                   -- with the right hand
+    end loop ;                                 -- side.
+
+    -- return result and add sign if required
+    if int < 0 then
+       return '-'& temp(1 to len);
+     else
+       return temp(1 to len);
+    end if;
+
+   end str;
+
+
+  -- convert integer to string, using base 10
+  function str(int: integer) return string is
+
+   begin
+
+    return str(int, 10) ;
+
+   end str;
+
+
+
+   -- converts a std_logic_vector into a hex string.
+   function hstr(slv: std_logic_vector) return string is
+       variable hexlen: integer;
+       variable longslv : std_logic_vector(67 downto 0) := (others => '0');
+       variable hex : string(1 to 16);
+       variable fourbit : std_logic_vector(3 downto 0);
+     begin
+       hexlen := (slv'left+1)/4;
+       if (slv'left+1) mod 4 /= 0 then
+         hexlen := hexlen + 1;
+       end if;
+       longslv(slv'left downto 0) := slv;
+       for i in (hexlen -1) downto 0 loop
+         fourbit := longslv(((i*4)+3) downto (i*4));
+         case fourbit is
+           when "0000" => hex(hexlen -I) := '0';
+           when "0001" => hex(hexlen -I) := '1';
+           when "0010" => hex(hexlen -I) := '2';
+           when "0011" => hex(hexlen -I) := '3';
+           when "0100" => hex(hexlen -I) := '4';
+           when "0101" => hex(hexlen -I) := '5';
+           when "0110" => hex(hexlen -I) := '6';
+           when "0111" => hex(hexlen -I) := '7';
+           when "1000" => hex(hexlen -I) := '8';
+           when "1001" => hex(hexlen -I) := '9';
+           when "1010" => hex(hexlen -I) := 'A';
+           when "1011" => hex(hexlen -I) := 'B';
+           when "1100" => hex(hexlen -I) := 'C';
+           when "1101" => hex(hexlen -I) := 'D';
+           when "1110" => hex(hexlen -I) := 'E';
+           when "1111" => hex(hexlen -I) := 'F';
+           when "ZZZZ" => hex(hexlen -I) := 'z';
+           when "UUUU" => hex(hexlen -I) := 'u';
+           when "XXXX" => hex(hexlen -I) := 'x';
+           when others => hex(hexlen -I) := '?';
+         end case;
+       end loop;
+       return hex(1 to hexlen);
+     end hstr;
+
+
+
+   -- functions to manipulate strings
+   -----------------------------------
+
+
+   -- convert a character to upper case
+
+   function to_upper(c: character) return character is
+
+      variable u: character;
+
+    begin
+
+       case c is
+        when 'a' => u := 'A';
+        when 'b' => u := 'B';
+        when 'c' => u := 'C';
+        when 'd' => u := 'D';
+        when 'e' => u := 'E';
+        when 'f' => u := 'F';
+        when 'g' => u := 'G';
+        when 'h' => u := 'H';
+        when 'i' => u := 'I';
+        when 'j' => u := 'J';
+        when 'k' => u := 'K';
+        when 'l' => u := 'L';
+        when 'm' => u := 'M';
+        when 'n' => u := 'N';
+        when 'o' => u := 'O';
+        when 'p' => u := 'P';
+        when 'q' => u := 'Q';
+        when 'r' => u := 'R';
+        when 's' => u := 'S';
+        when 't' => u := 'T';
+        when 'u' => u := 'U';
+        when 'v' => u := 'V';
+        when 'w' => u := 'W';
+        when 'x' => u := 'X';
+        when 'y' => u := 'Y';
+        when 'z' => u := 'Z';
+        when others => u := c;
+    end case;
+
+      return u;
+
+   end to_upper;
+
+
+   -- convert a character to lower case
+
+   function to_lower(c: character) return character is
+
+      variable l: character;
+
+    begin
+
+       case c is
+        when 'A' => l := 'a';
+        when 'B' => l := 'b';
+        when 'C' => l := 'c';
+        when 'D' => l := 'd';
+        when 'E' => l := 'e';
+        when 'F' => l := 'f';
+        when 'G' => l := 'g';
+        when 'H' => l := 'h';
+        when 'I' => l := 'i';
+        when 'J' => l := 'j';
+        when 'K' => l := 'k';
+        when 'L' => l := 'l';
+        when 'M' => l := 'm';
+        when 'N' => l := 'n';
+        when 'O' => l := 'o';
+        when 'P' => l := 'p';
+        when 'Q' => l := 'q';
+        when 'R' => l := 'r';
+        when 'S' => l := 's';
+        when 'T' => l := 't';
+        when 'U' => l := 'u';
+        when 'V' => l := 'v';
+        when 'W' => l := 'w';
+        when 'X' => l := 'x';
+        when 'Y' => l := 'y';
+        when 'Z' => l := 'z';
+        when others => l := c;
+    end case;
+
+      return l;
+
+   end to_lower;
+
+
+
+   -- convert a string to upper case
+
+   function to_upper(s: string) return string is
+
+     variable uppercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        uppercase(i):= to_upper(s(i));
+     end loop;
+     return uppercase;
+
+   end to_upper;
+
+
+
+   -- convert a string to lower case
+
+   function to_lower(s: string) return string is
+
+     variable lowercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        lowercase(i):= to_lower(s(i));
+     end loop;
+     return lowercase;
+
+   end to_lower;
+
+
+
+-- functions to convert strings into other types
+
+
+-- converts a character into a std_logic
+
+function to_std_logic(c: character) return std_logic is 
+    variable sl: std_logic;
+    begin
+      case c is
+        when 'U' => 
+           sl := 'U'; 
+        when 'X' =>
+           sl := 'X';
+        when '0' => 
+           sl := '0';
+        when '1' => 
+           sl := '1';
+        when 'Z' => 
+           sl := 'Z';
+        when 'W' => 
+           sl := 'W';
+        when 'L' => 
+           sl := 'L';
+        when 'H' => 
+           sl := 'H';
+        when '-' => 
+           sl := '-';
+        when others =>
+           sl := 'X'; 
+    end case;
+   return sl;
+  end to_std_logic;
+
+
+-- converts a string into std_logic_vector
+
+function to_std_logic_vector(s: string) return std_logic_vector is 
+  variable slv: std_logic_vector(s'high-s'low downto 0);
+  variable k: integer;
+begin
+   k := s'high-s'low;
+  for i in s'range loop
+     slv(k) := to_std_logic(s(i));
+     k      := k - 1;
+  end loop;
+  return slv;
+end to_std_logic_vector;                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+----------------
+--  file I/O  --
+----------------
+
+
+
+-- read variable length string from input file
+     
+procedure str_read(file in_file: TEXT; 
+                   res_string: out string) is
+       
+       variable l:         line;
+       variable c:         character;
+       variable is_string: boolean;
+       
+   begin
+           
+     readline(in_file, l);
+     -- clear the contents of the result string
+     for i in res_string'range loop
+         res_string(i) := ' ';
+     end loop;   
+     -- read all characters of the line, up to the length  
+     -- of the results string
+     for i in res_string'range loop
+        read(l, c, is_string);
+        res_string(i) := c;
+        if not is_string then -- found end of line
+           exit;
+        end if;   
+     end loop; 
+                     
+end str_read;
+
+
+-- print string to a file
+procedure print(file out_file: TEXT;
+                new_string: in  string) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, new_string);
+     writeline(out_file, l);
+                     
+end print;
+
+
+-- print character to a file and start new line
+procedure print(file out_file: TEXT;
+                char: in  character) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, char);
+     writeline(out_file, l);
+                     
+end print;
+
+
+
+-- appends contents of a string to a file until line feed occurs
+-- (LF is considered to be the end of the string)
+
+procedure str_write(file out_file: TEXT; 
+                    new_string: in  string) is
+ begin
+      
+   for i in new_string'range loop
+      print(out_file, new_string(i));
+      if new_string(i) = LF then -- end of string
+         exit;
+      end if;
+   end loop;               
+                     
+end str_write;
+
+
+
+
+end txt_util;
+
+
+
+
diff --git a/zpu/hdl/zy2000/zpu_config.vhd b/zpu/hdl/zy2000/zpu_config.vhd
index 61949c5..c0df294 100644
--- a/zpu/hdl/zy2000/zpu_config.vhd
+++ b/zpu/hdl/zy2000/zpu_config.vhd
@@ -1,20 +1,20 @@
-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.std_logic_unsigned.all;

-

-package zpu_config is

-	-- generate trace output or not.

-	constant	Generate_Trace		: boolean := false;

-	constant 	wordPower			: integer := 5;

-	-- during simulation, set this to '0' to get matching trace.txt 

-	constant	DontCareValue		: std_logic := '0';

-	-- Clock frequency in MHz.

-	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";

-	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)

-	constant 	maxAddrBitIncIO		: integer := 27;

-	

-	-- start byte address of stack. 

-	-- point to top of RAM - 2*words

-	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; 

-	

-end zpu_config;

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+	-- generate trace output or not.
+	constant	Generate_Trace		: boolean := false;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 27;
+	
+	-- start byte address of stack. 
+	-- point to top of RAM - 2*words
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; 
+	
+end zpu_config;
diff --git a/zpu/hdl/zy2000/zpu_config_fast.vhd b/zpu/hdl/zy2000/zpu_config_fast.vhd
index 61949c5..c0df294 100644
--- a/zpu/hdl/zy2000/zpu_config_fast.vhd
+++ b/zpu/hdl/zy2000/zpu_config_fast.vhd
@@ -1,20 +1,20 @@
-library ieee;

-use ieee.std_logic_1164.all;

-use ieee.std_logic_unsigned.all;

-

-package zpu_config is

-	-- generate trace output or not.

-	constant	Generate_Trace		: boolean := false;

-	constant 	wordPower			: integer := 5;

-	-- during simulation, set this to '0' to get matching trace.txt 

-	constant	DontCareValue		: std_logic := '0';

-	-- Clock frequency in MHz.

-	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";

-	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)

-	constant 	maxAddrBitIncIO		: integer := 27;

-	

-	-- start byte address of stack. 

-	-- point to top of RAM - 2*words

-	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; 

-	

-end zpu_config;

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+	-- generate trace output or not.
+	constant	Generate_Trace		: boolean := false;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 27;
+	
+	-- start byte address of stack. 
+	-- point to top of RAM - 2*words
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; 
+	
+end zpu_config;
diff --git a/zpu/hdl/zy2000/zpupkg.vhd b/zpu/hdl/zy2000/zpupkg.vhd
index 1a01563..a7e6cf1 100644
--- a/zpu/hdl/zy2000/zpupkg.vhd
+++ b/zpu/hdl/zy2000/zpupkg.vhd
@@ -1,168 +1,168 @@
-library IEEE;

-use IEEE.STD_LOGIC_1164.all;

-use IEEE.STD_LOGIC_ARITH.all;

-

-library work;

-use work.zpu_config.all;

-

-package zpupkg is

-

-	-- This bit is set for read/writes to IO

-	-- FIX!!! eventually this should be set to wordSize-1 so as to

-	-- to make the address of IO independent of amount of memory

-	-- reserved for CPU. Requires trivial tweaks in toolchain/runtime

-	-- libraries.

-	

-	constant byteBits			: integer := wordPower-3; -- # of bits in a word that addresses bytes

-	constant maxAddrBit			: integer := maxAddrBitIncIO-1;

-	constant ioBit				: integer := maxAddrBit+1;

-	constant wordSize			: integer := 2**wordPower;

-	constant wordBytes			: integer := wordSize/8;

-	constant minAddrBit			: integer := byteBits;

-	-- configurable internal stack size. Probably going to be 16 after toolchain is done

-	constant	stack_bits		: integer := 5; 

-	constant	stack_size		: integer := 2**stack_bits; 

-

-	component dualport_ram is

-	port (clk : in std_logic;

-		memAWriteEnable : in std_logic;

-		memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);

-		memAWrite : in std_logic_vector(wordSize-1 downto 0);

-		memARead : out std_logic_vector(wordSize-1 downto 0);

-		memBWriteEnable : in std_logic;

-		memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);

-		memBWrite : in std_logic_vector(wordSize-1 downto 0);

-		memBRead : out std_logic_vector(wordSize-1 downto 0));

-	end component;

-

-	component dram is

-		port (clk : in std_logic;

-			areset : in std_logic;

-			mem_writeEnable : in std_logic;

-			mem_readEnable : in std_logic;

-			mem_addr : in std_logic_vector(maxAddrBit downto 0);

-			mem_write : in std_logic_vector(wordSize-1 downto 0);

-			mem_read : out std_logic_vector(wordSize-1 downto 0);

-			mem_busy : out std_logic;

-			mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));

-	end component;

-

-

-	component trace is

-	  port(

-	       	clk         : in std_logic;

-	       	begin_inst  : in std_logic;

-	       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);

-			opcode		: in std_logic_vector(7 downto 0);

-			sp			: in std_logic_vector(maxAddrBitIncIO downto minAddrBit);

-			memA		: in std_logic_vector(wordSize-1 downto 0);

-			memB		: in std_logic_vector(wordSize-1 downto 0);

-			busy         : in std_logic;

-			intSp		: in std_logic_vector(stack_bits-1 downto 0)

-			);

-	end component;

-

-	component zpu_core is

-    port ( clk : in std_logic;

-	 		  areset : in std_logic;

-	 		  enable : in std_logic; 

-	 		  mem_req : out std_logic;

-	 		  mem_we : out std_logic;

-	 		  mem_ack : in std_logic; 

-	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);

-	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);

-			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);

-	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);

-	 		  interrupt : in std_logic;

-	 		  break : out std_logic;

-	 		  zpu_status : out std_logic_vector(63 downto 0));

-	end component;

-

-

-	

-	component timer is

-  	port(

-       	clk             : in std_logic;

-		areset			: in std_logic;

-		sample			: in std_logic;

-		reset			: in std_logic;

-		counter			: out std_logic_vector(63 downto 0));

-	end component;

-

-	component  zpuio is

-		port (	areset			: in std_logic;

-				cpu_clk			: in std_logic;

-				clk_status		: in std_logic_vector(2 downto 0);

-				cpu_din			: in std_logic_vector(15 downto 0);

-				cpu_a			: in std_logic_vector(20 downto 0);

-				cpu_we			: in std_logic_vector(1 downto 0);

-				cpu_re			: in std_logic;

-				cpu_dout		: inout std_logic_vector(15 downto 0));

-	end component;

-

-

-

-	

-	-- opcode decode constants

-	constant	OpCode_Im		: std_logic_vector(7 downto 7) := "1";

-	constant	OpCode_StoreSP	: std_logic_vector(7 downto 5) := "010";

-	constant	OpCode_LoadSP	: std_logic_vector(7 downto 5) := "011";

-	constant	OpCode_Emulate	: std_logic_vector(7 downto 5) := "001";

-	constant	OpCode_AddSP	: std_logic_vector(7 downto 4) := "0001";

-	constant	OpCode_Short	: std_logic_vector(7 downto 4) := "0000";

-	

-	constant	OpCode_Break	: std_logic_vector(3 downto 0) := "0000";

-	constant	OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";

-	constant	OpCode_PushSP	: std_logic_vector(3 downto 0) := "0010";

-	constant	OpCode_PushInt	: std_logic_vector(3 downto 0) := "0011";

-	

-	constant	OpCode_PopPC	: std_logic_vector(3 downto 0) := "0100";

-	constant	OpCode_Add		: std_logic_vector(3 downto 0) := "0101";

-	constant	OpCode_And		: std_logic_vector(3 downto 0) := "0110";

-	constant	OpCode_Or		: std_logic_vector(3 downto 0) := "0111";

-	

-	constant	OpCode_Load		: std_logic_vector(3 downto 0) := "1000";

-	constant	OpCode_Not		: std_logic_vector(3 downto 0) := "1001";

-	constant	OpCode_Flip		: std_logic_vector(3 downto 0) := "1010";

-	constant	OpCode_Nop		: std_logic_vector(3 downto 0) := "1011";

-	

-	constant	OpCode_Store	: std_logic_vector(3 downto 0) := "1100";

-	constant	OpCode_PopSP	: std_logic_vector(3 downto 0) := "1101";

-	constant	OpCode_Compare	: std_logic_vector(3 downto 0) := "1110";

-	constant	OpCode_PopInt	: std_logic_vector(3 downto 0) := "1111";

-	

-	constant	OpCode_Lessthan				: std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);

-	constant	OpCode_Lessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);

-	constant	OpCode_Ulessthan			: std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);

-	constant	OpCode_Ulessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);

-

-	constant	OpCode_Swap					: std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);

-	constant	OpCode_Mult					: std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);

-	

-	constant	OpCode_Lshiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);

-	constant	OpCode_Ashiftleft			: std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);

-	constant	OpCode_Ashiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);

-	constant	OpCode_Call					: std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);

-

-	constant	OpCode_Eq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);

-	constant	OpCode_Neq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);

-

-	constant	OpCode_Sub					: std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);

-	constant	OpCode_Loadb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);

-	constant	OpCode_Storeb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);

-

-	constant	OpCode_Eqbranch				: std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);

-	constant	OpCode_Neqbranch			: std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);

-	constant	OpCode_Poppcrel				: std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);

-

-	constant	OpCode_Pushspadd			: std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);

-	constant	OpCode_Mult16x16			: std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);

-	constant	OpCode_Callpcrel			: std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);

-	

-

-

-	constant OpCode_Size		: integer := 8;

-

-

-		

-end zpupkg;

+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+library work;
+use work.zpu_config.all;
+
+package zpupkg is
+
+	-- This bit is set for read/writes to IO
+	-- FIX!!! eventually this should be set to wordSize-1 so as to
+	-- to make the address of IO independent of amount of memory
+	-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
+	-- libraries.
+	
+	constant byteBits			: integer := wordPower-3; -- # of bits in a word that addresses bytes
+	constant maxAddrBit			: integer := maxAddrBitIncIO-1;
+	constant ioBit				: integer := maxAddrBit+1;
+	constant wordSize			: integer := 2**wordPower;
+	constant wordBytes			: integer := wordSize/8;
+	constant minAddrBit			: integer := byteBits;
+	-- configurable internal stack size. Probably going to be 16 after toolchain is done
+	constant	stack_bits		: integer := 5; 
+	constant	stack_size		: integer := 2**stack_bits; 
+
+	component dualport_ram is
+	port (clk : in std_logic;
+		memAWriteEnable : in std_logic;
+		memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+		memAWrite : in std_logic_vector(wordSize-1 downto 0);
+		memARead : out std_logic_vector(wordSize-1 downto 0);
+		memBWriteEnable : in std_logic;
+		memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+		memBWrite : in std_logic_vector(wordSize-1 downto 0);
+		memBRead : out std_logic_vector(wordSize-1 downto 0));
+	end component;
+
+	component dram is
+		port (clk : in std_logic;
+			areset : in std_logic;
+			mem_writeEnable : in std_logic;
+			mem_readEnable : in std_logic;
+			mem_addr : in std_logic_vector(maxAddrBit downto 0);
+			mem_write : in std_logic_vector(wordSize-1 downto 0);
+			mem_read : out std_logic_vector(wordSize-1 downto 0);
+			mem_busy : out std_logic;
+			mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+	end component;
+
+
+	component trace is
+	  port(
+	       	clk         : in std_logic;
+	       	begin_inst  : in std_logic;
+	       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
+			opcode		: in std_logic_vector(7 downto 0);
+			sp			: in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+			memA		: in std_logic_vector(wordSize-1 downto 0);
+			memB		: in std_logic_vector(wordSize-1 downto 0);
+			busy         : in std_logic;
+			intSp		: in std_logic_vector(stack_bits-1 downto 0)
+			);
+	end component;
+
+	component zpu_core is
+    port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  enable : in std_logic; 
+	 		  mem_req : out std_logic;
+	 		  mem_we : out std_logic;
+	 		  mem_ack : in std_logic; 
+	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
+	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
+			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic;
+	 		  zpu_status : out std_logic_vector(63 downto 0));
+	end component;
+
+
+	
+	component timer is
+  	port(
+       	clk             : in std_logic;
+		areset			: in std_logic;
+		sample			: in std_logic;
+		reset			: in std_logic;
+		counter			: out std_logic_vector(63 downto 0));
+	end component;
+
+	component  zpuio is
+		port (	areset			: in std_logic;
+				cpu_clk			: in std_logic;
+				clk_status		: in std_logic_vector(2 downto 0);
+				cpu_din			: in std_logic_vector(15 downto 0);
+				cpu_a			: in std_logic_vector(20 downto 0);
+				cpu_we			: in std_logic_vector(1 downto 0);
+				cpu_re			: in std_logic;
+				cpu_dout		: inout std_logic_vector(15 downto 0));
+	end component;
+
+
+
+	
+	-- opcode decode constants
+	constant	OpCode_Im		: std_logic_vector(7 downto 7) := "1";
+	constant	OpCode_StoreSP	: std_logic_vector(7 downto 5) := "010";
+	constant	OpCode_LoadSP	: std_logic_vector(7 downto 5) := "011";
+	constant	OpCode_Emulate	: std_logic_vector(7 downto 5) := "001";
+	constant	OpCode_AddSP	: std_logic_vector(7 downto 4) := "0001";
+	constant	OpCode_Short	: std_logic_vector(7 downto 4) := "0000";
+	
+	constant	OpCode_Break	: std_logic_vector(3 downto 0) := "0000";
+	constant	OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
+	constant	OpCode_PushSP	: std_logic_vector(3 downto 0) := "0010";
+	constant	OpCode_PushInt	: std_logic_vector(3 downto 0) := "0011";
+	
+	constant	OpCode_PopPC	: std_logic_vector(3 downto 0) := "0100";
+	constant	OpCode_Add		: std_logic_vector(3 downto 0) := "0101";
+	constant	OpCode_And		: std_logic_vector(3 downto 0) := "0110";
+	constant	OpCode_Or		: std_logic_vector(3 downto 0) := "0111";
+	
+	constant	OpCode_Load		: std_logic_vector(3 downto 0) := "1000";
+	constant	OpCode_Not		: std_logic_vector(3 downto 0) := "1001";
+	constant	OpCode_Flip		: std_logic_vector(3 downto 0) := "1010";
+	constant	OpCode_Nop		: std_logic_vector(3 downto 0) := "1011";
+	
+	constant	OpCode_Store	: std_logic_vector(3 downto 0) := "1100";
+	constant	OpCode_PopSP	: std_logic_vector(3 downto 0) := "1101";
+	constant	OpCode_Compare	: std_logic_vector(3 downto 0) := "1110";
+	constant	OpCode_PopInt	: std_logic_vector(3 downto 0) := "1111";
+	
+	constant	OpCode_Lessthan				: std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
+	constant	OpCode_Lessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
+	constant	OpCode_Ulessthan			: std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
+	constant	OpCode_Ulessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
+
+	constant	OpCode_Swap					: std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
+	constant	OpCode_Mult					: std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
+	
+	constant	OpCode_Lshiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
+	constant	OpCode_Ashiftleft			: std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
+	constant	OpCode_Ashiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
+	constant	OpCode_Call					: std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
+
+	constant	OpCode_Eq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
+	constant	OpCode_Neq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
+
+	constant	OpCode_Sub					: std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
+	constant	OpCode_Loadb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
+	constant	OpCode_Storeb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
+
+	constant	OpCode_Eqbranch				: std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
+	constant	OpCode_Neqbranch			: std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
+	constant	OpCode_Poppcrel				: std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
+
+	constant	OpCode_Pushspadd			: std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
+	constant	OpCode_Mult16x16			: std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
+	constant	OpCode_Callpcrel			: std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
+	
+
+
+	constant OpCode_Size		: integer := 8;
+
+
+		
+end zpupkg;