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-rw-r--r--zpu/hdl/zpu4/core/zpu_core.vhd154
1 files changed, 77 insertions, 77 deletions
diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd
index ff9449f..e2e4781 100644
--- a/zpu/hdl/zpu4/core/zpu_core.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core.vhd
@@ -1,68 +1,68 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Řyvind Harboe - oyvind.harboe@zylin.com
--- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com
---
--- The FreeBSD license
---
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
---
--- 1. Redistributions of source code must retain the above copyright
--- notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
--- copyright notice, this list of conditions and the following
--- disclaimer in the documentation and/or other materials
--- provided with the distribution.
---
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Řyvind Harboe - oyvind.harboe@zylin.com
+-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
library ieee;
use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-
--- mem_writeEnable - set to '1' for a single cycle to send off a write request.
--- mem_write is valid only while mem_writeEnable='1'.
--- mem_readEnable - set to '1' for a single cycle to send off a read request.
---
--- mem_busy - It is illegal to send off a read/write request when mem_busy='1'.
--- Set to '0' when mem_read is valid after a read request.
--- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable
--- is '1'.
--- mem_addr - address for read/write request
--- mem_read - read data. Valid only on the cycle after mem_busy='0' after
--- mem_readEnable='1' for a single cycle.
--- mem_write - data to write
--- mem_writeMask - set to '1' for those bits that are to be written to memory upon
--- write request
--- break - set to '1' when CPU hits break instruction
--- interrupt - set to '1' until interrupts are cleared by CPU.
-
-
-
-
-entity zpu_core is
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+-- mem_writeEnable - set to '1' for a single cycle to send off a write request.
+-- mem_write is valid only while mem_writeEnable='1'.
+-- mem_readEnable - set to '1' for a single cycle to send off a read request.
+--
+-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'.
+-- Set to '0' when mem_read is valid after a read request.
+-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable
+-- is '1'.
+-- mem_addr - address for read/write request
+-- mem_read - read data. Valid only on the cycle after mem_busy='0' after
+-- mem_readEnable='1' for a single cycle.
+-- mem_write - data to write
+-- mem_writeMask - set to '1' for those bits that are to be written to memory upon
+-- write request
+-- break - set to '1' when CPU hits break instruction
+-- interrupt - set to '1' until interrupts are cleared by CPU.
+
+
+
+
+entity zpu_core is
port (
clk : in std_logic;
areset : in std_logic;
@@ -77,10 +77,10 @@ entity zpu_core is
interrupt : in std_logic;
break : out std_logic
);
-end zpu_core;
-
-architecture behave of zpu_core is
-
+end zpu_core;
+
+architecture behave of zpu_core is
+
type InsnType is (
State_AddTop,
State_Dup,
@@ -196,12 +196,12 @@ architecture behave of zpu_core is
signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
-
--- state machine.
-
-begin
-
-
+
+-- state machine.
+
+begin
+
+
traceFileGenerate :
if Generate_Trace generate
trace_file : trace port map (
@@ -1009,7 +1009,7 @@ begin
end case; -- state
end if; -- clk'event
end process;
-
-
-
-end behave;
+
+
+
+end behave;
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