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* x86/smbios: Return index 0 for empty stringsBen Gardner2015-12-161-0/+7
| | | | | | | | | | | | | | Section 6.1.3 (Text Strings) of the SMBIOS specification states: If a string field references no string, a null (0) is placed in that string field. Change smbios_add_string() to do that. Change-Id: I9c28cb89dcfe2c8ef2366c23ee6203e15b7c2513 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12697 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* buildgcc: Add coreboot toolchain version to iaslMartin Roth2015-12-162-1/+13
| | | | | | | | | | | | | | | | | | | | | | | Add the coreboot toolchain version to iasl's version output. % ./xgcc/bin/iasl -v Intel ACPI Component Architecture ASL+ Optimizing Compiler version 20150619-64 Copyright (c) 2000 - 2015 Intel Corporation coreboot toolchain v1.33 November 25th, 2015 This won't actually be checked until the next version of iasl so that we don't have to rebuild again for no reason. The buildgcc version was intentionally not incremented for this minor change. Change-Id: I03a1a777fdb84e34bfceb7b1eb43fffbc1f3a2fc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* lib: Fix strncmpHannah Williams2015-12-161-1/+1
| | | | | | | | | | | | | | | | | | | strncmp continues to compare the characters in the input strings past any null termination it may encounter. Null termination check is added. Reviewed-on: https://chromium-review.googlesource.com/314815 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Hannah Williams <hannah.williams@intel.com> Tested-by: Hannah Williams <hannah.williams@intel.com> (cherry picked from commit ca7022752115eddbcb776f0c0d778249555ddf32) Reviewed-on: https://chromium-review.googlesource.com/315130 Change-Id: Ifc378966dcf6023efe3d32b026cc89d69b0bb990 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12721 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/fsp_baytrail: rename include folder baytrail to include/socBen Gardner2015-12-1673-164/+164
| | | | | | | | | | | This is to match the layout of the non-fsp baytrail to make comparisons easier and possibly remove duplicate files. Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12686 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* southbridge/amd/sb600: Update HPET base address with #defineMartin Roth2015-12-168-42/+41
| | | | | | | | | | | | | | | | | | | | | | | The SB600 code had the base address of the HPET hardcoded throughout. It looks like the plan was to have it be updated in ACPI if needed, but this wasn't ever implemented. The variable names being used to do this update were the same, causing an IASL warning. Because of this, the operation to update the HPET address actually did nothing. This was fine, because it didn't actually need to be updated. - Replace all that code with a #define. - Add and update some comments in the same area. Fixes IASL warning: dsdt.aml 1505: Store(HPBA, HPBA) Warning 3023 - ^ Duplicate value in list (Source is the same as Target) Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
* intel/fsp_baytrail: Fix PCI_DEV_PIRQ_ROUTE macro endingBen Gardner2015-12-161-1/+1
| | | | | | | | | | | | | | | | | | | The macro PCI_DEV_PIRQ_ROUTE ends with a comma and escaped newline. Ending a macro with an escaped newline is always wrong. The final comma is not necessary, as all uses of PCI_DEV_PIRQ_ROUTE() properly separate calls with a comma. I haven't investigated whether this is causing a real issue, but it should be leaving gaps in struct baytrail_irq_route.pcidev. The non-FSP baytrail does not have this issue. Change-Id: If6782176068b07cb3bc819c00d1cdb1b618bcea8 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* build system/x86: depend on directories before touch /empty targetsAlexander Couzens2015-12-161-1/+1
| | | | | | | | | | | | | | $(objgenerated)/empty would touch files before the directory is created on parallel builds. Thanks to reproducible-builds.org for hitting this bug. Change-Id: I7565e9fe130b4e9deaf1c7b9d568ff90b00dda52 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12717 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* soc/samsung/exynos5250: Implement hard_reset()Stefan Reinauer2015-12-162-0/+7
| | | | | | | | | | | Implement hard_reset() as power_reset() to make vboot happy. Change-Id: I16831055bd6ba8a8c95836fcf31f29c068153fcc Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12722 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
* intel/skylake: Work around ROMCC optimization bugStefan Reinauer2015-12-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | On Skylake systems, the bootblock fails to compile with the following error message: bootblock_simple.c:6.1: 0x13930e0 copy Internal compiler error: non dominated rhs use point 0x13a3f70? Aborted (core dumped) The option -fno-simplify-phi works around the issue, but will cause the code to use more registers, hence we also need to enable -mcpu=p4 (see intel/truxton mainboard for another example of where this has been done in the past) Change-Id: Iea1a1ba18d76c7323bb626c5f4b0032e4ee04a86 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12719 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* x86 acpi: remove ALIGN_CURRENT macroAaron Durbin2015-12-1511-42/+36
| | | | | | | | | | | | | | The ALIGN_CURRENT macro relied on a local variable name as well as being defined in numerous compilation units. Replace those instances with an acpi_align_current() inline function. Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12707 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mainboard/asus/kgpe-d16: Enable romstage spinlocksTimothy Pearson2015-12-152-5/+16
| | | | | | | | Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* src/console: Add x86 romstage spinlock option and printk spinlock supportTimothy Pearson2015-12-154-1/+33
| | | | | | | | | | | This paves the way for AP printk spinlock on AMD platforms Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/11958 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* google/oak: Move CHROMEOS specific Kconfig objects under CHROMEOSMartin Roth2015-12-151-2/+4
| | | | | | | | | | | The symbols CHROMEOS_VBNV_EC, EC_SOFTWARE_SYNC, and VIRTUAL_DEV_SWITCH should only be selected if CHROMEOS is selected. Change-Id: I07ef631d63be53cf99a6bf61d0e91b88728dbba3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12659 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* msrtool/configure: change svn to gitIru Cai2015-12-141-1/+1
| | | | | | | | Change-Id: I212e44fc7edfd1458b04fb42a8e964a3367dd72d Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/12710 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* amd/[nb/fam10|sb/sr5650]: Minor cosmetic changesTimothy Pearson2015-12-132-13/+13
| | | | | | | | Change-Id: Ia9cb4fe4f46327e38648f89da0ffce647fb118d3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12712 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cbfstool: add ppc64 supportRonald G. Minnich2015-12-124-0/+170
| | | | | | | | | | | | | | | | | | | The constant for ppc64 is 'hotstuff'. For many reasons. Note that line 2894 of elf.h is not indented. This is because in the original the line begins with a space. Checkpatch rejects that. Checkpatch also rejects changing the space to a tab because that makes it more than 80 chars. I rejected breaking the line because it makes it even less readable. All the changes forced by checkpatch make the code less readable. Herman Hollerith would be proud. Change-Id: I21f049fe8c655a30f17dff694b8f42789ad9efb7 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/12711 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
* build system: Switch to fmap based firmware layoutPatrick Georgi2015-12-114-4/+128
| | | | | | | | | | | | | | | | | | | | | | We still add a master header for compatibility purposes, and the default layouts don't cover anything non-coreboot (eg. IFD regions) yet. The default layouts can be overridden by specifying an fmd file, from which the fmap is generated. Future work: - map IFD regions to fmap regions - non-x86: build minimalistic trampolines that jump into the first cbfs file, so the bootblock can be part of CBFS instead of reserving a whole 64K for it. - teach coreboot's cbfs code to work without the master header - teach coreboot's cbfs code to work on different fmap regions Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/11692 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* fsp1_1: supply fsp version to mrc_cache APIAaron Durbin2015-12-113-5/+18
| | | | | | | | | | | | | | | | | The memory init code needs to match the saved mrc data. To ensure that invariant holds supply the FSP version when using the mrc cache API. BUG=chrome-os-partner:46050 BRANCH=None TEST=Built and booted on glados. Verified version mismatch checking works. Change-Id: I3f6dd19cb15a18761d34509749adafc89a72ed2d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12701 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mrc_cache: add version fieldAaron Durbin2015-12-112-12/+32
| | | | | | | | | | | | | | | | | | | In order to allow for updateable memory init code on intel x86 platforms one needs to ensure the saved mrc data matches the code consuming the data. To that end add a version field to the saved data structure. BUG=chrome-os-partner:46050 BRANCH=None TEST=Built and booted on glados. Suspended and resumed. Also verified version mismatch path. Change-Id: Ie86db1750af5d9bff6446999b0d04b60612f8d29 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12700 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* ati/ragexl: Change .h #defines named CONFIG_ to CFG_Martin Roth2015-12-102-21/+21
| | | | | | | | | | The CONFIG_ prefix should be reserved for Kconfig symbols. Change-Id: I1d3141e0f5f9e1161bc7f88158af8a5d5780829c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12564 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
* soc/mediatek/mt8173: SPI_ATOMIC_SEQUENCING depends on SPI_FLASHMartin Roth2015-12-101-1/+1
| | | | | | | | | | | | | Don't select SPI_ATOMIC_SEQUENCING unless SPI_FLASH is being used. warning: (... SOC_MEDIATEK_MT8173) selects SPI_ATOMIC_SEQUENCING which has unmet direct dependencies (SPI_FLASH) Change-Id: I93e9a7102d1d0ef62565110b5b3b677da8d0c72b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12657 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* emulation/qemu-arm7: Fix Kconfig symbols for stage compilersMartin Roth2015-12-101-3/+3
| | | | | | | | | | These had typos ARM_STAGE_ARM7 instead of ARCH_STAGE_ARM7 Change-Id: Iffe8fecb3e52a50ff02b774478a10c353093688b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12660 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ACPI: Fix IASL Warning about unused method for _S3 checkMartin Roth2015-12-1016-35/+35
| | | | | | | | | | | | | | | | According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 640: If (CondRefOf (\_S3, Local0)) Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: I758d198c33e585a6a4ad2c1c70f2370a01af5138 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12693 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ACPI: Work around IASL warning reading/writing same registerMartin Roth2015-12-1036-36/+73
| | | | | | | | | | | | | | | | | | | | | | | | The newer versions of IASL are unhappy when an operator has the same object as both source and destination. The warning can be completely disabled with a command line argument, but in general, I'd really rather not just disable warnings. The bits in this register are write 1 to clear, so reading and writing the same register is what we want to do. Instead, store it in a temporary register then write it in a second operation. Fixes warning: dsdt.aml 1396: Store(PWST, PWST) Warning 3023 - ^ Duplicate value in list (Source is the same as Target) Change-Id: I52d73d4431db237be83016d67cd397f31b53d9c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ACPI: Fix IASL Warning about unused method for _OSI checkMartin Roth2015-12-1040-41/+41
| | | | | | | | | | | | | | | | | According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 22: if(CondRefOf(\_OSI,Local1)) Warning 3144 - ^ Method Local is set but never used (Local1) Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ACPI: Fix IASL Warning about unused method for _TZ checksMartin Roth2015-12-104-8/+8
| | | | | | | | | | | | | | | | According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 640: If (CondRefOf (^GBUF, Local0)) { Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: Iddf46a4faab19019882847917397eee0614302b9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12695 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ACPI: Fix IASL Warning about unused method for GBUF checkMartin Roth2015-12-102-2/+2
| | | | | | | | | | | | | | | | According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 640: If (CondRefOf (^GBUF, Local0)) { Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: Ie2f46808e92c309a63ba7661bcbd77402a08366a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12694 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* intel/fsp_baytrail: Remove code for nonexistant BBARBen Gardner2015-12-101-16/+1
| | | | | | | | | | | | The BBAR register (BIOS Base Address Configuration Register) defined in the ICH9 datasheet does not exist in the Bay Trail E3800 datasheet. Accessing it seems harmless, but should likely be avoided. Change-Id: I5d9a6a1ccead84c8996796f516a2bdc5f248cfef Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12671 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* lib: remove assets infrastructureAaron Durbin2015-12-1015-215/+41
| | | | | | | | | | | | | | | | | Now that only CBFS access is supported for finding resources within the boot media the assets infrastructure can be removed. Remove it. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. Change-Id: I383fd6579280cf9cfe5a18c2851baf74cad004e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cbfs/vboot: remove firmware component supportAaron Durbin2015-12-1026-335/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Chrome OS verified boot path supported multiple CBFS instances in the boot media as well as stand-alone assets sitting in each vboot RW slot. Remove the support for the stand-alone assets and always use CBFS accesses as the way to retrieve data. This is implemented by adding a cbfs_locator object which is queried for locating the current CBFS. Additionally, it is also signalled prior to when a program is about to be loaded by coreboot for the subsequent stage/payload. This provides the same opportunity as previous for vboot to hook in and perform its logic. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. CQ-DEPEND=CL:307121,CL:31691,CL:31690 Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12689 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* MAINTAINERS: Define all subsystems and their filesStefan Reinauer2015-12-091-1/+155
| | | | | | | | | | | | Initial list of subsystems and the files that belong to that subsystem, so we can define maintainers for them. Change-Id: Icde0f387b486bea1bb63f9bbdf6330fa0a3ebcfa Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/10530 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
* mohonpeak/Kconfig: Fix whitespace issuesMartin Roth2015-12-091-4/+4
| | | | | | | | | | Auto-indent did me wrong, and I didn't notice it. Change-Id: I5a736cf53a3bdbe57b28b2d6a55befd341d8dfd8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12655 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
* sb/amd/sb700: Enable watchdog timer for OS useTimothy Pearson2015-12-092-1/+21
| | | | | | | | | Change-Id: Ib0281139cafe74a22a24a377b3fdec1c59e934f3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12687 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
* google/oak: define flash sizePatrick Georgi2015-12-091-0/+1
| | | | | | | | | | | | We never defined the flash size for this board, so the (too small) default was used. Instead, adopt the size given in depthcharge's fmap description. Change-Id: I63782922ee05a9595d6c0de56750460ebb67aec6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12674 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
* amdfwtool: Hide the prefix of targetZheng Bao2015-12-092-2/+2
| | | | | | | | | | | | Make the definitions of rules compliant with others. Change-Id: Ieef3a9c3fae5beaa1ea3e14e890cfb9145090c3b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12685 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* AMD/bettong: Add missing uart.c for UARTZheng Bao2015-12-091-0/+26
| | | | | | | | Change-Id: Ie49732c6874f2b443e314eb3412ddee054d9c0bb Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* cbfstool: make top-aligned address work per-regionPatrick Georgi2015-12-091-1/+9
| | | | | | | | | | | | | | | | The former interpretation sprung from the x86 way of doing things (assuming top-alignment to 4GB). Extend the mechanism to work with CBFS regions residing elsewhere. It's compatible with x86 because the default region there resides at the old location, so things fall in place. It also makes more complex layouts and non-x86 layouts work with negative base addresses. Change-Id: Ibcde973d85bad5d1195d657559f527695478f46c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12683 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* sb/amd/sr5650: Allow resource allocator to assign bus numbersTimothy Pearson2015-12-081-3/+4
| | | | | | | | | | | | | | | | | | At some point in the past disconnected PCIe bridges were completely disabled to work around a hang on bridge probe. This hang was resolved at some point, and the disconnected PCIe bridges should be enabled to receive a bus number per the RPR. This resolves a slew of warnings in the Linux boot log regarding invalid bridge configurations for disconnected bridge devices. Change-Id: Ic26e2d62ec5ddb9f22275c2afec7d560326263c7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12673 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* vendorcode/google/chromeos: Only select ELOG if SPI_FLASH is availableMartin Roth2015-12-081-1/+1
| | | | | | | | | | | ELOG requires SPI_FLASH, so don't bother selecting if if SPI_FLASH isn't available. Change-Id: I080ac47e74aba820c94409d4913647abee215076 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12661 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* intel/strago: Remove CONFIG_ from CONFIG_GOP_SUPPORT inside KconfigMartin Roth2015-12-081-2/+2
| | | | | | | | | | | | The CONFIG_ is only used for Kconfig symbols outside of Kconfig. If used inside Kconfig, you'd end up with CONFIG_CONFIG_GOP_SUPPORT when it was used in the C code. Change-Id: I572323ef08fdd937d33ded1c27a418b3ad856147 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12664 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* console: Allow ARM64 platforms to select bootblock consoleMartin Roth2015-12-081-1/+1
| | | | | | | | Change-Id: I09943aafe29f6e7a2a878e7b6141661982dfc645 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* toolchain.inc: fix typoMartin Roth2015-12-081-1/+1
| | | | | | | | | Change-Id: I6336881f0ec3568e14c03c55c7c060eba9f4be53 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* toolchain.inc: verify tool variable validity before using it.Martin Roth2015-12-081-2/+2
| | | | | | | | | | | | | | | | | If the toolchain for a stage/architecture wasn't present, we'd call the shell with '-v', generating an ugly warning: /bin/sh: - : invalid option Usage: /bin/sh [GNU long option] [option] ... /bin/sh [GNU long option] [option] script-file ... GNU long options: ... Change-Id: Icd6d7a00083ee1695591ff96da36b7868be0c2f0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* soc/intel/common: Remove USE_FMAP - symbol doesn't existMartin Roth2015-12-081-7/+0
| | | | | | | | | | | The USE_FMAP Kconfig symbol doesn't exist, so remove things that are depending on it not being enabled. Change-Id: I1946f5d13a762ab07744a1d9a6cb754433e6701d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* lenovo/t500: Add clone of Lenovo T400Francis Rowe2015-12-084-1/+16
| | | | | | | | | | | | | The existing code for the Lenovo T400 works without changes on the Lenovo T500. Same HDA verbs are provided by Lenovo BIOS on both laptops. Change-Id: I300408a8a0ed00476aee6061925befc2822fb505 Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: https://review.coreboot.org/10545 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/skylake: Remove obsolete Kconfig symbolsMartin Roth2015-12-081-2/+0
| | | | | | | | | | | | | | | | CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 (cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS) Both CPU_MICROCODE_IN_CBFS and SUPPORT_CPU_UCODE_IN_CBFS were present, so just remove CPU_MICROCODE_IN_CBFS. SMM_MODULES was removed in commit 44cbe10f (smm: Merge configs SMM_MODULES and SMM_TSEG) Change-Id: Icdd4fcc5a3a97aee443742aaab3df92b53ff4589 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* qemu-x86: Enable SMP supportPatrick Georgi2015-12-081-0/+1
| | | | | | | | | | | QEMU can do this for a while now. Change-Id: I3a5027a7afc9dd18463d26cb42fe68747a89f6b0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* amdfwtool: Fill the first 3 romsig entries as 0zbao2015-12-081-0/+3
| | | | | | | | | | | | | | | I didn't go back through the development guide for this. But based on test, if the empty entry is filled as 0xFFFFFFFF, instead of 0, the USB3 port can not be used. Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant with the case before the amdfwtool is used. Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12665 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* northbridge/amd/agesa/agesawrapper.c: Fix Kconfig symbolsMartin Roth2015-12-081-2/+2
| | | | | | | | | | | | The Kconfig symbols were missing an underscore, so were not getting evaluated properly. Change-Id: I619cf3f44f44f9c9699482d64164d3db28cd4c8f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12559 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* AMD/bettong: Remove the useless period (trivial)Zheng Bao2015-12-081-1/+1
| | | | | | | | | | It seems that no one add period in Kconfig. Change-Id: Ie9c585a8e6f1a73036b92b2873dc19284d82dc39 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12668 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
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