BranchCommit messageAuthorAge
4.1x86: flatten hierarchyStefan Reinauer5 years
4.2Revert "device/pciexp_device: Tune PCIe bridges before scanning children"Kyösti Mälkki5 years
classic-2014.10i945: Consolidate FADT codeVladimir Serbinenko6 years
experimentalAdd the Rangeley FSP include & srx directoriesMartin Roth6 years
mastersoc/intel/fsp_baytrail: Make sure i2c bus is < 7Martin Roth5 years
TagDownloadAuthorAge  coreboot-staging-4.2.tar.gz  Patrick Georgi5 years  coreboot-staging-4.1.tar.gz  Patrick Georgi5 years  coreboot-staging-4.0.tar.gz  Patrick Georgi9 years
AgeCommit messageAuthorFilesLines
2015-12-22soc/intel/fsp_baytrail: Make sure i2c bus is < 7HEADmasterMartin Roth1-1/+1
2015-12-22drivers/intel/fsp1_0/fsp_util.c: Fix indentationMartin Roth1-4/+5
2015-12-21imgtec/pistachio: DDR2, DDR3: DLL reset setIonela Voinescu2-2/+2
2015-12-21imgtec/pistachio: DDR2, DDR3: DQS gate earlyIonela Voinescu3-10/+25
2015-12-21imgtec/pistachio: increase CBFS cacheIonela Voinescu1-2/+2
2015-12-20buildgcc: Add coreboot toolchain string to clang versionMartin Roth1-0/+1 Move addition of payload rev & config to payload makefileMartin Roth2-8/+8
2015-12-20soc/intel/broadwell: Init var before use, only use when neededMartin Roth2-2/+3 Double quote variables to prevent globbing and word splitting.Martin Roth1-16/+16 checksum the rom and save it for later verificationMartin Roth1-0/+2
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