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path: root/sys/i386/include/intr_machdep.h
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* MFC 304637: Fix build for !SMP kernels after the Xen MSIX workaround.jhb2016-09-091-1/+2
* MFC r302635:royger2016-07-151-0/+2
* Add a new bus method to fetch device-specific CPU sets.jhb2016-05-091-0/+3
* Type of the interrupt handlers on x86 cannot be expressed in C.kib2016-03-291-1/+1
* Update Xen headers from 4.2 to 4.6royger2015-10-061-0/+1
* Remove support for Xen PV domU kernels. Support for HVM domU kernelsjhb2015-04-301-7/+1
* Use VT-d interrupt remapping block (IR) to perform FSB messageskib2015-03-191-0/+2
* Add support for suspend/resume/migration operations when running as agibbs2013-09-201-2/+2
* Implement vector callback for PVHVM and unify event channel implementationsgibbs2013-08-291-3/+21
* x86 suspend/resume: suspend pics and pseudo-pics in reverse orderavg2013-02-021-1/+1
* Reverts r234074,234105,234564,234723,234989,235231-235232 and part ofattilio2012-10-091-0/+2
* Revert part of r234723 by re-enabling the SMP protection forattilio2012-05-031-0/+2
* Clean up the intr* MD KPI from the SMP dependency, removing a cause ofattilio2012-04-261-4/+0
* bump INTRCNT_COUNT values to reflect actual numbers of IPI countersavg2012-04-131-2/+2
* Allow a native i386 kernel to be built with 'nodevice atpic'. Just as onjhb2012-03-091-0/+3
* Add a facility for associating optional descriptions with active interruptjhb2009-10-151-0/+1
* Improve the handling of cpuset with interrupts.jhb2009-07-011-1/+1
* Fix kernels compiled without SMP support. Make intr_next_cpu() availablejhb2009-06-251-2/+0
* - Restore the behavior of pre-allocating IDT vectors for MSI interrupts.jhb2009-06-251-0/+3
* - Allocate apic vectors on a per-cpu basis. This allows us to allocatejeff2009-01-291-1/+1
* Add preliminary support for binding interrupts to CPUs:jhb2008-03-141-0/+3
* Minor fixes and tweaks to the x86 interrupt code:jhb2007-05-081-4/+5
* Revamp the MSI/MSI-X code a bit to achieve two main goals:jhb2007-05-021-2/+2
* Change the x86 interrupt code to use FreeBSD CPU IDs (i.e. PCPU_GET(cpuid))jhb2007-03-061-3/+1
* o break newbus api: add a new argument of type driver_filter_t topiso2007-02-231-2/+2
* Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support.jhb2007-01-221-0/+1
* Sort function prototypes.jhb2006-12-121-1/+1
* MD support for PCI Message Signalled Interrupts on amd64 and i386:jhb2006-11-131-4/+17
* Change the x86 interrupt code to suspend/resume interrupt controllersjhb2006-10-101-2/+4
* Oops, fix sign bug in #ifdef for value of INTRCNT_COUNT.jhb2006-10-101-2/+2
* Rework how we wire up interrupt sources to CPUs:jhb2006-02-281-0/+7
* Change the i386 code to pass the interrupt vector as a separate argumentjhb2005-12-051-2/+2
* Change the x86 code to allocate IDT vectors on-demand when an interruptjhb2005-11-021-3/+29
* Reorganize the interrupt handling code a bit to make a few things cleanerjhb2005-10-251-1/+1
* Tweak the ELCR support slightly. Explicitly probe the ELCR during bootjhb2005-01-181-0/+1
* Add a simple 'intrcnt_add' function that other MD code can use to add ajhb2004-12-231-0/+1
* Optimize intr_execute_handlers() by combining the pic_disable_source() andscottl2004-08-021-1/+7
* - Add a new pic method pic_config_intr() to set the trigger mode andjhb2004-05-041-0/+4
* Add a simple mini-driver for the ELCR register. Originally, the ELCRjhb2004-05-041-0/+5
* Shuffle the APIC interrupt vectors around a bit:jhb2003-11-141-2/+2
* New device interrupt code. This defines an interrupt source abstractionjhb2003-11-031-0/+91
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