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author | jhb <jhb@FreeBSD.org> | 2006-11-13 22:23:34 +0000 |
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committer | jhb <jhb@FreeBSD.org> | 2006-11-13 22:23:34 +0000 |
commit | fa70d013974c2fa6347ccc628becfdfcdbddc617 (patch) | |
tree | 73f5aafc03e3a710fa43be47c1b42fa68959a2bb /sys/i386/include/intr_machdep.h | |
parent | d055bdf0ca2fa4ba26cc9a2bf7648eff24fb1cdd (diff) | |
download | FreeBSD-src-fa70d013974c2fa6347ccc628becfdfcdbddc617.zip FreeBSD-src-fa70d013974c2fa6347ccc628becfdfcdbddc617.tar.gz |
MD support for PCI Message Signalled Interrupts on amd64 and i386:
- Add a new apic_alloc_vectors() method to the local APIC support code
to allocate N contiguous IDT vectors (aligned on a M >= N boundary).
This function is used to allocate IDT vectors for a group of MSI
messages.
- Add MSI and MSI-X PICs. The PIC code here provides methods to manage
edge-triggered MSI messages as x86 interrupt sources. In addition to
the PIC methods, msi.c also includes methods to allocate and release
MSI and MSI-X messages. For x86, we allow for up to 128 different
MSI IRQs starting at IRQ 256 (IRQs 0-15 are reserved for ISA IRQs,
16-254 for APIC PCI IRQs, and IRQ 255 is reserved).
- Add pcib_(alloc|release)_msi[x]() methods to the MD x86 PCI bridge
drivers to bubble the request up to the nexus driver.
- Add pcib_(alloc|release)_msi[x]() methods to the x86 nexus drivers that
ask the MSI PIC code to allocate resources and IDT vectors.
MFC after: 2 months
Diffstat (limited to 'sys/i386/include/intr_machdep.h')
-rw-r--r-- | sys/i386/include/intr_machdep.h | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/sys/i386/include/intr_machdep.h b/sys/i386/include/intr_machdep.h index 4884fd5..bfeba5e 100644 --- a/sys/i386/include/intr_machdep.h +++ b/sys/i386/include/intr_machdep.h @@ -43,11 +43,18 @@ * 191 and still be safe since only interrupt sources in actual use will * allocate IDT vectors. * - * For now we stick with 255 as ISA IRQs and PCI intline IRQs only allow - * for IRQs in the range 0 - 254. When MSI support is added this number - * will likely increase. + * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. + * IRQ values beyond 256 are used by MSI. We leave 255 unused to avoid + * confusion since 255 is used in PCI to indicate an invalid IRQ. */ -#define NUM_IO_INTS 255 +#define NUM_MSI_INTS 128 +#define FIRST_MSI_INT 256 +#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS) + +/* + * Default base address for MSI messages on x86 platforms. + */ +#define MSI_INTEL_ADDR_BASE 0xfee00000 /* * - 1 ??? dummy counter. @@ -137,6 +144,12 @@ int intr_remove_handler(void *cookie); void intr_resume(void); void intr_suspend(void); void intrcnt_add(const char *name, u_long **countp); +void msi_init(void); +int msi_alloc(device_t dev, int count, int maxcount, int *irqs, int *newirq, + int *newcount); +int msi_release(int* irqs, int count); +int msix_alloc(device_t dev, int index, int *irq, int *new); +int msix_release(int irq); #endif /* !LOCORE */ #endif /* _KERNEL */ |