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* MFC r311169,r311898,r312925,r312973,r312975,r313007,r313040,r313080,mjg2017-03-161-0/+34
* MFC r313154:kib2017-02-241-29/+0
* MFC r312952:jah2017-02-171-0/+10
* MFC r312555:kib2017-02-031-0/+7
* MFC r310481:jah2017-01-071-1/+9
* MFC 305836: Remove 'cpu' and 'cpu_class' on amd64.jhb2016-11-082-0/+6
* Merge bde improvements for ddb on x86, mostly for single-stepping andkib2016-11-071-5/+14
* MFC r306680:kib2016-10-241-1/+2
* MFC 304637: Fix build for !SMP kernels after the Xen MSIX workaround.jhb2016-09-091-1/+2
* MFC r302635:royger2016-07-151-0/+2
* Replace a number of conflations of mp_ncpus and mp_maxid with eithernwhitehorn2016-07-061-3/+3
* atomic: Add testandclear on i386/amd64sephe2016-05-161-0/+26
* Add a new bus method to fetch device-specific CPU sets.jhb2016-05-091-0/+3
* xen/i386: enable the platform hypercall for i386royger2016-05-031-2/+2
* Type of the interrupt handlers on x86 cannot be expressed in C.kib2016-03-292-2/+1
* Move amd64 metadata.h to x86 and share with i386emaste2016-01-071-34/+3
* Move shared variables from {amd64,i386}/initcpu.c to x86/identcpu.c.jhb2015-12-231-21/+2
* Merge common parts of i386 and amd64 md_var.h and smp.h intokib2015-12-072-145/+6
* For amd64 non-PCID machines, and for i386 machines with support forkib2015-12-032-8/+3
* Export various helper variables describing the layout and size ofjhb2015-11-121-6/+10
* The prefix for CLFLUSHOPT is 0x66. It was right on amd64.kib2015-10-301-1/+1
* Use movw instead of movl (or plain mov) when moving segment registersjhb2015-10-291-3/+3
* Add CLFLUSHOPT instruction wrappers.kib2015-10-231-0/+7
* x86/xen: Consolidate xen-os.h in a single placeroyger2015-10-211-186/+4
* xen/console: Introduce a new console driver for Xen guestroyger2015-10-081-1/+1
* Update Xen headers from 4.2 to 4.6royger2015-10-061-0/+1
* Merge stack(9) implementations for i386 and amd64 under x86/.markj2015-09-111-39/+3
* Remove unused i386 header privatespace.h. For the native kernel, itskib2015-08-071-49/+0
* Remove some more vestiges of the Xen PV domu support. Specifically,jhb2015-08-062-117/+0
* Rationalize BSD license on sys/*/include/in_cksum.hemaste2015-08-051-1/+1
* Add two new pmap functions:jah2015-08-041-1/+2
* Give large kernel stack to the initial thread . Otherwise, ZFSkib2015-08-041-0/+5
* Clear the IA32_MISC_ENABLE MSR bit, which limits the max CPUIDkib2015-08-031-0/+1
* Improve comments.kib2015-07-301-3/+3
* Use private cache line for the locked nop in *mb() on i386.kib2015-07-301-32/+39
* MFamd64 r285934: Remove store/load (= full) barrier from the i386kib2015-07-291-17/+7
* Remove duplicate and useless declarations.kib2015-07-221-1/+0
* Duplicate the copyright from the i386/i386/machdep.c intokib2015-07-101-6/+36
* Add the atomic_thread_fence() family of functions with intent tokib2015-07-081-0/+32
* Use single instance of the identical INKERNEL() and PMC_IN_KERNEL()kib2015-07-023-4/+4
* Provide npx_get_fsave(9) and npx_set_fsave(9) functions to obtain andkib2015-06-291-0/+5
* Move CS_SECURE() and EFL_SECURE() macros to the machine/frame.h. Theykib2015-06-291-0/+8
* Add a comment about too strong semantic of atomic_load_acq() on x86.kib2015-06-291-0/+9
* Reduce code duplication. Add helper fill_based_sd(9) which creates akib2015-06-291-0/+2
* Remove unneeded data dependency, currently imposed bykib2015-06-281-49/+74
* Report the values of x86 segment registers to remote debuggers.jhb2015-06-121-1/+1
* Ensure that the upper 16 bits of segment registers manually saved injhb2015-06-121-3/+6
* Retire VM_FREEPOOL_CACHE as the next step in eliminating PG_CACHE pages.alc2015-06-081-3/+2
* Update print_INTEL_TLB() by the tag values from the Intel SDMkib2015-06-061-0/+1
* If x86 CPU implementation of the MWAIT instruction reasonablykib2015-05-091-0/+1
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