Change the x86 code to allocate IDT vectors on-demand when an interrupt

source is first enabled similar to how intr_event's now allocate ithreads
on-demand.  Previously, we would map IDT vectors 1:1 to IRQs.  Since we
only have 191 available IDT vectors for I/O interrupts, this limited us
to only supporting IRQs 0-190 corresponding to the first 190 I/O APIC
intpins.  On many machines, however, each PCI-X bus has its own APIC even
though it only has 1 or 2 devices, thus, we were reserving between 24 and
32 IRQs just for 1 or 2 devices and thus 24 or 32 IDT vectors.  With this
change, a machine with 100 IRQs but only 5 in use will only use up 5 IDT
vectors.  Also, this change provides an API (apic_alloc_vector() and
apic_free_vector()) that will allow a future MSI interrupt source driver to
request IDT vectors for use by MSI interrupts on x86 machines.

Tested on:	amd64, i386

1 files changed, 29 insertions, 3 deletions

diff --git a/sys/i386/include/intr_machdep.h b/sys/i386/include/intr_machdep.h
index cfc2e1f..d174ed0 100644
--- a/sys/i386/include/intr_machdep.h
+++ b/sys/i386/include/intr_machdep.h
@@ -31,9 +31,35 @@
 
 #ifdef _KERNEL
 
-/* With I/O APIC's we can have up to 191 interrupts. */
-#define	NUM_IO_INTS	191
-#define	INTRCNT_COUNT	(1 + NUM_IO_INTS * 2)
+/*
+ * The maximum number of I/O interrupts we allow.  This number is rather
+ * arbitrary as it is just the maximum IRQ resource value.  The interrupt
+ * source for a given IRQ maps that I/O interrupt to device interrupt
+ * source whether it be a pin on an interrupt controller or an MSI interrupt.
+ * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
+ * interrupts allocate IDT vectors on demand.  Currently we have 191 IDT
+ * vectors available for device interrupts.  On many systems with I/O APICs,
+ * a lot of the IRQs are not used, so this number can be much larger than
+ * 191 and still be safe since only interrupt sources in actual use will
+ * allocate IDT vectors.
+ *
+ * For now we stick with 255 as ISA IRQs and PCI intline IRQs only allow
+ * for IRQs in the range 0 - 254.  When MSI support is added this number
+ * will likely increase.
+ */
+#define	NUM_IO_INTS	255
+
+/*
+ * - 1 ??? dummy counter.
+ * - 2 counters for each I/O interrupt.
+ * - 1 counter for each CPU for lapic timer.
+ * - 7 counters for each CPU for IPI counters for SMP.
+ */
+#ifdef SMP
+#define	INTRCNT_COUNT	(1 + NUM_IO_INTS * 2 + 1)
+#else
+#define	INTRCNT_COUNT	(1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU)
+#endif
 
 #ifndef LOCORE