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| author | Bert Lange <b.lange@hzdr.de> | 2011-10-25 23:26:36 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@hzdr.de> | 2011-10-25 23:26:36 +0200 |
| commit | c883cd4a4e4fa1974e5d7d72a79240de88bd26da (patch) | |
| tree | ff3c0f3f7aa62f809001ea9ac9130683ab98a49e /zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do | |
| parent | 105f8b40509ea2657e36e13af76b7580029fd2e5 (diff) | |
| download | zpu-c883cd4a4e4fa1974e5d7d72a79240de88bd26da.zip zpu-c883cd4a4e4fa1974e5d7d72a79240de88bd26da.tar.gz | |
add: GPIO module to zealot SoC
Diffstat (limited to 'zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do')
| -rw-r--r-- | zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do index 7c5e18f..0d29e0a 100644 --- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do @@ -1,4 +1,2 @@ -add wave tb_rot_center -add wave tb_clk_50mhz -add wave tb_rs232_dce* -run -all +do wave.do
+run -all
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