| Commit message (Collapse) | Author | Age | Files | Lines |
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Serprog compilation is now controlled by a Makefile variable.
Replace munmap with physunmap where appropriate.
Corresponding to flashrom svn r671.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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If we only send an opcode and no additional data/address, the SPI controller
will read one byte too few from the chip. Basically, the last byte of the chip
response is discarded and will not end up in the FIFO. It is unclear if the
CS# line is set high too early as well. That hardware bug is undocumented as
of now, but I'm working with AMD to add a detailed description of it to the
errata. Add loads of additional debugging to SB600/SB700 init. Add explanatory
comments for unintuitive code flow. Thanks go to Uwe for testing quite a few
iterations of the patch. Kill the SB600 flash chip status register special
case, which was a somewhat misguided workaround for that hardware erratum.
Note for future added features in the SB600 SPI driver: It may be possible to
read up to 15 bytes of command response with overlapping reads due to the ring
buffer design of the FIFO if the command can be repeated without ill effects.
Same for skipping up to 7 bytes between command and response.
Corresponding to flashrom svn r661.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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- Properly escape '-' chars in manpage.
- Fix typo in chipset_enable.c.
- Drop useless 'return' in chip_readn().
- Random other whitespace or cosmetic fixes.
Corresponding to flashrom svn r636.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Corresponding to flashrom svn r635.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Corresponding to flashrom svn r603.
Signed-off-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Drop no longer needed MAX macro, we have a max() function.
Corresponding to flashrom svn r601.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Also, list how many chips/chipsets/boards we support in 'flashrom -L'.
Corresponding to flashrom svn r599.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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the VX800 PCI ID
Corresponding to flashrom svn r591.
Signed-off-by: Arjan Koers <0h3q2rmn2bdb@list.nospam.xutrox.com>
Acked-by: Bari Ari <bari@onelabs.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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this in the last commit
Also do some random cleanups while I'm at it.
Corresponding to flashrom svn r567.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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It doesn't make sense to probe for SPI chips on a LPC host, nor does it
make sense to probe for LPC chips on a Parallel host.
This change is backwards compatible, but adding host protocol info to
chipset init functions will speed up probing.
Once all chipset init functions are updated and the Winbond W29EE011 and
AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can
be deleted as the W29/A49 conflict magically disappears.
Tested on real hardware and
Corresponding to flashrom svn r560.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Right now, the annotation only differentiates between SPI and non-SPI. Anyone
who knows more about a specific flash chip should feel free to update it.
The existing flashbus variable was abused to denote the SPI controller type.
Use an aptly named variable for that purpose. Once this patch is merged,
the chipset/programmer init functions can set supported flash chip types
and flashrom can automatically select only matching probe/read/erase/write
functions. A side benefit of that will be the elimination of the Winbond
W29EE011 vs. AMIC A49LF040A conflict.
Corresponding to flashrom svn r556.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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While the other chipset enables for nvidia could potentially also work,
this one, by not touching other bits, seems like the safest solution.
Uwe tested this on his Asus A7N8X Deluxe, so hopefully the A7N8X-E
(reporter unknown) is now no longer an issue.
Corresponding to flashrom svn r548.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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- Update manpage, we now report supported boards via -L. - Add some missing
escaping for '-' characters in the manpage. - Shorten some of the really
long device names, so that -L output looks nicer. - Display a "table header"
for all entries/columns in -L output. - Make -L output tabular for all lists
for better readability. - Do not print "unknown XXXX SPI chip" entries in
-L output. - And random other cosmetics...
Corresponding to flashrom svn r543.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
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Some MMIO accesses used volatile, others didn't (and risked non-execution
of side effects) and even with volatile, some accesses looked dubious.
Since the MMIO accessor functions and the onboard flash accessor functions
are functionally identical (but have different signatures), make the flash
accessors wrappers for the MMIO accessors. For some of the conversions,
I used Coccinelle. Semantic patch follows: @@ typedef uint8_t; expression a;
volatile uint8_t *b; @@ - b[a] + *(b + a) @@ expression a; volatile uint8_t *b;
@@ - *(b) |= (a); + *(b) = *(b) | (a); @@ expression a; volatile uint8_t *b;
@@ - *(b) = (a); + mmio_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b)
+ mmio_readb(b) @@ type T; T b; @@ ( mmio_readb | mmio_writeb ) (..., - (T)
- (b) + b ) Uwe tested read, write, erase with this patch on a random board
to make sure nothing breaks.
Corresponding to flashrom svn r524.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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- Supported out of the box (no flash enables required)
- Verifiably not yet working (unknown flash enable)
Also, move some structs to flash.h in preparation for later wiki
output support.
Corresponding to flashrom svn r523.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Build-tested on 32bit x86.
Corresponding to flashrom svn r521.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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It seems some boards do not use SPI_HOLD at all. Take that into account when
trying to figure out if SPI is available. Print the SB600 ROM strap override
register status for better debugging.
Corresponding to flashrom svn r516.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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I know that the data sheets say we can't read the ROM straps, but
creative interpretation of the data sheets yielded a heuristic which
should work pretty well.
NOTE: If you test this, make sure you power down and _unplug_ the
machine for a few minutes before you boot and run flashrom with this
patch.
If the machine is not unplugged for some time, the test will yield
incorrect results.
If you run a slightly older flashrom version than svn HEAD, the test
will yield incorrect results.
If you run any flashrom version (except svn HEAD plus this patch) after
poweron, the test will yield incorrect results.
Explanation:
Older flashrom versions unconditionally write to registers which are
used for this heuristic. These registers are in the S5 power domain, so
even powering down does not clear them, you really have to unplug the
machine and remove the battery if this is a laptop.
Corresponding to flashrom svn r491.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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Corresponding to flashrom svn r477.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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The list of tested chipsets is synced from the wiki.
Also, split the chipset vendor and name into two fields for easier
wiki-syntax output later.
Corresponding to flashrom svn r472.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r469.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
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If unprotect succeeded, it will print "SB600 unprotect failed".
Corresponding to flashrom svn r467.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r466.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
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Corresponding to flashrom svn r465.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
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Use pci_dev_find() instead of setting up a filter and iterating over
PCI devices.
Corresponding to flashrom svn r464.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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- Check for read/write protected regions first.
- Region protection is write-once according to the data sheets. Check if
the write succeeded. Don't write if the region is not protected.
- Verbose region protection dumping.
- Improve readability of BAR mapping code.
- Align BAR mapping to a page boundary (4k) instead of a 16k boundary.
This patch prepares the code for a SPI detection heuristic.
Corresponding to flashrom svn r463.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
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Open fails so there is no reason to lseek in. Actually this is a trivial fix
for a bad return value from open.
Corresponding to flashrom svn r462.
Signed-off-by: Bertrand Jacquin <beber@meleeweb.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
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Only access LPC ROM if we boot via LPC ROM. Only access SPI ROM if we
boot via SPI ROM.
The code to force enable SPI is commented out in case someone wants to
reenable it for a particular board with LPC and SPI flash.
Corresponding to flashrom svn r459.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r429 and coreboot v2 svn r4117.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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It needs to have opcodes initialized same way as ICH7.
Corresponding to flashrom svn r413 and coreboot v2 svn r3926.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
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Corresponding to flashrom svn r411 and coreboot v2 svn r3919.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
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Corresponding to flashrom svn r397 and coreboot v2 svn r3903.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
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Corresponding to flashrom svn r386 and coreboot v2 svn r3890.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
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Corresponding to flashrom svn r384 and coreboot v2 svn r3869.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>
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Corresponding to flashrom svn r372 and coreboot v2 svn r3849.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Corresponding to flashrom svn r371 and coreboot v2 svn r3848.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Corresponding to flashrom svn r368 and coreboot v2 svn r3830.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
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* add a generic preop-opcode-pair table.
* rename ich_check_opcodes to ich_init_opcodes.
* let ich_init_opcodes do not need to access flashchip structure:
. move the definition of struct preop_opcode_pair to a better place
. remove preop_opcode_pairs from 'struct flashchip'
. modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure
* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.
* fix a coding style mistake.
Corresponding to flashrom svn r367 and coreboot v2 svn r3814.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
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configuration is locked down
Corresponding to flashrom svn r364 and coreboot v2 svn r3805.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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This patch adds SB700 support to flashrom. The code for enabling the flash
rom is the same as for SB600. It was tested (read, write, verify) with an
ASUS M3A-H/HDMI which contains a Macronix MX25L8005.
Corresponding to flashrom svn r361 and coreboot v2 svn r3799.
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Acked-by: Peter Stuge <peter@stuge.se>
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Fixes #109
Corresponding to flashrom svn r355 and coreboot v2 svn r3790.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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This has been tested by Uwe Hermann on an RS690/SB600 board.
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Corresponding to flashrom svn r351 and coreboot v2 svn r3779.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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configuration weirdnesses
Corresponding to flashrom svn r338 and coreboot v2 svn r3723.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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Corresponding to flashrom svn r332 and coreboot v2 svn r3706.
Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Ed Swierk <eswierk@aristanetworks.com>
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Untested, but should work just as well as the other *PIIX* southbridges
according to the datasheets.
Corresponding to flashrom svn r330 and coreboot v2 svn r3696.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Tested on PIIX3 hardware.
Corresponding to flashrom svn r329 and coreboot v2 svn r3694.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
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Corresponding to flashrom svn r328 and coreboot v2 svn r3693.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r326 and coreboot v2 svn r3669.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info
about SiS620.
Corresponding to flashrom svn r325 and coreboot v2 svn r3668.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
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It is not possible to write enable that area once the register is set so
print a warning.
Corresponding to flashrom svn r324 and coreboot v2 svn r3659.
Signed-off-by: Marc Jones <marcj.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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