| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | sandybridge: provide monotonic timer function | Patrick Georgi | 2015-07-07 | 1 | -0/+20 |
| * | Revert "sandy/ivybridge: use LAPIC timer in SMM" | Patrick Georgi | 2015-07-06 | 1 | -0/+55 |
| * | sandy/ivybridge: use LAPIC timer in SMM | Stefan Reinauer | 2015-07-02 | 1 | -55/+0 |
| * | Remove address from GPLv2 headers | Patrick Georgi | 2015-05-21 | 1 | -1/+1 |
| * | Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c` | Paul Menzel | 2013-07-02 | 1 | -2/+2 |
| * | Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h` | Ronald G. Minnich | 2013-05-25 | 1 | -13/+0 |
| * | Intel Sandy Bridge: udelay.c: Change comparison from <= to < | Paul Menzel | 2013-05-23 | 1 | -1/+1 |
| * | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel | 2013-03-01 | 1 | -1/+1 |
| * | Sandybridge: Fix integer overrun in romstage udelay() | Stefan Reinauer | 2012-08-09 | 1 | -6/+16 |
| * | Add support for Intel Sandybridge CPU (northbridge part) | Stefan Reinauer | 2012-04-05 | 1 | -0/+58 |
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index : coreboot-staging | |
| Partial non-authoritative staging tree (partial copy of Raptor Engineering's internal coreboot staging tree) Don't use unless Gerrit is malfunctioning or down! https://www.raptorengineering.com | Raptor Engineering, LLC |
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