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BranchCommit messageAuthorAge
4.1x86: flatten hierarchyStefan Reinauer5 years
4.2Revert "device/pciexp_device: Tune PCIe bridges before scanning children"Kyösti Mälkki5 years
classic-2014.10i945: Consolidate FADT codeVladimir Serbinenko6 years
experimentalAdd the Rangeley FSP include & srx directoriesMartin Roth6 years
mastersoc/intel/fsp_baytrail: Make sure i2c bus is < 7Martin Roth5 years
 
TagDownloadAuthorAge
4.2coreboot-staging-4.2.zip  coreboot-staging-4.2.tar.gz  Patrick Georgi5 years
4.1coreboot-staging-4.1.zip  coreboot-staging-4.1.tar.gz  Patrick Georgi5 years
4.0coreboot-staging-4.0.zip  coreboot-staging-4.0.tar.gz  Patrick Georgi9 years
 
AgeCommit messageAuthorFilesLines
2015-07-13x86: flatten hierarchy4.14.1Stefan Reinauer48-94/+77
2015-07-13x86: Port x86 over to compile cleanly with x86-64Stefan Reinauer13-50/+243
2015-07-13version: allow stating the coreboot revision in .coreboot-versionPatrick Georgi2-1/+4
2015-07-13superio/smsc: Add support for SMSC DME1737Jonathan A. Kollasch6-114/+30
2015-07-13superio/smsc/dme1737: copy superio/smsc/lpc47b397Jonathan A. Kollasch4-0/+271
2015-07-13tegra124/tegra210: Include stages.h in bootblock.cStefan Reinauer2-0/+2
2015-07-13tegra210: Fix coding style in clock.cStefan Reinauer1-7/+7
2015-07-13coreinfo: Fix build output (cosmetical)Stefan Reinauer1-18/+18
2015-07-13smaug: Set LDO2 voltage to 1.8VFurquan Shaikh1-0/+7
2015-07-13t210: Apply A57 hardware issue workaround during cpu startupFurquan Shaikh2-8/+29
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