diff options
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c | 16 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c | 5 |
2 files changed, 20 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c index e4db032..678ddaa 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c @@ -65,10 +65,26 @@ FchInitEnvGpp ( { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; + UINT8 GppS3Data; + UINT8 PortId; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; + /* + * The romstage will force link, but re-read the GPP params from CMOS, + * otherwise the late init will powerdown all ports including + * those which were just taken out of S3 + */ + if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { + ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data); + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + if ( GppS3Data & (1 << (PortId + 4))) { + LocalCfgPtr->Gpp.PortCfg[PortId].PortDetected = TRUE; + } + } + } + if ( !LocalCfgPtr->Gpp.NewGppAlgorithm) { ProgramFchGppInitReset (&LocalCfgPtr->Gpp, StdHeader); FchStall (5000, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c index d4c9fe9..4c77358 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c @@ -281,6 +281,9 @@ FchInitLateGpp ( RwAlink (0x310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader); RwAlink (FCH_RCINDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader); } - RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data); + + if (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3) { + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data); + } } |
