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| author | Werner Zeh <werner.zeh@siemens.com> | 2015-02-10 10:16:12 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-05 12:45:10 +0100 |
| commit | b5a374d58befa96f718d0c2cee9afafb60867f18 (patch) | |
| tree | 6be19a296a2155b51933901d83cdd3d2025a6654 /src/soc/intel/fsp_baytrail/microcode/microcode_size.h | |
| parent | fb9d4caf160436a9f9b16f2103cf635da8460685 (diff) | |
| download | coreboot-staging-b5a374d58befa96f718d0c2cee9afafb60867f18.zip coreboot-staging-b5a374d58befa96f718d0c2cee9afafb60867f18.tar.gz | |
fsp_baytrail: Add new microcode for Bay Trail M
Add a new microcode for Bay Trail M D0 stepping used
in cpu N2807 silicon.
In addition, a selection of the used CPU type has
been added (I or M/D) which allows to use only the
really needed microcode for a given CPU type.
Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8399
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/microcode/microcode_size.h')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index ec55314..2af2201 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,6 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x30000 +#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + #define MICROCODE_REGION_LENGTH 0x30000 +#else + #define MICROCODE_REGION_LENGTH 0x10000 +#endif |
