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| author | Martin Roth <martin.roth@se-eng.com> | 2013-07-08 16:23:54 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-11 22:36:59 +0200 |
| commit | 4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c (patch) | |
| tree | 6bd8440a05f6ea1184c0a5500d43cc92ab683f01 /src/cpu/samsung/exynos5250/clk.h | |
| parent | 0cb07e3476d9408d0935253f9f26c0a8ddc28401 (diff) | |
| download | coreboot-staging-4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c.zip coreboot-staging-4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c.tar.gz | |
cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/samsung/exynos5250/clk.h')
| -rw-r--r-- | src/cpu/samsung/exynos5250/clk.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index ba8d960..565cf2b 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -72,7 +72,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral); #define MCT_HZ 24000000 /* - * Set mshci controller instances clock drivder + * Set mshci controller instances clock divider * * @param enum periph_id instance of the mshci controller * @@ -521,7 +521,7 @@ struct exynos5_mct_regs { }; #define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ -#define EPLL_SRC_CLOCK 24000000 /*24 MHz Cristal Input */ +#define EPLL_SRC_CLOCK 24000000 /*24 MHz Crystal Input */ #define TIMEOUT_EPLL_LOCK 1000 #define AUDIO_0_RATIO_MASK 0x0f |
