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* MFC: r312939, r313250, r314811 (partial), r314887 (partial), r315760,marius2017-05-118-55/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r315845, 315430, r317981, r315466 o Fix some overly long lines, whitespace and other bugs according to style(9) as well as spelling etc. in mmc(4), mmcsd(4) and sdhci(4). o In the mmc(4) bridges and sdhci(4) (bus) front-ends: - Remove redundant assignments of the default bus_generic_print_child device method, - use DEVMETHOD_END, - use NULL instead of 0 for pointers. o Trim/adjust includes. o Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges as kernel drivers and their dependency onto mmc(4). o Add support for eMMC "partitions". Besides the user data area, i. e. the default partition, eMMC v4.41 and later devices can additionally provide up to: 1 enhanced user data area partition 2 boot partitions 1 RPMB (Replay Protected Memory Block) partition 4 general purpose partitions (optionally with a enhanced or extended attribute) Besides simply subdividing eMMC devices, some Intel NUCs having UEFI code in the boot partitions etc., another use case for the partition support is the activation of pseudo-SLC mode, which manufacturers of eMMC chips typically associate with the enhanced user data area and/ or the enhanced attribute of general purpose partitions. CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation. o Now that properly issuing CMD6 is crucial (so data isn't written to the wrong partition for example), make a step into the direction of correctly handling the timeout for these commands in the MMC layer. Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as recommended by relevant specifications. o Add an IOCTL interface to mmcsd(4); this is sufficiently compatible with Linux so that the GNU mmc-utils can be ported to and used with FreeBSD (note that due to the remaining deficiencies outlined above SANITIZE operations issued by/with `mmc` currently most likely will fail). These latter have been added to ports as sysutils/mmc-utils. Among others, the `mmc` tool of mmc-utils allows for partitioning eMMC devices (tested working). o For devices following the eMMC specification v4.41 or later, year 0 is 2013 rather than 1997; so correct this for assembling the device ID string properly. o Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at least for some of the above a matching pair is required. o In the ACPI front-end of sdhci(4) describe the Intel eMMC and SDXC controllers as such in order to match the PCI one. Additionally, in the entry for the 80860F14 SDXC controller remove the eMMC-only SDHCI_QUIRK_INTEL_POWER_UP_RESET.
* MFC r310343-r310344gonzo2017-05-093-12/+22
| | | | | | | | | | | | | | | | | | | | | r310343: [iMX6] Fix build for SSI driver and add dependency for SDMA driver - Pass correct pointer to OF_getencprop - Check the size of "dmas" property - Add dependency on sdma driver Reviewed by: br Differential Revision: https://reviews.freebsd.org/D8873 r310344: [iMX6] Fix SDMA driver build - Place const modifiers where required - Make sure sdma device is attahched before consumers like SSI Reviewed by: br Differential Revision: https://reviews.freebsd.org/D8874
* MFC r310791:gonzo2017-05-081-0/+11
| | | | | | | | | | [qemu] Fix VERSATILEPB kernel boot in QEMU broken by r300968 QEMU does not implement hardware debug registers so when dbg_monitor_is_enabled is called kernel receives "invalid instruction" exception. QEMU implements only DIDR register and on read returns all zeroes to indicate that it doesn't support other registers. Real hardware has Version bits set.
* MFC r308424, r310636gonzo2017-05-081-211/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r308424: Fix locking in bcm2835_audio driver - Move all VCHI activity to worker thread: channel methods are called with non-sleepable lock held and VCHI uses sleepable lock. - In worker thread use sx(9) lock instead of mutex(9) for the same reason. PR: 213801, 205979 r310636: [rpi] Fix bcm2835_audio locking and samples starvation Rework general approach to locking and working with audio worker thread: - Use flags to signal requested worker action - Fix submitted buffer calculations to avoid samples starvation - Protect buffer pointers with locks to fix race condition between callback and audio worker thread - Remove unnecessary vchi_service_use - Do not use lock to serialize VCHI requests since only one thread issues them now - Fix unloading signaling per hselasky@ suggestion - Add output to detect inconsistent callback data caused by possible firmware bug https://github.com/raspberrypi/firmware/issues/696 - Add stats/debug sysctls to troubleshoot possible bugs PR: 213687, 205979, 215194
* MFC r308569,r308570:skra2017-04-201-15/+9
| | | | | | | | | | | | | r308569: Always call PHYS_TO_VM_PAGE() in is_managed(). Fast road for addresses under first_page cannot be taken as this variable is connected only to vm_page_array segment. There could be more segments in system like the ones for various fictitious page ranges. These can be situated under vm_page_array segment and so, they could be skipped before this fix. However, as far as I know, there is no report associated with it. r308570: The return type of is_managed() was changed from boolean_t to bool type in r308569. Now, propagate this change further for consistency sake.
* MFC r309538:mmel2017-04-163-18/+89
| | | | | | | | | Fixes for NVIDIA Tegra124 clocks: - EMC clock have standard peripheral clock block. Use it. - Implement full frequency set method for PLLD2. This PLL is used as HDMI pixel clock so we must be able to set it to wide range of frequencies, within 5% tolerance allowed by HDMI specification. Due to this, full state space search (over m, n, p fields) is necessary.
* MFC r308286,r308287:mmel2017-04-165-124/+471
| | | | | | | | | r308286: TEGRA: Add basic driver for memory controller. For now, it only reports memory and SMMU access errors. r308287: TEGRA: Fix numerous issues in clock code. Define and export clocks related to XUSB driver.
* MFC r306442,r306444,r306445,r306550:mmel2017-04-164-3/+3
| | | | | | | | | | | | | r306442: TEGRA: Add support for MULTIDELAY option. r306444: TEGRA: Don't include files already included by system or arch configs. r306445: TEGRA: Return back kern_clocksource.c into tegra config file. It was removed in r306444 by mistake. r306550: TEGRA: Extend timeout for PLLs lock to 5 ms. Real lock time for PLLA has been very near to old limit.
* MFC r315900,r315973,r315974:mmel2017-04-169-220/+218
| | | | | | | | | | | | | | | r315900: Cleanup structures related to VFP and/or mcontext_t. - in mcontext_t, rename newer used 'union __vfp' to equaly sized 'mc_spare'. Space allocated by 'union __vfp' is too small and cannot hold full VFP context. - move structures defined in fp.h to more appropriate headers. - remove all unused VFP structures. r315973: Save VFP state on fork(). Update the copy of VFP state in PCB before it is cloned for new process. r315974: Preserve VFP state across signal delivery.
* MFC r303261,r315059:mmel2017-04-166-882/+1007
| | | | | | | | r303261: Add more UEFI/e820 memory types from latest specifications. r315059: Split overbloated machep.c to multiple files and do basic cleanup of these fragments.
* MFC r306704,r308406:mmel2017-04-163-15/+6
| | | | | | | r306704: ARM: Remove next bunch of unused cpu_functions from ARMv6. r308406: Only include sys/boot.h if LINUX_BOOT_ABI is defined
* MFC r306631,r306640,r306641,r306650,r306656:mmel2017-04-164-119/+44
| | | | | | | | | | | | | | | | | | r306631: Use C99 designated initializers to create the armv6 cpu_functions structs. This will help with a later cleanup of what functions we implement. r306640: Only define the CF_* macros on ARMv4/v5. They are unused on armv6. r306641: Remove the parts of cpu_functions from armv6 that are unused on that architecture. r306650: Add the Cortex-A{53,57,72} ID register values. These can all run 32-bit code so could run a 32-bit kernel. r306656: Use the cortex functions when booting on one of the Cortex-A ARMv8 CPUs. This list is incomplete, however we don't have the ID values for the missing Cortex-A32 or A35.
* Improvements for the brand detection and prioritization.kib2017-04-061-0/+1
| | | | | | | | | | | | | | | | | | | MFC r315701 (by ed): Set the interpreter path to /nonexistent. MFC r315749: Adjust r314851 to not require every brand to specify interpreter path. MFC r315753: Add a flag BI_BRAND_ONLY_STATIC to specify that the brand only matches static binaries. MFC r315754: Update r315753 with the proper flag name. MFC r316211: A followup to r315749, two more places where brand->interp_path was accessed unconditionally.
* Bring kernel space CloudABI code in sync with HEAD.ed2017-04-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MFC r312353, r312354 and r312355: Sync in the latest CloudABI generated source files. Languages like C++17 and Go provide direct support for slice types: pointer/length pairs. The CloudABI generator now has more complete for this, meaning that for the C binding, pointer/length pairs now use an automatic naming scheme of ${name} and ${name}_len. Apart from this change and some reformatting, the ABI definitions are identical. Binary compatibility is preserved entirely. MFC r315700: Make file descriptor passing work for CloudABI's sendmsg(). Reduce the potential amount of code duplication between cloudabi32 and cloudabi64 by creating a cloudabi_sock_recv() utility function. The cloudabi32 and cloudabi64 modules will then only contain code to convert the iovecs to the native pointer size. In cloudabi_sock_recv(), we can now construct an SCM_RIGHTS cmsghdr in an mbuf and pass that on to kern_sendit(). MFC r315736: Make file descriptor passing for CloudABI's recvmsg() work. Similar to the change for sendmsg(), create a pointer size independent implementation of recvmsg() and let cloudabi32 and cloudabi64 call into it. In case userspace requests one or more file descriptors, call kern_recvit() in such a way that we get the control message headers in an mbuf. Iterate over all of the headers and copy the file descriptors to userspace.
* MFC r315861:ed2017-04-061-1/+0
| | | | | | Stop providing the compat_3_brand. As of r315860, the ELF image activator works fine for CloudABI without it.
* MFC r312932,r312933,r312949,r313141mjg2017-03-232-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | (by cognet) Use strexeq instead of needlessly branch. == (by cognet) Remove useless labels. == (by cognet) Correct the IT instruction in atomic_fcmpset_64(). == (by andrew) Only define atomic_fcmpset_long in the kernel. We may include machine/atomic.h in userspace, however atomic_fcmpset_32 is unimplemented there.
* MFC r311169,r311898,r312925,r312973,r312975,r313007,r313040,r313080,mjg2017-03-163-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r313254,r313341 amd64: add atomic_fcmpset == sparc64: add atomic_fcmpset == Implement atomic_fcmpset_* for arm and arm64. == Add atomic_fcmpset_*() inlines for powerpc Summary: atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the read value from the target memory location into the 'old' pointer in the case of failure. == i386: add atomic_fcmpset == Don't retry a lost reservation in atomic_fcmpset() The desired behavior of atomic_fcmpset_() is to always exit on error. Instead of retrying on lost reservation, leave the retry to the caller, and return == Add atomic_fcmpset_*() inlines for MIPS atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the read value from the target memory location into the 'old' pointer. == i386: fixup fcmpset An incorrect output specifier was used which worked with clang by accident, but breaks with the in-tree gcc version. While here plug a whitespace nit. == Implement atomic_fcmpset_*() for RISC-V. == Use 64bit store instruction in atomic_fcmpset_64.
* MFC r310189:ian2017-03-161-1/+1
| | | | | Fix sscanf() format string to match an argument. This also fixes kernel build after r310171.
* MFC r312679:ian2017-03-021-0/+7
| | | | | | | Handle imx6 erratum ERR004346... to reboot, clear the SRS bit twice within the same cycle of the 32khz clock. I've never actually noticed this error happening, but it's an easy fix.
* MFC r312292, r313573:ian2017-03-0212-207/+27
| | | | | | | | | | | | | | | Stop including sys/types.h from arm's machine/atomic.h, fix the places where atomic.h was being included without ensuring that types.h (via param.h) was included first, as required by atomic(9). Remove arm's cpuconf.h, and references to it, after moving a few lines from it into pmap-v4.h where they are used. Other than those few lines of support for different MMU types, nothing in cpuconf.h has been used in our code for quite a while. The file existed to set up a variety of symbols to describe the architecture. Over the past few years we have converted all of our source to use the new architecture symbols standardized by ARM Inc, and predefined by both clang and gcc.
* MFC r312251:ian2017-03-011-4/+0
| | | | | Remove a bit of armv6 support that didn't get deleted when this file was split from trap.c into trap-v4.c and trap-v6.c.
* MFC r306901:ian2017-03-014-196/+416
| | | | | | ARM: Split identify_arm_cpu() into ARMv4 and ARMv6 variant. On ARMv6, be more verbose about supported CPU features and/or optional instructions.
* MFC r302506:ian2017-03-0119-22/+2
| | | | Remove HZ=<various> from all armv6 configs, put HZ=1000 in std.armv6.
* MFC r313917:ian2017-03-011-1/+1
| | | | | Change the naming of imx{5,6} gpio pins to exactly match the names used in the reference manual.
* MFC r314064, r314060:ian2017-03-011-1/+0
| | | | | | | | Fix typos in bootverbose printfs... display the write-protect pin info, not the card-detect pin info. Remove a variable that has been unused since r311735 (it should have been removed as part of those changes).
* MFC r313674:ian2017-03-011-0/+4
| | | | Enable usb low and full speed devices connected to the imx6 root hubs.
* MFC r312859:ian2017-03-012-1/+9
| | | | | | | | | | | | | | | | Configure the timer capture pin to input mode in the timer control register, in addition to configuring it as input with the pinmux driver. There was a control register bit commented as "no desc in datasheet". A later revision of the manual reveals the bit to be an input/output control for the timer pin. In addition to configuring capture or pulse mode, you apparently have to separately configure the pin direction in the timer control register. Before this change, the timer block was apparently driving a signal onto a pad configured by pinmux as input. Capture mode still accidentally worked for me during testing because I was using a very strong signal source that just out-muscled the weaker drive from the misconfigured pin.
* MFC r308186, r308188, r308231, r308232:ian2017-03-013-919/+2
| | | | | | | | | | | | | | | | | | Move imx_sdhci driver over to a dev/sdhci in preparation for QorIQ support. Freescale uses eSDHC in both i.MX (ARM) and QorIQ (PowerPC), with slight differences. This is part one in unifying the drivers. Merge i.MX and PowerPC SDHCI drivers Summary: i.MX5 and PowerPC use a very similar eSDHC controller, which is also similar to the uSDHC controller used by i.MX6. The imx_sdhci driver works almost completely with PowerPC, with some minor tweaks. Fix the build. protctl is only used on powerpc. While here, remove the need to check the SVR SPR, as others may be compatible with the p1022-esdhc type. Since it's no longer accessing a powerpc-specific register, drop the #ifdef.
* MFC r311734, r311735, r311951, r314071:ian2017-03-011-26/+32
| | | | | | | | | | | | | | Add new helper routines for sdhci bridge drivers that use gpio pins for card presence and write protect switch detection. Use the new sdhci_fdt_gpio helper functions to add full support for FDT gpio pins for detecting card insert/remove and write protect for ti_sdhci. Include sys/systm.h for use of bootverbose. Revert to ti_sdhci driver's historic behavior: assume an sd card is writable if the fdt data doesn't provide a gpio pin for reading the write protect switch and also doesn't contain a "wp-disable" property.
* MFC r306262, r306267, r310021: (needed to avoid conflicts on later merges)ian2017-03-0151-354/+39
| | | | | | | | | | Remove bus_dma_get_range and bus_dma_get_range_nb on armv6. We only need this on a few earlier arm SoCs. Restrict where we need to define fdt_fixup_table to just PowerPC and Marvell. Add the missing void to function signatures in much of the arm code.
* MFC r308640:ian2017-03-0123-125/+103
| | | | | Use the correct OF_getencprop over OF_getprop + fdt32_to_cpu to read integer data from the device tree.
* MFC r313933, r313939, r313966:kib2017-02-261-3/+2
| | | | | Microoptimize pmap_protect_pde() on amd64, i386 and pmap_protect_pte1() on armv6.
* MFC r313345:kib2017-02-201-13/+5
| | | | | | | Update arm and arm64 counters MD bits. MFC r313394 (by manu): subr_sfbus.c need sys/proc.h for struct thread definition.
* MFC r312610, r312792jah2017-02-152-131/+158
| | | | | | | | | | | | | | | | | | | | | | | r312610: Like r310481 for i386, move the objects used to create temporary mappings for armv6 pmap zero and copy operations to the MD PCPU region. Change sysmap initialization to only allocate KVA pages for CPUs that are actually present. While here, collapse CMAP3 into CMAP2 (their use was mutually exclusive anyway) and "recover" some space in PCPU padding that has always been available due to 64-byte cacheline padding. r312792: Further cleanup of per-CPU armv6 pmap data: - Replace pcpu_find(curcpu) with get_pcpu(), which is much more direct. - Remove armv4 pcpu fields which I added in r286296 but never needed to use. - armv6 pc_qmap_addr was leftover from the old armv6 pmap implementation. Rename it and put it to use in the new one.
* MFC r313194:kib2017-02-111-2/+0
| | | | Define the vm_ooffset_t and vm_pindex_t types as machine-independend.
* MFC r312604 and r312605:loos2017-01-252-97/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the handling of small packets padding in cpsw: - Pad small packets to 60 bytes and not 64 (exclude the CRC bytes); - Pad the packet using m_append(9), if the packet has enough space for padding, which is usually true, it will not be necessary append a newly allocated mbuf to the chain. Suggested by: yongari MFC r312608: Handle the rx queue stall while reading the packets from NIC (when the descriptor state will not change anymore). This seems to eliminate the race where we can miss a stalled queue under high load. While here remove the unnecessary curly brackets. Reported by: Konstantin Kormashev <konstantin@netgate.com> MFC r312636: Properly assemble an mbuf chain out of received fragments. Remove the rx_batch hack, it makes no difference now that most of bugs have been sorted out. MFC r312637: Be a little more pedantic here, the TRM says the hardware is supposed to only clean the OWNER bit on SOP descriptors. Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC r312411:loos2017-01-252-5/+23
| | | | | | | | | | | Handle the set capabilities ioctl, letting the hardware checksum be disabled (Hi netmap!). Only remove the CRC bytes from packets when the hardware tell us to do so. Fixes the 'discard frame w/o leading ethernet header' issues. Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC r312408:loos2017-01-251-9/+8
| | | | | | The port number and the to_port_en flag are valid only on SOP descriptor. Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC 307332,312086: Drop support for using mmap() with /dev/kmem.jhb2017-01-181-5/+4
| | | | | | | | | | | | | | | | | | | 307332: Drop support for using mmap() with /dev/kmem. Using the device pager with /dev/kmem is not stable since KVA mappings are transient, but the device pager caches the PA associated with a given offset forever. Interestingly, mips' implementation of memmap() already refused requests for /dev/kmem. Note that kvm_read/kvm_write do not use mmap, but use read and write on /dev/kmem, so this should not affect libkvm users. 312086: Trim a few comments on platforms that did not implement mmap of /dev/kmem. After r307332, no platforms implement mmap for /dev/kmem, so the lack of it for these platforms is no longer unique.
* MFC r309999, r310012gonzo2017-01-062-1/+2
| | | | | | | | | | | | | | | r309999: [iMX6] Fix platform compatibility string for i.MX6 Dual i.MX6 Dual boot was broken since r308533 because ofw_bus_node_is_compatible is more strict than fdt_is_compatible and does not accept partial matches r310012: [iMX6] Add compatibility string for GPT timer on i.MX6 Dual Up until r295436 GPT timer in i.MX6 Dual dts used the same compatiblity string as i.MX6 Quad. After the sync up with Linux in r295436, GPT timer stopped getting attached on the i.MX6 Dual
* Fixes the sensor initialization, always reset the digital outputs on start.loos2017-01-041-4/+7
| | | | | Obtained from: pfSense Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC r309345:loos2016-12-312-6/+3
| | | | | | | | | | | | | | | | | | | The RX_FREEBUFFER registers are a write to increment field. Writing the full queue size to it every time was makeing it overflow with a lot of bogus values. This fixes the interrupt storms on irq 40. MFC r309347: MDIO_PHYACCESS_ACK is only valid for read access, remove it from miibus_writereg. Reduce the DELAY() between reads while waiting for MII access. Spotted by: yongari Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC r309113:loos2016-12-313-4/+316
| | | | | | | | | | | Add the etherswitch(4) support for TI CPSW. Adds VLAN and port management abilities for etherswitchcfg(8). The code is conditionally enabled for now, because it is not necessary on single ethernet use cases. Obtained from: pfSense Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC r308692:loos2016-12-301-5/+8
| | | | | | Fix ti_gpio_detach() to avoid crashing if something goes wrong. Sponsored by: Rubicon Communication, LLC (Netgate)
* MFC r306717:loos2016-12-303-155/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if_cpsw overhaul: - Fix RX and TX teardown: . TX teardown would not reclaim the abandoned descriptors; . Interrupt storms in RX teardown; . Fixed the acknowledge of the teardown completion interrupt. - Remove temporary lists for the descriptors; - Simplified the descriptor handling (less writes and reads from descriptors where possible); - Better debug; - Add support for the RX threshold interrupts: With interrupt moderation only, an RX overrun is likely to happen. The RX threshold is set to trigger a non paced interrupt everytime your RX free buffers are under the minimum threshold, helping to prevent the rx overrun. The NIC now survive when pushed over its limits (where previously it would lock up in a few seconds). uFW (600MHz SoC) can now forward up to 560Mb/s of UDP traffic (netmap pkt-gen as source and sink). TCP forwarding rate is over 350Mb/s. No difference (other than CPU use) was seen on Beaglebone black (1GHz SoC) for his fast ethernet. Tested on: uFW, BBB Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC r306654:loos2016-12-301-16/+32
| | | | | | | | | | Enable the TX completion interrupt for the cpsw NIC to assure the free tx descriptors are reclaimed as soon as possible. Without this the free buffers are reclaimed only on watchdog runs or after trying to enqueue more packets. Sponsored by: Rubicon Communications, LLC (Netgte)
* MFC of r306388, r306510, r306511 and r306513:loos2016-12-301-68/+32
| | | | | | | | | | | | | | Fix a typo. Sort and remove unnecessary includes. Fix a typo in CPSW_DEBUG MACRO and then replace all the CPSWP_DEBUG() calls with CPSW_DEBUG(). Remove the GLOBAL queue lock which just adds unnecessary complexity to code (when used together with the individual tx and rx locks). Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC r306376:loos2016-12-303-0/+73
| | | | | | | | | | | Add a sysctl to control the interrupt pacing on AM335x integrated switch. The hardware can be set to limit the number of interrupts from 2 to 63 interrupts per ms. To keep the compatibility with the TI documentation the sysctl take the interval between the interrupts pulses: 16~500 us. Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC of r305114, r305115 and r305149:loos2016-12-304-1/+182
| | | | | | | | | | | | | | | | Allow the use of control module extensions to cope with specific platform features. Add a driver for the AM335x bandgap sensor, an on-die temperature sensor as part of the AM335x control module extension. TI says that the bandgap sensor is not very accurate on AM335x, but in our tests it seems to be a good reference for the SoC temperature. TI details: http://processors.wiki.ti.com/index.php/AM335x_Thermal_Considerations#Measuring_Case_Temperature Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC of r305112, r305113, r305119, r305141 and r305432:loos2016-12-303-8/+13
| | | | | | | | | Replace magic numbers with the proper register names. Fix the build, revert r305119, move the control module register data to am335x_scm.h and fix if_cpsw.c to include the correct header. Sponsored by: Rubicon Communications, LLC (Netgate)
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