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* Revert "Revert "MFC r319873:""Luiz Souza2018-02-232-7/+12
| | | | This reverts commit 4c9907d21517c211b27a3cf5b7a2a976623820cc.
* Revert "MFC r319873:"Luiz Souza2018-02-212-12/+7
| | | | This reverts commit 5dad0dd804a33b8a372d49fa342b24c67b1c2fb3.
* MFC r319873:kib2018-02-192-7/+12
| | | | | | | Move struct syscall_args syscall arguments parameters container into struct thread. (cherry picked from commit 985b26c6741218c134a15526fd32b736bd73fa8a)
* Add support to IF_ALLMULTI which enable the reception of all the multicast ↵Luiz Souza2017-11-162-9/+13
| | | | | | | | frames in a interface. Ticket #7710 (cherry picked from commit d292b5ce7adecee7f57cee347735bc336ec225ee)
* Add options IPSEC_SUPPORT to pfSense ARM kernel config.Luiz Souza2017-11-031-1/+3
| | | | (cherry picked from commit f0f1a6be4b54350ffc82b68d5f62afb46801ce70)
* Use the single byte FIFO, the correct implementation of the two bytes FIFO ↵Luiz Souza2017-10-201-69/+32
| | | | | | in FreeBSD would require more work (command and data buffers had both to be aligned). (cherry picked from commit 3dd92b2120658589d5b8c1f38012189e748b1ce9)
* White space fixes.Luiz Souza2017-10-191-4/+4
| | | | (cherry picked from commit 7caa01716bd9aac311a92814158ef328fcd40676)
* Revert "Disable the SPI driver in pfSense for now."Luiz Souza2017-10-191-4/+0
| | | | This reverts commit 8022527ae5f593071041bc01d5dbd242af4711fb.
* Disable the SPI driver in pfSense for now.Luiz Souza2017-10-191-0/+4
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* Disable the two bytes FIFO after the transfer to keep the controller in a ↵Luiz Souza2017-10-191-0/+3
| | | | | | consistent state for the next boot. (cherry picked from commit bd6ea3220b0fc802a963ef22e362238a9969457a)
* Speed up the SPI driver.Luiz Souza2017-10-181-1/+1
| | | | (cherry picked from commit 4f1e4b82cbc3dc3722e3c85eca3cdb87397b5227)
* Enable the two bytes FIFO when possible.Luiz Souza2017-10-181-29/+75
| | | | | | Change to polling mode as the interrupt mode generates too many interrupts even using two bytes at time. (cherry picked from commit c0a2357e7ddfb919847cc341ea56f3b9b9783664)
* ofw_spi: Parse property for the SPI mode and CS polarity.manu2017-10-176-0/+14
| | | | | | | | | | | As cs is stored in a uint32_t, use the last bit to store the active high flag as it's unlikely that we will have that much CS. Reviewed by: loos MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D8614 (cherry picked from commit f5f9058ccaec11fccc18817f45fff8859798a317)
* Enable the SPI driver and the SPI flash on ARMADA38X kernel.Luiz Souza2017-10-181-0/+5
| | | | (cherry picked from commit a3d4f012dd055711ac32b2722a09e8a7baf371a5)
* Add the SPI driver for the Marvell Armada 38x/Orion.Luiz Souza2017-10-182-0/+340
| | | | (cherry picked from commit 26b8b1dd71d1229bcd6f61ab1ae7f048fcf79675)
* Add the ARMADA38X-netboot kernel config that is going be used in factory ↵Luiz Souza2017-10-072-1/+34
| | | | | | installer images. (cherry picked from commit 631c9e43aaccc5c33a96996bbe56ffb069293aa2)
* Only print the spurious interrupts messages with bootverbose enabled.Luiz Otavio O Souza2017-10-041-4/+6
| | | | | | It cannot be fixed, produces no useful output and is harmless with the actual code. (cherry picked from commit f1e039d0090c45ff05a5127847e38d285cb57279)
* Enable ARM_L2_PREFETCH in ARMADA38X configMichal Mazur2017-09-181-1/+1
| | | | (cherry picked from commit d5a510a6f31efe0d5ad82af0c883b91462811d67)
* Add L2 prefetch to ARMADA38X. Disable by defaultZbigniew Bodek2017-09-181-1/+2
| | | | | | | Keep in mind that this can be used only when pl310 device is included. Disable this option by default to align with Marvell Linux. (cherry picked from commit 6442e10a95086180eb6ef45683c20cdb6665e70d)
* Enable L1 and L2 prefetch when possible for Cortex processorsZbigniew Bodek2017-09-181-0/+18
| | | | | | | | | | Enable Dcache prefetching for both cache levels if possible. Introduce new kernel option ARM_L2_PREFETCH to be used along with the supported L2 cache controller. This option should be enabled only if the slave cache controller connected to the Cortex AXI master port supports it (such as PL310). (cherry picked from commit 7ad029753b2b3af6b3c87cc5d6912d04efb3fe03)
* Rename the Rogue-1 kernel configuration file.Luiz Souza2017-09-151-1/+1
| | | | (cherry picked from commit 625c12c360bd9e2df2480cfb2d4befdb03945e54)
* Fix a broken merge on ARMADA kernel config.Luiz Souza2017-09-071-25/+0
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* Add a missing header.Luiz Souza2017-09-061-0/+1
| | | | (cherry picked from commit 9f2c71f9b8e1a514c395897c0ada18fbc9070690)
* Add ALTQ support to cpsw.Luiz Otavio O Souza2017-09-061-1/+1
| | | | | | Ticket #7199 (cherry picked from commit b95dbdb097fd2d5b148098bcc68e1f57b7dab544)
* Add 'device mii' as it is necessary to build the mvneta driver.Luiz Souza2017-09-061-0/+1
| | | | (cherry picked from commit e1f1e559fd5af92264e03561e17b065101d5567d)
* Fix a typo.Luiz Souza2017-09-061-1/+1
| | | | (cherry picked from commit c47d004ff6bd6618cfacd1a0f97fb20442a069c0)
* Do no reuse sysctl OIDs.Luiz Souza2017-09-062-2/+2
| | | | (cherry picked from commit 42e25c991c02726cfca043536568db688293238e)
* Declare the variable...Luiz Souza2017-09-061-0/+6
| | | | (cherry picked from commit 705c04fa47bebf390a54726190ed17957113e756)
* Remove duplicate and unnecessary options from ARM kernels.Luiz Souza2017-09-062-3/+0
| | | | (cherry picked from commit d71ccd7655d7c5447814d1a76011d45759d9b3d1)
* Enable the LED drivers on rogue-1.Luiz Souza2017-09-062-1/+6
| | | | (cherry picked from commit 93d0dfb01dd19bb4998f5f7ed1373bd85dc11b1c)
* The base pfSense kernel should not include any other file, remove the uFW ↵Luiz Souza2017-09-061-2/+1
| | | | | | include. (cherry picked from commit 13d2f38e535c68096f48f318e971f3288b4e8992)
* Include a pfSense for the ClearFog.Luiz Souza2017-09-065-290/+228
| | | | (cherry picked from commit 839fcfcd847014b820769963d1518dd0a93fde18)
* Disable the unused kernel MD_ROOT option.Luiz Souza2017-09-061-1/+1
| | | | (cherry picked from commit 26a836083492e0e9af222d17bd479f1292e71f54)
* Remove deprecated option DEVICE_POLLING from pfSense kernel.Luiz Otavio O Souza2017-09-061-2/+0
| | | | | | Ticket #7021 (cherry picked from commit 29f1eecf8c4325a772f69849331ce0f0114f5587)
* Add wireless modules to ARM kernel.Luiz Otavio O Souza2017-09-062-5/+72
| | | | | | Ticket #176/ARM (cherry picked from commit 2e470aef1ede67776cad5934e4a74413afd00a39)
* Enable the etherswitch driver on uFW kernel.Luiz Otavio O Souza2017-09-061-0/+3
| | | | (cherry picked from commit 52b18e60f7c89b873be3f0f4f8844ebb054a06ff)
* Break the kernel in three files to avoid the conflict of ROOTDEVNAME.Luiz Otavio O Souza2017-09-063-87/+111
| | | | (cherry picked from commit 8fb831d1d2b3a83483acddefb99a55df0b1c38d1)
* Increase number of L2 tables required for kernel bootstrapzbb2017-09-061-2/+3
| | | | | | | | | | | | | | | | | | | | Memory space reserved for pmap_kernel_l2dtable_kva and pmap_kernel_l2ptp_kva has not been taken into account in original code. All the memory reserved from kernel space by pmap_alloc_specials() function called in pmap_bootstrap() should be mapped initially by initarm(). To create initial mapping initarm() function reserves proper number of l2 page tables. However the number of the l2 page tables does not take into account memory for: pmap_kernel_l2ptp_kva, pmap_kernel_l2dtable_kva, crashdumpmap, etc. Submitted by: Grzegorz Bernacki <gjb@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: meloun-miracle-cz Differential revision: https://reviews.freebsd.org/D10217 (cherry picked from commit 2f72ed7d5a00369d3e7f83466fca58ff94b1c3a4)
* Fix building for ARM kernel that have FLASHADDR, PHYSADDR and LOADERRAMADDR ↵manu2017-09-061-1/+1
| | | | | | | | | | defined. Pointy Hat: myself Reported by: bz (cherry picked from commit 88b4a48518f9e0ebff21d16d2b163aa092b548da)
* Keep boot parameters in ARM trampoline codemanu2017-09-061-4/+31
| | | | | | | | | | | | | Currently boot parameters (r0 - r3) are forgotten in ARM trampoline code. This patch save them at startup and restore them before jumping into kernel _start() routine. This is usefull when booting with Linux ABI and/or custom bootloader. Submitted by: Grégory Soutadé <soutade@gmail.com> Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D7395 (cherry picked from commit 5292986b0f168ac2b020244298b5801430a851df)
* Fix TEX index acquisition using L2 attributeszbb2017-09-062-3/+9
| | | | | | | | | | The TEX index is selected using (TEX0 C B) bits from the L2 descriptor. Use correct index by masking and shifting those bits accordingly. Differential Revision: https://reviews.freebsd.org/D11703 (cherry picked from commit 90fde46fef4df1269c1855372f80834ea8e50143)
* [arm] Use correct index value when checking range validitygonzo2017-09-061-2/+2
| | | | | | | | Reviewed by: andrew MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D9145 (cherry picked from commit fd5dc900256d4f0edb75e5334e7e648cb613779d)
* Enable setting the dma tag at the nexus levelzbb2017-09-062-0/+61
| | | | | | | | | | | | | | Allow to set the dma tag for nexus in the platform init code, so that all busses and devices would be able to inherit it. This change is useful e.g. for setting coherent dma tag for the platforms with hardware IO cache coherency. Submitted by: ian Michal Mazur <mkm@semihalf.com> Reviewed by: ian Differential revision: https://reviews.freebsd.org/D11202 (cherry picked from commit 0b32b9947ce18e8f69828c42aa5a9ba8cc027857)
* Introduce support for DMA coherent ARM platformszbb2017-09-061-13/+27
| | | | | | | | | | | | | | | | - Inherit BUS_DMA_COHERENT flag from parent buses - Use cacheable memory attributes on dma coherent platform - Disable cache synchronization on coherent platform Changes are based on ARMv8 busdma code and commit r299683. Submitted by: Michal Mazur <mkm@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: ian Differential revision: https://reviews.freebsd.org/D11201 (cherry picked from commit dbbf5a80043fca8abfaa7ea9e855a468d0c44e88)
* Disable PL310 outer cache sync for IO coherent platformszbb2017-09-062-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe or Crypto controllers and the Cortex-A9. To avoid this, this commit introduces a new Device Tree property 'arm,io-coherent' for the L2 cache controller node, valid only for the PL310 cache. It identifies the usage of the PL310 cache in an I/O coherent configuration. Internally, it makes the driver disable the outer cache sync operation. Note, that other outer-cache operations are not removed, as they may be needed for certain situations, such as booting secondary CPUs. Moreover, in order to enable IO coherent operation, the decision whether to use L2 cache maintenance callbacks is done in busdma layer, which was enabled in one of the previous commits. Submitted by: Michal Mazur <mkm@semihalf.com> Marcin Wojtas <mw@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Differential revision: https://reviews.freebsd.org/D11245 (cherry picked from commit d4d94445f1fd0de66e64fd589865b027eab17726)
* Manually load tunable CPU quirks.mmel2017-09-061-0/+9
| | | | | | | | | | | These are needed too early, far before SYSINIT is processed. Reported by: zbb Pointy hat to: mmel MFC after: 3 weeks MFC with: r319896 (cherry picked from commit d425ca179a9613f12f17d5f283bac1eb5b85abe5)
* Revert change to description introduced in r320002zbb2017-09-061-1/+1
| | | | | | | | | | | Currently some ARM platforms implement their own platform_probe_and_attach() function and other use common routine that calls platform's PLATFORM_ATTACH method. Keep the old description to match the preferred way of naming things. Pointed out by: andrew (cherry picked from commit f914f0a2493da296ffd18fba31afc1f58b99b17b)
* Minor style improvements to pmap_remap_vm_attr()zbb2017-09-061-3/+3
| | | | | | | Use correct platform_ function name in the comment and remove redundant tabs. (cherry picked from commit 42b0dad3ee3dc59d7fcbd3b2d709cd2ba6f424da)
* Fix typo in "Marvell" stringzbb2017-09-061-2/+2
| | | | | | | | Change Marwell to Marvell Pointed out by: Ravi Pokala <rpokala@mac.com> (cherry picked from commit e23bb21bd5292f970933c1e4cad5fcb0b5d91e35)
* Add detection of CPU class for ARMv6/v7zbb2017-09-061-17/+36
| | | | | | | | | | Submitted by: Michal Mazur <mkm@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: andrew Differential revision: https://reviews.freebsd.org/D10909 (cherry picked from commit e843e48d3646bd18f8480005464fe31a71692d13)
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