diff options
author | kato <kato@FreeBSD.org> | 1997-04-26 04:08:54 +0000 |
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committer | kato <kato@FreeBSD.org> | 1997-04-26 04:08:54 +0000 |
commit | 80b96ecb2f86cc9a64bc39f7b7afb0f052645aef (patch) | |
tree | 6dd9c9d0adf8d3c5b4e4f8025a9749ab782b0f8b /sys/amd64/amd64/initcpu.c | |
parent | fae9d8a74aa4d7dbf71b61651e97cf8fdae19fd1 (diff) | |
download | FreeBSD-src-80b96ecb2f86cc9a64bc39f7b7afb0f052645aef.zip FreeBSD-src-80b96ecb2f86cc9a64bc39f7b7afb0f052645aef.tar.gz |
Add new cpu type, CPU_CY486DX, which shows Cyrix 486S/DX series CPUs,
and initialization routine for those CPUs.
Tested by: Bob Bishop <rb@gid.co.uk>
Diffstat (limited to 'sys/amd64/amd64/initcpu.c')
-rw-r--r-- | sys/amd64/amd64/initcpu.c | 34 |
1 files changed, 30 insertions, 4 deletions
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index e9ee947..0728dad 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -26,7 +26,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: initcpu.c,v 1.2 1997/03/24 07:23:05 kato Exp $ + * $Id: initcpu.c,v 1.3 1997/04/19 05:25:19 kato Exp $ */ #include "opt_cpu.h" @@ -45,6 +45,7 @@ void initializecpu(void); static void init_5x86(void); static void init_bluelightning(void); static void init_486dlc(void); +static void init_cy486dx(void); #ifdef CPU_I486_ON_386 static void init_i486_on_386(void); #endif @@ -90,7 +91,7 @@ init_bluelightning(void) } /* - * Cyrix 486 series + * Cyrix 486SLC/DLC/SR/DR series */ static void init_486dlc(void) @@ -133,6 +134,28 @@ init_486dlc(void) /* + * Cyrix 486S/DX series + */ +static void +init_cy486dx(void) +{ + u_long eflags; + u_char ccr2; + + eflags = read_eflags(); + disable_intr(); + invd(); + + ccr2 = read_cyrix_reg(CCR2); +#ifdef SUSP_HLT + ccr2 |= CCR2_SUSP_HTL; +#endif + write_cyrix_reg(CCR2, ccr2); + write_eflags(eflags); +} + + +/* * Cyrix 5x86 */ static void @@ -334,6 +357,9 @@ initializecpu(void) case CPU_486DLC: init_486dlc(); break; + case CPU_CY486DX: + init_cy486dx(); + break; case CPU_M1SC: init_5x86(); break; @@ -407,7 +433,7 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg) disable_intr(); - if (cpu != CPU_M1SC) { + if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { ccr0 = read_cyrix_reg(CCR0); } ccr1 = read_cyrix_reg(CCR1); @@ -424,7 +450,7 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg) } write_eflags(eflags); - if (cpu != CPU_M1SC) + if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) printf("CCR0=%x, ", (u_int)ccr0); printf("CCR1=%x, CCR2=%x, CCR3=%x", |