| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Revert "Revert "MFC r328083,328096,328116,328119,328120,328128,328135,328153,... | Luiz Souza | 2018-02-23 | 1 | -0/+1 |
| * | Revert "Revert "MFC r321899"" | Luiz Souza | 2018-02-23 | 1 | -0/+27 |
| * | Revert "MFC r321899" | Luiz Souza | 2018-02-21 | 1 | -27/+0 |
| * | Revert "MFC r328083,328096,328116,328119,328120,328128,328135,328153,328157," | Luiz Souza | 2018-02-21 | 1 | -1/+0 |
| * | MFC r328083,328096,328116,328119,328120,328128,328135,328153,328157, | kib | 2018-02-19 | 1 | -0/+1 |
| * | MFC r321899 | truckman | 2018-02-19 | 1 | -0/+27 |
| * | MFC r305539: work around AMD erratum 793 for family 16h, models 00h-0Fh | avg | 2016-10-27 | 1 | -0/+14 |
| * | MFC r302835: fix-up for configuration of AMD Family 10h processors | avg | 2016-08-15 | 1 | -0/+14 |
| * | fix missing variable in r298736 | avg | 2016-04-28 | 1 | -0/+1 |
| * | ensure that initial local apic id is sane on AMD 10h systems | avg | 2016-04-28 | 1 | -0/+13 |
| * | Move shared variables from {amd64,i386}/initcpu.c to x86/identcpu.c. | jhb | 2015-12-23 | 1 | -31/+0 |
| * | Intel SDM before revision 56 described the CLFLUSH instruction as only | kib | 2015-10-24 | 1 | -4/+9 |
| * | Update print_INTEL_TLB() by the tag values from the Intel SDM | kib | 2015-06-06 | 1 | -0/+1 |
| * | For x86, read MAXPHYADDR, defined in SDM vol 3 4.1.4 Enumeration of Paging | kib | 2015-01-12 | 1 | -0/+1 |
| * | Use an ANSI C definition of initializecpucache() to match the declaration | brooks | 2013-08-15 | 1 | -1/+1 |
| * | x86: detect mwait capabilities and extensions, when present | avg | 2013-07-28 | 1 | -0/+3 |
| * | Enable the new instructions for reading and writing bases for %fs, | kib | 2012-11-01 | 1 | -1/+16 |
| * | Provide the reading and display of the Standard Extended Features, | kib | 2012-11-01 | 1 | -0/+1 |
| * | Do not apply errata 721 workaround when under hypervisor, since | kib | 2012-08-07 | 1 | -1/+7 |
| * | Work around Erratum 721 for AMD Family 10h and 12h processors. | jkim | 2012-03-30 | 1 | -1/+28 |
| * | Add support for the extended FPU states on amd64, both for native | kib | 2012-01-21 | 1 | -0/+1 |
| * | Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta | jkim | 2011-03-26 | 1 | -50/+23 |
| * | Tweak the logic to disable CLFLUSH in virtual environments to work around | jhb | 2010-08-02 | 1 | -6/+6 |
| * | Amd64 init_secondary() calls initializecpu() while curthread is still | kib | 2009-11-13 | 1 | -0/+5 |
| * | - Style nits. | kuriyama | 2009-11-12 | 1 | -3/+1 |
| * | - Add hw.clflush_disable loader tunable to avoid panic (trap 9) at | kuriyama | 2009-11-09 | 1 | -1/+18 |
| * | As a workaround, for Intel CPUs, do not use CLFLUSH in | kib | 2009-10-01 | 1 | -0/+6 |
| * | Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce | jkim | 2009-09-10 | 1 | -2/+2 |
| * | When the page caching attributes are changed, after new mapping is | kib | 2009-07-22 | 1 | -0/+9 |
| * | Add basic amd64 support for VIA Nano processors. | jkim | 2009-01-12 | 1 | -0/+75 |
| * | Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "..."). | jkim | 2008-11-26 | 1 | -0/+1 |
| * | Detect Advanced Power Management Information for AMD CPUs. | jkim | 2008-10-21 | 1 | -0/+1 |
| * | Add variable cpu_mxcsr_mask to save valid bits of mxcsr register. | davidxu | 2006-06-19 | 1 | -0/+1 |
| * | - Print number of physical/logical cores and more CPUID info. | jkim | 2005-10-14 | 1 | -1/+3 |
| * | Initial PG_NX support (no-execute page bit) | peter | 2004-06-08 | 1 | -13/+13 |
| * | Cosmetic and/or trivial sync up with i386. | peter | 2003-11-21 | 1 | -1/+1 |
| * | Use __FBSDID(). | obrien | 2003-07-25 | 1 | -2/+3 |
| * | Commit MD parts of a loosely functional AMD64 port. This is based on | peter | 2003-05-01 | 1 | -810/+6 |
| * | Extend CPU_ATHLON_SSE_HACK to cover a few more revisions of Athlon CPUs. | dwmalone | 2003-03-20 | 1 | -1/+2 |
| * | - Move enable_sse()'s prototype to machine/md_var.h. | jhb | 2003-01-22 | 1 | -7/+6 |
| * | Rename cpuid_cpuinfo to cpu_procinfo. bde requested that I rename this | jhb | 2003-01-22 | 1 | -1/+1 |
| * | Rework part of the previous processor name changes so that we read | jhb | 2003-01-09 | 1 | -2/+0 |
| * | - Add a cpu_exthigh variable to hold the highest extended cpuid value | jhb | 2003-01-08 | 1 | -0/+2 |
| * | Add a cpuid_cpuinfo variable to hold the results of %ebx from cpuid with | jhb | 2003-01-08 | 1 | -0/+1 |
| * | Be consistent about functions being static. | phk | 2002-10-16 | 1 | -1/+1 |
| * | Be consistent about "static" functions: if the function is marked | phk | 2002-09-28 | 1 | -1/+1 |
| * | Automatically enable CPU_ENABLE_SSE (detect and enable SSE instructions) | peter | 2002-09-07 | 1 | -0/+7 |
| * | Fix abuses of cpu_critical_{enter,exit} by converting to | imp | 2002-03-21 | 1 | -4/+3 |
| * | Add an option CPU_ATHLON_SSE_HACK which attempts to enable the SSE | dwmalone | 2002-02-12 | 1 | -0/+18 |
| * | Modify the critical section API as follows: | jhb | 2001-12-18 | 1 | -2/+2 |
