blob: d1bbbbbcb55bafd56d16f484d3af52ce8a40a608 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package zpu_config is
constant Generate_Trace : boolean := true;
constant wordPower : integer := 5;
-- during simulation, set this to '0' to get matching trace.txt
constant DontCareValue : std_logic := '0';
-- Clock frequency in MHz.
constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
constant maxAddrBitIncIO : integer := 15;
end zpu_config;
|
