diff options
Diffstat (limited to 'mig_test/synthesis')
| -rw-r--r-- | mig_test/synthesis/Makefile | 46 | ||||
| -rw-r--r-- | mig_test/synthesis/top.ucf | 24 |
2 files changed, 54 insertions, 16 deletions
diff --git a/mig_test/synthesis/Makefile b/mig_test/synthesis/Makefile index 14df7bc..89e3aed 100644 --- a/mig_test/synthesis/Makefile +++ b/mig_test/synthesis/Makefile @@ -1,8 +1,8 @@ # # $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/trunk/hardware/board_prototyp1/synthesis/Makefile $ -# $Date: 2014-05-23 15:16:41 +0200 (Fr, 23. Mai 2014) $ -# $Author: lange $ -# $Revision: 3192 $ +# $Date$ +# $Author$ +# $Revision$ # MODULE = top @@ -11,7 +11,7 @@ SPEEDGRADE = 2 PACKAGE = fgg484 UCF_FILE = top.ucf CORES = ../cores/ -SOFTWARE = ../../../software +SOFTWARE = ../software BMM_FILE = zpu.bmm BMM_BD_FILE = zpu_bd.bmm @@ -79,8 +79,46 @@ run -infer_ramb8 No endef +# 16k +define BMM16 +ADDRESS_SPACE zpu_i0_memory + RAMB16 [0x00000000:0x00003fff] + BUS_BLOCK + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram8 [31:28]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram7 [27:24]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram6 [23:20]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram5 [19:16]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram4 [15:12]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram3 [11: 8]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram2 [ 7: 4]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram1 [ 3: 0]; + END_BUS_BLOCK; +END_ADDRESS_SPACE; +endef +# 32k define BMM +ADDRESS_SPACE zpu_core_medium_i0_memory + RAMB16 [0x00000000:0x00007fff] + BUS_BLOCK + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram16 [31:30]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram15 [29:28]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram14 [27:26]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram13 [25:24]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram12 [23:22]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram11 [21:20]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram10 [19:18]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram9 [17:16]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram8 [15:14]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram7 [13:12]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram6 [11:10]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram5 [ 9: 8]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram4 [ 7: 6]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram3 [ 5: 4]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram2 [ 3: 2]; + box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram1 [ 1: 0]; + END_BUS_BLOCK; +END_ADDRESS_SPACE; endef diff --git a/mig_test/synthesis/top.ucf b/mig_test/synthesis/top.ucf index e8e0f8f..6223064 100644 --- a/mig_test/synthesis/top.ucf +++ b/mig_test/synthesis/top.ucf @@ -5,7 +5,7 @@ CONFIG VCCAUX = "2.5"; ## system stuff #125MHz clock NET CLK LOC = AA12 | IOSTANDARD = LVCMOS33; -NET RESET_N LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN; +#NET RESET_N LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN; NET POWER_FAIL_N LOC = A2; # IO_L83P_3 NET WATCHDOG LOC = V9 | IOSTANDARD = LVCMOS33; # WATCHDOG INPUT, IO_L50N_2 @@ -52,14 +52,14 @@ NET MCB1_DRAM_DQ<13> LOC = U22 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_DQ<14> LOC = V21 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_DQ<15> LOC = V22 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_LDM LOC = L19 | IOSTANDARD = SSTL15_II; -NET MCB1_DRAM_LDQS_N LOC = L22 | IOSTANDARD = SSTL15_II; -NET MCB1_DRAM_LDQS_P LOC = L20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_N<0> LOC = L22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_P<0> LOC = L20 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_ODT LOC = G22 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_RAS_B LOC = H21 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_RESET_B LOC = F18 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_UDM LOC = M20 | IOSTANDARD = SSTL15_II; -NET MCB1_DRAM_UDQS_N LOC = T22 | IOSTANDARD = SSTL15_II; -NET MCB1_DRAM_UDQS_P LOC = T21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_N<1> LOC = T22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_P<1> LOC = T21 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_WE_B LOC = H19 | IOSTANDARD = SSTL15_II; # NET MCB3_DRAM_A<0> LOC = H2 | IOSTANDARD = SSTL15_II; @@ -101,14 +101,14 @@ NET MCB3_DRAM_DQ<13> LOC = U1 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_DQ<14> LOC = V2 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_DQ<15> LOC = V1 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_LDM LOC = L4 | IOSTANDARD = SSTL15_II; -NET MCB3_DRAM_LDQS_N LOC = L1 | IOSTANDARD = SSTL15_II; -NET MCB3_DRAM_LDQS_P LOC = L3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_N<0> LOC = L1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_P<0> LOC = L3 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_ODT LOC = J6 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_RAS_B LOC = K5 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_RESET_B LOC = C3 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_UDM LOC = M3 | IOSTANDARD = SSTL15_II; -NET MCB3_DRAM_UDQS_N LOC = T1 | IOSTANDARD = SSTL15_II; -NET MCB3_DRAM_UDQS_P LOC = T2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_N<1> LOC = T1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_P<1> LOC = T2 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_WE_B LOC = F2 | IOSTANDARD = SSTL15_II; ## Ethernet PHY @@ -152,7 +152,7 @@ NET SPI_FLASH_IO<2> LOC = U14; # MISO2/wp_n NET SPI_FLASH_IO<3> LOC = U13; # MISO3/hold_n ## EEPROM (48bit MAC address, DS2502-E48) -NET MAC_DATA LOC = T11; +NET MAC_DATA LOC = T11 | IOSTANDARD = LVCMOS33; ## B2B J1 user IO NET B2B_B2_L57_N LOC = AB4; @@ -196,7 +196,7 @@ NET B2B_B2_L8_P LOC = U17; # NET B2B_B2_L11_P LOC = V17; NET B2B_B2_L11_N LOC = W17; -NET B2B_B2_L6_P LOC = W18; +NET B2B_B2_L6_P LOC = W18 | IOSTANDARD = LVCMOS33; NET B2B_B2_L6_N LOC = Y18; # NET B2B_B2_L5_P LOC = Y19; @@ -254,7 +254,7 @@ NET B2B_B1_L21_P LOC = K16; NET B2B_B1_L61_P LOC = L17; NET B2B_B1_L61_N LOC = K18; # -#NET B2B_B0_L1 LOC = A4; # used as reset_n +NET B2B_B0_L1 LOC = A4; # used as reset_n # NET B2B_B0_L2_P LOC = C5; NET B2B_B0_L2_N LOC = A5; |
