diff options
Diffstat (limited to 'mig_test/synthesis/top.ucf')
| -rw-r--r-- | mig_test/synthesis/top.ucf | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/mig_test/synthesis/top.ucf b/mig_test/synthesis/top.ucf index e8e0f8f..6223064 100644 --- a/mig_test/synthesis/top.ucf +++ b/mig_test/synthesis/top.ucf @@ -5,7 +5,7 @@ CONFIG VCCAUX = "2.5"; ## system stuff #125MHz clock NET CLK LOC = AA12 | IOSTANDARD = LVCMOS33; -NET RESET_N LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN; +#NET RESET_N LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN; NET POWER_FAIL_N LOC = A2; # IO_L83P_3 NET WATCHDOG LOC = V9 | IOSTANDARD = LVCMOS33; # WATCHDOG INPUT, IO_L50N_2 @@ -52,14 +52,14 @@ NET MCB1_DRAM_DQ<13> LOC = U22 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_DQ<14> LOC = V21 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_DQ<15> LOC = V22 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_LDM LOC = L19 | IOSTANDARD = SSTL15_II; -NET MCB1_DRAM_LDQS_N LOC = L22 | IOSTANDARD = SSTL15_II; -NET MCB1_DRAM_LDQS_P LOC = L20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_N<0> LOC = L22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_P<0> LOC = L20 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_ODT LOC = G22 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_RAS_B LOC = H21 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_RESET_B LOC = F18 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_UDM LOC = M20 | IOSTANDARD = SSTL15_II; -NET MCB1_DRAM_UDQS_N LOC = T22 | IOSTANDARD = SSTL15_II; -NET MCB1_DRAM_UDQS_P LOC = T21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_N<1> LOC = T22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_P<1> LOC = T21 | IOSTANDARD = SSTL15_II; NET MCB1_DRAM_WE_B LOC = H19 | IOSTANDARD = SSTL15_II; # NET MCB3_DRAM_A<0> LOC = H2 | IOSTANDARD = SSTL15_II; @@ -101,14 +101,14 @@ NET MCB3_DRAM_DQ<13> LOC = U1 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_DQ<14> LOC = V2 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_DQ<15> LOC = V1 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_LDM LOC = L4 | IOSTANDARD = SSTL15_II; -NET MCB3_DRAM_LDQS_N LOC = L1 | IOSTANDARD = SSTL15_II; -NET MCB3_DRAM_LDQS_P LOC = L3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_N<0> LOC = L1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_P<0> LOC = L3 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_ODT LOC = J6 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_RAS_B LOC = K5 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_RESET_B LOC = C3 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_UDM LOC = M3 | IOSTANDARD = SSTL15_II; -NET MCB3_DRAM_UDQS_N LOC = T1 | IOSTANDARD = SSTL15_II; -NET MCB3_DRAM_UDQS_P LOC = T2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_N<1> LOC = T1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_P<1> LOC = T2 | IOSTANDARD = SSTL15_II; NET MCB3_DRAM_WE_B LOC = F2 | IOSTANDARD = SSTL15_II; ## Ethernet PHY @@ -152,7 +152,7 @@ NET SPI_FLASH_IO<2> LOC = U14; # MISO2/wp_n NET SPI_FLASH_IO<3> LOC = U13; # MISO3/hold_n ## EEPROM (48bit MAC address, DS2502-E48) -NET MAC_DATA LOC = T11; +NET MAC_DATA LOC = T11 | IOSTANDARD = LVCMOS33; ## B2B J1 user IO NET B2B_B2_L57_N LOC = AB4; @@ -196,7 +196,7 @@ NET B2B_B2_L8_P LOC = U17; # NET B2B_B2_L11_P LOC = V17; NET B2B_B2_L11_N LOC = W17; -NET B2B_B2_L6_P LOC = W18; +NET B2B_B2_L6_P LOC = W18 | IOSTANDARD = LVCMOS33; NET B2B_B2_L6_N LOC = Y18; # NET B2B_B2_L5_P LOC = Y19; @@ -254,7 +254,7 @@ NET B2B_B1_L21_P LOC = K16; NET B2B_B1_L61_P LOC = L17; NET B2B_B1_L61_N LOC = K18; # -#NET B2B_B0_L1 LOC = A4; # used as reset_n +NET B2B_B0_L1 LOC = A4; # used as reset_n # NET B2B_B0_L2_P LOC = C5; NET B2B_B0_L2_N LOC = A5; |
