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| author | oharboe <oharboe> | 2008-01-02 21:52:27 +0000 |
|---|---|---|
| committer | oharboe <oharboe> | 2008-01-02 21:52:27 +0000 |
| commit | f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9 (patch) | |
| tree | 2f53ff8c86e2708f838d26e3edede86c111b309e /zpu/hdl/wishbone/wishbone_pkg.vhd | |
| download | zpu-f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9.zip zpu-f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9.tar.gz | |
Initial import from www.ecosforge.net
Diffstat (limited to 'zpu/hdl/wishbone/wishbone_pkg.vhd')
| -rw-r--r-- | zpu/hdl/wishbone/wishbone_pkg.vhd | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/zpu/hdl/wishbone/wishbone_pkg.vhd b/zpu/hdl/wishbone/wishbone_pkg.vhd new file mode 100644 index 0000000..c3b0d9b --- /dev/null +++ b/zpu/hdl/wishbone/wishbone_pkg.vhd @@ -0,0 +1,52 @@ +library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+ type wishbone_bus_in is record
+ adr : std_logic_vector(31 downto 0);
+ sel : std_logic_vector(3 downto 0);
+ we : std_logic;
+ dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we'
+ cyc : std_logic;
+ stb : std_logic;
+ end record;
+
+ type wishbone_bus_out is record
+ dat : std_logic_vector(31 downto 0);
+ ack : std_logic;
+ end record;
+
+ type wishbone_bus is record
+ insig : wishbone_bus_in;
+ outsig : wishbone_bus_out;
+ end record;
+
+ component atomic32_access is
+ port ( cpu_clk : in std_logic;
+ areset : in std_logic;
+
+ -- Wishbone from CPU interface
+ wb_16_i : in wishbone_bus_in;
+ wb_16_o : out wishbone_bus_out;
+ -- Wishbone to FPGA registers and ethernet core
+ wb_32_i : in wishbone_bus_out;
+ wb_32_o : out wishbone_bus_in);
+ end component;
+
+ component eth_access_corr is
+ port ( cpu_clk : in std_logic;
+ areset : in std_logic;
+
+ -- Wishbone from Wishbone MUX
+ eth_raw_o : out wishbone_bus_out;
+ eth_raw_i : in wishbone_bus_in;
+
+ -- Wishbone ethernet core
+ eth_slave_i : in wishbone_bus_out;
+ eth_slave_o : out wishbone_bus_in);
+ end component;
+
+
+end wishbone_pkg;
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