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authoroharboe <oharboe>2008-01-02 21:52:27 +0000
committeroharboe <oharboe>2008-01-02 21:52:27 +0000
commitf2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9 (patch)
tree2f53ff8c86e2708f838d26e3edede86c111b309e
downloadzpu-f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9.zip
zpu-f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9.tar.gz
Initial import from www.ecosforge.net
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233 files changed, 91183 insertions, 0 deletions
diff --git a/.project b/.project
new file mode 100644
index 0000000..bdcda92
--- /dev/null
+++ b/.project
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>oczpu</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ </buildSpec>
+ <natures>
+ </natures>
+</projectDescription>
diff --git a/zpu/.project b/zpu/.project
new file mode 100644
index 0000000..55b1cb8
--- /dev/null
+++ b/zpu/.project
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>zpu</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ </buildSpec>
+ <natures>
+ </natures>
+</projectDescription>
diff --git a/zpu/COPYING b/zpu/COPYING
new file mode 100644
index 0000000..96b27d3
--- /dev/null
+++ b/zpu/COPYING
@@ -0,0 +1,12 @@
+About ZPU licensing:
+
+Licensing is not entirely fleshed out yet(there are many parts to a
+soft CPU), but the license for the HDL will be BSD/eCos-like to be
+friendly towards commercially oriented projects, however the
+architecture, documentation and tools will be GPL. This means that all
+updates to the architecture must be shared, but actual
+implementations(which are small and can be very project speific) can
+be friendly towards commercial considerations.
+
+
+Patches to update files w/correct licensing info will be most appreciated!
diff --git a/zpu/ChangeLog b/zpu/ChangeLog
new file mode 100644
index 0000000..827ede8
--- /dev/null
+++ b/zpu/ChangeLog
@@ -0,0 +1,11 @@
+2007-09-11 Řyvind Harboe
+ * Cleaning up zpu/hdl/example. simzpu.do file now uses zpu4/src files instead
+ of duplicating them. Hello world simzpu.do now works out of the box.
+2007-09-10 Řyvind Harboe
+ * Cleaning up .html files a bit.
+ * retired zpututorial.odt.
+2007-08-04 Řyvind Harboe
+ * small ZPU hello world example now simulates with valid log.txt/trace.txt file.
+ * Until files are properly organized, ChangeLog will not be kept up to date.
+2007-08-03 Řyvind Harboe
+ * Starting to commit files
diff --git a/zpu/STATUS b/zpu/STATUS
new file mode 100644
index 0000000..e28f191
--- /dev/null
+++ b/zpu/STATUS
@@ -0,0 +1,11 @@
+The current state of the ZPU:
+
+- Patches welcome!
+- Zylin is rummaging up the various files that might be of interest
+ to the open source ZPU project.
+- The ZPU, GCC toolchain and HDL works. Zylin eCosBoard 1.1 ships w/a
+ ZPU(see http://www.zylin.com), if you need a development board before
+ implementing on your own system.
+- The docs leave a lot to be desired at this point.
+- Licensing needs to be ironed out. After which lots of files will have
+ to be updated, strictly speaking. Patches welcome!
diff --git a/zpu/docs/presentations/zpu.odp b/zpu/docs/presentations/zpu.odp
new file mode 100644
index 0000000..e2a6554
--- /dev/null
+++ b/zpu/docs/presentations/zpu.odp
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diff --git a/zpu/docs/presentations/zpudemo.odp b/zpu/docs/presentations/zpudemo.odp
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diff --git a/zpu/docs/zpuprotoarch.odt b/zpu/docs/zpuprotoarch.odt
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diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd
new file mode 100644
index 0000000..9c99259
--- /dev/null
+++ b/zpu/hdl/example/helloworld.vhd
@@ -0,0 +1,12506 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"82f4e00c",
+3 => x"3a0b0b81",
+4 => x"e48c0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"81e4fd2d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c9040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88ac",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b82f4",
+162 => x"cc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88af0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8e",
+171 => x"c42d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b90",
+179 => x"8d2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"82f4dc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"0b0b0b83",
+257 => x"e93f0b0b",
+258 => x"82e4cc3f",
+259 => x"04101010",
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+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101010",
+266 => x"10101010",
+267 => x"53510473",
+268 => x"81ff0673",
+269 => x"83060981",
+270 => x"05830510",
+271 => x"10102b07",
+272 => x"72fc060c",
+273 => x"5151043c",
+274 => x"04727280",
+275 => x"728106ff",
+276 => x"05097206",
+277 => x"05711052",
+278 => x"720a100a",
+279 => x"5372ed38",
+280 => x"51515351",
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+283 => x"e8085384",
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+285 => x"2a708106",
+286 => x"51525270",
+287 => x"802e0b0b",
+288 => x"0b0bec38",
+289 => x"7181ff06",
+290 => x"800c843d",
+291 => x"0d04ff3d",
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+293 => x"84e80852",
+294 => x"71087088",
+295 => x"2a813270",
+296 => x"81065151",
+297 => x"51700b0b",
+298 => x"0b0bed38",
+299 => x"73720c83",
+300 => x"3d0d040b",
+301 => x"0b82f4dc",
+302 => x"08802e0b",
+303 => x"0b0b0bae",
+304 => x"380b0b82",
+305 => x"f4e00882",
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+307 => x"80c53883",
+308 => x"80800b0b",
+309 => x"0b8384e8",
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+311 => x"0b0b0b83",
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+315 => x"0c04f880",
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+321 => x"ec0cf880",
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+325 => x"c0a8808c",
+326 => x"0b0b0b83",
+327 => x"84e80c80",
+328 => x"c0a88094",
+329 => x"0b0b0b83",
+330 => x"84ec0c0b",
+331 => x"0b82ed90",
+332 => x"0b0b0b83",
+333 => x"84f00c04",
+334 => x"f23d0d60",
+335 => x"0b0b8384",
+336 => x"ec08565d",
+337 => x"82750c80",
+338 => x"59805a80",
+339 => x"0b8f3d5d",
+340 => x"5b7a1010",
+341 => x"15700871",
+342 => x"08719f2c",
+343 => x"7e852b58",
+344 => x"55557d53",
+345 => x"59570b0b",
+346 => x"0b81d13f",
+347 => x"7d7f7a72",
+348 => x"077c7207",
+349 => x"71716081",
+350 => x"05415f5d",
+351 => x"5b595755",
+352 => x"817b270b",
+353 => x"0b0b0b8f",
+354 => x"38767d0c",
+355 => x"77841e0c",
+356 => x"7c800c90",
+357 => x"3d0d040b",
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+364 => x"0b0bb738",
+365 => x"0b0b82f4",
+366 => x"e8087008",
+367 => x"52527080",
+368 => x"2e0b0b0b",
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+370 => x"120b0b82",
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+373 => x"f4e80870",
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+383 => x"380b0b0b",
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+387 => x"83385004",
+388 => x"0b0b8384",
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+391 => x"5004048c",
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+595 => x"0b0b0bff",
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+597 => x"90050880",
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+604 => x"398c08f8",
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+607 => x"518c08f4",
+608 => x"0508800c",
+609 => x"50505050",
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+11848 => x"255bba08",
+11849 => x"cf8c979d",
+11850 => x"0ac80628",
+11851 => x"64ac6f43",
+11852 => x"4341c379",
+11853 => x"37e08000",
+11854 => x"4693b8b5",
+11855 => x"b5056e17",
+11856 => x"4d384f03",
+11857 => x"e93ff9f5",
+11858 => x"5a827748",
+11859 => x"f9301d32",
+11860 => x"75154fdd",
+11861 => x"7f73bf3c",
+11862 => x"3ff00000",
+11863 => x"00000000",
+11864 => x"40240000",
+11865 => x"00000000",
+11866 => x"40590000",
+11867 => x"00000000",
+11868 => x"408f4000",
+11869 => x"00000000",
+11870 => x"40c38800",
+11871 => x"00000000",
+11872 => x"40f86a00",
+11873 => x"00000000",
+11874 => x"412e8480",
+11875 => x"00000000",
+11876 => x"416312d0",
+11877 => x"00000000",
+11878 => x"4197d784",
+11879 => x"00000000",
+11880 => x"41cdcd65",
+11881 => x"00000000",
+11882 => x"4202a05f",
+11883 => x"20000000",
+11884 => x"42374876",
+11885 => x"e8000000",
+11886 => x"426d1a94",
+11887 => x"a2000000",
+11888 => x"42a2309c",
+11889 => x"e5400000",
+11890 => x"42d6bcc4",
+11891 => x"1e900000",
+11892 => x"430c6bf5",
+11893 => x"26340000",
+11894 => x"4341c379",
+11895 => x"37e08000",
+11896 => x"43763457",
+11897 => x"85d8a000",
+11898 => x"43abc16d",
+11899 => x"674ec800",
+11900 => x"43e158e4",
+11901 => x"60913d00",
+11902 => x"4415af1d",
+11903 => x"78b58c40",
+11904 => x"444b1ae4",
+11905 => x"d6e2ef50",
+11906 => x"4480f0cf",
+11907 => x"064dd592",
+11908 => x"44b52d02",
+11909 => x"c7e14af6",
+11910 => x"44ea7843",
+11911 => x"79d99db4",
+11912 => x"00000005",
+11913 => x"00000019",
+11914 => x"0000007d",
+11915 => x"64756d6d",
+11916 => x"792e6578",
+11917 => x"65000000",
+11918 => x"00000000",
+11919 => x"00000000",
+11920 => x"00000000",
+11921 => x"00000000",
+11922 => x"00000000",
+11923 => x"00ffffff",
+11924 => x"ff00ffff",
+11925 => x"ffff00ff",
+11926 => x"ffffff00",
+11927 => x"00000000",
+11928 => x"00000000",
+11929 => x"00000000",
+11930 => x"0000c260",
+11931 => x"0000ba70",
+11932 => x"00000000",
+11933 => x"0000bcd8",
+11934 => x"0000bd34",
+11935 => x"0000bd90",
+11936 => x"00000000",
+11937 => x"00000000",
+11938 => x"00000000",
+11939 => x"00000000",
+11940 => x"00000000",
+11941 => x"00000000",
+11942 => x"00000000",
+11943 => x"00000000",
+11944 => x"00000000",
+11945 => x"0000b8c8",
+11946 => x"00000000",
+11947 => x"00000000",
+11948 => x"00000000",
+11949 => x"00000000",
+11950 => x"00000000",
+11951 => x"00000000",
+11952 => x"00000000",
+11953 => x"00000000",
+11954 => x"00000000",
+11955 => x"00000000",
+11956 => x"00000000",
+11957 => x"00000000",
+11958 => x"00000000",
+11959 => x"00000000",
+11960 => x"00000000",
+11961 => x"00000000",
+11962 => x"00000000",
+11963 => x"00000000",
+11964 => x"00000000",
+11965 => x"00000000",
+11966 => x"00000000",
+11967 => x"00000000",
+11968 => x"00000000",
+11969 => x"00000000",
+11970 => x"00000000",
+11971 => x"00000000",
+11972 => x"00000000",
+11973 => x"00000000",
+11974 => x"00000001",
+11975 => x"330eabcd",
+11976 => x"1234e66d",
+11977 => x"deec0005",
+11978 => x"000b0000",
+11979 => x"00000000",
+11980 => x"00000000",
+11981 => x"00000000",
+11982 => x"00000000",
+11983 => x"00000000",
+11984 => x"00000000",
+11985 => x"00000000",
+11986 => x"00000000",
+11987 => x"00000000",
+11988 => x"00000000",
+11989 => x"00000000",
+11990 => x"00000000",
+11991 => x"00000000",
+11992 => x"00000000",
+11993 => x"00000000",
+11994 => x"00000000",
+11995 => x"00000000",
+11996 => x"00000000",
+11997 => x"00000000",
+11998 => x"00000000",
+11999 => x"00000000",
+12000 => x"00000000",
+12001 => x"00000000",
+12002 => x"00000000",
+12003 => x"00000000",
+12004 => x"00000000",
+12005 => x"00000000",
+12006 => x"00000000",
+12007 => x"00000000",
+12008 => x"00000000",
+12009 => x"00000000",
+12010 => x"00000000",
+12011 => x"00000000",
+12012 => x"00000000",
+12013 => x"00000000",
+12014 => x"00000000",
+12015 => x"00000000",
+12016 => x"00000000",
+12017 => x"00000000",
+12018 => x"00000000",
+12019 => x"00000000",
+12020 => x"00000000",
+12021 => x"00000000",
+12022 => x"00000000",
+12023 => x"00000000",
+12024 => x"00000000",
+12025 => x"00000000",
+12026 => x"00000000",
+12027 => x"00000000",
+12028 => x"00000000",
+12029 => x"00000000",
+12030 => x"00000000",
+12031 => x"00000000",
+12032 => x"00000000",
+12033 => x"00000000",
+12034 => x"00000000",
+12035 => x"00000000",
+12036 => x"00000000",
+12037 => x"00000000",
+12038 => x"00000000",
+12039 => x"00000000",
+12040 => x"00000000",
+12041 => x"00000000",
+12042 => x"00000000",
+12043 => x"00000000",
+12044 => x"00000000",
+12045 => x"00000000",
+12046 => x"00000000",
+12047 => x"00000000",
+12048 => x"00000000",
+12049 => x"00000000",
+12050 => x"00000000",
+12051 => x"00000000",
+12052 => x"00000000",
+12053 => x"00000000",
+12054 => x"00000000",
+12055 => x"00000000",
+12056 => x"00000000",
+12057 => x"00000000",
+12058 => x"00000000",
+12059 => x"00000000",
+12060 => x"00000000",
+12061 => x"00000000",
+12062 => x"00000000",
+12063 => x"00000000",
+12064 => x"00000000",
+12065 => x"00000000",
+12066 => x"00000000",
+12067 => x"00000000",
+12068 => x"00000000",
+12069 => x"00000000",
+12070 => x"00000000",
+12071 => x"00000000",
+12072 => x"00000000",
+12073 => x"00000000",
+12074 => x"00000000",
+12075 => x"00000000",
+12076 => x"00000000",
+12077 => x"00000000",
+12078 => x"00000000",
+12079 => x"00000000",
+12080 => x"00000000",
+12081 => x"00000000",
+12082 => x"00000000",
+12083 => x"00000000",
+12084 => x"00000000",
+12085 => x"00000000",
+12086 => x"00000000",
+12087 => x"00000000",
+12088 => x"00000000",
+12089 => x"00000000",
+12090 => x"00000000",
+12091 => x"00000000",
+12092 => x"00000000",
+12093 => x"00000000",
+12094 => x"00000000",
+12095 => x"00000000",
+12096 => x"00000000",
+12097 => x"00000000",
+12098 => x"00000000",
+12099 => x"00000000",
+12100 => x"00000000",
+12101 => x"00000000",
+12102 => x"00000000",
+12103 => x"00000000",
+12104 => x"00000000",
+12105 => x"00000000",
+12106 => x"00000000",
+12107 => x"00000000",
+12108 => x"00000000",
+12109 => x"00000000",
+12110 => x"00000000",
+12111 => x"00000000",
+12112 => x"00000000",
+12113 => x"00000000",
+12114 => x"00000000",
+12115 => x"00000000",
+12116 => x"00000000",
+12117 => x"00000000",
+12118 => x"00000000",
+12119 => x"00000000",
+12120 => x"00000000",
+12121 => x"00000000",
+12122 => x"00000000",
+12123 => x"00000000",
+12124 => x"00000000",
+12125 => x"00000000",
+12126 => x"00000000",
+12127 => x"00000000",
+12128 => x"00000000",
+12129 => x"00000000",
+12130 => x"00000000",
+12131 => x"00000000",
+12132 => x"00000000",
+12133 => x"00000000",
+12134 => x"00000000",
+12135 => x"00000000",
+12136 => x"00000000",
+12137 => x"00000000",
+12138 => x"00000000",
+12139 => x"00000000",
+12140 => x"00000000",
+12141 => x"00000000",
+12142 => x"00000000",
+12143 => x"00000000",
+12144 => x"00000000",
+12145 => x"00000000",
+12146 => x"00000000",
+12147 => x"00000000",
+12148 => x"00000000",
+12149 => x"00000000",
+12150 => x"00000000",
+12151 => x"00000000",
+12152 => x"00000000",
+12153 => x"00000000",
+12154 => x"00000000",
+12155 => x"43000000",
+12156 => x"00000000",
+12157 => x"00000000",
+12158 => x"00000000",
+12159 => x"00000000",
+12160 => x"00000000",
+12161 => x"00000001",
+12162 => x"0000b8cc",
+12163 => x"00000000",
+12164 => x"00000000",
+12165 => x"00000000",
+12166 => x"00000000",
+12167 => x"00000000",
+12168 => x"00000000",
+12169 => x"00000000",
+12170 => x"00000000",
+12171 => x"00000000",
+12172 => x"00000000",
+12173 => x"00000000",
+12174 => x"00000000",
+12175 => x"ffffffff",
+12176 => x"00000000",
+12177 => x"00020000",
+12178 => x"00000000",
+12179 => x"00000000",
+12180 => x"0000be48",
+12181 => x"0000be48",
+12182 => x"0000be50",
+12183 => x"0000be50",
+12184 => x"0000be58",
+12185 => x"0000be58",
+12186 => x"0000be60",
+12187 => x"0000be60",
+12188 => x"0000be68",
+12189 => x"0000be68",
+12190 => x"0000be70",
+12191 => x"0000be70",
+12192 => x"0000be78",
+12193 => x"0000be78",
+12194 => x"0000be80",
+12195 => x"0000be80",
+12196 => x"0000be88",
+12197 => x"0000be88",
+12198 => x"0000be90",
+12199 => x"0000be90",
+12200 => x"0000be98",
+12201 => x"0000be98",
+12202 => x"0000bea0",
+12203 => x"0000bea0",
+12204 => x"0000bea8",
+12205 => x"0000bea8",
+12206 => x"0000beb0",
+12207 => x"0000beb0",
+12208 => x"0000beb8",
+12209 => x"0000beb8",
+12210 => x"0000bec0",
+12211 => x"0000bec0",
+12212 => x"0000bec8",
+12213 => x"0000bec8",
+12214 => x"0000bed0",
+12215 => x"0000bed0",
+12216 => x"0000bed8",
+12217 => x"0000bed8",
+12218 => x"0000bee0",
+12219 => x"0000bee0",
+12220 => x"0000bee8",
+12221 => x"0000bee8",
+12222 => x"0000bef0",
+12223 => x"0000bef0",
+12224 => x"0000bef8",
+12225 => x"0000bef8",
+12226 => x"0000bf00",
+12227 => x"0000bf00",
+12228 => x"0000bf08",
+12229 => x"0000bf08",
+12230 => x"0000bf10",
+12231 => x"0000bf10",
+12232 => x"0000bf18",
+12233 => x"0000bf18",
+12234 => x"0000bf20",
+12235 => x"0000bf20",
+12236 => x"0000bf28",
+12237 => x"0000bf28",
+12238 => x"0000bf30",
+12239 => x"0000bf30",
+12240 => x"0000bf38",
+12241 => x"0000bf38",
+12242 => x"0000bf40",
+12243 => x"0000bf40",
+12244 => x"0000bf48",
+12245 => x"0000bf48",
+12246 => x"0000bf50",
+12247 => x"0000bf50",
+12248 => x"0000bf58",
+12249 => x"0000bf58",
+12250 => x"0000bf60",
+12251 => x"0000bf60",
+12252 => x"0000bf68",
+12253 => x"0000bf68",
+12254 => x"0000bf70",
+12255 => x"0000bf70",
+12256 => x"0000bf78",
+12257 => x"0000bf78",
+12258 => x"0000bf80",
+12259 => x"0000bf80",
+12260 => x"0000bf88",
+12261 => x"0000bf88",
+12262 => x"0000bf90",
+12263 => x"0000bf90",
+12264 => x"0000bf98",
+12265 => x"0000bf98",
+12266 => x"0000bfa0",
+12267 => x"0000bfa0",
+12268 => x"0000bfa8",
+12269 => x"0000bfa8",
+12270 => x"0000bfb0",
+12271 => x"0000bfb0",
+12272 => x"0000bfb8",
+12273 => x"0000bfb8",
+12274 => x"0000bfc0",
+12275 => x"0000bfc0",
+12276 => x"0000bfc8",
+12277 => x"0000bfc8",
+12278 => x"0000bfd0",
+12279 => x"0000bfd0",
+12280 => x"0000bfd8",
+12281 => x"0000bfd8",
+12282 => x"0000bfe0",
+12283 => x"0000bfe0",
+12284 => x"0000bfe8",
+12285 => x"0000bfe8",
+12286 => x"0000bff0",
+12287 => x"0000bff0",
+12288 => x"0000bff8",
+12289 => x"0000bff8",
+12290 => x"0000c000",
+12291 => x"0000c000",
+12292 => x"0000c008",
+12293 => x"0000c008",
+12294 => x"0000c010",
+12295 => x"0000c010",
+12296 => x"0000c018",
+12297 => x"0000c018",
+12298 => x"0000c020",
+12299 => x"0000c020",
+12300 => x"0000c028",
+12301 => x"0000c028",
+12302 => x"0000c030",
+12303 => x"0000c030",
+12304 => x"0000c038",
+12305 => x"0000c038",
+12306 => x"0000c040",
+12307 => x"0000c040",
+12308 => x"0000c048",
+12309 => x"0000c048",
+12310 => x"0000c050",
+12311 => x"0000c050",
+12312 => x"0000c058",
+12313 => x"0000c058",
+12314 => x"0000c060",
+12315 => x"0000c060",
+12316 => x"0000c068",
+12317 => x"0000c068",
+12318 => x"0000c070",
+12319 => x"0000c070",
+12320 => x"0000c078",
+12321 => x"0000c078",
+12322 => x"0000c080",
+12323 => x"0000c080",
+12324 => x"0000c088",
+12325 => x"0000c088",
+12326 => x"0000c090",
+12327 => x"0000c090",
+12328 => x"0000c098",
+12329 => x"0000c098",
+12330 => x"0000c0a0",
+12331 => x"0000c0a0",
+12332 => x"0000c0a8",
+12333 => x"0000c0a8",
+12334 => x"0000c0b0",
+12335 => x"0000c0b0",
+12336 => x"0000c0b8",
+12337 => x"0000c0b8",
+12338 => x"0000c0c0",
+12339 => x"0000c0c0",
+12340 => x"0000c0c8",
+12341 => x"0000c0c8",
+12342 => x"0000c0d0",
+12343 => x"0000c0d0",
+12344 => x"0000c0d8",
+12345 => x"0000c0d8",
+12346 => x"0000c0e0",
+12347 => x"0000c0e0",
+12348 => x"0000c0e8",
+12349 => x"0000c0e8",
+12350 => x"0000c0f0",
+12351 => x"0000c0f0",
+12352 => x"0000c0f8",
+12353 => x"0000c0f8",
+12354 => x"0000c100",
+12355 => x"0000c100",
+12356 => x"0000c108",
+12357 => x"0000c108",
+12358 => x"0000c110",
+12359 => x"0000c110",
+12360 => x"0000c118",
+12361 => x"0000c118",
+12362 => x"0000c120",
+12363 => x"0000c120",
+12364 => x"0000c128",
+12365 => x"0000c128",
+12366 => x"0000c130",
+12367 => x"0000c130",
+12368 => x"0000c138",
+12369 => x"0000c138",
+12370 => x"0000c140",
+12371 => x"0000c140",
+12372 => x"0000c148",
+12373 => x"0000c148",
+12374 => x"0000c150",
+12375 => x"0000c150",
+12376 => x"0000c158",
+12377 => x"0000c158",
+12378 => x"0000c160",
+12379 => x"0000c160",
+12380 => x"0000c168",
+12381 => x"0000c168",
+12382 => x"0000c170",
+12383 => x"0000c170",
+12384 => x"0000c178",
+12385 => x"0000c178",
+12386 => x"0000c180",
+12387 => x"0000c180",
+12388 => x"0000c188",
+12389 => x"0000c188",
+12390 => x"0000c190",
+12391 => x"0000c190",
+12392 => x"0000c198",
+12393 => x"0000c198",
+12394 => x"0000c1a0",
+12395 => x"0000c1a0",
+12396 => x"0000c1a8",
+12397 => x"0000c1a8",
+12398 => x"0000c1b0",
+12399 => x"0000c1b0",
+12400 => x"0000c1b8",
+12401 => x"0000c1b8",
+12402 => x"0000c1c0",
+12403 => x"0000c1c0",
+12404 => x"0000c1c8",
+12405 => x"0000c1c8",
+12406 => x"0000c1d0",
+12407 => x"0000c1d0",
+12408 => x"0000c1d8",
+12409 => x"0000c1d8",
+12410 => x"0000c1e0",
+12411 => x"0000c1e0",
+12412 => x"0000c1e8",
+12413 => x"0000c1e8",
+12414 => x"0000c1f0",
+12415 => x"0000c1f0",
+12416 => x"0000c1f8",
+12417 => x"0000c1f8",
+12418 => x"0000c200",
+12419 => x"0000c200",
+12420 => x"0000c208",
+12421 => x"0000c208",
+12422 => x"0000c210",
+12423 => x"0000c210",
+12424 => x"0000c218",
+12425 => x"0000c218",
+12426 => x"0000c220",
+12427 => x"0000c220",
+12428 => x"0000c228",
+12429 => x"0000c228",
+12430 => x"0000c230",
+12431 => x"0000c230",
+12432 => x"0000c238",
+12433 => x"0000c238",
+12434 => x"0000c240",
+12435 => x"0000c240",
+12436 => x"0000ba2c",
+12437 => x"ffffffff",
+12438 => x"00000000",
+12439 => x"ffffffff",
+12440 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+ report "write collision" severity failure;
+ end if;
+
+ if (memAWriteEnable = '1') then
+ ram(conv_integer(memAAddr)) := memAWrite;
+ memARead <= memAWrite;
+ else
+ memARead <= ram(conv_integer(memAAddr));
+ end if;
+ end if;
+end process;
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memBWriteEnable = '1') then
+ ram(conv_integer(memBAddr)) := memBWrite;
+ memBRead <= memBWrite;
+ else
+ memBRead <= ram(conv_integer(memBAddr));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/io.vhd b/zpu/hdl/example/io.vhd
new file mode 100644
index 0000000..7dbe36f
--- /dev/null
+++ b/zpu/hdl/example/io.vhd
@@ -0,0 +1,97 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+
+entity zpu_io is
+ generic (
+ log_file: string := "log.txt"
+ );
+ port(
+ clk : in std_logic;
+ areset : in std_logic;
+ busy : out std_logic;
+ writeEnable : in std_logic;
+ readEnable : in std_logic;
+ write : in std_logic_vector(wordSize-1 downto 0);
+ read : out std_logic_vector(wordSize-1 downto 0);
+ addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+ );
+end zpu_io;
+
+
+architecture behave of zpu_io is
+
+
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+signal serving : std_logic;
+
+file l_file : TEXT open write_mode is log_file;
+
+begin
+
+
+ timerinst: timer port map (
+ clk => clk,
+ areset => areset,
+ we => timer_we,
+ din => write(7 downto 0),
+ adr => addr(4 downto 2),
+ dout => timer_read);
+
+ busy <= writeEnable or readEnable;
+ timer_we <= writeEnable and addr(12);
+
+ process(areset, clk)
+ begin
+ if (areset = '1') then
+-- timer_we <= '0';
+ elsif (clk'event and clk = '1') then
+-- timer_we <= '0';
+ if writeEnable = '1' then
+ -- external interface
+ if addr=x"2028003" then
+ -- Write to UART
+ -- report "" & character'image(conv_integer(memBint)) severity note;
+ print(l_file, character'val(conv_integer(write)));
+ elsif addr(12)='1' then
+-- report "xxx" severity failure;
+-- timer_we <= '1';
+ else
+ print(l_file, character'val(conv_integer(write)));
+ report "Illegal IO write" severity warning;
+ end if;
+
+ end if;
+ read <= (others => '0');
+ if (readEnable = '1') then
+ if addr=x"1001" then
+ read <= (0=>'1', others => '0'); -- recieve empty
+ elsif addr(12)='1' then
+ read(7 downto 0) <= timer_read;
+ elsif addr(11)='1' then
+ read(7 downto 0) <= ZPU_Frequency;
+ elsif addr=x"2028003" then
+ read <= (others => '0');
+ else
+ read <= (others => '0');
+ read(8) <= '1';
+ report "Illegal IO read" severity warning;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+end behave;
+
diff --git a/zpu/hdl/example/log.txt b/zpu/hdl/example/log.txt
new file mode 100644
index 0000000..6954a81
--- /dev/null
+++ b/zpu/hdl/example/log.txt
@@ -0,0 +1,15 @@
+H
+e
+l
+l
+o
+
+w
+o
+r
+l
+d
+!
+
+
+
diff --git a/zpu/hdl/example/sim_fpga_top.vhd b/zpu/hdl/example/sim_fpga_top.vhd
new file mode 100644
index 0000000..b51fea0
--- /dev/null
+++ b/zpu/hdl/example/sim_fpga_top.vhd
@@ -0,0 +1,179 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:15:31 04/14/05
+-- Design Name:
+-- Module Name: fpga_top - behave
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity fpga_top is
+end fpga_top;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal areset : std_logic;
+
+
+component zpu_io is
+ generic (
+ log_file: string := "log.txt"
+ );
+ port(
+ clk : in std_logic;
+ areset : in std_logic;
+ busy : out std_logic;
+ writeEnable : in std_logic;
+ readEnable : in std_logic;
+ write : in std_logic_vector(wordSize-1 downto 0);
+ read : out std_logic_vector(wordSize-1 downto 0);
+ addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+ );
+end component;
+
+
+
+
+
+signal mem_busy : std_logic;
+signal mem_read : std_logic_vector(wordSize-1 downto 0);
+signal mem_write : std_logic_vector(wordSize-1 downto 0);
+signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal mem_writeEnable : std_logic;
+signal mem_readEnable : std_logic;
+signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal enable : std_logic;
+
+signal dram_mem_busy : std_logic;
+signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal dram_mem_writeEnable : std_logic;
+signal dram_mem_readEnable : std_logic;
+signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+signal io_busy : std_logic;
+
+signal io_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal io_mem_writeEnable : std_logic;
+signal io_mem_readEnable : std_logic;
+
+
+signal dram_ready : std_logic;
+signal io_ready : std_logic;
+signal io_reading : std_logic;
+
+
+signal break : std_logic;
+
+begin
+ poweronreset: roc port map (O => areset);
+
+
+
+ zpu: zpu_core port map (
+ clk => clk ,
+ areset => areset,
+ enable => enable,
+ in_mem_busy => mem_busy,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => mem_addr,
+ out_mem_writeEnable => mem_writeEnable,
+ out_mem_readEnable => mem_readEnable,
+ mem_writeMask => mem_writeMask,
+ interrupt => '0',
+ break => break);
+
+
+ ioMap: zpu_io port map (
+ clk => clk,
+ areset => areset,
+ busy => io_busy,
+ writeEnable => io_mem_writeEnable,
+ readEnable => io_mem_readEnable,
+ write => mem_write,
+ read => io_mem_read,
+ addr => mem_addr(maxAddrBit downto minAddrBit)
+ );
+
+ dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+ dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+ io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+ io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+ mem_busy <= io_busy;
+
+
+
+ -- Memory reads either come from IO or DRAM. We need to pick the right one.
+ memorycontrol:
+ process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+ begin
+ mem_read <= (others => 'U');
+ if dram_ready='1' then
+ mem_read <= dram_mem_read;
+ end if;
+
+ if io_ready='1' then
+ mem_read <= (others => '0');
+ mem_read <= io_mem_read;
+ end if;
+ end process;
+
+
+ io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+ memoryControlSync:
+ process(clk, areset)
+ begin
+ if areset = '1' then
+ enable <= '0';
+ io_reading <= '0';
+ dram_ready <= '0';
+ elsif (clk'event and clk = '1') then
+ enable <= '1';
+ io_reading <= io_busy or io_mem_readEnable;
+ dram_ready<=dram_mem_readEnable;
+
+ end if;
+ end process;
+
+ -- wiggle the clock @ 100MHz
+ clock : PROCESS
+ begin
+ clk <= '0';
+ wait for 5 ns;
+ clk <= '1';
+ wait for 5 ns;
+ end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/example/simzpu.do b/zpu/hdl/example/simzpu.do
new file mode 100644
index 0000000..083187f
--- /dev/null
+++ b/zpu/hdl/example/simzpu.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+# 1. Change directory to this source directory
+# cd C:/workspace/zpunew/hdl/example
+# "do zimzpu.do"
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/src/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit ../zpu4/src/zpu_core_small.vhd
+vcom -93 -explicit helloworld.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd
new file mode 100644
index 0000000..a59ac8e
--- /dev/null
+++ b/zpu/hdl/example/zpu_config.vhd
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+ -- generate trace output
+ constant Generate_Trace : boolean := true;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
+ -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+ constant maxAddrBitIncIO : integer := 27;
+ constant maxAddrBitBRAM : integer := 16;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8";
+end zpu_config;
diff --git a/zpu/hdl/index.html b/zpu/hdl/index.html
new file mode 100644
index 0000000..d3b4c1a
--- /dev/null
+++ b/zpu/hdl/index.html
@@ -0,0 +1,47 @@
+<html>
+<body>
+<h1>Getting started - FPGA </h1>
+The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART
+is a good place to start.
+<p>
+You'll find a working simulation script in hdl/example/simzpu.do.
+<p>
+When implementing the ZPU, copy the following files and modify them to your needs:
+<ol>
+ <li>hdl/example/zpu_config.vhd - set up RAM size here
+ <li>hdl/example/helloworld.vhd - dual port BRAM implementation.
+</ol>
+Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is memory mapped(read/write) in the ZPU.
+<h2>Generating VHDL BRAM initialization </h2>
+
+<code>
+../install/bin/zpu-elf-objdump -O binary hello.elf hello.bin<br>
+java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin &gt;hello.bram<br>
+
+</code>
+<h2>Running example simulation</h2>
+The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt:
+<ol>
+<li>cd c:/&lt;installfolder&gt;/hdl/example
+<li>do zpusim.do
+</ol>
+<p>
+After running the hello world simulation (see zpusim.do), two files are written to the hdl/exmaple directory:
+<ol>
+<li>log.txt - contains the "Hello world!" text written to the debug channel/simplified UART.
+<li>trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking
+this file as input in order to verify that the HDL implementation matches the instruction set simulator.
+When a mismatch is found, the GDB debugger will break. Very handy for debugging custom ZPU implementations.
+</ol>
+<h2>HDL Directories & files </h2>
+<ul>
+<li>example - contains example files & working ZPU. Start here.
+<li>wishbone - contains wishbone interface for the ZPU
+<li>zpu3 - if you are interested in developing ZPU cores and not only using them, then this directory contains various stuff of more or less historical interest.
+<li>zpu4 - if you are interested in developing ZPU cores and not only using them, then this is the active development version. You'll also want to copy out the
+files you need from this folder to your own project.
+</ul>
+
+The HDL files need a bit of spit and polish!
+</body>
+</html>
diff --git a/zpu/hdl/wishbone/wishbone_pkg.vhd b/zpu/hdl/wishbone/wishbone_pkg.vhd
new file mode 100644
index 0000000..c3b0d9b
--- /dev/null
+++ b/zpu/hdl/wishbone/wishbone_pkg.vhd
@@ -0,0 +1,52 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+ type wishbone_bus_in is record
+ adr : std_logic_vector(31 downto 0);
+ sel : std_logic_vector(3 downto 0);
+ we : std_logic;
+ dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we'
+ cyc : std_logic;
+ stb : std_logic;
+ end record;
+
+ type wishbone_bus_out is record
+ dat : std_logic_vector(31 downto 0);
+ ack : std_logic;
+ end record;
+
+ type wishbone_bus is record
+ insig : wishbone_bus_in;
+ outsig : wishbone_bus_out;
+ end record;
+
+ component atomic32_access is
+ port ( cpu_clk : in std_logic;
+ areset : in std_logic;
+
+ -- Wishbone from CPU interface
+ wb_16_i : in wishbone_bus_in;
+ wb_16_o : out wishbone_bus_out;
+ -- Wishbone to FPGA registers and ethernet core
+ wb_32_i : in wishbone_bus_out;
+ wb_32_o : out wishbone_bus_in);
+ end component;
+
+ component eth_access_corr is
+ port ( cpu_clk : in std_logic;
+ areset : in std_logic;
+
+ -- Wishbone from Wishbone MUX
+ eth_raw_o : out wishbone_bus_out;
+ eth_raw_i : in wishbone_bus_in;
+
+ -- Wishbone ethernet core
+ eth_slave_i : in wishbone_bus_out;
+ eth_slave_o : out wishbone_bus_in);
+ end component;
+
+
+end wishbone_pkg;
diff --git a/zpu/hdl/wishbone/zpu_system.vhd b/zpu/hdl/wishbone/zpu_system.vhd
new file mode 100644
index 0000000..6e79370
--- /dev/null
+++ b/zpu/hdl/wishbone/zpu_system.vhd
@@ -0,0 +1,71 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+use work.ic300pkg.all;
+
+entity zpu_system is
+ generic(
+ simulate : boolean := false);
+ port ( areset : in std_logic;
+ cpu_clk : in std_logic;
+
+ -- ZPU Control signals
+ enable : in std_logic;
+ interrupt : in std_logic;
+
+ zpu_status : out std_logic_vector(63 downto 0);
+
+ -- wishbone interfaces
+ zpu_wb_i : in wishbone_bus_out;
+ zpu_wb_o : out wishbone_bus_in);
+end zpu_system;
+
+architecture behave of zpu_system is
+
+signal mem_req : std_logic;
+signal mem_we : std_logic;
+signal mem_ack : std_logic;
+signal mem_read : std_logic_vector(wordSize-1 downto 0);
+signal mem_write : std_logic_vector(wordSize-1 downto 0);
+signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+
+begin
+
+ my_zpu_core:
+ zpu_core port map (
+ clk => cpu_clk,
+ areset => areset,
+ enable => enable,
+ mem_req => mem_req,
+ mem_we => mem_we,
+ mem_ack => mem_ack,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => out_mem_addr,
+ mem_writeMask => mem_writeMask,
+ interrupt => interrupt,
+ zpu_status => zpu_status,
+ break => open);
+
+ my_zpu_wb_bridge:
+ zpu_wb_bridge port map (
+ clk => cpu_clk,
+ areset => areset,
+ mem_req => mem_req,
+ mem_we => mem_we,
+ mem_ack => mem_ack,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => out_mem_addr,
+ mem_writeMask => mem_writeMask,
+ zpu_wb_i => zpu_wb_i,
+ zpu_wb_o => zpu_wb_o);
+
+end behave;
diff --git a/zpu/hdl/wishbone/zpu_wb_bridge.vhd b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
new file mode 100644
index 0000000..4182f7a
--- /dev/null
+++ b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
@@ -0,0 +1,49 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.phi_config.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_wb_bridge is
+ port ( -- Native ZPU interface
+ clk : in std_logic;
+ areset : in std_logic;
+
+ mem_req : in std_logic;
+ mem_we : in std_logic;
+ mem_ack : out std_logic;
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0);
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0);
+
+ -- Wishbone from ZPU
+ zpu_wb_i : in wishbone_bus_out;
+ zpu_wb_o : out wishbone_bus_in);
+
+end zpu_wb_bridge;
+
+architecture behave of zpu_wb_bridge is
+
+begin
+
+ mem_read <= zpu_wb_i.dat;
+ mem_ack <= zpu_wb_i.ack;
+
+ zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0);
+ zpu_wb_o.dat <= mem_write;
+ zpu_wb_o.sel <= mem_writeMask;
+ zpu_wb_o.stb <= mem_req;
+ zpu_wb_o.cyc <= mem_req;
+ zpu_wb_o.we <= mem_we;
+
+end behave;
+
+
+
+
+
diff --git a/zpu/hdl/zpu3/src/.cvsignore b/zpu/hdl/zpu3/src/.cvsignore
new file mode 100644
index 0000000..760be11
--- /dev/null
+++ b/zpu/hdl/zpu3/src/.cvsignore
@@ -0,0 +1 @@
+xilinx_device_details.xml
diff --git a/zpu/hdl/zpu3/src/build.xml b/zpu/hdl/zpu3/src/build.xml
new file mode 100644
index 0000000..e1b268a
--- /dev/null
+++ b/zpu/hdl/zpu3/src/build.xml
@@ -0,0 +1,114 @@
+<!--
+
+FIX!!! start /b /wait /belownormal does not propagate return code..
+-->
+<project name="ZPU3" default="all" basedir=".">
+ <property name="chipname" value="ic300"/>
+ <property name="packagetype" value="xc3s400-ft256-4"/>
+
+
+ <description>eCosBoard firmware build file</description>
+
+ <target name="setuplibs">
+ <!-- N/A yet
+ <copy todir="../src">
+ <fileset dir="..\fpgalib\" includes="foo_top.ngc" />
+ </copy>
+ -->
+ </target>
+
+ <target name="setup">
+ <mkdir dir="..\reports"/>
+ <mkdir dir="..\syn"/>
+ <mkdir dir="..\ngo"/>
+ <mkdir dir="..\output"/>
+ <mkdir dir="..\tmp"/>
+ <mkdir dir="..\xst"/>
+ </target>
+
+ <target name="clean">
+ <delete dir="..\reports"/>
+ <delete dir="..\syn"/>
+ <delete dir="..\ngo"/>
+ <delete dir="..\output"/>
+ <delete dir="..\tmp"/>
+ <delete dir="..\xst"/>
+ </target>
+
+ <target name="synthesis" depends="setup">
+ <exec executable="cmd" failonerror="true">
+ <arg line="/c xst -intstyle ise -ifn xmake.xst -ofn ..\reports\1_synthesis.txt"/>
+ </exec>
+ </target>
+
+
+ <target name="translate" depends="setup">
+ <exec executable="cmd" failonerror="true">
+ <arg line="/c ngdbuild -intstyle ise -dd ..\ngo -uc ${chipname}.ucf -a -p ${packagetype} ..\syn\${chipname}.ngc ..\ngo\${chipname}.ngd"/>
+ </exec>
+ <move tofile="..\reports\2_translate.txt">
+ <fileset dir="..\ngo" includes="${chipname}.bld"/>
+ </move>
+ </target>
+
+ <target name="mapping" depends="setup">
+ <exec executable="cmd" failonerror="true">
+ <arg line="/c map -intstyle ise -p ${packagetype} -ol high -timing -detail -cm area -ignore_keep_hierarchy -pr b -k 6 -r -c 100 -tx off -o ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ngd ..\ngo\${chipname}.pcf"/>
+ </exec>
+ <move tofile="..\reports\3_mapping.txt">
+ <fileset dir="..\ngo" includes="${chipname}_map.mrp"/>
+ </move>
+ </target>
+
+
+ <target name="placeandroute" depends="setup">
+ <exec executable="cmd" failonerror="true">
+ <arg line="/c par -w -intstyle ise -ol high -t 1 ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ncd ..\ngo\${chipname}.pcf"/>
+ </exec>
+ <move tofile="..\reports\4_placeandroute.txt">
+ <fileset dir="..\ngo" includes="${chipname}.par"/>
+ </move>
+ <move tofile="..\reports\5_pads.txt">
+ <fileset dir="..\ngo" includes="${chipname}_pad.txt"/>
+ </move>
+ </target>
+
+
+ <target name="gentime" depends="setup">
+ <exec executable="cmd" failonerror="true">
+ <arg line="/c trce -intstyle ise -v 3 -l 3 -a -u 100 ..\ngo\${chipname}.ncd -o ..\reports\timing.twr ..\ngo\${chipname}.pcf"/>
+ </exec>
+ <delete file="..\reports\6_timing.txt"/>
+ <move tofile="..\reports\6_timing.txt">
+ <fileset dir="..\reports" includes="timing.twr"/>
+ </move>
+ </target>
+
+
+ <target name="genbit" depends="setup">
+ <exec executable="cmd" failonerror="true">
+ <arg line="/c bitgen -intstyle ise -w -f ${chipname}.bitgen ..\ngo\${chipname}.ncd"/>
+ </exec>
+ <move tofile="..\reports\7_bitgen.txt">
+ <fileset dir="..\ngo" includes="${chipname}.bgn"/>
+ </move>
+ </target>
+
+ <target name="copyfiles" depends="setup">
+ <copy todir="../output">
+ <fileset dir="..\ngo" includes="${chipname}.bin"/>
+ </copy>
+ <!--
+ <copy tofile="${workspace_loc}\firmware\board\xeddvifpgadata.rawdata">
+ <fileset dir="..\ngo" includes="${chipname}.bin"/>
+ </copy>
+ -->
+ </target>
+
+
+ <target name="all" depends="setuplibs,synthesis,translate,mapping,placeandroute,gentime,genbit,copyfiles">
+
+ </target>
+
+
+</project> \ No newline at end of file
diff --git a/zpu/hdl/zpu3/src/clocks.vhd b/zpu/hdl/zpu3/src/clocks.vhd
new file mode 100644
index 0000000..a352b3c
--- /dev/null
+++ b/zpu/hdl/zpu3/src/clocks.vhd
@@ -0,0 +1,246 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clocks is
+ port ( areset : in std_logic;
+ cpu_clk_p : in std_logic;
+ sdr_clk_fb_p : in std_logic;
+ cpu_clk : out std_logic;
+ cpu_clk_2x : out std_logic;
+ cpu_clk_4x : out std_logic;
+ ddr_in_clk : out std_logic;
+ ddr_in_clk_2x : out std_logic;
+ locked : out std_logic_vector(2 downto 0));
+end clocks;
+
+architecture behave of clocks is
+
+signal low : std_logic;
+
+signal cpu_clk_in : std_logic;
+signal sdr_clk_fb_in : std_logic;
+
+signal dcm_cpu1 : std_logic;
+signal dcm_cpu2 : std_logic;
+signal dcm_cpu2_dum : std_logic;
+signal dcm_cpu4 : std_logic;
+signal dcm_ddr2 : std_logic;
+signal dcm_ddr2_2x : std_logic;
+
+signal cpu_clk_int : std_logic;
+signal cpu_clk_2x_int : std_logic;
+signal cpu_clk_2x_dum_int : std_logic;
+signal cpu_clk_4x_int : std_logic;
+signal ddr_in_clk_int : std_logic;
+signal ddr_in_clk_2x_int : std_logic;
+
+signal dcm1_locked_del : std_logic;
+signal dcm2_locked_del : std_logic;
+signal dcm2_reset : std_logic;
+signal dcm3_reset : std_logic;
+
+signal locked_int : std_logic_vector(2 downto 0);
+signal del_addr : std_logic_vector(3 downto 0);
+
+begin
+
+ low <= '0';
+ del_addr <= "1111";
+
+ cpu_clk <= cpu_clk_int;
+ cpu_clk_2x <= cpu_clk_2x_int;
+ cpu_clk_4x <= cpu_clk_4x_int;
+ ddr_in_clk <= ddr_in_clk_int;
+ ddr_in_clk_2x <= ddr_in_clk_2x_int;
+ locked <= locked_int;
+
+
+ CPU_IBUFG:
+ IBUFG port map (
+ O => cpu_clk_in,
+ I => cpu_clk_p);
+
+ SDR_FB_IBUFG:
+ IBUFG port map (
+ O => sdr_clk_fb_in,
+ I => sdr_clk_fb_p);
+
+ dcm2_rst:
+ SRL16 generic map (
+ INIT => X"0000")
+ port map (
+ Q => dcm1_locked_del,
+ A0 => del_addr(0),
+ A1 => del_addr(1),
+ A2 => del_addr(2),
+ A3 => del_addr(3),
+ CLK => cpu_clk_int,
+ D => locked_int(0));
+
+ dcm2_reset <= not(dcm1_locked_del);
+
+ dcm3_rst:
+ SRL16 generic map (
+ INIT => X"0000")
+ port map (
+ Q => dcm2_locked_del,
+ A0 => del_addr(0),
+ A1 => del_addr(1),
+ A2 => del_addr(2),
+ A3 => del_addr(3),
+ CLK => cpu_clk_int,
+ D => locked_int(1));
+
+ dcm3_reset <= not(dcm2_locked_del);
+
+ cpu1_dcm:
+ DCM generic map (
+ CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+ -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+ CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
+ CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
+ CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+ CLKIN_PERIOD => 15.625, -- Specify period of input clock
+ CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+ CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+ -- an integer from 0 to 15
+ DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
+ DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
+ DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+ FACTORY_JF => X"8080", -- FACTORY JF Values
+ PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
+ STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ port map (
+ CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput
+ CLK180 => open, -- 180 degree DCM CLK output
+ CLK270 => open, -- 270 degree DCM CLK output
+ CLK2X => dcm_cpu2, -- 2X DCM CLK output
+ CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+ CLK90 => open, -- 90 degree DCM CLK output
+ CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+ CLKFX => open, -- DCM CLK synthesis out (M/D)
+ CLKFX180 => open, -- 180 degree CLK synthesis out
+ LOCKED => locked_int(0), -- DCM LOCK status output
+ PSDONE => open, -- Dynamic phase adjust done output
+ STATUS => open, -- 8-bit DCM status bits output
+ CLKFB => cpu_clk_int, -- DCM clock feedback
+ CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM)
+ PSCLK => low, -- Dynamic phase adjust clock input
+ PSEN => low, -- Dynamic phase adjust enable input
+ PSINCDEC => low, -- Dynamic phase adjust increment/decrement
+ RST => areset); -- DCM asynchronous reset input
+
+ cpu2_dcm:
+ DCM generic map (
+ CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+ -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+ CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
+ CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
+ CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+ CLKIN_PERIOD => 7.8125, -- Specify period of input clock
+ CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+ CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+ -- an integer from 0 to 15
+ DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
+ DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
+ DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+ FACTORY_JF => X"8080", -- FACTORY JF Values
+ PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
+ STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ port map (
+ CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput
+ CLK180 => open, -- 180 degree DCM CLK output
+ CLK270 => open, -- 270 degree DCM CLK output
+ CLK2X => dcm_cpu4, -- 2X DCM CLK output
+ CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+ CLK90 => open, -- 90 degree DCM CLK output
+ CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+ CLKFX => open, -- DCM CLK synthesis out (M/D)
+ CLKFX180 => open, -- 180 degree CLK synthesis out
+ LOCKED => locked_int(1), -- DCM LOCK status output
+ PSDONE => open, -- Dynamic phase adjust done output
+ STATUS => open, -- 8-bit DCM status bits output
+ CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback
+ CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM)
+ PSCLK => low, -- Dynamic phase adjust clock input
+ PSEN => low, -- Dynamic phase adjust enable input
+ PSINCDEC => low, -- Dynamic phase adjust increment/decrement
+ RST => dcm2_reset); -- DCM asynchronous reset input
+
+ ddr_read_dcm:
+ DCM generic map (
+ CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+ -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+ CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
+ CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
+ CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+ CLKIN_PERIOD => 7.8125, -- Specify period of input clock
+ CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE
+-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+ CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+ -- an integer from 0 to 15
+ DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
+ DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
+ DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+ FACTORY_JF => X"8080", -- FACTORY JF Values
+ PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255
+-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
+ STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ port map (
+ CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput
+ CLK180 => open, -- 180 degree DCM CLK output
+ CLK270 => open, -- 270 degree DCM CLK output
+ CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output
+ CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+ CLK90 => open, -- 90 degree DCM CLK output
+ CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+ CLKFX => open, -- DCM CLK synthesis out (M/D)
+ CLKFX180 => open, -- 180 degree CLK synthesis out
+ LOCKED => locked_int(2), -- DCM LOCK status output
+ PSDONE => open, -- Dynamic phase adjust done output
+ STATUS => open, -- 8-bit DCM status bits output
+ CLKFB => ddr_in_clk_int, -- DCM clock feedback
+ CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
+ PSCLK => low, -- Dynamic phase adjust clock input
+ PSEN => low, -- Dynamic phase adjust enable input
+ PSINCDEC => low, -- Dynamic phase adjust increment/decrement
+ RST => dcm3_reset); -- DCM asynchronous reset input
+
+ cpu1:
+ BUFG port map (
+ I => dcm_cpu1,
+ O => cpu_clk_int);
+
+ cpu2:
+ BUFG port map (
+ I => dcm_cpu2,
+ O => cpu_clk_2x_int);
+
+ cpu2_dum:
+ BUFG port map (
+ I => dcm_cpu2_dum,
+ O => cpu_clk_2x_dum_int);
+
+ cpu4:
+ BUFG port map (
+ I => dcm_cpu4,
+ O => cpu_clk_4x_int);
+
+ ddr_clk:
+ BUFG port map (
+ I => dcm_ddr2,
+ O => ddr_in_clk_int);
+
+ ddr_clk_2x:
+ BUFG port map (
+ I => dcm_ddr2_2x,
+ O => ddr_in_clk_2x_int);
+
+end behave; \ No newline at end of file
diff --git a/zpu/hdl/zpu3/src/ddr_bridge.vhd b/zpu/hdl/zpu3/src/ddr_bridge.vhd
new file mode 100644
index 0000000..7dece76
--- /dev/null
+++ b/zpu/hdl/zpu3/src/ddr_bridge.vhd
@@ -0,0 +1,203 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library zylin;
+use zylin.ddr.all;
+
+library work;
+use work.phi_config.all;
+
+entity ddr_bridge is
+ port ( areset : in std_logic;
+ cpu_clk : in std_logic;
+ cpu_clk_2x : in std_logic;
+ cpu_clk_4x : in std_logic;
+ ddr_in_clk : in std_logic;
+ ddr_in_clk_2x : in std_logic;
+
+ cpu_we : in std_logic_vector(1 downto 0);
+ cpu_re : in std_logic;
+ cpu_din : in std_logic_vector(15 downto 0);
+ cpu_a : in std_logic_vector(20 downto 0);
+ cpu_dout : inout std_logic_vector(15 downto 0);
+
+ sdr_clk_p : out std_logic; -- ddr_sdram_clock
+ sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
+ cke_q_p : out std_logic; -- clock enable
+ cs_qn_p : out std_logic; -- /chip select
+ ras_qn_p : inout std_logic; -- /ras
+ cas_qn_p : inout std_logic; -- /cas
+ we_qn_p : inout std_logic; -- /write enable
+ dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
+ dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
+ ba_q_p : out std_logic_vector(1 downto 0); -- bank select
+ sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
+ sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus
+end ddr_bridge;
+
+architecture behave of ddr_bridge is
+
+signal refresh_en : std_logic;
+signal ddr_command_we : std_logic;
+signal ddr_command : std_logic_vector(15 downto 0);
+
+signal ddr_req : std_logic;
+signal ddr_req_adr : std_logic_vector(23 downto 1);
+signal ddr_rd_wr_n : std_logic;
+signal ddr_req_len : std_logic;
+
+signal ddr_read_en : std_logic;
+signal ddr_write_en : std_logic;
+signal ddr_data_read : std_logic_vector(31 downto 0);
+signal ddr_data_write : std_logic_vector(35 downto 0);
+
+signal ddr_read_smp : std_logic_vector(31 downto 0);
+signal ddr_read_delay : std_logic_vector(15 downto 0);
+
+signal ddr_write_smp : std_logic_vector(15 downto 0);
+signal ddr_addr_smp : std_logic_vector(15 downto 0);
+
+signal ddr_req_type_smp : std_logic;
+signal ddr_req_on : std_logic;
+signal ddr_req_off : std_logic;
+signal ddr_req_int : std_logic;
+
+constant Sim_Delay : time := 1.0 ns;
+
+begin
+
+ ddr_req_len <= '0';
+ ddr_data_write <= "0000" & ddr_write_smp & ddr_write_smp;
+ ddr_req_adr <= "0000000" & ddr_addr_smp;
+ ddr_rd_wr_n <= ddr_req_type_smp;
+ ddr_req <= ddr_req_int;
+
+ process(cpu_clk, areset) -- CPU writeable registers
+ begin
+ if areset = '1' then
+ refresh_en <= '0';
+ ddr_command_we <= '0';
+ ddr_command <= "0000000000000000";
+ ddr_write_smp <= "0000000000000000";
+ ddr_req_type_smp <= '0';
+ ddr_req_on <= '0';
+ elsif (cpu_clk'event and cpu_clk = '1') then
+
+ if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Ctrl_Reg_Addr then
+ refresh_en <= cpu_din(0);
+ else
+ refresh_en <= refresh_en;
+ end if;
+
+ if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Mode_Reg_Addr then
+ ddr_command <= cpu_din;
+ ddr_command_we <= '1';
+ else
+ ddr_command <= ddr_command;
+ ddr_command_we <= '0';
+ end if;
+
+ if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr then
+ ddr_write_smp <= cpu_din;
+ else
+ ddr_write_smp <= ddr_write_smp;
+ end if;
+
+ if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Addr_Reg_Addr then
+ ddr_addr_smp <= cpu_din;
+ else
+ ddr_addr_smp <= ddr_addr_smp;
+ end if;
+
+ if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Req_Reg_Addr then
+ ddr_req_type_smp <= cpu_din(0);
+ ddr_req_on <= '1';
+ else
+ ddr_req_type_smp <= ddr_req_type_smp;
+ ddr_req_on <= '0';
+ end if;
+
+ end if;
+ end process;
+
+ -- CPU readable registers
+ cpu_dout <= ddr_read_delay when (cpu_re = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr) else "ZZZZZZZZZZZZZZZZ";
+
+ -- Capture data read from DDR
+ process(cpu_clk_2x, areset)
+ begin
+ if areset = '1' then
+ ddr_read_smp <= (others => '0');
+ elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+ if ddr_read_en = '1' then
+ ddr_read_smp <= ddr_data_read after Sim_Delay;
+ else
+ ddr_read_smp <= ddr_read_smp after Sim_Delay;
+ end if;
+ end if;
+ end process;
+
+ -- Move captured data from DDR to cpu_clk domain (for better routing timing)
+ process(cpu_clk, areset)
+ begin
+ if areset = '1' then
+ ddr_read_delay <= "0000000000000000";
+ elsif (cpu_clk'event and cpu_clk = '1') then
+ ddr_read_delay <= ddr_read_smp(15 downto 0);
+ end if;
+ end process;
+
+ process(cpu_clk_2x, areset)
+ begin
+ if areset = '1' then
+ ddr_req_int <= '0';
+ elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+ if ddr_req_on = '1' then
+ ddr_req_int <= '1' after Sim_Delay;
+ elsif ddr_read_en = '1' or ddr_write_en = '1' then
+ ddr_req_int <= '0' after Sim_Delay;
+ else
+ ddr_req_int <= ddr_req_int after Sim_Delay;
+ end if;
+ end if;
+ end process;
+
+
+ ddr_interface:
+ ddr_top port map(
+ areset => areset,
+ cpu_clk => cpu_clk,
+ cpu_clk_2x => cpu_clk_2x,
+ cpu_clk_4x => cpu_clk_4x,
+ ddr_in_clk => ddr_in_clk,
+ ddr_in_clk_2x => ddr_in_clk_2x,
+ ddr_command => ddr_command,
+ ddr_command_we => ddr_command_we,
+ refresh_en => refresh_en,
+ ddr_data_read => ddr_data_read,
+ ddr_data_write => ddr_data_write,
+ ddr_req => ddr_req,
+ ddr_req_adr => ddr_req_adr,
+ ddr_rd_wr_n => ddr_rd_wr_n,
+ ddr_req_len => ddr_req_len,
+ ddr_read_en => ddr_read_en,
+ ddr_write_en => ddr_write_en,
+ sdr_clk_p => sdr_clk_p,
+ sdr_clk_n_p => sdr_clk_n_p,
+ cke_q_p => cke_q_p,
+ cs_qn_p => cs_qn_p,
+ ras_qn_p => ras_qn_p,
+ cas_qn_p => cas_qn_p,
+ we_qn_p => we_qn_p,
+ dm_q_p => dm_q_p,
+ dqs_q_p => dqs_q_p,
+ ba_q_p => ba_q_p,
+ sdr_a_p => sdr_a_p,
+ sdr_d_p => sdr_d_p);
+
+
+end behave;
diff --git a/zpu/hdl/zpu3/src/dmips_ram.vhd b/zpu/hdl/zpu3/src/dmips_ram.vhd
new file mode 100644
index 0000000..f472653
--- /dev/null
+++ b/zpu/hdl/zpu3/src/dmips_ram.vhd
@@ -0,0 +1,3824 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"800b0b0b",
+1 => x"0b0b8070",
+2 => x"0b0b80e5",
+3 => x"d00c3a0b",
+4 => x"0b0bbed7",
+5 => x"04000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0bbfa72d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"0b0b0400",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"530b0b51",
+38 => x"04000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"0b0b5104",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"530b0b51",
+55 => x"04000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"0b0b5104",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c6040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a530b0b",
+82 => x"51040000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"0607530b",
+101 => x"0b510400",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"7171530b",
+105 => x"0b510406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"0b0b5104",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"530b0b51",
+125 => x"04000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"520b0b04",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
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+3229 => x"08080808",
+3230 => x"08080808",
+3231 => x"08080808",
+3232 => x"08080808",
+3233 => x"08080808",
+3234 => x"08080808",
+3235 => x"08080808",
+3236 => x"08080808",
+3237 => x"08080808",
+3238 => x"08080808",
+3239 => x"08080808",
+3240 => x"08080808",
+3241 => x"08080808",
+3242 => x"08080808",
+3243 => x"08080808",
+3244 => x"08080808",
+3245 => x"08080808",
+3246 => x"08080808",
+3247 => x"00ffffff",
+3248 => x"ff00ffff",
+3249 => x"ffff00ff",
+3250 => x"ffffff00",
+3251 => x"00000000",
+3252 => x"00000000",
+3253 => x"00000000",
+3254 => x"00003ab8",
+3255 => x"000186a0", -- iterations
+3256 => x"00000000",
+3257 => x"00000000",
+3258 => x"00000000",
+3259 => x"00000000",
+3260 => x"00000000",
+3261 => x"00000000",
+3262 => x"00000000",
+3263 => x"00000000",
+3264 => x"00000000",
+3265 => x"00000000",
+3266 => x"00000000",
+3267 => x"00000000",
+3268 => x"00000000",
+3269 => x"ffffffff",
+3270 => x"00000000",
+3271 => x"00020000",
+3272 => x"00000000",
+3273 => x"00000000",
+3274 => x"00003320",
+3275 => x"00003320",
+3276 => x"00003328",
+3277 => x"00003328",
+3278 => x"00003330",
+3279 => x"00003330",
+3280 => x"00003338",
+3281 => x"00003338",
+3282 => x"00003340",
+3283 => x"00003340",
+3284 => x"00003348",
+3285 => x"00003348",
+3286 => x"00003350",
+3287 => x"00003350",
+3288 => x"00003358",
+3289 => x"00003358",
+3290 => x"00003360",
+3291 => x"00003360",
+3292 => x"00003368",
+3293 => x"00003368",
+3294 => x"00003370",
+3295 => x"00003370",
+3296 => x"00003378",
+3297 => x"00003378",
+3298 => x"00003380",
+3299 => x"00003380",
+3300 => x"00003388",
+3301 => x"00003388",
+3302 => x"00003390",
+3303 => x"00003390",
+3304 => x"00003398",
+3305 => x"00003398",
+3306 => x"000033a0",
+3307 => x"000033a0",
+3308 => x"000033a8",
+3309 => x"000033a8",
+3310 => x"000033b0",
+3311 => x"000033b0",
+3312 => x"000033b8",
+3313 => x"000033b8",
+3314 => x"000033c0",
+3315 => x"000033c0",
+3316 => x"000033c8",
+3317 => x"000033c8",
+3318 => x"000033d0",
+3319 => x"000033d0",
+3320 => x"000033d8",
+3321 => x"000033d8",
+3322 => x"000033e0",
+3323 => x"000033e0",
+3324 => x"000033e8",
+3325 => x"000033e8",
+3326 => x"000033f0",
+3327 => x"000033f0",
+3328 => x"000033f8",
+3329 => x"000033f8",
+3330 => x"00003400",
+3331 => x"00003400",
+3332 => x"00003408",
+3333 => x"00003408",
+3334 => x"00003410",
+3335 => x"00003410",
+3336 => x"00003418",
+3337 => x"00003418",
+3338 => x"00003420",
+3339 => x"00003420",
+3340 => x"00003428",
+3341 => x"00003428",
+3342 => x"00003430",
+3343 => x"00003430",
+3344 => x"00003438",
+3345 => x"00003438",
+3346 => x"00003440",
+3347 => x"00003440",
+3348 => x"00003448",
+3349 => x"00003448",
+3350 => x"00003450",
+3351 => x"00003450",
+3352 => x"00003458",
+3353 => x"00003458",
+3354 => x"00003460",
+3355 => x"00003460",
+3356 => x"00003468",
+3357 => x"00003468",
+3358 => x"00003470",
+3359 => x"00003470",
+3360 => x"00003478",
+3361 => x"00003478",
+3362 => x"00003480",
+3363 => x"00003480",
+3364 => x"00003488",
+3365 => x"00003488",
+3366 => x"00003490",
+3367 => x"00003490",
+3368 => x"00003498",
+3369 => x"00003498",
+3370 => x"000034a0",
+3371 => x"000034a0",
+3372 => x"000034a8",
+3373 => x"000034a8",
+3374 => x"000034b0",
+3375 => x"000034b0",
+3376 => x"000034b8",
+3377 => x"000034b8",
+3378 => x"000034c0",
+3379 => x"000034c0",
+3380 => x"000034c8",
+3381 => x"000034c8",
+3382 => x"000034d0",
+3383 => x"000034d0",
+3384 => x"000034d8",
+3385 => x"000034d8",
+3386 => x"000034e0",
+3387 => x"000034e0",
+3388 => x"000034e8",
+3389 => x"000034e8",
+3390 => x"000034f0",
+3391 => x"000034f0",
+3392 => x"000034f8",
+3393 => x"000034f8",
+3394 => x"00003500",
+3395 => x"00003500",
+3396 => x"00003508",
+3397 => x"00003508",
+3398 => x"00003510",
+3399 => x"00003510",
+3400 => x"00003518",
+3401 => x"00003518",
+3402 => x"00003520",
+3403 => x"00003520",
+3404 => x"00003528",
+3405 => x"00003528",
+3406 => x"00003530",
+3407 => x"00003530",
+3408 => x"00003538",
+3409 => x"00003538",
+3410 => x"00003540",
+3411 => x"00003540",
+3412 => x"00003548",
+3413 => x"00003548",
+3414 => x"00003550",
+3415 => x"00003550",
+3416 => x"00003558",
+3417 => x"00003558",
+3418 => x"00003560",
+3419 => x"00003560",
+3420 => x"00003568",
+3421 => x"00003568",
+3422 => x"00003570",
+3423 => x"00003570",
+3424 => x"00003578",
+3425 => x"00003578",
+3426 => x"00003580",
+3427 => x"00003580",
+3428 => x"00003588",
+3429 => x"00003588",
+3430 => x"00003590",
+3431 => x"00003590",
+3432 => x"00003598",
+3433 => x"00003598",
+3434 => x"000035a0",
+3435 => x"000035a0",
+3436 => x"000035a8",
+3437 => x"000035a8",
+3438 => x"000035b0",
+3439 => x"000035b0",
+3440 => x"000035b8",
+3441 => x"000035b8",
+3442 => x"000035c0",
+3443 => x"000035c0",
+3444 => x"000035c8",
+3445 => x"000035c8",
+3446 => x"000035d0",
+3447 => x"000035d0",
+3448 => x"000035d8",
+3449 => x"000035d8",
+3450 => x"000035e0",
+3451 => x"000035e0",
+3452 => x"000035e8",
+3453 => x"000035e8",
+3454 => x"000035f0",
+3455 => x"000035f0",
+3456 => x"000035f8",
+3457 => x"000035f8",
+3458 => x"00003600",
+3459 => x"00003600",
+3460 => x"00003608",
+3461 => x"00003608",
+3462 => x"00003610",
+3463 => x"00003610",
+3464 => x"00003618",
+3465 => x"00003618",
+3466 => x"00003620",
+3467 => x"00003620",
+3468 => x"00003628",
+3469 => x"00003628",
+3470 => x"00003630",
+3471 => x"00003630",
+3472 => x"00003638",
+3473 => x"00003638",
+3474 => x"00003640",
+3475 => x"00003640",
+3476 => x"00003648",
+3477 => x"00003648",
+3478 => x"00003650",
+3479 => x"00003650",
+3480 => x"00003658",
+3481 => x"00003658",
+3482 => x"00003660",
+3483 => x"00003660",
+3484 => x"00003668",
+3485 => x"00003668",
+3486 => x"00003670",
+3487 => x"00003670",
+3488 => x"00003678",
+3489 => x"00003678",
+3490 => x"00003680",
+3491 => x"00003680",
+3492 => x"00003688",
+3493 => x"00003688",
+3494 => x"00003690",
+3495 => x"00003690",
+3496 => x"00003698",
+3497 => x"00003698",
+3498 => x"000036a0",
+3499 => x"000036a0",
+3500 => x"000036a8",
+3501 => x"000036a8",
+3502 => x"000036b0",
+3503 => x"000036b0",
+3504 => x"000036b8",
+3505 => x"000036b8",
+3506 => x"000036c0",
+3507 => x"000036c0",
+3508 => x"000036c8",
+3509 => x"000036c8",
+3510 => x"000036d0",
+3511 => x"000036d0",
+3512 => x"000036d8",
+3513 => x"000036d8",
+3514 => x"000036e0",
+3515 => x"000036e0",
+3516 => x"000036e8",
+3517 => x"000036e8",
+3518 => x"000036f0",
+3519 => x"000036f0",
+3520 => x"000036f8",
+3521 => x"000036f8",
+3522 => x"00003700",
+3523 => x"00003700",
+3524 => x"00003708",
+3525 => x"00003708",
+3526 => x"00003710",
+3527 => x"00003710",
+3528 => x"00003718",
+3529 => x"00003718",
+3530 => x"0000372c",
+3531 => x"00000000",
+3532 => x"00003994",
+3533 => x"000039f0",
+3534 => x"00003a4c",
+3535 => x"00000000",
+3536 => x"00000000",
+3537 => x"00000000",
+3538 => x"00000000",
+3539 => x"00000000",
+3540 => x"00000000",
+3541 => x"00000000",
+3542 => x"00000000",
+3543 => x"00000000",
+3544 => x"000031ac",
+3545 => x"00000000",
+3546 => x"00000000",
+3547 => x"00000000",
+3548 => x"00000000",
+3549 => x"00000000",
+3550 => x"00000000",
+3551 => x"00000000",
+3552 => x"00000000",
+3553 => x"00000000",
+3554 => x"00000000",
+3555 => x"00000000",
+3556 => x"00000000",
+3557 => x"00000000",
+3558 => x"00000000",
+3559 => x"00000000",
+3560 => x"00000000",
+3561 => x"00000000",
+3562 => x"00000000",
+3563 => x"00000000",
+3564 => x"00000000",
+3565 => x"00000000",
+3566 => x"00000000",
+3567 => x"00000000",
+3568 => x"00000000",
+3569 => x"00000000",
+3570 => x"00000000",
+3571 => x"00000000",
+3572 => x"00000000",
+3573 => x"00000001",
+3574 => x"330eabcd",
+3575 => x"1234e66d",
+3576 => x"deec0005",
+3577 => x"000b0000",
+3578 => x"00000000",
+3579 => x"00000000",
+3580 => x"00000000",
+3581 => x"00000000",
+3582 => x"00000000",
+3583 => x"00000000",
+3584 => x"00000000",
+3585 => x"00000000",
+3586 => x"00000000",
+3587 => x"00000000",
+3588 => x"00000000",
+3589 => x"00000000",
+3590 => x"00000000",
+3591 => x"00000000",
+3592 => x"00000000",
+3593 => x"00000000",
+3594 => x"00000000",
+3595 => x"00000000",
+3596 => x"00000000",
+3597 => x"00000000",
+3598 => x"00000000",
+3599 => x"00000000",
+3600 => x"00000000",
+3601 => x"00000000",
+3602 => x"00000000",
+3603 => x"00000000",
+3604 => x"00000000",
+3605 => x"00000000",
+3606 => x"00000000",
+3607 => x"00000000",
+3608 => x"00000000",
+3609 => x"00000000",
+3610 => x"00000000",
+3611 => x"00000000",
+3612 => x"00000000",
+3613 => x"00000000",
+3614 => x"00000000",
+3615 => x"00000000",
+3616 => x"00000000",
+3617 => x"00000000",
+3618 => x"00000000",
+3619 => x"00000000",
+3620 => x"00000000",
+3621 => x"00000000",
+3622 => x"00000000",
+3623 => x"00000000",
+3624 => x"00000000",
+3625 => x"00000000",
+3626 => x"00000000",
+3627 => x"00000000",
+3628 => x"00000000",
+3629 => x"00000000",
+3630 => x"00000000",
+3631 => x"00000000",
+3632 => x"00000000",
+3633 => x"00000000",
+3634 => x"00000000",
+3635 => x"00000000",
+3636 => x"00000000",
+3637 => x"00000000",
+3638 => x"00000000",
+3639 => x"00000000",
+3640 => x"00000000",
+3641 => x"00000000",
+3642 => x"00000000",
+3643 => x"00000000",
+3644 => x"00000000",
+3645 => x"00000000",
+3646 => x"00000000",
+3647 => x"00000000",
+3648 => x"00000000",
+3649 => x"00000000",
+3650 => x"00000000",
+3651 => x"00000000",
+3652 => x"00000000",
+3653 => x"00000000",
+3654 => x"00000000",
+3655 => x"00000000",
+3656 => x"00000000",
+3657 => x"00000000",
+3658 => x"00000000",
+3659 => x"00000000",
+3660 => x"00000000",
+3661 => x"00000000",
+3662 => x"00000000",
+3663 => x"00000000",
+3664 => x"00000000",
+3665 => x"00000000",
+3666 => x"00000000",
+3667 => x"00000000",
+3668 => x"00000000",
+3669 => x"00000000",
+3670 => x"00000000",
+3671 => x"00000000",
+3672 => x"00000000",
+3673 => x"00000000",
+3674 => x"00000000",
+3675 => x"00000000",
+3676 => x"00000000",
+3677 => x"00000000",
+3678 => x"00000000",
+3679 => x"00000000",
+3680 => x"00000000",
+3681 => x"00000000",
+3682 => x"00000000",
+3683 => x"00000000",
+3684 => x"00000000",
+3685 => x"00000000",
+3686 => x"00000000",
+3687 => x"00000000",
+3688 => x"00000000",
+3689 => x"00000000",
+3690 => x"00000000",
+3691 => x"00000000",
+3692 => x"00000000",
+3693 => x"00000000",
+3694 => x"00000000",
+3695 => x"00000000",
+3696 => x"00000000",
+3697 => x"00000000",
+3698 => x"00000000",
+3699 => x"00000000",
+3700 => x"00000000",
+3701 => x"00000000",
+3702 => x"00000000",
+3703 => x"00000000",
+3704 => x"00000000",
+3705 => x"00000000",
+3706 => x"00000000",
+3707 => x"00000000",
+3708 => x"00000000",
+3709 => x"00000000",
+3710 => x"00000000",
+3711 => x"00000000",
+3712 => x"00000000",
+3713 => x"00000000",
+3714 => x"00000000",
+3715 => x"00000000",
+3716 => x"00000000",
+3717 => x"00000000",
+3718 => x"00000000",
+3719 => x"00000000",
+3720 => x"00000000",
+3721 => x"00000000",
+3722 => x"00000000",
+3723 => x"00000000",
+3724 => x"00000000",
+3725 => x"00000000",
+3726 => x"00000000",
+3727 => x"00000000",
+3728 => x"00000000",
+3729 => x"00000000",
+3730 => x"00000000",
+3731 => x"00000000",
+3732 => x"00000000",
+3733 => x"00000000",
+3734 => x"00000000",
+3735 => x"00000000",
+3736 => x"00000000",
+3737 => x"00000000",
+3738 => x"00000000",
+3739 => x"00000000",
+3740 => x"00000000",
+3741 => x"00000000",
+3742 => x"00000000",
+3743 => x"00000000",
+3744 => x"00000000",
+3745 => x"00000000",
+3746 => x"00000000",
+3747 => x"00000000",
+3748 => x"00000000",
+3749 => x"00000000",
+3750 => x"00000000",
+3751 => x"00000000",
+3752 => x"00000000",
+3753 => x"00000000",
+3754 => x"000031b0",
+3755 => x"ffffffff",
+3756 => x"00000000",
+3757 => x"ffffffff",
+3758 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+ report "write collision" severity failure;
+ end if;
+
+ if (memAWriteEnable = '1') then
+ ram(conv_integer(memAAddr)) := memAWrite;
+ memARead <= memAWrite;
+ else
+ memARead <= ram(conv_integer(memAAddr));
+ end if;
+ end if;
+end process;
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memBWriteEnable = '1') then
+ ram(conv_integer(memBAddr)) := memBWrite;
+ memBRead <= memBWrite;
+ else
+ memBRead <= ram(conv_integer(memBAddr));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/dualport_ram.vhd b/zpu/hdl/zpu3/src/dualport_ram.vhd
new file mode 100644
index 0000000..54380ce
--- /dev/null
+++ b/zpu/hdl/zpu3/src/dualport_ram.vhd
@@ -0,0 +1,4996 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"800b0b0b",
+1 => x"0b0b8070",
+2 => x"0b0b818a",
+3 => x"880c3a0b",
+4 => x"0b80fae8",
+5 => x"04000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80fbba2d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"530b0b51",
+38 => x"04000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"0b0b5104",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"530b0b51",
+55 => x"04000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"0b0b5104",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"72728072",
+73 => x"8106ff05",
+74 => x"09720605",
+75 => x"71105272",
+76 => x"0a100a53",
+77 => x"0b0b72eb",
+78 => x"38515153",
+79 => x"0b0b5104",
+80 => x"720a722b",
+81 => x"0a530b0b",
+82 => x"51040000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"0607530b",
+101 => x"0b510400",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"7171530b",
+105 => x"0b510406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"0b0b5104",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
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