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authorBert Lange <b.lange@fzd.de>2011-11-07 14:37:59 +0100
committerBert Lange <b.lange@fzd.de>2011-11-07 14:37:59 +0100
commit83f5520b62663857ce8e4813ee8de2bb3cbd07b0 (patch)
tree4d717fa205c5603c4136bb97d7baad8041d3274b /hw_v5_fx30t_extension/bsp/top.xst
parent96d587425f73e57dcfc6dffde48258a39dfb05f0 (diff)
downloadzpu-83f5520b62663857ce8e4813ee8de2bb3cbd07b0.zip
zpu-83f5520b62663857ce8e4813ee8de2bb3cbd07b0.tar.gz
initial commit
Diffstat (limited to 'hw_v5_fx30t_extension/bsp/top.xst')
-rw-r--r--hw_v5_fx30t_extension/bsp/top.xst60
1 files changed, 60 insertions, 0 deletions
diff --git a/hw_v5_fx30t_extension/bsp/top.xst b/hw_v5_fx30t_extension/bsp/top.xst
new file mode 100644
index 0000000..a3b6123
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+++ b/hw_v5_fx30t_extension/bsp/top.xst
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+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc5vfx30t-1-ff665
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Off
+-reduce_control_sets Off
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 32
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
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