summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--hw_v5_fx30t_extension/bsp/avnet-eval-xc5vfx30t.ucf470
-rwxr-xr-xhw_v5_fx30t_extension/bsp/build.sh28
-rw-r--r--hw_v5_fx30t_extension/bsp/top.prj1
-rw-r--r--hw_v5_fx30t_extension/bsp/top.ut39
-rw-r--r--hw_v5_fx30t_extension/bsp/top.vhd189
-rw-r--r--hw_v5_fx30t_extension/bsp/top.xst60
-rw-r--r--hw_v5_fx30t_extension/future_extension/Audio_codec/see_altium_data_sheet.txt0
-rw-r--r--hw_v5_fx30t_extension/future_extension/NanoBoard 3000XN Schematics (Xilinx variant).pdfbin0 -> 9107601 bytes
-rw-r--r--hw_v5_fx30t_extension/future_extension/PS2/pins.txt4
-rw-r--r--hw_v5_fx30t_extension/future_extension/PS2/ps2.pngbin0 -> 12582 bytes
-rw-r--r--hw_v5_fx30t_extension/future_extension/PS2/ps2_connector.pngbin0 -> 12620 bytes
-rw-r--r--hw_v5_fx30t_extension/future_extension/SD_card/pins.txt7
-rw-r--r--hw_v5_fx30t_extension/future_extension/VGA_out/pins.txt8
-rw-r--r--hw_v5_fx30t_extension/future_extension/VGA_out/vga_connector.pngbin0 -> 20390 bytes
-rw-r--r--hw_v5_fx30t_extension/future_extension/VGA_out/vga_out.pngbin0 -> 36062 bytes
-rw-r--r--hw_v5_fx30t_extension/future_extension/VGA_out/video_dac.pngbin0 -> 78969 bytes
-rwxr-xr-xhw_v5_fx30t_extension/readme.txt18
-rw-r--r--hw_v5_fx30t_extension/rtl/top.vhd144
-rw-r--r--hw_v5_fx30t_extension/simulation/Makefile47
-rw-r--r--hw_v5_fx30t_extension/simulation/run.do65
-rw-r--r--hw_v5_fx30t_extension/simulation/vhdl_files.txt1
-rw-r--r--hw_v5_fx30t_extension/synthese/Makefile138
-rw-r--r--hw_v5_fx30t_extension/synthese/top.prj1
-rw-r--r--hw_v5_fx30t_extension/synthese/top.ut39
-rw-r--r--hw_v5_fx30t_extension/synthese/top.xst61
-rw-r--r--hw_v5_fx30t_extension/synthese/virtex5_fx30t_eval.ucf247
26 files changed, 1567 insertions, 0 deletions
diff --git a/hw_v5_fx30t_extension/bsp/avnet-eval-xc5vfx30t.ucf b/hw_v5_fx30t_extension/bsp/avnet-eval-xc5vfx30t.ucf
new file mode 100644
index 0000000..085c55e
--- /dev/null
+++ b/hw_v5_fx30t_extension/bsp/avnet-eval-xc5vfx30t.ucf
@@ -0,0 +1,470 @@
+############################################################
+# Avnet Virtex 5 FX Evaluation Board constraints file
+#
+# Familiy: Virtex5
+# Device: XC5VFX30T
+# Package: FF665
+# Speed: -1
+#
+#
+# Bank 0 3.3V
+# Bank 1 3.3V
+# Bank 2 3.3V
+# Bank 3 3.3V
+# Bank 4 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V
+# Bank 11 1.8V
+# Bank 12 3.3V
+# Bank 13 1.8V
+# Bank 15 3.3V
+# Bank 16 2.5V or 3.3V (JP3, VIO_EXP1_SE), here 2.5V
+# Bank 17 1.8V
+# Bank 18 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+TIMESPEC "TS_clk_100" = PERIOD "clk_100" 100 MHz;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "clk_100MHz" LOC= E18 | IOSTANDARD = LVCMOS33 | TNM_NET = "clk_100";
+NET "clk_socket" LOC= E13 | IOSTANDARD = LVCMOS33;
+NET "user_clk_p" LOC= AB15 ;
+NET "user_clk_n" LOC= AC16 ;
+
+# RS232
+NET "RS232_RX" LOC= K8 | IOSTANDARD = LVCMOS33;
+NET "RS232_TX" LOC= L8 | IOSTANDARD = LVCMOS33;
+NET "RS232_RTS" LOC= N8 | IOSTANDARD = LVCMOS33; # Jumper J3
+NET "RS232_CTS" LOC= R8 | IOSTANDARD = LVCMOS33; # Jumper J4
+
+# RS232_USB
+NET "RS232_USB_RX" LOC= AA10 | IOSTANDARD = LVCMOS33;
+NET "RS232_USB_TX" LOC= AA19 | IOSTANDARD = LVCMOS33;
+NET "RS232_USB_reset_n" LOC= Y20 | IOSTANDARD = LVCMOS33;
+
+# GPIO LEDs, active low
+NET "GPIO_LED_n<0>" LOC= AF22 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<1>" LOC= AF23 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<2>" LOC= AF25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<3>" LOC= AE25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<4>" LOC= AD25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<5>" LOC= AE26 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<6>" LOC= AD26 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<7>" LOC= AC26 | IOSTANDARD = LVCMOS18 | PULLUP;
+
+# GPIO DIP_Switches
+NET "GPIO_DIPswitch<0>" LOC= AD13 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<1>" LOC= AE13 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<2>" LOC= AF13 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<3>" LOC= AD15 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<4>" LOC= AD14 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<5>" LOC= AF14 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<6>" LOC= AE15 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<7>" LOC= AF15 | IOSTANDARD = LVCMOS18;
+
+# Push Buttons
+NET "GPIO_button<0>" LOC= AF20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB1
+NET "GPIO_button<1>" LOC= AE20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB2
+NET "GPIO_button<2>" LOC= AD19 | IOSTANDARD = LVCMOS18 | PULLUP; #PB3
+NET "GPIO_button<3>" LOC= AD20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB4
+
+# FLASH_8Mx16
+NET "FLASH_A<31>" LOC= Y11 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<30>" LOC= H9 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<29>" LOC= G10 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<28>" LOC= H21 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<27>" LOC= G20 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<26>" LOC= H11 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<25>" LOC= G11 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<24>" LOC= H19 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<23>" LOC= H18 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<22>" LOC= G12 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<21>" LOC= F13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<20>" LOC= G19 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<19>" LOC= F18 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<18>" LOC= F14 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<17>" LOC= F15 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<16>" LOC= F17 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<15>" LOC= G17 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<14>" LOC= G14 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<13>" LOC= H13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<12>" LOC= G16 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<11>" LOC= G15 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<10>" LOC= Y18 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<9>" LOC= AA18 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<8>" LOC= Y10 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<7>" LOC= W11 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<0>" LOC= AA15 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<1>" LOC= Y15 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<2>" LOC= W14 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<3>" LOC= Y13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<4>" LOC= W16 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<5>" LOC= Y16 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<6>" LOC= AA14 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<7>" LOC= AA13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<8>" LOC= AB12 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<9>" LOC= AC11 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<10>" LOC= AB20 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<11>" LOC= AB21 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<12>" LOC= AB11 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<13>" LOC= AB10 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<14>" LOC= AA20 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<15>" LOC= Y21 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_WEN" LOC= AA17 | IOSTANDARD = LVCMOS33;
+NET "FLASH_OEN<0>" LOC= AA12 | IOSTANDARD = LVCMOS33;
+NET "FLASH_CEN<0>" LOC= Y12 | IOSTANDARD = LVCMOS33;
+NET "FLASH_rp_n" LOC= D13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_byte_n" LOC= Y17 | IOSTANDARD = LVCMOS33;
+NET "FLASH_adv_n" LOC= F19 | IOSTANDARD = LVCMOS33;
+NET "FLASH_clk" LOC= E12 | IOSTANDARD = LVCMOS33;
+NET "FLASH_wait" LOC= D16 | IOSTANDARD = LVCMOS33;
+
+# DDR2_SDRAM_16Mx32
+NET "DDR2_ODT<0>" LOC= AF24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<0>" LOC= U25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<1>" LOC= T25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<2>" LOC= T24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<3>" LOC= T23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<4>" LOC= U24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<5>" LOC= V24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<6>" LOC= Y23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<7>" LOC= W23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<8>" LOC= AA25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<9>" LOC= AB26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<10>" LOC= AB25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<11>" LOC= AB24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<12>" LOC= AA23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_BA<0>" LOC= U21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_BA<1>" LOC= V22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_CAS_N" LOC= W24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_CKE" LOC= T22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_CS_N" LOC= AD24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_RAS_N" LOC= Y22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_WE_N" LOC= AA22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<0>" LOC= U26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<1>" LOC= N24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<2>" LOC= M24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<3>" LOC= M25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<0>" LOC= W26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<1>" LOC= L23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<2>" LOC= K22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<3>" LOC= J21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<0>" LOC= W25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<1>" LOC= L22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<2>" LOC= K23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<3>" LOC= K21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<0>" LOC= R22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<1>" LOC= R23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<2>" LOC= P23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<3>" LOC= P24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<4>" LOC= R25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<5>" LOC= P25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<6>" LOC= R26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<7>" LOC= P26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<8>" LOC= M26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<9>" LOC= N26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<10>" LOC= K25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<11>" LOC= L24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<12>" LOC= K26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<13>" LOC= J26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<14>" LOC= J25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<15>" LOC= N21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<16>" LOC= M21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<17>" LOC= J23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<18>" LOC= H23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<19>" LOC= H22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<20>" LOC= G22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<21>" LOC= F22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<22>" LOC= F23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<23>" LOC= E23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<24>" LOC= G24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<25>" LOC= F24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<26>" LOC= G25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<27>" LOC= H26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<28>" LOC= G26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<29>" LOC= F25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<30>" LOC= E25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<31>" LOC= E26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_CK_p<0>" LOC= V21 | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CK_p<1>" LOC= N22 | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CK_n<0>" LOC= W21 | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CK_n<1>" LOC= M22 | IOSTANDARD = DIFF_SSTL18_II;
+
+# Ethernet MAC
+NET "GMII_txer" LOC= A22 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_clk" LOC= E17 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
+NET "GMII_rx_clk" LOC= E20 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
+NET "GMII_gtc_clk" LOC= A19 | IOSTANDARD = LVCMOS33;
+NET "GMII_crs" LOC= A25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_dv" LOC= C21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<0>" LOC= D24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<1>" LOC= D23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<2>" LOC= D21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<3>" LOC= C26 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<4>" LOC= D20 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<5>" LOC= C23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<6>" LOC= B25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<7>" LOC= C22 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_col" LOC= A24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_er" LOC= B24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_tx_en" LOC= A23 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<0>" LOC= D19 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<1>" LOC= C19 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<2>" LOC= A20 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<3>" LOC= B20 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<4>" LOC= B19 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<5>" LOC= A15 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<6>" LOC= B22 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<7>" LOC= B21 | IOSTANDARD = LVCMOS33;
+NET "GBE_rst_n" LOC= B26 | IOSTANDARD = LVCMOS33;
+NET "GBE_mdc" LOC= D26 | IOSTANDARD = LVCMOS33;
+NET "GBE_mdio" LOC= D25 | IOSTANDARD = LVCMOS33;
+NET "GBE_int_n" LOC= C24 | IOSTANDARD = LVCMOS33;
+NET "GBE_mclk" LOC= F20 | IOSTANDARD = LVCMOS33;
+
+# SysACE CompactFlash
+NET "SAM_CLK" LOC= F12 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<0>" LOC= Y5 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<1>" LOC= V7 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<2>" LOC= W6 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<3>" LOC= W5 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<4>" LOC= K6 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<5>" LOC= J5 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<6>" LOC= J6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<0>" LOC= F5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<1>" LOC= U7 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<2>" LOC= V6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<3>" LOC= U5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<4>" LOC= U6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<5>" LOC= T5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<6>" LOC= T7 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<7>" LOC= R6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<8>" LOC= R7 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<9>" LOC= R5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<10>" LOC= P6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<11>" LOC= P8 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<12>" LOC= N6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<13>" LOC= M7 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<14>" LOC= K5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<15>" LOC= L7 | IOSTANDARD = LVCMOS33;
+NET "SAM_CEN" LOC= G4 | IOSTANDARD = LVCMOS33;
+NET "SAM_OEN" LOC= Y6 | IOSTANDARD = LVCMOS33;
+NET "SAM_WEN" LOC= Y4 | IOSTANDARD = LVCMOS33;
+NET "SAM_MPIRQ" LOC= H4 | IOSTANDARD = LVCMOS33;
+NET "SAM_BRDY" LOC= G5 | IOSTANDARD = LVCMOS33;
+NET "SAM_RESET_n" LOC= H6 | IOSTANDARD = LVCMOS33;
+
+# Expansion Header
+NET "EXP1_SE_IO<0>" LOC= A8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<1>" LOC= A12 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<2>" LOC= B10 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<3>" LOC= A10 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<4>" LOC= B9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<5>" LOC= A9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<6>" LOC= A5 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<7>" LOC= B11 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<8>" LOC= B6 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<9>" LOC= A7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<10>" LOC= D8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<11>" LOC= C9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<12>" LOC= B7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<13>" LOC= A4 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<14>" LOC= B5 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<15>" LOC= C8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<16>" LOC= C7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<17>" LOC= A3 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<18>" LOC= C6 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<19>" LOC= B4 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<20>" LOC= D6 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<21>" LOC= D9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<22>" LOC= E8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<23>" LOC= D5 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<24>" LOC= F7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<25>" LOC= E7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<26>" LOC= E5 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<27>" LOC= E6 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<28>" LOC= F8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<29>" LOC= H7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<30>" LOC= G7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<31>" LOC= H8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<32>" LOC= G9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<33>" LOC= J8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_DIFF_P<0>" LOC= AF9 ;
+NET "EXP1_DIFF_N<0>" LOC= AF10 ;
+NET "EXP1_DIFF_P<1>" LOC= AF12 ;
+NET "EXP1_DIFF_N<1>" LOC= AE12 ;
+NET "EXP1_DIFF_P<2>" LOC= AF7 ;
+NET "EXP1_DIFF_N<2>" LOC= AF8 ;
+NET "EXP1_DIFF_P<3>" LOC= AE11 ;
+NET "EXP1_DIFF_N<3>" LOC= AD11 ;
+NET "EXP1_DIFF_P<4>" LOC= AF4 ;
+NET "EXP1_DIFF_N<4>" LOC= AF3 ;
+NET "EXP1_DIFF_P<5>" LOC= AD10 ;
+NET "EXP1_DIFF_N<5>" LOC= AE10 ;
+NET "EXP1_DIFF_P<6>" LOC= AE8 ;
+NET "EXP1_DIFF_N<6>" LOC= AE7 ;
+NET "EXP1_DIFF_P<7>" LOC= AC8 ;
+NET "EXP1_DIFF_N<7>" LOC= AD8 ;
+NET "EXP1_DIFF_P<8>" LOC= AD9 ;
+NET "EXP1_DIFF_N<8>" LOC= AC9 ;
+NET "EXP1_DIFF_P<9>" LOC= AE6 ;
+NET "EXP1_DIFF_N<9>" LOC= AF5 ;
+NET "EXP1_DIFF_P<10>" LOC= AB6 ;
+NET "EXP1_DIFF_N<10>" LOC= AB7 ;
+NET "EXP1_DIFF_P<11>" LOC= AC6 ;
+NET "EXP1_DIFF_N<11>" LOC= AD5 ;
+NET "EXP1_DIFF_P<12>" LOC= AD6 ;
+NET "EXP1_DIFF_N<12>" LOC= AC7 ;
+NET "EXP1_DIFF_P<13>" LOC= AE5 ;
+NET "EXP1_DIFF_N<13>" LOC= AD4 ;
+NET "EXP1_DIFF_P<14>" LOC= AB9 ;
+NET "EXP1_DIFF_N<14>" LOC= AA9 ;
+NET "EXP1_DIFF_P<15>" LOC= AC12 ;
+NET "EXP1_DIFF_N<15>" LOC= AC13 ;
+NET "EXP1_DIFF_P<16>" LOC= AA7 ;
+NET "EXP1_DIFF_N<16>" LOC= AA8 ;
+NET "EXP1_DIFF_P<17>" LOC= AA5 ;
+NET "EXP1_DIFF_N<17>" LOC= AB5 ;
+NET "EXP1_DIFF_P<18>" LOC= AB19 ;
+NET "EXP1_DIFF_N<18>" LOC= AC19 ;
+NET "EXP1_DIFF_P<19>" LOC= Y7 ;
+NET "EXP1_DIFF_N<19>" LOC= Y8 ;
+NET "EXP1_DIFF_P<20>" LOC= W9 ;
+NET "EXP1_DIFF_N<20>" LOC= W8 ;
+NET "EXP1_DIFF_P<21>" LOC= V8 ;
+NET "EXP1_DIFF_N<21>" LOC= V9 ;
+NET "EXP1_SE_CLK_OUT" LOC= B12 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_CLK_IN" LOC= E10 | IOSTANDARD = LVCMOS33;
+NET "EXP1_DIFF_CLK_OUT_P" LOC= AC18 ;
+NET "EXP1_DIFF_CLK_OUT_N" LOC= AB17 ;
+NET "EXP1_DIFF_CLK_IN_P" LOC= AB14 ;
+NET "EXP1_DIFF_CLK_IN_N" LOC= AC14 ;
+#NET "EXP1_RCLK_DIFF_P" LOC= AB6 ;
+#NET "EXP1_RCLK_DIFF_N" LOC= AB7 ;
+
+# CPU Debug Trace
+NET "ATDD<8>" LOC= C16 | IOSTANDARD = LVCMOS33;
+NET "ATDD<9>" LOC= A17 | IOSTANDARD = LVCMOS33;
+NET "ATDD<10>" LOC= B15 | IOSTANDARD = LVCMOS33;
+NET "ATDD<11>" LOC= E15 | IOSTANDARD = LVCMOS33;
+NET "ATDD<12>" LOC= A14 | IOSTANDARD = LVCMOS33;
+NET "ATDD<13>" LOC= D18 | IOSTANDARD = LVCMOS33;
+NET "ATDD<14>" LOC= A13 | IOSTANDARD = LVCMOS33;
+NET "ATDD<15>" LOC= C13 | IOSTANDARD = LVCMOS33;
+NET "ATDD<16>" LOC= D14 | IOSTANDARD = LVCMOS33;
+NET "ATDD<17>" LOC= C17 | IOSTANDARD = LVCMOS33;
+NET "ATDD<18>" LOC= E16 | IOSTANDARD = LVCMOS33;
+NET "ATDD<19>" LOC= C14 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS10" LOC= B16 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS20" LOC= E21 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS1E" LOC= B14 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS2E" LOC= B17 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS3" LOC= C18 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS4" LOC= G21 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS5" LOC= A18 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS6" LOC= F10 | IOSTANDARD = LVCMOS33;
+NET "TRACE_CLK" LOC= D15 | IOSTANDARD = LVCMOS33;
+NET "CPU_HRESET" LOC= E11 | IOSTANDARD = LVCMOS33;
+NET "CPU_TDO" LOC= K7 | IOSTANDARD = LVCMOS33;
+NET "CPU_TMS" LOC= L5 | IOSTANDARD = LVCMOS33;
+NET "CPU_TDI" LOC= M6 | IOSTANDARD = LVCMOS33;
+NET "CPU_TRST" LOC= N7 | IOSTANDARD = LVCMOS33;
+NET "CPU_TCK" LOC= T8 | IOSTANDARD = LVCMOS33;
+NET "CPU_HALT_n" LOC= W4 | IOSTANDARD = LVCMOS33;
+
+
+# voltage termination
+CONFIG PROHIBIT = AA24;
+CONFIG PROHIBIT = AE23;
+CONFIG PROHIBIT = AF17;
+CONFIG PROHIBIT = V26;
+CONFIG PROHIBIT = E22;
+CONFIG PROHIBIT = L25;
+
+# unused pins
+CONFIG PROHIBIT = F9;
+CONFIG PROHIBIT = D10;
+CONFIG PROHIBIT = C12;
+CONFIG PROHIBIT = C11;
+CONFIG PROHIBIT = D11;
+CONFIG PROHIBIT = AB16;
+CONFIG PROHIBIT = AB22;
+CONFIG PROHIBIT = AC17;
+CONFIG PROHIBIT = AC21;
+CONFIG PROHIBIT = AE22;
+CONFIG PROHIBIT = AD23;
+CONFIG PROHIBIT = AC24;
+CONFIG PROHIBIT = AC23;
+CONFIG PROHIBIT = AC22;
+CONFIG PROHIBIT = AB22;
+CONFIG PROHIBIT = AE21;
+CONFIG PROHIBIT = AD21;
+CONFIG PROHIBIT = AF19;
+CONFIG PROHIBIT = AF18;
+CONFIG PROHIBIT = AE18;
+CONFIG PROHIBIT = AD18;
+CONFIG PROHIBIT = AE17;
+CONFIG PROHIBIT = AE16;
+CONFIG PROHIBIT = AD16;
+CONFIG PROHIBIT = G6;
+CONFIG PROHIBIT = H24;
+CONFIG PROHIBIT = J24;
+CONFIG PROHIBIT = N23;
+CONFIG PROHIBIT = N15;
+CONFIG PROHIBIT = P14;
+CONFIG PROHIBIT = V23;
+CONFIG PROHIBIT = Y26;
+CONFIG PROHIBIT = Y25;
+CONFIG PROHIBIT = P21;
+CONFIG PROHIBIT = R21;
+CONFIG PROHIBIT = U22;
+
+# grounded pins from gigabit transcievers
+CONFIG PROHIBIT = P4;
+CONFIG PROHIBIT = K4;
+CONFIG PROHIBIT = K3;
+CONFIG PROHIBIT = J1;
+CONFIG PROHIBIT = K1;
+CONFIG PROHIBIT = M1;
+CONFIG PROHIBIT = L1;
+CONFIG PROHIBIT = T3;
+CONFIG PROHIBIT = T4;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = T1;
+CONFIG PROHIBIT = V1;
+CONFIG PROHIBIT = U1;
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = D4;
+CONFIG PROHIBIT = C1;
+CONFIG PROHIBIT = D1;
+CONFIG PROHIBIT = E1;
+CONFIG PROHIBIT = F1;
+CONFIG PROHIBIT = AB3;
+CONFIG PROHIBIT = AB4;
+CONFIG PROHIBIT = AA1;
+CONFIG PROHIBIT = AB1;
+CONFIG PROHIBIT = AC1;
+CONFIG PROHIBIT = AD1;
+CONFIG PROHIBIT = H2;
+CONFIG PROHIBIT = J2;
+CONFIG PROHIBIT = N2;
+CONFIG PROHIBIT = M2;
+CONFIG PROHIBIT = P2;
+CONFIG PROHIBIT = R2;
+CONFIG PROHIBIT = V2;
+CONFIG PROHIBIT = W2;
+CONFIG PROHIBIT = B2;
+CONFIG PROHIBIT = C2;
+CONFIG PROHIBIT = G2;
+CONFIG PROHIBIT = F2;
+CONFIG PROHIBIT = Y2;
+CONFIG PROHIBIT = AA2;
+CONFIG PROHIBIT = AD2;
+CONFIG PROHIBIT = AE2;
+
diff --git a/hw_v5_fx30t_extension/bsp/build.sh b/hw_v5_fx30t_extension/bsp/build.sh
new file mode 100755
index 0000000..0787fa5
--- /dev/null
+++ b/hw_v5_fx30t_extension/bsp/build.sh
@@ -0,0 +1,28 @@
+# need project files:
+# top.xst
+# top.prj
+# top.ut
+
+# need Xilinx tools:
+# xst
+# ngdbuild
+# map
+# par
+# trce
+# bitgen
+
+# generate build directory
+mkdir build
+cd build
+mkdir tmp
+
+# start processes
+xst -ifn "../top.xst" -ofn "top.syr"
+ngdbuild -dd _ngo -nt timestamp -uc ../avnet-eval-xc5vfx30t.ucf -p xc5vfx30t-ff665-1 top.ngc top.ngd
+map -p xc5vfx30t-ff665-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf
+par -w -ol high -mt off top_map.ncd top.ncd top.pcf
+trce -v 3 -s 1 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf
+bitgen -f ../top.ut top.ncd
+
+# get bitfile
+cp top.bit ..
diff --git a/hw_v5_fx30t_extension/bsp/top.prj b/hw_v5_fx30t_extension/bsp/top.prj
new file mode 100644
index 0000000..3975c05
--- /dev/null
+++ b/hw_v5_fx30t_extension/bsp/top.prj
@@ -0,0 +1 @@
+vhdl work "../top.vhd"
diff --git a/hw_v5_fx30t_extension/bsp/top.ut b/hw_v5_fx30t_extension/bsp/top.ut
new file mode 100644
index 0000000..e0159fb
--- /dev/null
+++ b/hw_v5_fx30t_extension/bsp/top.ut
@@ -0,0 +1,39 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:2
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g InitPin:Pullup
+-g CsPin:Pullup
+-g DinPin:Pullup
+-g BusyPin:Pullup
+-g RdWrPin:Pullup
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ConfigFallback:Enable
+-g SelectMAPAbort:Enable
+-g BPI_page_size:1
+-g OverTempPowerDown:Disable
+-g JTAG_SysMon:Enable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g Encrypt:No
diff --git a/hw_v5_fx30t_extension/bsp/top.vhd b/hw_v5_fx30t_extension/bsp/top.vhd
new file mode 100644
index 0000000..1964fed
--- /dev/null
+++ b/hw_v5_fx30t_extension/bsp/top.vhd
@@ -0,0 +1,189 @@
+-- top module of
+-- Avnet Virtex 5 FX Evaluation Board
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.ibufds;
+
+
+entity top is
+ port (
+ clk_100MHz : in std_logic; -- 100 MHz clock
+ clk_socket : in std_logic; -- user clock
+ user_clk_p : in std_logic; -- diff user clock
+ user_clk_n : in std_logic; -- diff user clock
+ --
+ -- RS232
+ rs232_rx : in std_logic;
+ rs232_tx : out std_logic;
+ rs232_rts : in std_logic;
+ rs232_cts : out std_logic;
+ -- RS232 USB
+ rs232_usb_rx : in std_logic;
+ rs232_usb_tx : out std_logic;
+ rs232_usb_reset_n : out std_logic;
+ --
+ gpio_led_n : out std_logic_vector(7 downto 0);
+ gpio_dipswitch : in std_logic_vector(7 downto 0);
+ gpio_button : in std_logic_vector(3 downto 0);
+ --
+ -- FLASH 8Mx16
+ flash_a : out std_logic_vector(31 downto 7);
+ flash_dq : inout std_logic_vector(15 downto 0);
+ flash_wen : out std_logic;
+ flash_oen : out std_logic_vector(0 downto 0);
+ flash_cen : out std_logic_vector(0 downto 0);
+ flash_rp_n : out std_logic;
+ flash_byte_n : out std_logic;
+ flash_adv_n : out std_logic;
+ flash_clk : out std_logic;
+ flash_wait : in std_logic;
+ --
+ -- DDR2 SDRAM 16Mx32
+ ddr2_odt : in std_logic_vector(0 downto 0);
+ ddr2_a : out std_logic_vector(12 downto 0);
+ ddr2_ba : out std_logic_vector(1 downto 0);
+ ddr2_cas_n : out std_logic;
+ ddr2_cke : out std_logic;
+ ddr2_cs_n : out std_logic;
+ ddr2_ras_n : out std_logic;
+ ddr2_we_n : out std_logic;
+ ddr2_dm : out std_logic_vector(3 downto 0);
+ ddr2_dqs_p : inout std_logic_vector(3 downto 0);
+ ddr2_dqs_n : inout std_logic_vector(3 downto 0);
+ ddr2_dq : inout std_logic_vector(31 downto 0);
+ ddr2_ck_p : in std_logic_vector(1 downto 0);
+ ddr2_ck_n : in std_logic_vector(1 downto 0);
+ --
+ -- Ethernet MAC
+ gmii_txer : out std_logic;
+ gmii_tx_clk : in std_logic; -- 25 MHz
+ gmii_rx_clk : in std_logic; -- 25 MHz
+ gmii_gtc_clk : out std_logic;
+ gmii_crs : in std_logic;
+ gmii_dv : in std_logic;
+ gmii_rx_data : in std_logic_vector(7 downto 0);
+ gmii_col : in std_logic;
+ gmii_rx_er : in std_logic;
+ gmii_tx_en : out std_logic;
+ gmii_tx_data : out std_logic_vector(7 downto 0);
+ gbe_rst_n : out std_logic;
+ gbe_mdc : out std_logic;
+ gbe_mdio : inout std_logic;
+ gbe_int_n : inout std_logic;
+ gbe_mclk : in std_logic;
+ --
+ -- SysACE CompactFlash
+ sam_clk : in std_logic;
+ sam_a : out std_logic_vector(6 downto 0);
+ sam_d : inout std_logic_vector(15 downto 0);
+ sam_cen : out std_logic;
+ sam_oen : out std_logic;
+ sam_wen : out std_logic;
+ sam_mpirq : in std_logic;
+ sam_brdy : in std_logic;
+ sam_reset_n : out std_logic;
+ --
+ -- Expansion Header
+ exp1_se_io : inout std_logic_vector(33 downto 0);
+ exp1_diff_p : inout std_logic_vector(21 downto 0);
+ exp1_diff_n : inout std_logic_vector(21 downto 0);
+ exp1_se_clk_out : out std_logic;
+ exp1_se_clk_in : in std_logic;
+ exp1_diff_clk_out_p : out std_logic;
+ exp1_diff_clk_out_n : out std_logic;
+ exp1_diff_clk_in_p : in std_logic;
+ exp1_diff_clk_in_n : in std_logic;
+ --
+ -- Debug/Trace
+ atdd : inout std_logic_vector(19 downto 8);
+ trace_ts10 : inout std_logic;
+ trace_ts20 : inout std_logic;
+ trace_ts1e : inout std_logic;
+ trace_ts2e : inout std_logic;
+ trace_ts3 : inout std_logic;
+ trace_ts4 : inout std_logic;
+ trace_ts5 : inout std_logic;
+ trace_ts6 : inout std_logic;
+ trace_clk : in std_logic;
+ cpu_hreset : in std_logic;
+ cpu_tdo : out std_logic;
+ cpu_tms : in std_logic;
+ cpu_tdi : in std_logic;
+ cpu_trst : in std_logic;
+ cpu_tck : in std_logic;
+ cpu_halt_n : in std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ signal ibufds_i0_o : std_ulogic;
+ signal ibufds_i1_o : std_ulogic;
+
+begin
+
+ ibufds_i0 : ibufds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ o => ibufds_i0_o,
+ i => ddr2_ck_p(0),
+ ib => ddr2_ck_n(0)
+ );
+
+ ibufds_i1 : ibufds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ o => ibufds_i1_o,
+ i => ddr2_ck_p(1),
+ ib => ddr2_ck_n(1)
+ );
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ rs232_tx <= '1';
+ rs232_cts <= '1';
+ rs232_usb_tx <= '1';
+ rs232_usb_reset_n <= '1';
+ gpio_led_n <= (others => '1');
+ flash_cen <= "1";
+ flash_oen <= "1";
+ flash_wen <= '1';
+ flash_rp_n <= '1';
+ flash_byte_n <= '1';
+ flash_adv_n <= '1';
+ flash_clk <= '0';
+ flash_a <= (others => '0');
+ ddr2_a <= (others => '0');
+ ddr2_ba <= (others => '0');
+ ddr2_dm <= (others => '0');
+ ddr2_cs_n <= '1';
+ ddr2_we_n <= '1';
+ ddr2_cke <= '1';
+ ddr2_cas_n <= '1';
+ ddr2_ras_n <= '1';
+ gmii_gtc_clk <= '0';
+ gmii_tx_data <= (others => '0');
+ gmii_tx_en <= '0';
+ gmii_txer <= '0';
+ gbe_rst_n <= '1';
+ gbe_mdc <= '1';
+ sam_cen <= '1';
+ sam_oen <= '1';
+ sam_wen <= '1';
+ sam_a <= (others => '0');
+ sam_reset_n <= '1';
+ exp1_se_clk_out <= '0';
+ exp1_diff_clk_out_p <= '0';
+ exp1_diff_clk_out_n <= '1';
+ cpu_tdo <= '1';
+
+end architecture rtl;
+
diff --git a/hw_v5_fx30t_extension/bsp/top.xst b/hw_v5_fx30t_extension/bsp/top.xst
new file mode 100644
index 0000000..a3b6123
--- /dev/null
+++ b/hw_v5_fx30t_extension/bsp/top.xst
@@ -0,0 +1,60 @@
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc5vfx30t-1-ff665
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Off
+-reduce_control_sets Off
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 32
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/hw_v5_fx30t_extension/future_extension/Audio_codec/see_altium_data_sheet.txt b/hw_v5_fx30t_extension/future_extension/Audio_codec/see_altium_data_sheet.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/Audio_codec/see_altium_data_sheet.txt
diff --git a/hw_v5_fx30t_extension/future_extension/NanoBoard 3000XN Schematics (Xilinx variant).pdf b/hw_v5_fx30t_extension/future_extension/NanoBoard 3000XN Schematics (Xilinx variant).pdf
new file mode 100644
index 0000000..eaca66e
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/NanoBoard 3000XN Schematics (Xilinx variant).pdf
Binary files differ
diff --git a/hw_v5_fx30t_extension/future_extension/PS2/pins.txt b/hw_v5_fx30t_extension/future_extension/PS2/pins.txt
new file mode 100644
index 0000000..24e572f
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/PS2/pins.txt
@@ -0,0 +1,4 @@
+data 1
+clock 1
+
+sum 2
diff --git a/hw_v5_fx30t_extension/future_extension/PS2/ps2.png b/hw_v5_fx30t_extension/future_extension/PS2/ps2.png
new file mode 100644
index 0000000..829e696
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/PS2/ps2.png
Binary files differ
diff --git a/hw_v5_fx30t_extension/future_extension/PS2/ps2_connector.png b/hw_v5_fx30t_extension/future_extension/PS2/ps2_connector.png
new file mode 100644
index 0000000..a39c9e2
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/PS2/ps2_connector.png
Binary files differ
diff --git a/hw_v5_fx30t_extension/future_extension/SD_card/pins.txt b/hw_v5_fx30t_extension/future_extension/SD_card/pins.txt
new file mode 100644
index 0000000..6dd09f7
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/SD_card/pins.txt
@@ -0,0 +1,7 @@
+protect 1
+detect 1
+cmd 1
+clk 1
+data 4
+
+sum 8
diff --git a/hw_v5_fx30t_extension/future_extension/VGA_out/pins.txt b/hw_v5_fx30t_extension/future_extension/VGA_out/pins.txt
new file mode 100644
index 0000000..cb7f392
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/VGA_out/pins.txt
@@ -0,0 +1,8 @@
+red 8
+green 8
+blue 8
+hsync 1
+vsync 1
+dac_clk 1
+
+sum 27
diff --git a/hw_v5_fx30t_extension/future_extension/VGA_out/vga_connector.png b/hw_v5_fx30t_extension/future_extension/VGA_out/vga_connector.png
new file mode 100644
index 0000000..fd31718
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/VGA_out/vga_connector.png
Binary files differ
diff --git a/hw_v5_fx30t_extension/future_extension/VGA_out/vga_out.png b/hw_v5_fx30t_extension/future_extension/VGA_out/vga_out.png
new file mode 100644
index 0000000..2e777e5
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/VGA_out/vga_out.png
Binary files differ
diff --git a/hw_v5_fx30t_extension/future_extension/VGA_out/video_dac.png b/hw_v5_fx30t_extension/future_extension/VGA_out/video_dac.png
new file mode 100644
index 0000000..9ad137e
--- /dev/null
+++ b/hw_v5_fx30t_extension/future_extension/VGA_out/video_dac.png
Binary files differ
diff --git a/hw_v5_fx30t_extension/readme.txt b/hw_v5_fx30t_extension/readme.txt
new file mode 100755
index 0000000..ad96102
--- /dev/null
+++ b/hw_v5_fx30t_extension/readme.txt
@@ -0,0 +1,18 @@
+done:
+ucf und top angelegt
+LED leuchten auf Tastendruck
+Desing läuft aus dem BPI-Flash
+
+todo:
+grlib mit folgender IP:
+RS232
+USB-UART
+GPIO (LED switch button)
+Flash 8Mx16
+DDR2 16Mx32
+Ethernet (10/100/1000)
+Sysace? eher nicht -> 28 Pins extra
+
+Portierung ZPU + grlib (Größe + Geschwindigkeit)
+Portierung LEON3 + grlib (Größe + Geschwindigkeit)
+Portierung PPC + grlib (Größe + Geschwindigkeit)
diff --git a/hw_v5_fx30t_extension/rtl/top.vhd b/hw_v5_fx30t_extension/rtl/top.vhd
new file mode 100644
index 0000000..34c82b8
--- /dev/null
+++ b/hw_v5_fx30t_extension/rtl/top.vhd
@@ -0,0 +1,144 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.ibufds;
+
+
+
+entity top is
+ port
+ (
+ sys_clk : in std_logic; -- 100 MHz clock
+ clk_socket : in std_logic; -- user clock
+ --sys_rst : in std_logic;
+ --
+ -- RS232
+ RS232_RX : in std_logic;
+ RS232_TX : out std_logic;
+ -- RS232_USB
+ RS232_USB_RX : in std_logic;
+ RS232_USB_TX : out std_logic;
+ RS232_USB_reset_dummy : out std_logic;
+ --
+ GPIO_LED_out : out std_logic_vector(7 downto 0);
+ GPIO_DIPswitch_in : in std_logic_vector(7 downto 0);
+ GPIO_button_in : in std_logic_vector(3 downto 0);
+ --
+ -- FLASH_8Mx16
+ FLASH_8Mx16_Mem_A : out std_logic_vector(31 downto 7);
+ FLASH_8Mx16_Mem_DQ : inout std_logic_vector(15 downto 0);
+ FLASH_8Mx16_Mem_WEN : out std_logic;
+ FLASH_8Mx16_Mem_OEN : out std_logic_vector(0 downto 0);
+ FLASH_8Mx16_Mem_CEN : out std_logic_vector(0 downto 0);
+ FLASH_8Mx16_rpn_dummy : out std_logic;
+ --FLASH_8Mx16_byte_dummy : std_logic;
+ --FLASH_8Mx16_adv_dummy : std_logic;
+ --FLASH_8Mx16_clk_dummy : std_logic;
+ --FLASH_8Mx16_wait_dummy : std_logic;
+ --
+ -- DDR2_SDRAM_16Mx32
+ DDR2_SDRAM_16Mx32_DDR2_ODT : in std_logic_vector( 0 downto 0);
+ DDR2_SDRAM_16Mx32_DDR2_A : out std_logic_vector(12 downto 0);
+ DDR2_SDRAM_16Mx32_DDR2_BA : out std_logic_vector( 1 downto 0);
+ DDR2_SDRAM_16Mx32_DDR2_CAS_N : out std_logic;
+ DDR2_SDRAM_16Mx32_DDR2_CKE : out std_logic;
+ DDR2_SDRAM_16Mx32_DDR2_CS_N : out std_logic;
+ DDR2_SDRAM_16Mx32_DDR2_RAS_N : out std_logic;
+ DDR2_SDRAM_16Mx32_DDR2_WE_N : out std_logic;
+ DDR2_SDRAM_16Mx32_DDR2_DM : out std_logic_vector( 3 downto 0);
+ DDR2_SDRAM_16Mx32_DDR2_DQS : inout std_logic_vector( 3 downto 0);
+ DDR2_SDRAM_16Mx32_DDR2_DQS_N : inout std_logic_vector( 3 downto 0);
+ DDR2_SDRAM_16Mx32_DDR2_DQ : inout std_logic_vector(31 downto 0);
+ DDR2_SDRAM_16Mx32_DDR2_CK : in std_logic_vector( 1 downto 0);
+ DDR2_SDRAM_16Mx32_DDR2_CK_N : in std_logic_vector( 1 downto 0);
+ --
+ -- Ethernet_MAC
+ Ethernet_MAC_DUMMY_ETH_TXER : out std_logic;
+ Ethernet_MAC_PHY_tx_clk : in std_logic; -- 25 MHz
+ Ethernet_MAC_PHY_rx_clk : in std_logic; -- 25 MHz
+ Ethernet_MAC_PHY_crs : in std_logic;
+ Ethernet_MAC_PHY_dv : in std_logic;
+ Ethernet_MAC_PHY_rx_data : in std_logic_vector(3 downto 0);
+ Ethernet_MAC_PHY_col : in std_logic;
+ Ethernet_MAC_PHY_rx_er : in std_logic;
+ Ethernet_MAC_PHY_tx_en : out std_logic;
+ Ethernet_MAC_PHY_tx_data : out std_logic_vector(3 downto 0);
+ Ethernet_MAC_PHY_rst_n : out std_logic;
+ Ethernet_MAC_PHY_Mii_clk : out std_logic;
+ Ethernet_MAC_PHY_Mii_data : inout std_logic;
+ --
+ -- SysACE_CompactFlash
+ SysACE_CompactFlash_SysACE_CLK : in std_logic;
+ SysACE_CompactFlash_SysACE_MPA : out std_logic_vector( 6 downto 0);
+ SysACE_CompactFlash_SysACE_MPD : inout std_logic_vector(15 downto 0);
+ SysACE_CompactFlash_SysACE_CEN : out std_logic;
+ SysACE_CompactFlash_SysACE_OEN : out std_logic;
+ SysACE_CompactFlash_SysACE_WEN : out std_logic;
+ SysACE_CompactFlash_SysACE_MPIRQ : in std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ signal ibufds_i0_o : std_ulogic;
+ signal ibufds_i1_o : std_ulogic;
+
+begin
+
+ ibufds_i0 : ibufds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ o => ibufds_i0_o,
+ i => DDR2_SDRAM_16Mx32_DDR2_CK(0),
+ ib => DDR2_SDRAM_16Mx32_DDR2_CK_N(0)
+ );
+
+ ibufds_i1 : ibufds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ o => ibufds_i1_o,
+ i => DDR2_SDRAM_16Mx32_DDR2_CK(1),
+ ib => DDR2_SDRAM_16Mx32_DDR2_CK_N(1)
+ );
+
+ -- some default assignments
+ -- to pass bitgen DRC
+ RS232_TX <= '1';
+ RS232_USB_TX <= '1';
+ RS232_USB_reset_dummy <= '0';
+ FLASH_8Mx16_Mem_CEN <= "1";
+ FLASH_8Mx16_Mem_OEN <= "1";
+ FLASH_8Mx16_Mem_WEN <= '1';
+ FLASH_8Mx16_rpn_dummy <= '1';
+ FLASH_8Mx16_Mem_A <= (others => '0');
+ DDR2_SDRAM_16Mx32_DDR2_A <= (others => '0');
+ DDR2_SDRAM_16Mx32_DDR2_BA <= (others => '0');
+ DDR2_SDRAM_16Mx32_DDR2_DM <= (others => '0');
+ DDR2_SDRAM_16Mx32_DDR2_CS_N <= '1';
+ DDR2_SDRAM_16Mx32_DDR2_WE_N <= '1';
+ DDR2_SDRAM_16Mx32_DDR2_CKE <= '1';
+ DDR2_SDRAM_16Mx32_DDR2_CAS_N <= '1';
+ DDR2_SDRAM_16Mx32_DDR2_RAS_N <= '1';
+ Ethernet_MAC_PHY_rst_n <= '1';
+ Ethernet_MAC_PHY_tx_data <= (others => '0');
+ Ethernet_MAC_PHY_tx_en <= '0';
+ Ethernet_MAC_DUMMY_ETH_TXER <= '0';
+ Ethernet_MAC_PHY_Mii_clk <= '1';
+ SysACE_CompactFlash_SysACE_CEN <= '1';
+ SysACE_CompactFlash_SysACE_OEN <= '1';
+ SysACE_CompactFlash_SysACE_WEN <= '1';
+ SysACE_CompactFlash_SysACE_MPA <= (others => '0');
+
+
+ -- small function:
+ GPIO_LED_out <= GPIO_DIPswitch_in when GPIO_button_in(0) = '0' else not GPIO_DIPswitch_in;
+
+end architecture rtl;
+
diff --git a/hw_v5_fx30t_extension/simulation/Makefile b/hw_v5_fx30t_extension/simulation/Makefile
new file mode 100644
index 0000000..7c41f84
--- /dev/null
+++ b/hw_v5_fx30t_extension/simulation/Makefile
@@ -0,0 +1,47 @@
+#
+# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/hardware/board_sp605/simulation/Makefile $
+# $Date: 2011-09-05 16:49:43 +0200 (Mo, 05. Sep 2011) $
+# $Author: lange $
+# $Revision: 1240 $
+#
+
+library = work
+top = top
+
+all: compile simulate
+
+
+compile: Makefile.msim
+ export ANAFLAGS="-quiet -2008"; \
+ make -f Makefile.msim | ccze -A
+
+
+simulate:
+ export top=$(top); \
+ vsim -quiet -gui $(library).$(top) -do run.do -nowlfmcl -l transcript.log
+
+
+clean:
+ rm -rf $(library)
+ rm -f transcript
+ rm -f *.wlf
+ rm -f wlf*
+ @#
+ make -f Makefile.msim clean
+ rm -f Makefile.msim
+ rm -f .stamp
+
+
+# default patterns
+
+lib: $(library)
+
+$(library):
+ vlib $(library)
+
+
+# generate Makefile.msim with vmk
+Makefile.msim: vhdl_files.txt lib
+ vlib work
+ vmk -t modelsim -O -w $(library) -F vhdl_files.txt
+
diff --git a/hw_v5_fx30t_extension/simulation/run.do b/hw_v5_fx30t_extension/simulation/run.do
new file mode 100644
index 0000000..339fac7
--- /dev/null
+++ b/hw_v5_fx30t_extension/simulation/run.do
@@ -0,0 +1,65 @@
+
+#
+# helper functions
+#
+
+# restart + run
+proc r {} {
+ restart -f
+ set sim_start [clock seconds]
+
+ run -all
+
+ puts "# simulation run time: [clock format [expr [clock seconds] - $sim_start] -gmt 1 -format %H:%M:%S] "
+}
+
+
+# restart with clear
+proc rc {} {
+ .main clear
+ r
+}
+
+# print varables
+proc my_debug {} {
+ global env
+ foreach key [array names env] {
+ puts "$key=$env($key)"
+ }
+}
+
+
+# fast exit
+proc e {} {
+ exit -force
+}
+
+# fast exit
+proc x {} {
+ exit -force
+}
+
+
+# get env variables
+global env
+quietly set top $env(top)
+
+
+if {[file exists wave.do]} {
+ do wave.do
+} else {
+ if {[file exists wave_$top.do]} {
+ do wave_$top.do
+ } else {
+ puts "INFO: no wave file (wave_$top.do) found"
+ }
+ puts "INFO: no wave file (wave.do) found"
+}
+
+
+
+set sim_start [clock seconds]
+
+run -all
+
+puts "# simulation run time: [clock format [expr [clock seconds] - $sim_start] -gmt 1 -format %H:%M:%S] "
diff --git a/hw_v5_fx30t_extension/simulation/vhdl_files.txt b/hw_v5_fx30t_extension/simulation/vhdl_files.txt
new file mode 100644
index 0000000..a994fc5
--- /dev/null
+++ b/hw_v5_fx30t_extension/simulation/vhdl_files.txt
@@ -0,0 +1 @@
+work ../rtl/top.vhd
diff --git a/hw_v5_fx30t_extension/synthese/Makefile b/hw_v5_fx30t_extension/synthese/Makefile
new file mode 100644
index 0000000..712fa75
--- /dev/null
+++ b/hw_v5_fx30t_extension/synthese/Makefile
@@ -0,0 +1,138 @@
+#
+# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/hardware/board_sp605/synthese/Makefile $
+# $Date: 2011-08-29 13:52:33 +0200 (Mo, 29. Aug 2011) $
+# $Author: lange $
+# $Revision: 1226 $
+#
+
+MODULE = top
+DEVICE = xc5vfx30t-ff665-1
+UCF_FILE = virtex5_fx30t_eval.ucf
+CORES = ../cores/
+SOFTWARE = ../../../software/test
+DATE = $(shell date +"%Y-%m-%d__%H_%M")
+LOGFILE = synthesis_log_$(DATE).txt
+export XST_LOGFILE := $(LOGFILE)
+
+
+all:
+ @echo "check - look for timing and other synthesis issues"
+ @echo "xst - generate ngc file (netlist, replaces edif and netlist constrains)"
+ @echo "translate - generate ngd file (native generic database [reduced to primitives])"
+ @echo "map - generate ncd file (native ciruit description)"
+ @echo "par - place&route ncd file (design implementation)"
+ @echo "trace - generate timing report"
+ @echo "bitgen - generate bit file (ncd -> bit)"
+ @echo "update - update bitstream with elf file"
+ @echo "program - program fpga with bit file"
+ @echo "genmcs - genrate mcs file"
+ @echo "progspi - program spi flash with mcs file"
+ @echo "clean"
+ @echo "..."
+ @echo "testflow - update bitgen update program check"
+ @echo "finalflow - update bitgen update progspi check"
+
+testflow:
+ $(MAKE) bitgen update program check 2>&1 | tee $(XST_LOGFILE)
+
+finalflow:
+ $(MAKE) bitgen update progspi check 2>&1 | tee $(XST_LOGFILE)
+
+
+check:
+ @echo -e "Timing score: "
+ @grep --with-filename "Timing Score" xst/*.par
+ @echo -e "\nUnwanted Latches (737): "
+ @grep --with-filename "WARNING:Xst:737" xst/*.syr || echo -n
+ @echo -e "\nUnassigned signals (653): "
+ @grep --with-filename "WARNING:Xst:653" xst/*.syr || echo -n
+ @echo -e "\nCombinatoric loops (2170): "
+ @grep --with-filename "WARNING:Xst:2170" xst/*.syr || echo -n
+
+
+update:
+ make all --directory $(SOFTWARE)
+ data2mem -bm zpu_i0_memory_64k.bmm -bd $(SOFTWARE)/*.elf -bt xst/$(MODULE).bit -o b xst/$(MODULE)_update.bit
+
+
+program:
+ impact -batch program_fpga.cmd
+
+
+genmcs:
+ promgen -spi -p mcs -w -o $(MODULE)_update.mcs -s 8192 -u 0 xst/$(MODULE)_update.bit
+
+
+progspi: genmcs
+ impact -batch program_spi.cmd
+
+
+clean:
+ rm -f *.log
+ rm -f _impact.cmd
+ rm -f *.cfi
+ rm -f *.prm
+ rm -rf xst
+
+
+dir:
+ mkdir -p xst
+ mkdir -p xst/projnav.tmp
+ cp *.xst xst
+ cp *.prj xst
+ cp *.ut xst
+
+xst: $(MODULE).ngc
+translate: $(MODULE).ngd
+map: $(MODULE)_map.ncd
+par: $(MODULE).ncd
+
+#.PHONY: xst
+
+hw_timestamp:
+ make --directory ../rtl
+
+$(MODULE).ngc: dir
+ cd xst ; xst -ifn $(MODULE).xst -ofn $(MODULE).syr
+
+
+$(MODULE).ngd: $(MODULE).ngc $(UCF_FILE)
+ cd xst ; ngdbuild -dd _ngo -nt timestamp -uc ../$(UCF_FILE) -p $(DEVICE) -sd ../$(CORES) $(MODULE).ngc $(MODULE).ngd
+
+ # -p part number
+ # -mt multi-threading
+ # -w overwrite existing files
+ # -logic_opt logic optimization
+ # -ol overall effor level (std|high)
+ # -t placer cost table
+ # -register_duplication duplicate registers
+ # -global_opt Global Optimization (off|speed|area|power)
+ # -ir ignore RLOCs
+ # -pr pack registers in IO (off|i|o|b)
+ # -lc lut combining (auto|area|off)
+ # -power Virtex 6 Power Optimization (on|off|high|xe)
+ # -detail Generate Detailed MAP Report
+ # -o Output File Name
+ # -bp enables block RAM mapping
+$(MODULE)_map.ncd: $(MODULE).ngd
+ cd xst ; export XIL_PAR_DESIGN_CHECK_VERBOSE=1; map -p $(DEVICE) -mt 2 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -ir off -pr off -lc off -power off -detail -o $(MODULE)_map.ncd $(MODULE).ngd $(MODULE).pcf
+
+
+$(MODULE).ncd: $(MODULE)_map.ncd
+ cd xst ; par -w -mt 4 -ol high $(MODULE)_map.ncd $(MODULE).ncd $(MODULE).pcf
+
+
+trace:
+ cd xst ; trce -e -a -u -s 2 -xml $(MODULE).twx $(MODULE).ncd -o $(MODULE).twr $(MODULE).pcf
+
+tracefast:
+ cd xst ; trce -v 12 -fastpaths -xml $(MODULE).twx -o $(MODULE).twr $(MODULE).ncd $(MODULE).pcf
+
+
+bitgen: $(MODULE).ncd
+ cd xst ; bitgen -d -f $(MODULE).ut $(MODULE).ncd
+
+upload: xst/$(MODULE).bit
+ scp xst/$(MODULE).bit bl5599@uts:
+
+
diff --git a/hw_v5_fx30t_extension/synthese/top.prj b/hw_v5_fx30t_extension/synthese/top.prj
new file mode 100644
index 0000000..83c45d1
--- /dev/null
+++ b/hw_v5_fx30t_extension/synthese/top.prj
@@ -0,0 +1 @@
+vhdl work "../../rtl/top.vhd"
diff --git a/hw_v5_fx30t_extension/synthese/top.ut b/hw_v5_fx30t_extension/synthese/top.ut
new file mode 100644
index 0000000..613bf04
--- /dev/null
+++ b/hw_v5_fx30t_extension/synthese/top.ut
@@ -0,0 +1,39 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:2
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g InitPin:Pullup
+-g CsPin:Pullup
+-g DinPin:Pullup
+-g BusyPin:Pullup
+-g RdWrPin:Pullup
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ConfigFallback:Enable
+-g SelectMAPAbort:Enable
+-g BPI_page_size:1
+-g OverTempPowerDown:Disable
+-g JTAG_SysMon:Enable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:Yes
+-g Encrypt:No
diff --git a/hw_v5_fx30t_extension/synthese/top.xst b/hw_v5_fx30t_extension/synthese/top.xst
new file mode 100644
index 0000000..10878e1
--- /dev/null
+++ b/hw_v5_fx30t_extension/synthese/top.xst
@@ -0,0 +1,61 @@
+set -tmpdir "projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc5vfx30t-1-ff665
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+# lut combinig
+-lc Off
+-reduce_control_sets Off
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 32
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/hw_v5_fx30t_extension/synthese/virtex5_fx30t_eval.ucf b/hw_v5_fx30t_extension/synthese/virtex5_fx30t_eval.ucf
new file mode 100644
index 0000000..81e18ec
--- /dev/null
+++ b/hw_v5_fx30t_extension/synthese/virtex5_fx30t_eval.ucf
@@ -0,0 +1,247 @@
+############################################################################
+## This system.ucf file is generated by Base System Builder based on the
+## settings in the selected Xilinx Board Definition file. Please add other
+## user constraints to this file based on customer design specifications.
+##
+##
+## modified Bert Lange
+## 2011-09-08
+############################################################################
+
+NET sys_clk LOC= E18 | IOSTANDARD = LVCMOS33;
+NET clk_socket LOC= E13 | IOSTANDARD = LVCMOS33;
+#NET sys_rst LOC= AF20 | IOSTANDARD = LVCMOS18; button sw1
+#NET sys_rst TIG;
+
+
+## System level constraints
+NET sys_clk TNM_NET = sys_clk;
+TIMESPEC TS_sys_clk = PERIOD sys_clk 10000 ps;
+
+
+## IO Devices constraints
+
+#### Module RS232 constraints
+
+NET RS232_RX LOC= K8 | IOSTANDARD = LVCMOS33;
+NET RS232_TX LOC= L8 | IOSTANDARD = LVCMOS33;
+#NET RS232_RTS LOC= N8 | IOSTANDARD = LVCMOS33; # Jumper J3
+#NET RS232_CTS LOC= R8 | IOSTANDARD = LVCMOS33; # Jumper J4
+
+#### Module RS232_USB constraints
+
+NET RS232_USB_RX LOC= AA10 | IOSTANDARD = LVCMOS33;
+NET RS232_USB_TX LOC= AA19 | IOSTANDARD = LVCMOS33;
+NET RS232_USB_reset_dummy LOC= Y20 | IOSTANDARD = LVCMOS33;
+
+#### Module LEDs_8Bit constraints
+
+NET GPIO_LED_out<0> LOC= AF22 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET GPIO_LED_out<1> LOC= AF23 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET GPIO_LED_out<2> LOC= AF25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET GPIO_LED_out<3> LOC= AE25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET GPIO_LED_out<4> LOC= AD25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET GPIO_LED_out<5> LOC= AE26 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET GPIO_LED_out<6> LOC= AD26 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET GPIO_LED_out<7> LOC= AC26 | IOSTANDARD = LVCMOS18 | PULLUP;
+
+#### Module DIP_Switches_8Bit constraints
+
+NET GPIO_DIPswitch_in<0> LOC= AD13 | IOSTANDARD = LVCMOS18;
+NET GPIO_DIPswitch_in<1> LOC= AE13 | IOSTANDARD = LVCMOS18;
+NET GPIO_DIPswitch_in<2> LOC= AF13 | IOSTANDARD = LVCMOS18;
+NET GPIO_DIPswitch_in<3> LOC= AD15 | IOSTANDARD = LVCMOS18;
+NET GPIO_DIPswitch_in<4> LOC= AD14 | IOSTANDARD = LVCMOS18;
+NET GPIO_DIPswitch_in<5> LOC= AF14 | IOSTANDARD = LVCMOS18;
+NET GPIO_DIPswitch_in<6> LOC= AE15 | IOSTANDARD = LVCMOS18;
+NET GPIO_DIPswitch_in<7> LOC= AF15 | IOSTANDARD = LVCMOS18;
+
+#### Module Push_Buttons_3Bit constraints
+
+NET GPIO_button_in<0> LOC= AF20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB1
+NET GPIO_button_in<1> LOC= AE20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB2
+NET GPIO_button_in<2> LOC= AD19 | IOSTANDARD = LVCMOS18 | PULLUP; #PB3
+NET GPIO_button_in<3> LOC= AD20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB4
+
+#### Module FLASH_8Mx16 constraints
+
+
+NET FLASH_8Mx16_Mem_A<31> LOC= Y11 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<30> LOC= H9 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<29> LOC= G10 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<28> LOC= H21 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<27> LOC= G20 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<26> LOC= H11 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<25> LOC= G11 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<24> LOC= H19 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<23> LOC= H18 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<22> LOC= G12 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<21> LOC= F13 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<20> LOC= G19 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<19> LOC= F18 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<18> LOC= F14 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<17> LOC= F15 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<16> LOC= F17 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<15> LOC= G17 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<14> LOC= G14 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<13> LOC= H13 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<12> LOC= G16 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<11> LOC= G15 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<10> LOC= Y18 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<9> LOC= AA18 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<8> LOC= Y10 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_A<7> LOC= W11 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<15> LOC= AA15 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<14> LOC= Y15 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<13> LOC= W14 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<12> LOC= Y13 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<11> LOC= W16 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<10> LOC= Y16 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<9> LOC= AA14 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<8> LOC= AA13 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<7> LOC= AB12 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<6> LOC= AC11 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<5> LOC= AB20 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<4> LOC= AB21 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<3> LOC= AB11 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<2> LOC= AB10 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<1> LOC= AA20 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_DQ<0> LOC= Y21 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_WEN LOC= AA17 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_OEN<0> LOC= AA12 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_Mem_CEN<0> LOC= Y12 | IOSTANDARD = LVCMOS33;
+NET FLASH_8Mx16_rpn_dummy LOC= D13 | IOSTANDARD = LVCMOS33;
+#NET FLASH_8Mx16_byte_dummy LOC= Y17 | IOSTANDARD = LVCMOS33;
+#NET FLASH_8Mx16_adv_dummy LOC= F19 | IOSTANDARD = LVCMOS33;
+#NET FLASH_8Mx16_clk_dummy LOC= E12 | IOSTANDARD = LVCMOS33;
+#NET FLASH_8Mx16_wait_dummy LOC= D16 | IOSTANDARD = LVCMOS33;
+
+
+
+
+#### Module DDR2_SDRAM_16Mx32 constraints
+
+NET DDR2_SDRAM_16Mx32_DDR2_ODT<0> LOC= AF24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<0> LOC= U25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<1> LOC= T25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<2> LOC= T24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<3> LOC= T23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<4> LOC= U24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<5> LOC= V24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<6> LOC= Y23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<7> LOC= W23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<8> LOC= AA25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<9> LOC= AB26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<10> LOC= AB25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<11> LOC= AB24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_A<12> LOC= AA23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_BA<0> LOC= U21 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_BA<1> LOC= V22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_CAS_N LOC= W24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_CKE LOC= T22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_CS_N LOC= AD24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_RAS_N LOC= Y22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_WE_N LOC= AA22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DM<0> LOC= U26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DM<1> LOC= N24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DM<2> LOC= M24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DM<3> LOC= M25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQS<0> LOC= W26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQS<1> LOC= L23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQS<2> LOC= K22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQS<3> LOC= J21 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQS_N<0> LOC= W25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQS_N<1> LOC= L22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQS_N<2> LOC= K23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQS_N<3> LOC= K21 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<0> LOC= R22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<1> LOC= R23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<2> LOC= P23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<3> LOC= P24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<4> LOC= R25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<5> LOC= P25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<6> LOC= R26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<7> LOC= P26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<8> LOC= M26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<9> LOC= N26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<10> LOC= K25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<11> LOC= L24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<12> LOC= K26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<13> LOC= J26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<14> LOC= J25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<15> LOC= N21 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<16> LOC= M21 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<17> LOC= J23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<18> LOC= H23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<19> LOC= H22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<20> LOC= G22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<21> LOC= F22 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<22> LOC= F23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<23> LOC= E23 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<24> LOC= G24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<25> LOC= F24 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<26> LOC= G25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<27> LOC= H26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<28> LOC= G26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<29> LOC= F25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<30> LOC= E25 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_DQ<31> LOC= E26 | IOSTANDARD = SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_CK<0> LOC= V21 | IOSTANDARD = DIFF_SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_CK<1> LOC= N22 | IOSTANDARD = DIFF_SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_CK_N<0> LOC= W21 | IOSTANDARD = DIFF_SSTL18_II;
+NET DDR2_SDRAM_16Mx32_DDR2_CK_N<1> LOC= M22 | IOSTANDARD = DIFF_SSTL18_II;
+
+#### Module Ethernet_MAC constraints
+
+NET Ethernet_MAC_DUMMY_ETH_TXER LOC= A22 | IOSTANDARD = LVCMOS33;
+NET Ethernet_MAC_PHY_tx_clk LOC= E17 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
+NET Ethernet_MAC_PHY_rx_clk LOC= E20 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
+NET Ethernet_MAC_PHY_crs LOC= A25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET Ethernet_MAC_PHY_dv LOC= C21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET Ethernet_MAC_PHY_rx_data<0> LOC= D24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET Ethernet_MAC_PHY_rx_data<1> LOC= D23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET Ethernet_MAC_PHY_rx_data<2> LOC= D21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET Ethernet_MAC_PHY_rx_data<3> LOC= C26 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET Ethernet_MAC_PHY_col LOC= A24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET Ethernet_MAC_PHY_rx_er LOC= B24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET Ethernet_MAC_PHY_tx_en LOC= A23 | IOSTANDARD = LVCMOS33;
+NET Ethernet_MAC_PHY_tx_data<0> LOC= D19 | IOSTANDARD = LVCMOS33;
+NET Ethernet_MAC_PHY_tx_data<1> LOC= C19 | IOSTANDARD = LVCMOS33;
+NET Ethernet_MAC_PHY_tx_data<2> LOC= A20 | IOSTANDARD = LVCMOS33;
+NET Ethernet_MAC_PHY_tx_data<3> LOC= B20 | IOSTANDARD = LVCMOS33;
+NET Ethernet_MAC_PHY_rst_n LOC= B26 | IOSTANDARD = LVCMOS33;
+NET Ethernet_MAC_PHY_Mii_clk LOC= D26 | IOSTANDARD = LVCMOS33;
+NET Ethernet_MAC_PHY_Mii_data LOC= D25 | IOSTANDARD = LVCMOS33;
+
+#### Module SysACE_CompactFlash constraints
+
+NET SysACE_CompactFlash_SysACE_CLK LOC= F12 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPA<0> LOC= Y5 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPA<1> LOC= V7 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPA<2> LOC= W6 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPA<3> LOC= W5 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPA<4> LOC= K6 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPA<5> LOC= J5 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPA<6> LOC= J6 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<0> LOC= F5 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<1> LOC= U7 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<2> LOC= V6 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<3> LOC= U5 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<4> LOC= U6 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<5> LOC= T5 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<6> LOC= T7 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<7> LOC= R6 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<8> LOC= R7 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<9> LOC= R5 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<10> LOC= P6 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<11> LOC= P8 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<12> LOC= N6 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<13> LOC= M7 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<14> LOC= K5 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPD<15> LOC= L7 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_CEN LOC= G4 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_OEN LOC= Y6 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_WEN LOC= Y4 | IOSTANDARD = LVCMOS33;
+NET SysACE_CompactFlash_SysACE_MPIRQ LOC= H4 | IOSTANDARD = LVCMOS33;
+
+
OpenPOWER on IntegriCloud