hqemu - HQEMU

	Commit message (Expand)	Author	Age	Files	Lines
*	target-arm: Don't decode RFE or SRS on M profile cores	Peter Maydell	2013-03-05	1	-2/+3
*	target-arm: Factor out handling of SRS instruction	Peter Maydell	2013-03-05	1	-67/+69
*	gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end	Peter Maydell	2013-03-03	1	-2/+2
*	target-arm: Fix sbc_CC carry	Richard Henderson	2013-02-25	1	-24/+4
*	arm/translate.c: Fix adc_CC/sbc_CC implementation	Peter Crosthwaite	2013-02-25	1	-2/+2
*	target-arm: Implement sbc_cc inline	Richard Henderson	2013-02-23	1	-8/+39
*	target-arm: Implement adc_cc inline	Richard Henderson	2013-02-23	1	-5/+34
*	target-arm: Use add2 in gen_add_CC	Richard Henderson	2013-02-23	1	-4/+3
*	target-arm: Use mul[us]2 and add2 in umlal et al	Richard Henderson	2013-02-23	1	-12/+14
*	target-arm: Use mul[us]2 in gen_mul[us]_i64_i32	Richard Henderson	2013-02-23	1	-16/+22
*	target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes	Peter Maydell	2013-01-30	1	-1/+4
*	misc: move include files to include/qemu/	Paolo Bonzini	2012-12-19	1	-1/+1
*	exec: move include files to include/exec/	Paolo Bonzini	2012-12-19	1	-1/+1
*	build: kill libdis, move disassemblers to disas/	Paolo Bonzini	2012-12-19	1	-1/+1
*	TCG: Use gen_opc_instr_start from context instead of global variable.	Evgeny Voevodin	2012-12-08	1	-3/+3
*	TCG: Use gen_opc_icount from context instead of global variable.	Evgeny Voevodin	2012-12-08	1	-1/+1
*	TCG: Use gen_opc_pc from context instead of global variable.	Evgeny Voevodin	2012-12-08	1	-2/+2
*	TCG: Use gen_opc_buf from context instead of global variable.	Evgeny Voevodin	2012-11-17	1	-3/+3
*	TCG: Use gen_opc_ptr from context instead of global variable.	Evgeny Voevodin	2012-11-17	1	-4/+4
*	disas: avoid using cpu_single_env	Blue Swirl	2012-11-10	1	-1/+1
*	target-arm: Implement abs_i32 inline rather than as a helper	Peter Maydell	2012-10-24	1	-2/+9
*	target-arm: Use TCG operation for Neon 64 bit negation	Peter Maydell	2012-10-24	1	-1/+3
*	target-arm/translate: Fix RRX operands	Peter Crosthwaite	2012-10-17	1	-1/+1
*	target-arm: use deposit instead of hardcoded version	Aurelien Jarno	2012-10-05	1	-14/+6
*	target-arm: convert sar, shl and shr helpers to TCG	Aurelien Jarno	2012-10-05	1	-6/+43
*	target-arm: convert add_cc and sub_cc helpers to TCG	Aurelien Jarno	2012-10-05	1	-18/+48
*	target-arm: use globals for CC flags	Aurelien Jarno	2012-10-05	1	-81/+46
*	target-arm: Reinstate display of VFP registers in cpu_dump_state	Peter Maydell	2012-10-05	1	-26/+16
*	Emit debug_insn for CPU_LOG_TB_OP_OPT as well.	Richard Henderson	2012-09-27	1	-1/+1
*	target-arm: final conversion to AREG0 free mode	Blue Swirl	2012-09-15	1	-3/+3
*	target-arm: convert remaining helpers	Blue Swirl	2012-09-15	1	-67/+67
*	target-arm: convert void helpers	Blue Swirl	2012-09-15	1	-4/+4
*	target-arm: Fix typos in comments	Peter Maydell	2012-08-10	1	-5/+5
*	arm: translate: comment typo - s/middel/middle/	Peter A. G. Crosthwaite	2012-08-10	1	-1/+1
*	target-arm: Fix TCG temp handling in 64 bit cp writes	Peter Maydell	2012-07-12	1	-0/+2
*	target-arm: Fix CP15 based WFI	Paul Brook	2012-07-12	1	-1/+1
*	target-arm: Remove remaining old cp15 infrastructure	Peter Maydell	2012-06-20	1	-58/+1
*	target-arm: Move block cache ops to new cp15 framework	Peter Maydell	2012-06-20	1	-6/+1
*	target-arm: Convert performance monitor registers	Peter Maydell	2012-06-20	1	-25/+1
*	target-arm: Convert TLS registers	Peter Maydell	2012-06-20	1	-58/+0
*	target-arm: Convert WFI/barriers special cases to cp_reginfo	Peter Maydell	2012-06-20	1	-51/+0
*	target-arm: Convert TEECR, TEEHBR to new scheme	Peter Maydell	2012-06-20	1	-66/+0
*	target-arm: Convert debug registers to cp_reginfo	Peter Maydell	2012-06-20	1	-28/+0
*	target-arm: Remove old cpu_arm_set_cp_io infrastructure	Peter Maydell	2012-06-20	1	-40/+1
*	target-arm: initial coprocessor register framework	Peter Maydell	2012-06-20	1	-1/+155
*	target-arm: Make SETEND respect bswap_code (BE8) setting	Peter Maydell	2012-04-27	1	-4/+4
*	Userspace ARM BE8 support	Paul Brook	2012-04-06	1	-4/+7
*	ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.	Andrew Towers	2012-03-30	1	-1/+1
*	target-arm: Decode SETEND correctly in Thumb	Peter Maydell	2012-03-15	1	-23/+40
*	target-arm: Don't overuse CPUState	Andreas Färber	2012-03-14	1	-52/+52