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author | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 11:57:11 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 12:04:54 +0000 |
commit | 4d31c5967979d11c22c69a52beb1a03cab377e4f (patch) | |
tree | 43aec08cc32e5184c501b5649872debd2f508a47 /target-arm/translate.c | |
parent | 7d57f40877675db150d8afbf781de385c3828012 (diff) | |
download | hqemu-4d31c5967979d11c22c69a52beb1a03cab377e4f.zip hqemu-4d31c5967979d11c22c69a52beb1a03cab377e4f.tar.gz |
target-arm: Convert TLS registers
Convert TLS registers to the new cp15 framework
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r-- | target-arm/translate.c | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index a4429ea..e6b0d87 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2460,64 +2460,9 @@ static int cp15_user_ok(CPUARMState *env, uint32_t insn) } return 0; } - - if (cpn == 13 && cpm == 0) { - /* TLS register. */ - if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT))) - return 1; - } return 0; } -static int cp15_tls_load_store(CPUARMState *env, DisasContext *s, uint32_t insn, uint32_t rd) -{ - TCGv tmp; - int cpn = (insn >> 16) & 0xf; - int cpm = insn & 0xf; - int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); - - if (!arm_feature(env, ARM_FEATURE_V6K)) - return 0; - - if (!(cpn == 13 && cpm == 0)) - return 0; - - if (insn & ARM_CP_RW_BIT) { - switch (op) { - case 2: - tmp = load_cpu_field(cp15.c13_tls1); - break; - case 3: - tmp = load_cpu_field(cp15.c13_tls2); - break; - case 4: - tmp = load_cpu_field(cp15.c13_tls3); - break; - default: - return 0; - } - store_reg(s, rd, tmp); - - } else { - tmp = load_reg(s, rd); - switch (op) { - case 2: - store_cpu_field(tmp, cp15.c13_tls1); - break; - case 3: - store_cpu_field(tmp, cp15.c13_tls2); - break; - case 4: - store_cpu_field(tmp, cp15.c13_tls3); - break; - default: - tcg_temp_free_i32(tmp); - return 0; - } - } - return 1; -} - /* Disassemble system coprocessor (cp15) instruction. Return nonzero if instruction is not defined. */ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) @@ -2548,9 +2493,6 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) rd = (insn >> 12) & 0xf; - if (cp15_tls_load_store(env, s, insn, rd)) - return 0; - tmp2 = tcg_const_i32(insn); if (insn & ARM_CP_RW_BIT) { tmp = tcg_temp_new_i32(); |