blob: 94f4f0cd4563d035527aa5347edabe6682821c30 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_
/* northbridge customize options */
/**
* Max number of northbridges in the system
*/
#define MAX_NB_COUNT 1 //TODO: only 1 NB tested
/**
* Enable check for PCIe endpoint to be ready for PCI enumeration.
*
*/
//#define EPREADY_WORKAROUND_DISABLED
/**
* Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
*
*/
#define IOMMU_SUPPORT_DISABLE //TODO: enable it
/**
* Disable server PCIe hotplug support.
*/
//#define HOTPLUG_SUPPORT_DISABLED
/**
* Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
*/
//#define DEVICE_REMAP_DISABLE
#endif //_PLATFORM_CFG_H_
|
