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* Add predefined __ROMSTAGE__ and __RAMSTAGE__ macrosJulius Werner2015-04-065-17/+3
* tegra132: Add tegra_lp0_resume codeYen Lin2015-04-063-0/+787
* baytrail: Fix hdmi audio choppy issueKein Yuan2015-04-062-5/+13
* baytrail: reinitialize spi controller in SMM finalizationAaron Durbin2015-04-061-0/+21
* build system: rename __BOOT_BLOCK__ and __VER_STAGE__Patrick Georgi2015-04-043-8/+8
* rk3288: set cpu frequency up to 1.8GHzhuang lin2015-04-045-33/+82
* rk3288: guarantee i2c low period more than 1.3ushuang lin2015-04-041-4/+4
* t132: Enable SMMU translationsFurquan Shaikh2015-04-042-0/+5
* tegra132: Store ODMDATA from BCT into PMC scratch for use by kernelTom Warren2015-04-041-0/+26
* tegra132: remove framebuffer reservationAaron Durbin2015-04-045-37/+11
* veyron_pinky/rk3288: Use KHz, MHz and GHz constantsJulius Werner2015-04-046-37/+36
* broadwell: Enable turbo ratio if availableDuncan Laurie2015-04-041-4/+7
* Broadwell: Pass TSC value to romstage_mainLee Leahy2015-04-041-0/+6
* broadwell: fix typo in pei_dataDuncan Laurie2015-04-041-1/+1
* broadwell: Add USB3 PHY tuning fields to PEI DATADuncan Laurie2015-04-041-1/+14
* Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.Kenji Chen2015-04-041-0/+1
* Broadwell: Fix PCIe L1 Sub-State capability ID not filled.Kenji Chen2015-04-041-1/+4
* broadwell: Fix building with USE=quiet-cbDuncan Laurie2015-04-041-6/+6
* tegra124: use known-good drive for fast-train onlyNeil Chen2015-04-043-23/+29
* tegra124: add support for full DP link trainingNeil Chen2015-04-044-44/+652
* rk3288: Replace SPI fifo_size with constantDavid Hendricks2015-04-041-12/+6
* rk3288: Pass SPI bus speed in as parameter to init functionDavid Hendricks2015-04-042-7/+3
* tegra132: implement platform_prog_run()Aaron Durbin2015-04-031-30/+7
* tegra124: implement platform_prog_run()Aaron Durbin2015-04-031-18/+21
* rmodule: use struct prog while loading rmodulesAaron Durbin2015-04-032-16/+24
* pinky: Move some init to mainboard bootblockDavid Hendricks2015-04-021-21/+15
* rk3288/pinky: Move uart address to mainboard KconfigDavid Hendricks2015-04-021-5/+0
* rk3288: remove duplicated #define `PERI_ACLK_DIV_SHIFT`Aaron Durbin2015-04-021-1/+0
* Nyans: replace cpu_reset with hard_resetDaisuke Nojiri2015-04-021-0/+1
* Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.Kenji Chen2015-04-022-0/+8
* pistachio: add gpio type definitionVadim Bendebury2015-04-021-0/+25
* urara: Fix CBFS header definitionsVadim Bendebury2015-04-021-0/+4
* coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhzjinkun.hong2015-04-021-11/+26
* rockchip: support pwm regulatorhuang lin2015-04-026-6/+217
* rockchip: support i2c clock settinghuang lin2015-04-026-1/+72
* veyron_pinky: Add rev2 support, clean up mainboard.cJulius Werner2015-04-022-0/+8
* veyron: select rw romstage using vboot2Daisuke Nojiri2015-04-024-5/+35
* broadwell: Disable ADSP power gating feature by defaultDuncan Laurie2015-04-022-13/+18
* broadwell: Add event log entry for GPIO27Duncan Laurie2015-04-021-0/+4
* Broadwell: Reg_Script: add END tag to array "smbus_init_script"Ryan Lin2015-04-021-0/+2
* Broadwell: Synchronize for power management with FRCKenji Chen2015-04-024-0/+41
* Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRCKenji Chen2015-04-021-2/+7
* Broadwell: Revise programming flow for write-once registersKenji Chen2015-04-021-4/+3
* broadwell: Configure IOSF Port and Grant CountKenji Chen2015-04-021-1/+25
* Samus: Synchronization with FRC to enable PCIe Relaxed Order.Kenji Chen2015-04-021-0/+3
* baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPUKein Yuan2015-04-021-0/+9
* broadwell: Update PCIe configuration to follow BWGKane Chen2015-04-021-0/+1
* broadwell: Clear pending GPE events before entering sleep stateDuncan Laurie2015-04-021-0/+3
* Baytrail: Change PCIe root disable algorithmKenji Chen2015-04-022-3/+38
* Baytrail: add _PRT to each PCIe root port deviceTed Kuo2015-04-022-0/+112
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