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* t132: Replace fallback with CONFIG_CBFS_PREFIXMarc Jones2015-03-042-2/+4
* t132: Add shared romstageAaron Durbin2015-03-043-0/+74
* coreboot rush: Add dram init codeFurquan Shaikh2015-03-048-0/+2590
* coreboot rush: Add support for basic romstageFurquan Shaikh2015-03-041-1/+2
* coreboot t132: Enable loading of romstage from CBFS mediaFurquan Shaikh2015-03-043-2/+26
* coreboot t132: Remove init pllx for nowFurquan Shaikh2015-03-042-8/+5
* coreboot t132,rush: Add mainboard specific bootblock_initFurquan Shaikh2015-03-049-0/+1517
* coreboot t132: Add clock.c to all three stages of corebootFurquan Shaikh2015-03-033-53/+6
* coreboot arm: Define function for setting cntfrq registerFurquan Shaikh2015-03-022-37/+50
* tegra132: Enable bootblock support in tegra132 including UART supportFurquan Shaikh2015-03-0215-8/+2501
* x86: Fix pointer arithmetic regressions from MMIO changesKevin Paul Herbert2015-02-271-2/+2
* tegra124: Clean up ARM UART driver buildMarc Jones2015-02-251-4/+4
* soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`Paul Menzel2015-02-251-1/+0
* intel/broadwell: free local heap objectPatrick Georgi2015-02-251-0/+1
* soc/fsp_baytrail: Fix use of microcode-related Kconfig variablesAlexandru Gagniuc2015-02-242-11/+9
* tegra132: Postprocess bootblock properlyPatrick Georgi2015-02-171-2/+2
* tegra132: Add BCT support in tegra132 socFurquan Shaikh2015-02-172-2/+31
* T124: perform ram_repair when CPU rail is powered on in warmbootYen Lin2015-02-171-0/+29
* T124: perform ram_repair when CPU rail is powered on in coldbootYen Lin2015-02-174-1/+35
* tegra124: Correct cpu power on sequence and CPUPWRGOOD_TIMEJimmy Zhang2015-02-175-28/+41
* acpi: Generate valid ACPI processor objectsTimothy Pearson2015-02-165-107/+107
* x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert2015-02-1536-202/+213
* tegra132: Fix build for verstageMarc Jones2015-02-131-0/+1
* fsp_baytrail: Add macros to define 20K pull-up and downWerner Zeh2015-02-131-0/+14
* Baytrail_fsp: Make ME path configurable in menuconfigWerner Zeh2015-02-101-1/+1
* fsp_baytrail: Get FSP reserved memory from the FSP HOB listMartin Roth2015-02-093-16/+8
* Intel FSP platforms: Fix timestampsKyösti Mälkki2015-02-091-5/+6
* include/types.h: Provide BIT() macroAlexandru Gagniuc2015-02-063-2/+1
* FSP & CBMEM: Fix broken cbmem CAR transition.Martin Roth2015-02-062-1/+2
* CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki2015-01-277-8/+0
* CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki2015-01-277-61/+35
* CBMEM: Move cbmemc_reinit()Kyösti Mälkki2015-01-271-1/+0
* vboot2: implement select_firmware for pre-romstage verificationDaisuke Nojiri2015-01-273-1/+26
* vboot2: add verstageStefan Reinauer2015-01-2712-2/+26
* tegra132: Add support for tegra132 socFurquan Shaikh2015-01-2611-0/+713
* baytrail: there is a chance that USBPHY_COMPBG is set to 0Kane Chen2015-01-161-1/+3
* baytrail: use the setting in devicetree.cb to config USBPHY_COMPBGKane Chen2015-01-162-1/+3
* baytrail broadwell: Use timestamps internal stashKyösti Mälkki2015-01-144-50/+10
* Revert "vboot2: add verstage"Paul Menzel2015-01-145-22/+1
* vboot2: add verstageDaisuke Nojiri2015-01-135-1/+22
* soc/intel/fsp_baytrail/gpio.c: Silence unused variable warningEdward O'Callaghan2015-01-131-2/+5
* soc/intel/broadwell/me.c: Prevent unused function warningEdward O'Callaghan2015-01-121-7/+7
* soc/intel/broadwell/spi_loading.c: Remove dead codeEdward O'Callaghan2015-01-122-68/+0
* nyan*: I2C: Fix bus clear BC_TERMINATE naming.Tom Warren2015-01-092-4/+4
* tegra124: fix and fine tune the warm boot codeJoseph Lo2015-01-091-13/+14
* tegra: i2c: re-init i2c controller after resetJimmy Zhang2015-01-091-0/+5
* storm: Reserve memory from 0x4000_0000-0x414f_ffffDavid Hendricks2015-01-091-2/+8
* broadwell: Use correct include file for console functionsStefan Reinauer2015-01-061-1/+1
* Revert "Re-factor 'to_flash_offset()' into 'spi_flash.h'"Kyösti Mälkki2015-01-062-4/+19
* doxygen fixes: change @var to @param varMartin Roth2015-01-063-6/+6
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