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path: root/src/soc/intel
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* acpi: Remove monolithic ACPIVladimir Serbinenko2015-05-263-3/+0
* baytrail: Switch to per-device ACPIVladimir Serbinenko2015-05-2313-56/+144
* Braswell: Use Baytrail as Comparison BaseLee Leahy2015-05-2392-0/+14329
* Remove address from GPLv2 headersPatrick Georgi2015-05-21260-291/+260
* acpi: make fill_slit and fill_srat into arguments.Vladimir Serbinenko2015-05-201-12/+0
* baytrail: broadwell: correct refcode loadingAaron Durbin2015-05-132-2/+2
* 3rdparty: move to 3rdparty/blobsPatrick Georgi2015-05-054-9/+9
* 3rdparty: Move to blobsPatrick Georgi2015-05-054-9/+9
* intel/fsp_baytrail: Fix SPI debuggingDavid Imhoff2015-05-041-6/+6
* intel: Correct MMIO related ACPI table settingsDave Frodin2015-05-013-9/+12
* intel/broadwell: Allow using non-fake IFD descriptorPatrick Georgi2015-04-301-1/+1
* intel/broadwell: bootstate mechanism only exists in ramstagePatrick Georgi2015-04-301-0/+2
* intel/broadwell: Don't select MONOTONIC_TIMER_MSRPatrick Georgi2015-04-301-6/+0
* intel/broadwell: Build monotonic timer driver for SMMPatrick Georgi2015-04-301-0/+1
* chromeos: Add missing headersPatrick Georgi2015-04-301-0/+1
* kbuild: Don't require intel/common changes for every socStefan Reinauer2015-04-304-1/+8
* kbuild: automatically include SOCsStefan Reinauer2015-04-295-5/+17
* fsp platforms: consolidate FspNotify callsMartin Roth2015-04-281-20/+0
* intel/fsp_baytrail: Fix default SMM_TSEG_SIZE valueDavid Imhoff2015-04-271-1/+1
* fsp: Move fsp to fsp1_0Marc Jones2015-04-248-8/+8
* intel/broadwell: guard CHROMEOS support betterPatrick Georgi2015-04-221-2/+2
* coreboot: common stage cacheAaron Durbin2015-04-228-125/+42
* broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare.Todd Broch2015-04-211-0/+9
* broadwell: indent xhci codePatrick Georgi2015-04-211-17/+17
* broadwell: Skip pre-graphics delay in resume pathDuncan Laurie2015-04-211-4/+7
* broadwell: Implement Recovery ButtonRyan Lin2015-04-211-0/+4
* broadwell: Set C9/C10 vccminDuncan Laurie2015-04-182-0/+25
* broadwell: Disable XHCI compliance mode entryDuncan Laurie2015-04-181-0/+19
* soc/intel/common: Add common reset codeLee Leahy2015-04-183-0/+60
* soc/intel/common: Add function to protect MRC cacheDuncan Laurie2015-04-184-0/+75
* broadwell: add ROM stage pre console init call backWenkai Du2015-04-182-0/+7
* broadwell: Fixes for _SWS supportDuncan Laurie2015-04-153-23/+23
* broadwell: Remove unused bootblock codeDuncan Laurie2015-04-151-15/+0
* broadwell: Clean up ME device and add new ME10 flowDuncan Laurie2015-04-154-148/+215
* soc/baytrail: Use microcode from the blobs repositoryMarc Jones2015-04-153-16322/+1
* soc/broadwell: Use microcode from the blobs repositoryMarc Jones2015-04-156-4254/+1
* broadwell: Remove TPM device from lpc.aslDuncan Laurie2015-04-143-26/+3
* broadwell: Work around VBIOS framebuffer issueDuncan Laurie2015-04-131-0/+9
* broadwell: Fix incorrect SATA port map maskWenkai Du2015-04-131-3/+3
* broadwell: Enable double self refresh by defaultDuncan Laurie2015-04-131-0/+1
* baytrail: correct NC pin to GPO pin according to BYT platform design guideKane Chen2015-04-101-1/+1
* broadwell: Correct XHCI offset for USB 3.0 portsJulius Werner2015-04-101-1/+1
* broadwell: Set PCIe replay timeout to 0xDDuncan Laurie2015-04-101-1/+1
* baytrail: add code for supporting 2x ddr refresh rateKane Chen2015-04-102-0/+14
* broadwell: Add configuration for tuning VR for C-state operationsDuncan Laurie2015-04-102-4/+38
* broadwell: Preserve VbNv around cmos_initDuncan Laurie2015-04-101-0/+27
* broadwell: Add function to apply PRR to a range of SPI flashDuncan Laurie2015-04-103-0/+50
* broadwell: Turn off panel backlight in S5 SMI handlerDuncan Laurie2015-04-101-0/+43
* broadwell: Skip steps when disabling PCIe portDuncan Laurie2015-04-101-2/+2
* broadwell: Remove XHCI workarounds on WPTDuncan Laurie2015-04-101-22/+46
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