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* Set PCI bus operations at buildtime for ramstageKyösti Mälkki2013-07-1122-22/+22
* usbdebug: Move ehci_debug_info allocationKyösti Mälkki2013-07-101-1/+1
* Rename hardwaremain() to main()Stefan Reinauer2013-07-101-1/+1
* FUI: reorganize include filesRonald G. Minnich2013-07-102-4117/+0
* Drop some duplicates of PCI-e config functionsKyösti Mälkki2013-07-106-226/+0
* Fix MMCONF_SUPPORT_DEFAULT for ramstageKyösti Mälkki2013-07-1011-54/+11
* fox_wtm2: First step support for coreboot-based graphics startupRonald G. Minnich2013-07-093-10/+4127
* FOX_WTM2: First pass at FUI.Ronald G. Minnich2013-07-091-1/+20
* intel/i5000: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki2013-07-042-1/+30
* Move select MMCONF_SUPPORT under northbridge (fix)Kyösti Mälkki2013-07-042-1/+1
* intel/i945: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki2013-07-043-1/+30
* intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki2013-07-043-2/+34
* Move select MMCONF_SUPPORT under northbridgeKyösti Mälkki2013-07-034-0/+4
* Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`Paul Menzel2013-07-023-8/+6
* Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900Dave Frodin2013-07-021-0/+4
* amd/cimx/rd890/amd.h: Eliminate redefinition of NULLBruce Griffith2013-06-281-4/+1
* amd/agesa/family15/northbridge.c: Delete unused variableBruce Griffith2013-06-281-1/+0
* Add support to enable/disable builtin GbE (again)Stefan Reinauer2013-06-284-9/+5
* Revert "Add support to enable/disable builtin GbE"Kyösti Mälkki2013-06-272-4/+2
* Vortex86EX northbridge.c : Remove Vortex86DX PCI N/B related code.Andrew Wu2013-06-251-6/+0
* intel/sch: Use MMCONF_BASE_ADDRESSKyösti Mälkki2013-06-251-1/+1
* AMD: Drop empty root_complexKyösti Mälkki2013-06-2414-48/+0
* AMD Fam15tn: Add support for AGESA runtime allocation in CBMEMRudolf Marek2013-06-241-0/+27
* AMD Fam15tn: Add IOMMU BAR allocation to northbridgeRudolf Marek2013-06-242-0/+74
* intel/sandybridge: Locate CBMEM TOC early in ramstageKyösti Mälkki2013-06-221-0/+15
* Add support for DMP Vortex86EX PCI northbridge.Andrew Wu2013-06-2211-0/+685
* Add support to enable/disable builtin GbEStefan Reinauer2013-06-212-2/+4
* sandybridge: Store MRC cache in CBFSPatrick Georgi2013-06-202-2/+12
* AMD: Kconfig cleanupKyösti Mälkki2013-06-134-12/+12
* VX900: Use MIN/MAX from stdlib.h instead of redefining themAlexandru Gagniuc2013-06-104-26/+25
* VIA VX900: Add minimal ramstage needed to boot linuxAlexandru Gagniuc2013-06-109-0/+1545
* VX900: Add DDR3 initializationAlexandru Gagniuc2013-06-104-3/+1785
* VX900: Add support for early romstageAlexandru Gagniuc2013-06-1012-0/+778
* i945: Add Display defines for int15h handler.Denis 'GNUtoo' Carikli2013-06-071-0/+11
* Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGSDenis 'GNUtoo' Carikli2013-06-051-0/+1
* Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architectureRonald G. Minnich2013-06-042-16/+0
* AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"Christian Gmeiner2013-06-041-0/+2
* AMD Northbridge LX: convert spd_read_byte() to non-static versionChristian Gmeiner2013-06-041-0/+3
* AMD Northbridge LX: rename get_systop() to get_top_of_ram()Christian Gmeiner2013-06-043-3/+3
* AMD Northbridge LX: include northbridge.h in raminit.cChristian Gmeiner2013-06-041-0/+1
* AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-staticChristian Gmeiner2013-06-042-1/+6
* AMD Northbridge LX: add some missing includesChristian Gmeiner2013-06-041-0/+2
* AMD Northbridge LX: make sdram_* function prototypes non-staticChristian Gmeiner2013-06-042-3/+8
* AMD Fam 15tn: Use all memory on systems with more than 4 GBSiyuan Wang2013-06-041-1/+2
* haswell: fix overflow handling TOUUDAaron Durbin2013-06-031-2/+4
* northbridge/amd/amdmct: Use `static const` instead of `const static`Paul Menzel2013-06-034-10/+10
* Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`Ronald G. Minnich2013-05-253-37/+0
* Intel Sandy Bridge: udelay.c: Change comparison from <= to <Paul Menzel2013-05-231-1/+1
* intel/gm45: Add more debug output to read/write trainingNico Huber2013-05-221-6/+22
* intel/gm45: Handle overflows during DDR3 write trainingNico Huber2013-05-221-28/+63
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