summaryrefslogtreecommitdiffstats
path: root/src/northbridge/intel
Commit message (Collapse)AuthorAgeFilesLines
* northbridge,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-174-4/+0
| | | | | | | | Change-Id: Id1fcd3d1cd8a156a76e1a9a3ca4c7b4004c2c015 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6289 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* northbridge,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-1717-24/+0
| | | | | | | | Change-Id: I8d4bf17fe9fd82499b1515a8e85dff9cba498350 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6294 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* intel/i945/raminit.c: Remove trailing whitespace from `printk()`Paul Menzel2014-07-161-1/+1
| | | | | | | | | | | | | Remove a trailing space after the ellipse in the debug messages. Setting Graphics Frequency... FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz Change-Id: Iac8a5e89179104685dc54975ae7f833c1f3de69d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6280 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* src: Make use of 'CEIL_DIV(a, b)' macro across treeEdward O'Callaghan2014-07-113-8/+8
| | | | | | | | | | | | | The objective here is to tighten coreboot up a bit by not repeating common helpers. This makes the code base more consistent and unified/tight. Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* northbridge: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-0840-52/+0
| | | | | | | | Change-Id: I9515778e97cc5ae0e366b888da90a651ae5994fe Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6210 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black2014-07-052-2/+2
| | | | | | | | | | | | | | | | | | | | | | | The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel: Make monotonic timer a first class citizenEdward O'Callaghan2014-07-051-0/+1
| | | | | | | | | | | | | The monotonic time now needs to be a first class citizen in Coreboot as it is a hard dependency of the drivers/spi flash command polling function. Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6135 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* intel/haswell: Allow overriding PRE_GRAPHICS_DELAY in configStefan Reinauer2014-07-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | Without a prompt the config option will always stay 0 due to the way Kconfig works. BUG=chrome-os-partner:25387 BRANCH=panther TEST=Boot into dev mode with Mohammed's TV screen, see the dev mode screen appear. Change-Id: Ib7d9ec82b4a4a29daddc29aa7702fc420279017d Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/185970 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6010 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* intel/haswell: Allow pre-graphics delayStefan Reinauer2014-07-042-0/+10
| | | | | | | | | | | | | | | | | | | | | | Some slow monitors/TVs can't wake up quickly enough for coreboot, so when the VBIOS is run it won't detect them. Hence, add an option to wait for a while before running the VBIOS. BUG=none BRANCH=panther TEST=Boot to dev mode on one of the systems that exposed the problem and see it go away. Change-Id: Ib9524f1c7ee08bedf96a6468da8b4ccf712fe0e2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183545 Reviewed-by: Mohammed Habibulla <moch@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/6009 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* stdlib: Drop duplicates of min() and max()Kyösti Mälkki2014-07-012-4/+2
| | | | | | | | Change-Id: Ib2f6fad735e085d237a0d46e0586e123eef6e0e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6161 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* northbridge/intel/nehalem/raminit.c: Extraneous parentheseEdward O'Callaghan2014-06-301-1/+1
| | | | | | | | | | Equality comparison with extraneous parenthese, spotted by Clang. Change-Id: I8d532392a0365753583ed441958e06d5da784587 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6124 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* gm45 boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki2014-06-251-0/+1
| | | | | | | | Change-Id: Id19d31a2d114bb796b31ad61802d40c8608e4020 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6038 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
* nehalem boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki2014-06-251-0/+1
| | | | | | | | Change-Id: Ie4df2199e746de58c926f35bc9000752d399aa37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6037 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
* i945 boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki2014-06-251-0/+1
| | | | | | | | Change-Id: I1bbcba086f841a90544b827ae807a3c351d19d21 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
* sandy/ivy boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki2014-06-251-0/+2
| | | | | | | | | | | Like with other more recent boards already using DYNAMIC_CBMEM, the pointer to TOC is no longer stored in GNVS for ACPI. Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6034 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
* nehalem sandy ivy: Check cbmem_add() result for MRC dataKyösti Mälkki2014-06-252-30/+29
| | | | | | | | | | | In theory we could run out of CBMEM space so check the entry was added. There is no interest to support builds without EARLY_CBMEM_INIT. Change-Id: I68dd7c20e3d3692331aaafa2a692c5c0dfce95d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6033 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* intel/haswell: Report x32 memory as "x8 or x32"Duncan Laurie2014-06-251-4/+4
| | | | | | | | | | | | | | | | | | | There is only one bit for memory width reporting, either x16 or other. With x32 memory this code is reporting it as x8 so instead report "x8 or x32" in this condition. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-coreboot-samus Change-Id: I2a7c49bcb8de19084947b9dc42b93140641886fc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174120 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6008 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Remove guarding #includes by CONFIG_FOO combinationsEdward O'Callaghan2014-06-211-2/+0
| | | | | | | | | | | | | | First of many to remove guarding the inclusion of headers based on CONFIG_ options. This *potentially* could hide issues such as functions being swapped from under our feet, since different runtime behaviour could be declared with the function same name and type-signature. Hence, depending on the header we happen to get may change runtime behaviour. Change-Id: Ife56801c783c44e1882abef711e09b85b7f295a4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6055 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* northbridge/intel: Drop use of set_top_of_ram()Kyösti Mälkki2014-06-184-8/+0
| | | | | | | | | | | | | We implement get_top_of_ram() on these chipset to resolve CBMEM location early in romstage. Call to set_top_ram() is not required. Change-Id: I492e436b0c32d2c24677265b35afd05f29dcd0f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6031 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* intel/nehalem: Add get_top_top_ram() in ramstageKyösti Mälkki2014-06-183-9/+33
| | | | | | | | | | | | Needed to resolve CBMEM location early in ramstage. With DYNAMIC_CBMEM set_top_of_ram() will no longer be available. Change-Id: If50f1c5455a587b096348ffedadbe1dd2350a714 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6030 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* lenovo/x60: Fix build issue with DO_NATIVE_VGA_INITKyösti Mälkki2014-06-181-0/+1
| | | | | | | | | | Use the value from hardware for uma_memory_base. Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR`Paul Menzel2014-06-032-2/+4
| | | | | | | | Change-Id: I0f39b35fbf8e053ba21454a2847d6bb3ac5d2e1c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5923 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* northbridge/intel/i945/i945.h: Move define `BSM` to section D2F0Paul Menzel2014-06-031-2/+1
| | | | | | | | | | | The Base of Stolen Memory (BSM) register belongs to device 2, function 0. Change-Id: I2381f87ffaccb2f8034c160fc30c1d92f8b19402 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5922 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* sandybridge: Pass chip info to i915lightup.Vladimir Serbinenko2014-06-022-2/+7
| | | | | | | | Change-Id: I280441aadb0575dc0b99584cdcd48cc76a0289a2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5284 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* i945: Fix TSEG size allocation for get_top_of_ram()Kyösti Mälkki2014-06-021-4/+4
| | | | | | | | | | | Seems boards with i945 had TSEG disabled so this had gone unnoticed. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I6a00ea9121847ce2fede22538e1b53a870d761f1 Reviewed-on: http://review.coreboot.org/5892 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* i945: Fix resource bases for UMA and TSEGKyösti Mälkki2014-06-021-23/+23
| | | | | | | | | | | | | TSEG appears in memory below graphics UMA region. Seems boards with i945 had TSEG disabled, so the incorrect order did not make a difference. Change-Id: Ie293aab17b60b5f06a871a773cd42577c7dc7c7b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5891 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* northbridge/intel/i945/i945.h: Trivial, fixup header guardsEdward O'Callaghan2014-06-011-5/+7
| | | | | | | | Change-Id: Iff15ab436e5b7b4e189c7341e7c508faaef07a3a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5896 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* i945: Use defines for DEVENKyösti Mälkki2014-05-312-7/+6
| | | | | | | | | Change-Id: I32461449354155510c0e14e9d0ce396068ea50d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5890 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* northbridge/intel/i945/northbridge.c: Use define `TOLUD` instead of ↵Paul Menzel2014-05-311-1/+1
| | | | | | | | | | | hardcoded value Change-Id: I4739c5544aade105399347d239ba64f5115db397 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5869 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* northbridge/intel/i945: Add define for register `BSM` and use itPaul Menzel2014-05-313-2/+4
| | | | | | | | | | Add a define for the register Base of Stolen Memory (BSM) and use it. Change-Id: I5b1df4e088d88344fac8cd8d218e76b08a885f58 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5884 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* northbridge/intel/i82810/raminit.c: Unused func spd_read_byte()Edward O'Callaghan2014-05-251-5/+0
| | | | | | | | | | Spotted by Clang Change-Id: Ib119f46fbbbd09a660bd6c4647b96a55d2c532a7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5846 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* northbridge/intel/e7505/raminit.c: Silence warn of unused funcEdward O'Callaghan2014-05-251-1/+3
| | | | | | | | | | Spotted by Clang. Change-Id: Iec34a23d0cf193ca6a4af0407b0763bf77ea03b3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5845 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* northbridge/intel/i3100/raminit.c: Uninitialized variableEdward O'Callaghan2014-05-252-3/+3
| | | | | | | | | | Spotted by Clang Change-Id: If524a5cd984602a332c4ca28a8167a3597206b94 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5844 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/intel/i945/raminit.c: duplicate 'const' declaration specifierEdward O'Callaghan2014-05-251-2/+2
| | | | | | | | | | | Spotted by Clang Change-Id: I7e91f3edfa773560131e267a7776d8bf1ff7e295 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5843 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* baytrail: Fix some minor errors in FSPDavid Hendricks2014-05-211-1/+1
| | | | | | | | | | | | | | - Duplicate declaration of GetFspReservedMemoryFromGuid - Corrupt line that was only compiled for a southbridge that no board in coreboot currently uses. (thanks for Mike Hibbett <mhibbett@ircona.com> for pointing this out) Change-Id: I847e807272acbaa93c87a89c0d2f94829c9121e6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/5798 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* intel: Remove GFXUMA and related global variablesKyösti Mälkki2014-05-196-0/+12
| | | | | | | | | | | | | | | | Remove use of global variables uma_memory_base and uma_memory_size from builds with Intel northbridges, as these variables can be kept within the chipset or even as stack locals. Intel platforms have no functional implemenation for option GFXUMA. If we did implement some choice between external and integrated graphics, it needs to be named in less obscure fashion. Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5720 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* fix printk typesPatrick Georgi2014-05-191-1/+1
| | | | | | | | | | | | Some size_ts were considered long int and some compilers are picky about that. Change-Id: I671daa18eb3bfa2a7defc120e77bbb1ef72bd417 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5788 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* build: separate CPPFLAGS from CFLAGSPatrick Georgi2014-05-171-1/+1
| | | | | | | | | | | There are a couple of places where CPPFLAGS are pasted into CFLAGS, eliminate them. Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5765 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* build: CPPFLAGS is more common than INCLUDESPatrick Georgi2014-05-171-1/+1
| | | | | | | | | | | Rename INCLUDES to CPPFLAGS since the latter is more commonly used for preprocessor options. Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5764 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* intel: Drop obsolete comments on MTRR usageKyösti Mälkki2014-05-143-33/+0
| | | | | | | | | | | | Problem with UMA region allocation was fixed when MTRRs changed to use memrange implementation. Change-Id: I420dac30de2836a91596d81f88bb45b46f248532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5719 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth2014-05-0912-858/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* northbridge/intel/sandybridge/pei_data.h: Fix typo in hig*h*est in commentPaul Menzel2014-05-061-1/+1
| | | | | | | | Change-Id: I0daf5d1d446de1f09b695f177b0491301613e278 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5667 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* ChromeOS: Remove oprom_is_loadedKyösti Mälkki2014-05-013-2/+11
| | | | | | | | | | | | | | | | | A global flag oprom_is_loaded was used to indicate to U-boot that VGA option ROM was loaded and run, or that native VGA init was completed on GMA device. Implement this feature without dependency to CHROMEOS option and replace use of global variable oprom_is_loaded with call to gfx_get_init_done(). Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Declare recovery and developer modes outside ChromeOSKyösti Mälkki2014-05-012-11/+2
| | | | | | | | | | | Move the implementation for recovery and developer modes from vendorcode/google/chromes to lib/. Change-Id: I33335fb282de2c7bc613dc58d6912c47f3b5c06c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* console: Move newline translation outside console_tx_byteKyösti Mälkki2014-04-092-2/+2
| | | | | | | | | | | This gives us completely transparent low-level function to transmit data. Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5336 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* console: Fix includesKyösti Mälkki2014-03-041-0/+1
| | | | | | | | | | | | | | | Do not pull in console hw-specific prototypes everywhere with console.h as those are not needed for higher levels. Move prototypes for UARTs next to other consoles. Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5232 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* nehalem: Replace video init.Vladimir Serbinenko2014-03-044-1831/+460
| | | | | | | | | | | Old video init just replayed the sequence. This one actually computes the values. Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5270 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* nehalem: Remove SSKPD.Vladimir Serbinenko2014-03-031-1/+0
| | | | | | | | | | Not really used and conflicts with SSKPD from i915_regs.h Change-Id: I1462457f656310df99e78aee8cbfe0206f6e2a1e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5268 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* intel/nehalem: Fix soft reset detection.Vladimir Serbinenko2014-03-031-1/+1
| | | | | | | | Change-Id: I4575cddc35dc8309372beafec441d194bc145242 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5267 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* intel/nehalem: Use non-powercycle reset.Vladimir Serbinenko2014-03-031-1/+1
| | | | | | | | Change-Id: Ibc2421a50e272a580461e4eacec6cfcd38654fe8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5266 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
OpenPOWER on IntegriCloud