coreboot-staging - Partial non-authoritative staging tree (partial copy of Raptor Engineering's internal coreboot staging tree) Don't use unless Gerrit is malfunctioning or down! https://www.raptorengineering.com

	Commit message (Expand)	Author	Age	Files	Lines
*	sandy/ivy: Fix mrc.cache file in CBFS	Kyösti Mälkki	2014-02-17	1	-1/+3
*	nb/sandybridge: Move MRC cache above mrc.bin	Alexandru Gagniuc	2014-01-24	1	-1/+1
*	CBMEM intel: Define get_top_of_ram() once per chipset	Kyösti Mälkki	2014-01-15	1	-0/+2
*	sandybridge: Allow skipping mrc.cache	Vladimir Serbinenko	2014-01-15	1	-1/+1
*	Add support to enable/disable builtin GbE (again)	Stefan Reinauer	2013-06-28	1	-5/+0
*	sandybridge: Store MRC cache in CBFS	Patrick Georgi	2013-06-20	1	-0/+10
*	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel	2013-03-01	1	-1/+1
*	Remove AMD special case for LAPIC based udelay()	Patrick Georgi	2012-11-27	1	-1/+0
*	Get rid of drivers class	Patrick Georgi	2012-11-27	1	-2/+2
*	Initial IGD OpRegion implementation	Stefan Reinauer	2012-11-12	1	-0/+2
*	Rework Sandybridge MRC cache handling	Stefan Reinauer	2012-05-11	1	-0/+2
*	Strip quotes from Sandybridge MRC blob	Stefan Reinauer	2012-05-02	1	-1/+1
*	Sandybridge: Display platform information early	Vadim Bendebury	2012-05-02	1	-0/+1
*	SMM: Add udelay on Sandybridge systems	Stefan Reinauer	2012-04-27	1	-0/+1
*	Add support for Intel Sandybridge CPU (northbridge part)	Stefan Reinauer	2012-04-05	1	-0/+41