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* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* cpu/x86/mtrr: Add MTRR index and total MTRRs to error messagePaul Menzel2015-10-151-1/+3
* cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc2015-10-152-26/+26
* Verify Kconfigs symbols are not zero for hex and int type symbolsMartin Roth2015-07-121-1/+1
* Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()Martin Roth2015-07-121-1/+1
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-1/+1
* x86/mtrr: Enable MTRR's before enabling cachingIsaac Christensen2014-09-251-4/+4
* x86: Minimize work done with the caches disabled in mtrr functions.Gabe Black2014-09-241-38/+78
* x86 MTRR: Drop unused return valueKyösti Mälkki2014-06-301-2/+1
* Use MTRR definesKyösti Mälkki2014-06-301-4/+3
* Remove CACHE_ROM.Vladimir Serbinenko2014-02-251-76/+0
* mtrr: only add prefetchable resources as WRCOMB for VGA devicesAaron Durbin2014-02-091-2/+17
* MTRR: Mark all prefetchable resources as WRCOMB.Vladimir Serbinenko2014-02-061-3/+2
* mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocationAaron Durbin2014-02-061-2/+25
* src/cpu: Fix spelling of MTTR to MTRRPaul Menzel2014-01-262-4/+4
* Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki2014-01-151-2/+2
* AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki2013-12-261-7/+4
* cpu/x86/mtrr/mtrr.c: Remove superfluous assignment to `type_index`Paul Menzel2013-10-031-1/+0
* cpu: Fix spellingMartin Roth2013-07-112-11/+11
* x86: use boot state callbacks to disable rom cacheAaron Durbin2013-05-011-1/+9
* AMD: Drop six copies of wrmsr_amd and rdmsr_amdKyösti Mälkki2013-04-041-1/+1
* boot: add disable_cache_rom() functionAaron Durbin2013-04-011-0/+6
* x86: mtrr: optimize hole carving above 4GiBAaron Durbin2013-03-291-1/+18
* x86: mtrr: add hole punching supportAaron Durbin2013-03-291-48/+188
* x86: add rom cache variable MTRR index to tablesAaron Durbin2013-03-291-0/+5
* x86: mtrr: add CONFIG_CACHE_ROM supportAaron Durbin2013-03-291-0/+59
* mtrr: honor IORESOURCE_WRCOMBAaron Durbin2013-03-291-1/+11
* x86: add new mtrr implementationAaron Durbin2013-03-291-354/+401
* x86: unify amd and non-amd MTRR routinesAaron Durbin2013-03-221-7/+16
* Google Link: Add remaining code to support native graphicsRonald G. Minnich2013-03-151-1/+1
* Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki2012-08-011-0/+4
* Rename cache_lbmem() to cache_ramstage()Stefan Reinauer2012-07-241-3/+3
* MTRR: drop repetetive debug messageStefan Reinauer2012-07-241-2/+0
* Check for IORESOURCE_UMA_FB in MTRR setupKyösti Mälkki2012-07-161-15/+13
* Define global uma_memory variablesKyösti Mälkki2012-07-161-4/+0
* Drop Kconfig VAR_MTRR_HOLE optionKyösti Mälkki2012-07-121-12/+4
* Fix the location of "Setting variable MTRR" printk.Denis 'GNUtoo' Carikli2012-05-301-5/+6
* Some more #if cleanupPatrick Georgi2012-05-082-2/+2
* Cache 8MB flash instead of 4MBStefan Reinauer2012-04-061-25/+21
* Make MTRR min hole alignment 64MBDuncan Laurie2012-03-301-3/+6
* Fix MB calculation in the reporting of the MTRR holeDuncan Laurie2012-03-301-1/+1
* MTRR: add alternate allocation method for odd memory mapsDuncan Laurie2012-03-301-7/+45
* Add an option to keep the ROM cached after romstageStefan Reinauer2012-03-301-1/+13
* MTRR: get physical address size from CPUIDSven Schnelle2012-01-101-2/+6
* Get rid of AUTO_XIP_ROM_BASEPatrick Georgi2011-10-281-1/+6
* earlymtrr.c: wipe some dead code, use names instead of numbers and someStefan Reinauer2011-04-141-40/+6
* Now that the VIA code is run above 1Meg (like other boards), it shouldKevin O'Connor2011-01-191-2/+2
* MTRR related improvements for AMD family 10h and family 0Fh systemsScott Duplichan2010-11-131-18/+31
* Rename build system variables to be more intuitive, andPatrick Georgi2010-09-301-1/+1
* We call this cache as ram everywhere, so let's call it the same in KconfigStefan Reinauer2010-08-301-1/+1
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